1/*
 2 *	sp5100_tco:	TCO timer driver for sp5100 chipsets.
 3 *
 4 *	(c) Copyright 2009 Google Inc., All Rights Reserved.
 5 *
 6 *	TCO timer driver for sp5100 chipsets
 7 */
 8
 
 
 9/*
10 * Some address definitions for the Watchdog
11 */
12
13#define SP5100_WDT_MEM_MAP_SIZE		0x08
14#define SP5100_WDT_CONTROL(base)	((base) + 0x00) /* Watchdog Control */
15#define SP5100_WDT_COUNT(base)		((base) + 0x04) /* Watchdog Count */
16
17#define SP5100_WDT_START_STOP_BIT	1
18#define SP5100_WDT_TRIGGER_BIT		(1 << 7)
19
20#define SP5100_PCI_WATCHDOG_MISC_REG	0x41
21#define SP5100_PCI_WATCHDOG_DECODE_EN	(1 << 3)
22
23#define SP5100_PM_IOPORTS_SIZE		0x02
24
25/* These two IO registers are hardcoded and there doesn't seem to be a way to
 
26 * read them from a register.
27 */
 
 
28#define SP5100_IO_PM_INDEX_REG		0xCD6
29#define SP5100_IO_PM_DATA_REG		0xCD7
30
 
 
 
31#define SP5100_PM_WATCHDOG_CONTROL	0x69
32#define SP5100_PM_WATCHDOG_BASE0	0x6C
33#define SP5100_PM_WATCHDOG_BASE1	0x6D
34#define SP5100_PM_WATCHDOG_BASE2	0x6E
35#define SP5100_PM_WATCHDOG_BASE3	0x6F
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
36
37#define SP5100_PM_WATCHDOG_FIRED	(1 << 1)
38#define SP5100_PM_WATCHDOG_ACTION_RESET	(1 << 2)
39
40#define SP5100_PM_WATCHDOG_DISABLE	1
41#define SP5100_PM_WATCHDOG_SECOND_RES	(3 << 1)

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 *	sp5100_tco:	TCO timer driver for sp5100 chipsets.
 4 *
 5 *	(c) Copyright 2009 Google Inc., All Rights Reserved.
 6 *
 7 *	TCO timer driver for sp5100 chipsets
 8 */
 9
10#include <linux/bitops.h>
11
12/*
13 * Some address definitions for the Watchdog
14 */
 
15#define SP5100_WDT_MEM_MAP_SIZE		0x08
16#define SP5100_WDT_CONTROL(base)	((base) + 0x00) /* Watchdog Control */
17#define SP5100_WDT_COUNT(base)		((base) + 0x04) /* Watchdog Count */
18
19#define SP5100_WDT_START_STOP_BIT	BIT(0)
20#define SP5100_WDT_FIRED		BIT(1)
21#define SP5100_WDT_ACTION_RESET		BIT(2)
22#define SP5100_WDT_DISABLED		BIT(3)
23#define SP5100_WDT_TRIGGER_BIT		BIT(7)
24
25#define SP5100_PM_IOPORTS_SIZE		0x02
26
27/*
28 * These two IO registers are hardcoded and there doesn't seem to be a way to
29 * read them from a register.
30 */
31
32/*  For SP5100/SB7x0/SB8x0 chipset */
33#define SP5100_IO_PM_INDEX_REG		0xCD6
34#define SP5100_IO_PM_DATA_REG		0xCD7
35
36/* For SP5100/SB7x0 chipset */
37#define SP5100_SB_RESOURCE_MMIO_BASE	0x9C
38
39#define SP5100_PM_WATCHDOG_CONTROL	0x69
40#define SP5100_PM_WATCHDOG_BASE		0x6C
41
42#define SP5100_PCI_WATCHDOG_MISC_REG	0x41
43#define SP5100_PCI_WATCHDOG_DECODE_EN	BIT(3)
44
45#define SP5100_PM_WATCHDOG_DISABLE	((u8)BIT(0))
46#define SP5100_PM_WATCHDOG_SECOND_RES	GENMASK(2, 1)
47
48#define SP5100_DEVNAME			"SP5100 TCO"
49
50/*  For SB8x0(or later) chipset */
51#define SB800_PM_ACPI_MMIO_EN		0x24
52#define SB800_PM_WATCHDOG_CONTROL	0x48
53#define SB800_PM_WATCHDOG_BASE		0x48
54#define SB800_PM_WATCHDOG_CONFIG	0x4C
55
56#define SB800_PCI_WATCHDOG_DECODE_EN	BIT(0)
57#define SB800_PM_WATCHDOG_DISABLE	((u8)BIT(1))
58#define SB800_PM_WATCHDOG_SECOND_RES	GENMASK(1, 0)
59#define SB800_ACPI_MMIO_DECODE_EN	BIT(0)
60#define SB800_ACPI_MMIO_SEL		BIT(1)
61
62#define SB800_PM_WDT_MMIO_OFFSET	0xB00
63
64#define SB800_DEVNAME			"SB800 TCO"
65
66/* For recent chips with embedded FCH (rev 40+) */
67
68#define EFCH_PM_DECODEEN		0x00
69
70#define EFCH_PM_DECODEEN_WDT_TMREN	BIT(7)
71
72
73#define EFCH_PM_DECODEEN3		0x00
74#define EFCH_PM_DECODEEN_SECOND_RES	GENMASK(1, 0)
75#define EFCH_PM_WATCHDOG_DISABLE	((u8)GENMASK(3, 2))
76
77/* WDT MMIO if enabled with PM00_DECODEEN_WDT_TMREN */
78#define EFCH_PM_WDT_ADDR		0xfeb00000
79
80#define EFCH_PM_ISACONTROL		0x04
81
82#define EFCH_PM_ISACONTROL_MMIOEN	BIT(1)
 
83
84#define EFCH_PM_ACPI_MMIO_ADDR		0xfed80000
85#define EFCH_PM_ACPI_MMIO_WDT_OFFSET	0x00000b00