1/*
 2 *      Intel_SCU 0.2:  An Intel SCU IOH Based Watchdog Device
 3 *			for Intel part #(s):
 4 *				- AF82MP20 PCH
 5 *
 6 *      Copyright (C) 2009-2010 Intel Corporation. All rights reserved.
 7 *
 8 *      This program is free software; you can redistribute it and/or
 9 *      modify it under the terms of version 2 of the GNU General
10 *      Public License as published by the Free Software Foundation.
11 *
12 *      This program is distributed in the hope that it will be
13 *      useful, but WITHOUT ANY WARRANTY; without even the implied
14 *      warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
15 *      PURPOSE.  See the GNU General Public License for more details.
16 *      You should have received a copy of the GNU General Public
17 *      License along with this program; if not, write to the Free
18 *      Software Foundation, Inc., 59 Temple Place - Suite 330,
19 *      Boston, MA  02111-1307, USA.
20 *      The full GNU General Public License is included in this
21 *      distribution in the file called COPYING.
22 *
23 */
24
25#ifndef __INTEL_SCU_WATCHDOG_H
26#define __INTEL_SCU_WATCHDOG_H
27
28#define PFX "Intel_SCU: "
29#define WDT_VER "0.3"
30
31/* minimum time between interrupts */
32#define MIN_TIME_CYCLE 1
33
34/* Time from warning to reboot is 2 seconds */
35#define DEFAULT_SOFT_TO_HARD_MARGIN 2
36
37#define MAX_TIME 170
38
39#define DEFAULT_TIME 5
40
41#define MAX_SOFT_TO_HARD_MARGIN (MAX_TIME-MIN_TIME_CYCLE)
42
43/* Ajustment to clock tick frequency to make timing come out right */
44#define FREQ_ADJUSTMENT 8
45
46struct intel_scu_watchdog_dev {
47	ulong driver_open;
48	ulong driver_closed;
49	u32 timer_started;
50	u32 timer_set;
51	u32 threshold;
52	u32 soft_threshold;
53	u32 __iomem *timer_load_count_addr;
54	u32 __iomem *timer_current_value_addr;
55	u32 __iomem *timer_control_addr;
56	u32 __iomem *timer_clear_interrupt_addr;
57	u32 __iomem *timer_interrupt_status_addr;
58	struct sfi_timer_table_entry *timer_tbl_ptr;
59	struct notifier_block intel_scu_notifier;
60	struct miscdevice miscdev;
61};
62
63extern int sfi_mtimer_num;
64
65/* extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint); */
66#endif /* __INTEL_SCU_WATCHDOG_H */

 1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 *      Intel_SCU 0.2:  An Intel SCU IOH Based Watchdog Device
 4 *			for Intel part #(s):
 5 *				- AF82MP20 PCH
 6 *
 7 *      Copyright (C) 2009-2010 Intel Corporation. All rights reserved.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 8 */
 9
10#ifndef __INTEL_SCU_WATCHDOG_H
11#define __INTEL_SCU_WATCHDOG_H
12
 
13#define WDT_VER "0.3"
14
15/* minimum time between interrupts */
16#define MIN_TIME_CYCLE 1
17
18/* Time from warning to reboot is 2 seconds */
19#define DEFAULT_SOFT_TO_HARD_MARGIN 2
20
21#define MAX_TIME 170
22
23#define DEFAULT_TIME 5
24
25#define MAX_SOFT_TO_HARD_MARGIN (MAX_TIME-MIN_TIME_CYCLE)
26
27/* Ajustment to clock tick frequency to make timing come out right */
28#define FREQ_ADJUSTMENT 8
29
30struct intel_scu_watchdog_dev {
31	ulong driver_open;
32	ulong driver_closed;
33	u32 timer_started;
34	u32 timer_set;
35	u32 threshold;
36	u32 soft_threshold;
37	u32 __iomem *timer_load_count_addr;
38	u32 __iomem *timer_current_value_addr;
39	u32 __iomem *timer_control_addr;
40	u32 __iomem *timer_clear_interrupt_addr;
41	u32 __iomem *timer_interrupt_status_addr;
42	struct sfi_timer_table_entry *timer_tbl_ptr;
43	struct notifier_block intel_scu_notifier;
44	struct miscdevice miscdev;
45};
46
47extern int sfi_mtimer_num;
48
49/* extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint); */
50#endif /* __INTEL_SCU_WATCHDOG_H */