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1/*
2 * This file contains code to reset and initialize USB host controllers.
3 * Some of it includes work-arounds for PCI hardware and BIOS quirks.
4 * It may need to run early during booting -- before USB would normally
5 * initialize -- to ensure that Linux doesn't use any legacy modes.
6 *
7 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
8 * (and others)
9 */
10
11#include <linux/types.h>
12#include <linux/kernel.h>
13#include <linux/pci.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/acpi.h>
17#include <linux/dmi.h>
18#include "pci-quirks.h"
19#include "xhci-ext-caps.h"
20
21
22#define UHCI_USBLEGSUP 0xc0 /* legacy support */
23#define UHCI_USBCMD 0 /* command register */
24#define UHCI_USBINTR 4 /* interrupt register */
25#define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
26#define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
27#define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */
28#define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */
29#define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */
30#define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */
31#define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */
32
33#define OHCI_CONTROL 0x04
34#define OHCI_CMDSTATUS 0x08
35#define OHCI_INTRSTATUS 0x0c
36#define OHCI_INTRENABLE 0x10
37#define OHCI_INTRDISABLE 0x14
38#define OHCI_FMINTERVAL 0x34
39#define OHCI_HCR (1 << 0) /* host controller reset */
40#define OHCI_OCR (1 << 3) /* ownership change request */
41#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
42#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
43#define OHCI_INTR_OC (1 << 30) /* ownership change */
44
45#define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
46#define EHCI_USBCMD 0 /* command register */
47#define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
48#define EHCI_USBSTS 4 /* status register */
49#define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
50#define EHCI_USBINTR 8 /* interrupt register */
51#define EHCI_CONFIGFLAG 0x40 /* configured flag register */
52#define EHCI_USBLEGSUP 0 /* legacy support register */
53#define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
54#define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
55#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
56#define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
57
58/* AMD quirk use */
59#define AB_REG_BAR_LOW 0xe0
60#define AB_REG_BAR_HIGH 0xe1
61#define AB_REG_BAR_SB700 0xf0
62#define AB_INDX(addr) ((addr) + 0x00)
63#define AB_DATA(addr) ((addr) + 0x04)
64#define AX_INDXC 0x30
65#define AX_DATAC 0x34
66
67#define NB_PCIE_INDX_ADDR 0xe0
68#define NB_PCIE_INDX_DATA 0xe4
69#define PCIE_P_CNTL 0x10040
70#define BIF_NB 0x10002
71#define NB_PIF0_PWRDOWN_0 0x01100012
72#define NB_PIF0_PWRDOWN_1 0x01100013
73
74#define USB_INTEL_XUSB2PR 0xD0
75#define USB_INTEL_USB3_PSSEN 0xD8
76
77static struct amd_chipset_info {
78 struct pci_dev *nb_dev;
79 struct pci_dev *smbus_dev;
80 int nb_type;
81 int sb_type;
82 int isoc_reqs;
83 int probe_count;
84 int probe_result;
85} amd_chipset;
86
87static DEFINE_SPINLOCK(amd_lock);
88
89int usb_amd_find_chipset_info(void)
90{
91 u8 rev = 0;
92 unsigned long flags;
93 struct amd_chipset_info info;
94 int ret;
95
96 spin_lock_irqsave(&amd_lock, flags);
97
98 /* probe only once */
99 if (amd_chipset.probe_count > 0) {
100 amd_chipset.probe_count++;
101 spin_unlock_irqrestore(&amd_lock, flags);
102 return amd_chipset.probe_result;
103 }
104 memset(&info, 0, sizeof(info));
105 spin_unlock_irqrestore(&amd_lock, flags);
106
107 info.smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 0x4385, NULL);
108 if (info.smbus_dev) {
109 rev = info.smbus_dev->revision;
110 if (rev >= 0x40)
111 info.sb_type = 1;
112 else if (rev >= 0x30 && rev <= 0x3b)
113 info.sb_type = 3;
114 } else {
115 info.smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
116 0x780b, NULL);
117 if (!info.smbus_dev) {
118 ret = 0;
119 goto commit;
120 }
121
122 rev = info.smbus_dev->revision;
123 if (rev >= 0x11 && rev <= 0x18)
124 info.sb_type = 2;
125 }
126
127 if (info.sb_type == 0) {
128 if (info.smbus_dev) {
129 pci_dev_put(info.smbus_dev);
130 info.smbus_dev = NULL;
131 }
132 ret = 0;
133 goto commit;
134 }
135
136 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL);
137 if (info.nb_dev) {
138 info.nb_type = 1;
139 } else {
140 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL);
141 if (info.nb_dev) {
142 info.nb_type = 2;
143 } else {
144 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
145 0x9600, NULL);
146 if (info.nb_dev)
147 info.nb_type = 3;
148 }
149 }
150
151 ret = info.probe_result = 1;
152 printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n");
153
154commit:
155
156 spin_lock_irqsave(&amd_lock, flags);
157 if (amd_chipset.probe_count > 0) {
158 /* race - someone else was faster - drop devices */
159
160 /* Mark that we where here */
161 amd_chipset.probe_count++;
162 ret = amd_chipset.probe_result;
163
164 spin_unlock_irqrestore(&amd_lock, flags);
165
166 if (info.nb_dev)
167 pci_dev_put(info.nb_dev);
168 if (info.smbus_dev)
169 pci_dev_put(info.smbus_dev);
170
171 } else {
172 /* no race - commit the result */
173 info.probe_count++;
174 amd_chipset = info;
175 spin_unlock_irqrestore(&amd_lock, flags);
176 }
177
178 return ret;
179}
180EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info);
181
182/*
183 * The hardware normally enables the A-link power management feature, which
184 * lets the system lower the power consumption in idle states.
185 *
186 * This USB quirk prevents the link going into that lower power state
187 * during isochronous transfers.
188 *
189 * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of
190 * some AMD platforms may stutter or have breaks occasionally.
191 */
192static void usb_amd_quirk_pll(int disable)
193{
194 u32 addr, addr_low, addr_high, val;
195 u32 bit = disable ? 0 : 1;
196 unsigned long flags;
197
198 spin_lock_irqsave(&amd_lock, flags);
199
200 if (disable) {
201 amd_chipset.isoc_reqs++;
202 if (amd_chipset.isoc_reqs > 1) {
203 spin_unlock_irqrestore(&amd_lock, flags);
204 return;
205 }
206 } else {
207 amd_chipset.isoc_reqs--;
208 if (amd_chipset.isoc_reqs > 0) {
209 spin_unlock_irqrestore(&amd_lock, flags);
210 return;
211 }
212 }
213
214 if (amd_chipset.sb_type == 1 || amd_chipset.sb_type == 2) {
215 outb_p(AB_REG_BAR_LOW, 0xcd6);
216 addr_low = inb_p(0xcd7);
217 outb_p(AB_REG_BAR_HIGH, 0xcd6);
218 addr_high = inb_p(0xcd7);
219 addr = addr_high << 8 | addr_low;
220
221 outl_p(0x30, AB_INDX(addr));
222 outl_p(0x40, AB_DATA(addr));
223 outl_p(0x34, AB_INDX(addr));
224 val = inl_p(AB_DATA(addr));
225 } else if (amd_chipset.sb_type == 3) {
226 pci_read_config_dword(amd_chipset.smbus_dev,
227 AB_REG_BAR_SB700, &addr);
228 outl(AX_INDXC, AB_INDX(addr));
229 outl(0x40, AB_DATA(addr));
230 outl(AX_DATAC, AB_INDX(addr));
231 val = inl(AB_DATA(addr));
232 } else {
233 spin_unlock_irqrestore(&amd_lock, flags);
234 return;
235 }
236
237 if (disable) {
238 val &= ~0x08;
239 val |= (1 << 4) | (1 << 9);
240 } else {
241 val |= 0x08;
242 val &= ~((1 << 4) | (1 << 9));
243 }
244 outl_p(val, AB_DATA(addr));
245
246 if (!amd_chipset.nb_dev) {
247 spin_unlock_irqrestore(&amd_lock, flags);
248 return;
249 }
250
251 if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) {
252 addr = PCIE_P_CNTL;
253 pci_write_config_dword(amd_chipset.nb_dev,
254 NB_PCIE_INDX_ADDR, addr);
255 pci_read_config_dword(amd_chipset.nb_dev,
256 NB_PCIE_INDX_DATA, &val);
257
258 val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
259 val |= bit | (bit << 3) | (bit << 12);
260 val |= ((!bit) << 4) | ((!bit) << 9);
261 pci_write_config_dword(amd_chipset.nb_dev,
262 NB_PCIE_INDX_DATA, val);
263
264 addr = BIF_NB;
265 pci_write_config_dword(amd_chipset.nb_dev,
266 NB_PCIE_INDX_ADDR, addr);
267 pci_read_config_dword(amd_chipset.nb_dev,
268 NB_PCIE_INDX_DATA, &val);
269 val &= ~(1 << 8);
270 val |= bit << 8;
271
272 pci_write_config_dword(amd_chipset.nb_dev,
273 NB_PCIE_INDX_DATA, val);
274 } else if (amd_chipset.nb_type == 2) {
275 addr = NB_PIF0_PWRDOWN_0;
276 pci_write_config_dword(amd_chipset.nb_dev,
277 NB_PCIE_INDX_ADDR, addr);
278 pci_read_config_dword(amd_chipset.nb_dev,
279 NB_PCIE_INDX_DATA, &val);
280 if (disable)
281 val &= ~(0x3f << 7);
282 else
283 val |= 0x3f << 7;
284
285 pci_write_config_dword(amd_chipset.nb_dev,
286 NB_PCIE_INDX_DATA, val);
287
288 addr = NB_PIF0_PWRDOWN_1;
289 pci_write_config_dword(amd_chipset.nb_dev,
290 NB_PCIE_INDX_ADDR, addr);
291 pci_read_config_dword(amd_chipset.nb_dev,
292 NB_PCIE_INDX_DATA, &val);
293 if (disable)
294 val &= ~(0x3f << 7);
295 else
296 val |= 0x3f << 7;
297
298 pci_write_config_dword(amd_chipset.nb_dev,
299 NB_PCIE_INDX_DATA, val);
300 }
301
302 spin_unlock_irqrestore(&amd_lock, flags);
303 return;
304}
305
306void usb_amd_quirk_pll_disable(void)
307{
308 usb_amd_quirk_pll(1);
309}
310EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable);
311
312void usb_amd_quirk_pll_enable(void)
313{
314 usb_amd_quirk_pll(0);
315}
316EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable);
317
318void usb_amd_dev_put(void)
319{
320 struct pci_dev *nb, *smbus;
321 unsigned long flags;
322
323 spin_lock_irqsave(&amd_lock, flags);
324
325 amd_chipset.probe_count--;
326 if (amd_chipset.probe_count > 0) {
327 spin_unlock_irqrestore(&amd_lock, flags);
328 return;
329 }
330
331 /* save them to pci_dev_put outside of spinlock */
332 nb = amd_chipset.nb_dev;
333 smbus = amd_chipset.smbus_dev;
334
335 amd_chipset.nb_dev = NULL;
336 amd_chipset.smbus_dev = NULL;
337 amd_chipset.nb_type = 0;
338 amd_chipset.sb_type = 0;
339 amd_chipset.isoc_reqs = 0;
340 amd_chipset.probe_result = 0;
341
342 spin_unlock_irqrestore(&amd_lock, flags);
343
344 if (nb)
345 pci_dev_put(nb);
346 if (smbus)
347 pci_dev_put(smbus);
348}
349EXPORT_SYMBOL_GPL(usb_amd_dev_put);
350
351/*
352 * Make sure the controller is completely inactive, unable to
353 * generate interrupts or do DMA.
354 */
355void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
356{
357 /* Turn off PIRQ enable and SMI enable. (This also turns off the
358 * BIOS's USB Legacy Support.) Turn off all the R/WC bits too.
359 */
360 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC);
361
362 /* Reset the HC - this will force us to get a
363 * new notification of any already connected
364 * ports due to the virtual disconnect that it
365 * implies.
366 */
367 outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
368 mb();
369 udelay(5);
370 if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
371 dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
372
373 /* Just to be safe, disable interrupt requests and
374 * make sure the controller is stopped.
375 */
376 outw(0, base + UHCI_USBINTR);
377 outw(0, base + UHCI_USBCMD);
378}
379EXPORT_SYMBOL_GPL(uhci_reset_hc);
380
381/*
382 * Initialize a controller that was newly discovered or has just been
383 * resumed. In either case we can't be sure of its previous state.
384 *
385 * Returns: 1 if the controller was reset, 0 otherwise.
386 */
387int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)
388{
389 u16 legsup;
390 unsigned int cmd, intr;
391
392 /*
393 * When restarting a suspended controller, we expect all the
394 * settings to be the same as we left them:
395 *
396 * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
397 * Controller is stopped and configured with EGSM set;
398 * No interrupts enabled except possibly Resume Detect.
399 *
400 * If any of these conditions are violated we do a complete reset.
401 */
402 pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup);
403 if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) {
404 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n",
405 __func__, legsup);
406 goto reset_needed;
407 }
408
409 cmd = inw(base + UHCI_USBCMD);
410 if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) ||
411 !(cmd & UHCI_USBCMD_EGSM)) {
412 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n",
413 __func__, cmd);
414 goto reset_needed;
415 }
416
417 intr = inw(base + UHCI_USBINTR);
418 if (intr & (~UHCI_USBINTR_RESUME)) {
419 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n",
420 __func__, intr);
421 goto reset_needed;
422 }
423 return 0;
424
425reset_needed:
426 dev_dbg(&pdev->dev, "Performing full reset\n");
427 uhci_reset_hc(pdev, base);
428 return 1;
429}
430EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);
431
432static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
433{
434 u16 cmd;
435 return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask);
436}
437
438#define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
439#define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
440
441static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
442{
443 unsigned long base = 0;
444 int i;
445
446 if (!pio_enabled(pdev))
447 return;
448
449 for (i = 0; i < PCI_ROM_RESOURCE; i++)
450 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
451 base = pci_resource_start(pdev, i);
452 break;
453 }
454
455 if (base)
456 uhci_check_and_reset_hc(pdev, base);
457}
458
459static int __devinit mmio_resource_enabled(struct pci_dev *pdev, int idx)
460{
461 return pci_resource_start(pdev, idx) && mmio_enabled(pdev);
462}
463
464static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
465{
466 void __iomem *base;
467 u32 control;
468
469 if (!mmio_resource_enabled(pdev, 0))
470 return;
471
472 base = pci_ioremap_bar(pdev, 0);
473 if (base == NULL)
474 return;
475
476 control = readl(base + OHCI_CONTROL);
477
478/* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
479#ifdef __hppa__
480#define OHCI_CTRL_MASK (OHCI_CTRL_RWC | OHCI_CTRL_IR)
481#else
482#define OHCI_CTRL_MASK OHCI_CTRL_RWC
483
484 if (control & OHCI_CTRL_IR) {
485 int wait_time = 500; /* arbitrary; 5 seconds */
486 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
487 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
488 while (wait_time > 0 &&
489 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
490 wait_time -= 10;
491 msleep(10);
492 }
493 if (wait_time <= 0)
494 dev_warn(&pdev->dev, "OHCI: BIOS handoff failed"
495 " (BIOS bug?) %08x\n",
496 readl(base + OHCI_CONTROL));
497 }
498#endif
499
500 /* reset controller, preserving RWC (and possibly IR) */
501 writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL);
502 readl(base + OHCI_CONTROL);
503
504 /* Some NVIDIA controllers stop working if kept in RESET for too long */
505 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) {
506 u32 fminterval;
507 int cnt;
508
509 /* drive reset for at least 50 ms (7.1.7.5) */
510 msleep(50);
511
512 /* software reset of the controller, preserving HcFmInterval */
513 fminterval = readl(base + OHCI_FMINTERVAL);
514 writel(OHCI_HCR, base + OHCI_CMDSTATUS);
515
516 /* reset requires max 10 us delay */
517 for (cnt = 30; cnt > 0; --cnt) { /* ... allow extra time */
518 if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0)
519 break;
520 udelay(1);
521 }
522 writel(fminterval, base + OHCI_FMINTERVAL);
523
524 /* Now we're in the SUSPEND state with all devices reset
525 * and wakeups and interrupts disabled
526 */
527 }
528
529 /*
530 * disable interrupts
531 */
532 writel(~(u32)0, base + OHCI_INTRDISABLE);
533 writel(~(u32)0, base + OHCI_INTRSTATUS);
534
535 iounmap(base);
536}
537
538static const struct dmi_system_id __devinitconst ehci_dmi_nohandoff_table[] = {
539 {
540 /* Pegatron Lucid (ExoPC) */
541 .matches = {
542 DMI_MATCH(DMI_BOARD_NAME, "EXOPG06411"),
543 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-CE-133"),
544 },
545 },
546 {
547 /* Pegatron Lucid (Ordissimo AIRIS) */
548 .matches = {
549 DMI_MATCH(DMI_BOARD_NAME, "M11JB"),
550 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-GE-133"),
551 },
552 },
553 { }
554};
555
556static void __devinit ehci_bios_handoff(struct pci_dev *pdev,
557 void __iomem *op_reg_base,
558 u32 cap, u8 offset)
559{
560 int try_handoff = 1, tried_handoff = 0;
561
562 /* The Pegatron Lucid tablet sporadically waits for 98 seconds trying
563 * the handoff on its unused controller. Skip it. */
564 if (pdev->vendor == 0x8086 && pdev->device == 0x283a) {
565 if (dmi_check_system(ehci_dmi_nohandoff_table))
566 try_handoff = 0;
567 }
568
569 if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) {
570 dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
571
572#if 0
573/* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
574 * but that seems dubious in general (the BIOS left it off intentionally)
575 * and is known to prevent some systems from booting. so we won't do this
576 * unless maybe we can determine when we're on a system that needs SMI forced.
577 */
578 /* BIOS workaround (?): be sure the pre-Linux code
579 * receives the SMI
580 */
581 pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val);
582 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS,
583 val | EHCI_USBLEGCTLSTS_SOOE);
584#endif
585
586 /* some systems get upset if this semaphore is
587 * set for any other reason than forcing a BIOS
588 * handoff..
589 */
590 pci_write_config_byte(pdev, offset + 3, 1);
591 }
592
593 /* if boot firmware now owns EHCI, spin till it hands it over. */
594 if (try_handoff) {
595 int msec = 1000;
596 while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
597 tried_handoff = 1;
598 msleep(10);
599 msec -= 10;
600 pci_read_config_dword(pdev, offset, &cap);
601 }
602 }
603
604 if (cap & EHCI_USBLEGSUP_BIOS) {
605 /* well, possibly buggy BIOS... try to shut it down,
606 * and hope nothing goes too wrong
607 */
608 if (try_handoff)
609 dev_warn(&pdev->dev, "EHCI: BIOS handoff failed"
610 " (BIOS bug?) %08x\n", cap);
611 pci_write_config_byte(pdev, offset + 2, 0);
612 }
613
614 /* just in case, always disable EHCI SMIs */
615 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0);
616
617 /* If the BIOS ever owned the controller then we can't expect
618 * any power sessions to remain intact.
619 */
620 if (tried_handoff)
621 writel(0, op_reg_base + EHCI_CONFIGFLAG);
622}
623
624static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
625{
626 void __iomem *base, *op_reg_base;
627 u32 hcc_params, cap, val;
628 u8 offset, cap_length;
629 int wait_time, delta, count = 256/4;
630
631 if (!mmio_resource_enabled(pdev, 0))
632 return;
633
634 base = pci_ioremap_bar(pdev, 0);
635 if (base == NULL)
636 return;
637
638 cap_length = readb(base);
639 op_reg_base = base + cap_length;
640
641 /* EHCI 0.96 and later may have "extended capabilities"
642 * spec section 5.1 explains the bios handoff, e.g. for
643 * booting from USB disk or using a usb keyboard
644 */
645 hcc_params = readl(base + EHCI_HCC_PARAMS);
646 offset = (hcc_params >> 8) & 0xff;
647 while (offset && --count) {
648 pci_read_config_dword(pdev, offset, &cap);
649
650 switch (cap & 0xff) {
651 case 1:
652 ehci_bios_handoff(pdev, op_reg_base, cap, offset);
653 break;
654 case 0: /* Illegal reserved cap, set cap=0 so we exit */
655 cap = 0; /* then fallthrough... */
656 default:
657 dev_warn(&pdev->dev, "EHCI: unrecognized capability "
658 "%02x\n", cap & 0xff);
659 }
660 offset = (cap >> 8) & 0xff;
661 }
662 if (!count)
663 dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n");
664
665 /*
666 * halt EHCI & disable its interrupts in any case
667 */
668 val = readl(op_reg_base + EHCI_USBSTS);
669 if ((val & EHCI_USBSTS_HALTED) == 0) {
670 val = readl(op_reg_base + EHCI_USBCMD);
671 val &= ~EHCI_USBCMD_RUN;
672 writel(val, op_reg_base + EHCI_USBCMD);
673
674 wait_time = 2000;
675 delta = 100;
676 do {
677 writel(0x3f, op_reg_base + EHCI_USBSTS);
678 udelay(delta);
679 wait_time -= delta;
680 val = readl(op_reg_base + EHCI_USBSTS);
681 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
682 break;
683 }
684 } while (wait_time > 0);
685 }
686 writel(0, op_reg_base + EHCI_USBINTR);
687 writel(0x3f, op_reg_base + EHCI_USBSTS);
688
689 iounmap(base);
690}
691
692/*
693 * handshake - spin reading a register until handshake completes
694 * @ptr: address of hc register to be read
695 * @mask: bits to look at in result of read
696 * @done: value of those bits when handshake succeeds
697 * @wait_usec: timeout in microseconds
698 * @delay_usec: delay in microseconds to wait between polling
699 *
700 * Polls a register every delay_usec microseconds.
701 * Returns 0 when the mask bits have the value done.
702 * Returns -ETIMEDOUT if this condition is not true after
703 * wait_usec microseconds have passed.
704 */
705static int handshake(void __iomem *ptr, u32 mask, u32 done,
706 int wait_usec, int delay_usec)
707{
708 u32 result;
709
710 do {
711 result = readl(ptr);
712 result &= mask;
713 if (result == done)
714 return 0;
715 udelay(delay_usec);
716 wait_usec -= delay_usec;
717 } while (wait_usec > 0);
718 return -ETIMEDOUT;
719}
720
721bool usb_is_intel_switchable_xhci(struct pci_dev *pdev)
722{
723 return pdev->class == PCI_CLASS_SERIAL_USB_XHCI &&
724 pdev->vendor == PCI_VENDOR_ID_INTEL &&
725 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI;
726}
727EXPORT_SYMBOL_GPL(usb_is_intel_switchable_xhci);
728
729/*
730 * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that
731 * share some number of ports. These ports can be switched between either
732 * controller. Not all of the ports under the EHCI host controller may be
733 * switchable.
734 *
735 * The ports should be switched over to xHCI before PCI probes for any device
736 * start. This avoids active devices under EHCI being disconnected during the
737 * port switchover, which could cause loss of data on USB storage devices, or
738 * failed boot when the root file system is on a USB mass storage device and is
739 * enumerated under EHCI first.
740 *
741 * We write into the xHC's PCI configuration space in some Intel-specific
742 * registers to switch the ports over. The USB 3.0 terminations and the USB
743 * 2.0 data wires are switched separately. We want to enable the SuperSpeed
744 * terminations before switching the USB 2.0 wires over, so that USB 3.0
745 * devices connect at SuperSpeed, rather than at USB 2.0 speeds.
746 */
747void usb_enable_xhci_ports(struct pci_dev *xhci_pdev)
748{
749 u32 ports_available;
750
751 ports_available = 0xffffffff;
752 /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable
753 * Register, to turn on SuperSpeed terminations for all
754 * available ports.
755 */
756 pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
757 cpu_to_le32(ports_available));
758
759 pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
760 &ports_available);
761 dev_dbg(&xhci_pdev->dev, "USB 3.0 ports that are now enabled "
762 "under xHCI: 0x%x\n", ports_available);
763
764 ports_available = 0xffffffff;
765 /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to
766 * switch the USB 2.0 power and data lines over to the xHCI
767 * host.
768 */
769 pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
770 cpu_to_le32(ports_available));
771
772 pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
773 &ports_available);
774 dev_dbg(&xhci_pdev->dev, "USB 2.0 ports that are now switched over "
775 "to xHCI: 0x%x\n", ports_available);
776}
777EXPORT_SYMBOL_GPL(usb_enable_xhci_ports);
778
779/**
780 * PCI Quirks for xHCI.
781 *
782 * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS.
783 * It signals to the BIOS that the OS wants control of the host controller,
784 * and then waits 5 seconds for the BIOS to hand over control.
785 * If we timeout, assume the BIOS is broken and take control anyway.
786 */
787static void __devinit quirk_usb_handoff_xhci(struct pci_dev *pdev)
788{
789 void __iomem *base;
790 int ext_cap_offset;
791 void __iomem *op_reg_base;
792 u32 val;
793 int timeout;
794
795 if (!mmio_resource_enabled(pdev, 0))
796 return;
797
798 base = ioremap_nocache(pci_resource_start(pdev, 0),
799 pci_resource_len(pdev, 0));
800 if (base == NULL)
801 return;
802
803 /*
804 * Find the Legacy Support Capability register -
805 * this is optional for xHCI host controllers.
806 */
807 ext_cap_offset = xhci_find_next_cap_offset(base, XHCI_HCC_PARAMS_OFFSET);
808 do {
809 if (!ext_cap_offset)
810 /* We've reached the end of the extended capabilities */
811 goto hc_init;
812 val = readl(base + ext_cap_offset);
813 if (XHCI_EXT_CAPS_ID(val) == XHCI_EXT_CAPS_LEGACY)
814 break;
815 ext_cap_offset = xhci_find_next_cap_offset(base, ext_cap_offset);
816 } while (1);
817
818 /* If the BIOS owns the HC, signal that the OS wants it, and wait */
819 if (val & XHCI_HC_BIOS_OWNED) {
820 writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset);
821
822 /* Wait for 5 seconds with 10 microsecond polling interval */
823 timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED,
824 0, 5000, 10);
825
826 /* Assume a buggy BIOS and take HC ownership anyway */
827 if (timeout) {
828 dev_warn(&pdev->dev, "xHCI BIOS handoff failed"
829 " (BIOS bug ?) %08x\n", val);
830 writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset);
831 }
832 }
833
834 /* Disable any BIOS SMIs */
835 writel(XHCI_LEGACY_DISABLE_SMI,
836 base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
837
838 if (usb_is_intel_switchable_xhci(pdev))
839 usb_enable_xhci_ports(pdev);
840hc_init:
841 op_reg_base = base + XHCI_HC_LENGTH(readl(base));
842
843 /* Wait for the host controller to be ready before writing any
844 * operational or runtime registers. Wait 5 seconds and no more.
845 */
846 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0,
847 5000, 10);
848 /* Assume a buggy HC and start HC initialization anyway */
849 if (timeout) {
850 val = readl(op_reg_base + XHCI_STS_OFFSET);
851 dev_warn(&pdev->dev,
852 "xHCI HW not ready after 5 sec (HC bug?) "
853 "status = 0x%x\n", val);
854 }
855
856 /* Send the halt and disable interrupts command */
857 val = readl(op_reg_base + XHCI_CMD_OFFSET);
858 val &= ~(XHCI_CMD_RUN | XHCI_IRQS);
859 writel(val, op_reg_base + XHCI_CMD_OFFSET);
860
861 /* Wait for the HC to halt - poll every 125 usec (one microframe). */
862 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1,
863 XHCI_MAX_HALT_USEC, 125);
864 if (timeout) {
865 val = readl(op_reg_base + XHCI_STS_OFFSET);
866 dev_warn(&pdev->dev,
867 "xHCI HW did not halt within %d usec "
868 "status = 0x%x\n", XHCI_MAX_HALT_USEC, val);
869 }
870
871 iounmap(base);
872}
873
874static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
875{
876 if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI)
877 quirk_usb_handoff_uhci(pdev);
878 else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI)
879 quirk_usb_handoff_ohci(pdev);
880 else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI)
881 quirk_usb_disable_ehci(pdev);
882 else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI)
883 quirk_usb_handoff_xhci(pdev);
884}
885DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * This file contains code to reset and initialize USB host controllers.
4 * Some of it includes work-arounds for PCI hardware and BIOS quirks.
5 * It may need to run early during booting -- before USB would normally
6 * initialize -- to ensure that Linux doesn't use any legacy modes.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 * (and others)
10 */
11
12#include <linux/types.h>
13#include <linux/kernel.h>
14#include <linux/pci.h>
15#include <linux/delay.h>
16#include <linux/export.h>
17#include <linux/acpi.h>
18#include <linux/dmi.h>
19
20#include <soc/bcm2835/raspberrypi-firmware.h>
21
22#include "pci-quirks.h"
23#include "xhci-ext-caps.h"
24
25
26#define UHCI_USBLEGSUP 0xc0 /* legacy support */
27#define UHCI_USBCMD 0 /* command register */
28#define UHCI_USBINTR 4 /* interrupt register */
29#define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
30#define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
31#define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */
32#define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */
33#define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */
34#define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */
35#define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */
36
37#define OHCI_CONTROL 0x04
38#define OHCI_CMDSTATUS 0x08
39#define OHCI_INTRSTATUS 0x0c
40#define OHCI_INTRENABLE 0x10
41#define OHCI_INTRDISABLE 0x14
42#define OHCI_FMINTERVAL 0x34
43#define OHCI_HCFS (3 << 6) /* hc functional state */
44#define OHCI_HCR (1 << 0) /* host controller reset */
45#define OHCI_OCR (1 << 3) /* ownership change request */
46#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
47#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
48#define OHCI_INTR_OC (1 << 30) /* ownership change */
49
50#define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
51#define EHCI_USBCMD 0 /* command register */
52#define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
53#define EHCI_USBSTS 4 /* status register */
54#define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
55#define EHCI_USBINTR 8 /* interrupt register */
56#define EHCI_CONFIGFLAG 0x40 /* configured flag register */
57#define EHCI_USBLEGSUP 0 /* legacy support register */
58#define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
59#define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
60#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
61#define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
62
63/* AMD quirk use */
64#define AB_REG_BAR_LOW 0xe0
65#define AB_REG_BAR_HIGH 0xe1
66#define AB_REG_BAR_SB700 0xf0
67#define AB_INDX(addr) ((addr) + 0x00)
68#define AB_DATA(addr) ((addr) + 0x04)
69#define AX_INDXC 0x30
70#define AX_DATAC 0x34
71
72#define PT_ADDR_INDX 0xE8
73#define PT_READ_INDX 0xE4
74#define PT_SIG_1_ADDR 0xA520
75#define PT_SIG_2_ADDR 0xA521
76#define PT_SIG_3_ADDR 0xA522
77#define PT_SIG_4_ADDR 0xA523
78#define PT_SIG_1_DATA 0x78
79#define PT_SIG_2_DATA 0x56
80#define PT_SIG_3_DATA 0x34
81#define PT_SIG_4_DATA 0x12
82#define PT4_P1_REG 0xB521
83#define PT4_P2_REG 0xB522
84#define PT2_P1_REG 0xD520
85#define PT2_P2_REG 0xD521
86#define PT1_P1_REG 0xD522
87#define PT1_P2_REG 0xD523
88
89#define NB_PCIE_INDX_ADDR 0xe0
90#define NB_PCIE_INDX_DATA 0xe4
91#define PCIE_P_CNTL 0x10040
92#define BIF_NB 0x10002
93#define NB_PIF0_PWRDOWN_0 0x01100012
94#define NB_PIF0_PWRDOWN_1 0x01100013
95
96#define USB_INTEL_XUSB2PR 0xD0
97#define USB_INTEL_USB2PRM 0xD4
98#define USB_INTEL_USB3_PSSEN 0xD8
99#define USB_INTEL_USB3PRM 0xDC
100
101/* ASMEDIA quirk use */
102#define ASMT_DATA_WRITE0_REG 0xF8
103#define ASMT_DATA_WRITE1_REG 0xFC
104#define ASMT_CONTROL_REG 0xE0
105#define ASMT_CONTROL_WRITE_BIT 0x02
106#define ASMT_WRITEREG_CMD 0x10423
107#define ASMT_FLOWCTL_ADDR 0xFA30
108#define ASMT_FLOWCTL_DATA 0xBA
109#define ASMT_PSEUDO_DATA 0
110
111/*
112 * amd_chipset_gen values represent AMD different chipset generations
113 */
114enum amd_chipset_gen {
115 NOT_AMD_CHIPSET = 0,
116 AMD_CHIPSET_SB600,
117 AMD_CHIPSET_SB700,
118 AMD_CHIPSET_SB800,
119 AMD_CHIPSET_HUDSON2,
120 AMD_CHIPSET_BOLTON,
121 AMD_CHIPSET_YANGTZE,
122 AMD_CHIPSET_TAISHAN,
123 AMD_CHIPSET_UNKNOWN,
124};
125
126struct amd_chipset_type {
127 enum amd_chipset_gen gen;
128 u8 rev;
129};
130
131static struct amd_chipset_info {
132 struct pci_dev *nb_dev;
133 struct pci_dev *smbus_dev;
134 int nb_type;
135 struct amd_chipset_type sb_type;
136 int isoc_reqs;
137 int probe_count;
138 bool need_pll_quirk;
139} amd_chipset;
140
141static DEFINE_SPINLOCK(amd_lock);
142
143/*
144 * amd_chipset_sb_type_init - initialize amd chipset southbridge type
145 *
146 * AMD FCH/SB generation and revision is identified by SMBus controller
147 * vendor, device and revision IDs.
148 *
149 * Returns: 1 if it is an AMD chipset, 0 otherwise.
150 */
151static int amd_chipset_sb_type_init(struct amd_chipset_info *pinfo)
152{
153 u8 rev = 0;
154 pinfo->sb_type.gen = AMD_CHIPSET_UNKNOWN;
155
156 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI,
157 PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL);
158 if (pinfo->smbus_dev) {
159 rev = pinfo->smbus_dev->revision;
160 if (rev >= 0x10 && rev <= 0x1f)
161 pinfo->sb_type.gen = AMD_CHIPSET_SB600;
162 else if (rev >= 0x30 && rev <= 0x3f)
163 pinfo->sb_type.gen = AMD_CHIPSET_SB700;
164 else if (rev >= 0x40 && rev <= 0x4f)
165 pinfo->sb_type.gen = AMD_CHIPSET_SB800;
166 } else {
167 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
168 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
169
170 if (pinfo->smbus_dev) {
171 rev = pinfo->smbus_dev->revision;
172 if (rev >= 0x11 && rev <= 0x14)
173 pinfo->sb_type.gen = AMD_CHIPSET_HUDSON2;
174 else if (rev >= 0x15 && rev <= 0x18)
175 pinfo->sb_type.gen = AMD_CHIPSET_BOLTON;
176 else if (rev >= 0x39 && rev <= 0x3a)
177 pinfo->sb_type.gen = AMD_CHIPSET_YANGTZE;
178 } else {
179 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
180 0x145c, NULL);
181 if (pinfo->smbus_dev) {
182 rev = pinfo->smbus_dev->revision;
183 pinfo->sb_type.gen = AMD_CHIPSET_TAISHAN;
184 } else {
185 pinfo->sb_type.gen = NOT_AMD_CHIPSET;
186 return 0;
187 }
188 }
189 }
190 pinfo->sb_type.rev = rev;
191 return 1;
192}
193
194void sb800_prefetch(struct device *dev, int on)
195{
196 u16 misc;
197 struct pci_dev *pdev = to_pci_dev(dev);
198
199 pci_read_config_word(pdev, 0x50, &misc);
200 if (on == 0)
201 pci_write_config_word(pdev, 0x50, misc & 0xfcff);
202 else
203 pci_write_config_word(pdev, 0x50, misc | 0x0300);
204}
205EXPORT_SYMBOL_GPL(sb800_prefetch);
206
207static void usb_amd_find_chipset_info(void)
208{
209 unsigned long flags;
210 struct amd_chipset_info info;
211 info.need_pll_quirk = false;
212
213 spin_lock_irqsave(&amd_lock, flags);
214
215 /* probe only once */
216 if (amd_chipset.probe_count > 0) {
217 amd_chipset.probe_count++;
218 spin_unlock_irqrestore(&amd_lock, flags);
219 return;
220 }
221 memset(&info, 0, sizeof(info));
222 spin_unlock_irqrestore(&amd_lock, flags);
223
224 if (!amd_chipset_sb_type_init(&info)) {
225 goto commit;
226 }
227
228 switch (info.sb_type.gen) {
229 case AMD_CHIPSET_SB700:
230 info.need_pll_quirk = info.sb_type.rev <= 0x3B;
231 break;
232 case AMD_CHIPSET_SB800:
233 case AMD_CHIPSET_HUDSON2:
234 case AMD_CHIPSET_BOLTON:
235 info.need_pll_quirk = true;
236 break;
237 default:
238 info.need_pll_quirk = false;
239 break;
240 }
241
242 if (!info.need_pll_quirk) {
243 if (info.smbus_dev) {
244 pci_dev_put(info.smbus_dev);
245 info.smbus_dev = NULL;
246 }
247 goto commit;
248 }
249
250 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL);
251 if (info.nb_dev) {
252 info.nb_type = 1;
253 } else {
254 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL);
255 if (info.nb_dev) {
256 info.nb_type = 2;
257 } else {
258 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
259 0x9600, NULL);
260 if (info.nb_dev)
261 info.nb_type = 3;
262 }
263 }
264
265 printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n");
266
267commit:
268
269 spin_lock_irqsave(&amd_lock, flags);
270 if (amd_chipset.probe_count > 0) {
271 /* race - someone else was faster - drop devices */
272
273 /* Mark that we where here */
274 amd_chipset.probe_count++;
275
276 spin_unlock_irqrestore(&amd_lock, flags);
277
278 pci_dev_put(info.nb_dev);
279 pci_dev_put(info.smbus_dev);
280
281 } else {
282 /* no race - commit the result */
283 info.probe_count++;
284 amd_chipset = info;
285 spin_unlock_irqrestore(&amd_lock, flags);
286 }
287}
288
289int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev)
290{
291 /* Make sure amd chipset type has already been initialized */
292 usb_amd_find_chipset_info();
293 if (amd_chipset.sb_type.gen == AMD_CHIPSET_YANGTZE ||
294 amd_chipset.sb_type.gen == AMD_CHIPSET_TAISHAN) {
295 dev_dbg(&pdev->dev, "QUIRK: Enable AMD remote wakeup fix\n");
296 return 1;
297 }
298 return 0;
299}
300EXPORT_SYMBOL_GPL(usb_hcd_amd_remote_wakeup_quirk);
301
302bool usb_amd_hang_symptom_quirk(void)
303{
304 u8 rev;
305
306 usb_amd_find_chipset_info();
307 rev = amd_chipset.sb_type.rev;
308 /* SB600 and old version of SB700 have hang symptom bug */
309 return amd_chipset.sb_type.gen == AMD_CHIPSET_SB600 ||
310 (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 &&
311 rev >= 0x3a && rev <= 0x3b);
312}
313EXPORT_SYMBOL_GPL(usb_amd_hang_symptom_quirk);
314
315bool usb_amd_prefetch_quirk(void)
316{
317 usb_amd_find_chipset_info();
318 /* SB800 needs pre-fetch fix */
319 return amd_chipset.sb_type.gen == AMD_CHIPSET_SB800;
320}
321EXPORT_SYMBOL_GPL(usb_amd_prefetch_quirk);
322
323bool usb_amd_quirk_pll_check(void)
324{
325 usb_amd_find_chipset_info();
326 return amd_chipset.need_pll_quirk;
327}
328EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_check);
329
330/*
331 * The hardware normally enables the A-link power management feature, which
332 * lets the system lower the power consumption in idle states.
333 *
334 * This USB quirk prevents the link going into that lower power state
335 * during isochronous transfers.
336 *
337 * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of
338 * some AMD platforms may stutter or have breaks occasionally.
339 */
340static void usb_amd_quirk_pll(int disable)
341{
342 u32 addr, addr_low, addr_high, val;
343 u32 bit = disable ? 0 : 1;
344 unsigned long flags;
345
346 spin_lock_irqsave(&amd_lock, flags);
347
348 if (disable) {
349 amd_chipset.isoc_reqs++;
350 if (amd_chipset.isoc_reqs > 1) {
351 spin_unlock_irqrestore(&amd_lock, flags);
352 return;
353 }
354 } else {
355 amd_chipset.isoc_reqs--;
356 if (amd_chipset.isoc_reqs > 0) {
357 spin_unlock_irqrestore(&amd_lock, flags);
358 return;
359 }
360 }
361
362 if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB800 ||
363 amd_chipset.sb_type.gen == AMD_CHIPSET_HUDSON2 ||
364 amd_chipset.sb_type.gen == AMD_CHIPSET_BOLTON) {
365 outb_p(AB_REG_BAR_LOW, 0xcd6);
366 addr_low = inb_p(0xcd7);
367 outb_p(AB_REG_BAR_HIGH, 0xcd6);
368 addr_high = inb_p(0xcd7);
369 addr = addr_high << 8 | addr_low;
370
371 outl_p(0x30, AB_INDX(addr));
372 outl_p(0x40, AB_DATA(addr));
373 outl_p(0x34, AB_INDX(addr));
374 val = inl_p(AB_DATA(addr));
375 } else if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 &&
376 amd_chipset.sb_type.rev <= 0x3b) {
377 pci_read_config_dword(amd_chipset.smbus_dev,
378 AB_REG_BAR_SB700, &addr);
379 outl(AX_INDXC, AB_INDX(addr));
380 outl(0x40, AB_DATA(addr));
381 outl(AX_DATAC, AB_INDX(addr));
382 val = inl(AB_DATA(addr));
383 } else {
384 spin_unlock_irqrestore(&amd_lock, flags);
385 return;
386 }
387
388 if (disable) {
389 val &= ~0x08;
390 val |= (1 << 4) | (1 << 9);
391 } else {
392 val |= 0x08;
393 val &= ~((1 << 4) | (1 << 9));
394 }
395 outl_p(val, AB_DATA(addr));
396
397 if (!amd_chipset.nb_dev) {
398 spin_unlock_irqrestore(&amd_lock, flags);
399 return;
400 }
401
402 if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) {
403 addr = PCIE_P_CNTL;
404 pci_write_config_dword(amd_chipset.nb_dev,
405 NB_PCIE_INDX_ADDR, addr);
406 pci_read_config_dword(amd_chipset.nb_dev,
407 NB_PCIE_INDX_DATA, &val);
408
409 val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
410 val |= bit | (bit << 3) | (bit << 12);
411 val |= ((!bit) << 4) | ((!bit) << 9);
412 pci_write_config_dword(amd_chipset.nb_dev,
413 NB_PCIE_INDX_DATA, val);
414
415 addr = BIF_NB;
416 pci_write_config_dword(amd_chipset.nb_dev,
417 NB_PCIE_INDX_ADDR, addr);
418 pci_read_config_dword(amd_chipset.nb_dev,
419 NB_PCIE_INDX_DATA, &val);
420 val &= ~(1 << 8);
421 val |= bit << 8;
422
423 pci_write_config_dword(amd_chipset.nb_dev,
424 NB_PCIE_INDX_DATA, val);
425 } else if (amd_chipset.nb_type == 2) {
426 addr = NB_PIF0_PWRDOWN_0;
427 pci_write_config_dword(amd_chipset.nb_dev,
428 NB_PCIE_INDX_ADDR, addr);
429 pci_read_config_dword(amd_chipset.nb_dev,
430 NB_PCIE_INDX_DATA, &val);
431 if (disable)
432 val &= ~(0x3f << 7);
433 else
434 val |= 0x3f << 7;
435
436 pci_write_config_dword(amd_chipset.nb_dev,
437 NB_PCIE_INDX_DATA, val);
438
439 addr = NB_PIF0_PWRDOWN_1;
440 pci_write_config_dword(amd_chipset.nb_dev,
441 NB_PCIE_INDX_ADDR, addr);
442 pci_read_config_dword(amd_chipset.nb_dev,
443 NB_PCIE_INDX_DATA, &val);
444 if (disable)
445 val &= ~(0x3f << 7);
446 else
447 val |= 0x3f << 7;
448
449 pci_write_config_dword(amd_chipset.nb_dev,
450 NB_PCIE_INDX_DATA, val);
451 }
452
453 spin_unlock_irqrestore(&amd_lock, flags);
454 return;
455}
456
457void usb_amd_quirk_pll_disable(void)
458{
459 usb_amd_quirk_pll(1);
460}
461EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable);
462
463static int usb_asmedia_wait_write(struct pci_dev *pdev)
464{
465 unsigned long retry_count;
466 unsigned char value;
467
468 for (retry_count = 1000; retry_count > 0; --retry_count) {
469
470 pci_read_config_byte(pdev, ASMT_CONTROL_REG, &value);
471
472 if (value == 0xff) {
473 dev_err(&pdev->dev, "%s: check_ready ERROR", __func__);
474 return -EIO;
475 }
476
477 if ((value & ASMT_CONTROL_WRITE_BIT) == 0)
478 return 0;
479
480 udelay(50);
481 }
482
483 dev_warn(&pdev->dev, "%s: check_write_ready timeout", __func__);
484 return -ETIMEDOUT;
485}
486
487void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev)
488{
489 if (usb_asmedia_wait_write(pdev) != 0)
490 return;
491
492 /* send command and address to device */
493 pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_WRITEREG_CMD);
494 pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_FLOWCTL_ADDR);
495 pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT);
496
497 if (usb_asmedia_wait_write(pdev) != 0)
498 return;
499
500 /* send data to device */
501 pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_FLOWCTL_DATA);
502 pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_PSEUDO_DATA);
503 pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT);
504}
505EXPORT_SYMBOL_GPL(usb_asmedia_modifyflowcontrol);
506
507void usb_amd_quirk_pll_enable(void)
508{
509 usb_amd_quirk_pll(0);
510}
511EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable);
512
513void usb_amd_dev_put(void)
514{
515 struct pci_dev *nb, *smbus;
516 unsigned long flags;
517
518 spin_lock_irqsave(&amd_lock, flags);
519
520 amd_chipset.probe_count--;
521 if (amd_chipset.probe_count > 0) {
522 spin_unlock_irqrestore(&amd_lock, flags);
523 return;
524 }
525
526 /* save them to pci_dev_put outside of spinlock */
527 nb = amd_chipset.nb_dev;
528 smbus = amd_chipset.smbus_dev;
529
530 amd_chipset.nb_dev = NULL;
531 amd_chipset.smbus_dev = NULL;
532 amd_chipset.nb_type = 0;
533 memset(&amd_chipset.sb_type, 0, sizeof(amd_chipset.sb_type));
534 amd_chipset.isoc_reqs = 0;
535 amd_chipset.need_pll_quirk = false;
536
537 spin_unlock_irqrestore(&amd_lock, flags);
538
539 pci_dev_put(nb);
540 pci_dev_put(smbus);
541}
542EXPORT_SYMBOL_GPL(usb_amd_dev_put);
543
544/*
545 * Check if port is disabled in BIOS on AMD Promontory host.
546 * BIOS Disabled ports may wake on connect/disconnect and need
547 * driver workaround to keep them disabled.
548 * Returns true if port is marked disabled.
549 */
550bool usb_amd_pt_check_port(struct device *device, int port)
551{
552 unsigned char value, port_shift;
553 struct pci_dev *pdev;
554 u16 reg;
555
556 pdev = to_pci_dev(device);
557 pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_1_ADDR);
558
559 pci_read_config_byte(pdev, PT_READ_INDX, &value);
560 if (value != PT_SIG_1_DATA)
561 return false;
562
563 pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_2_ADDR);
564
565 pci_read_config_byte(pdev, PT_READ_INDX, &value);
566 if (value != PT_SIG_2_DATA)
567 return false;
568
569 pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_3_ADDR);
570
571 pci_read_config_byte(pdev, PT_READ_INDX, &value);
572 if (value != PT_SIG_3_DATA)
573 return false;
574
575 pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_4_ADDR);
576
577 pci_read_config_byte(pdev, PT_READ_INDX, &value);
578 if (value != PT_SIG_4_DATA)
579 return false;
580
581 /* Check disabled port setting, if bit is set port is enabled */
582 switch (pdev->device) {
583 case 0x43b9:
584 case 0x43ba:
585 /*
586 * device is AMD_PROMONTORYA_4(0x43b9) or PROMONTORYA_3(0x43ba)
587 * PT4_P1_REG bits[7..1] represents USB2.0 ports 6 to 0
588 * PT4_P2_REG bits[6..0] represents ports 13 to 7
589 */
590 if (port > 6) {
591 reg = PT4_P2_REG;
592 port_shift = port - 7;
593 } else {
594 reg = PT4_P1_REG;
595 port_shift = port + 1;
596 }
597 break;
598 case 0x43bb:
599 /*
600 * device is AMD_PROMONTORYA_2(0x43bb)
601 * PT2_P1_REG bits[7..5] represents USB2.0 ports 2 to 0
602 * PT2_P2_REG bits[5..0] represents ports 9 to 3
603 */
604 if (port > 2) {
605 reg = PT2_P2_REG;
606 port_shift = port - 3;
607 } else {
608 reg = PT2_P1_REG;
609 port_shift = port + 5;
610 }
611 break;
612 case 0x43bc:
613 /*
614 * device is AMD_PROMONTORYA_1(0x43bc)
615 * PT1_P1_REG[7..4] represents USB2.0 ports 3 to 0
616 * PT1_P2_REG[5..0] represents ports 9 to 4
617 */
618 if (port > 3) {
619 reg = PT1_P2_REG;
620 port_shift = port - 4;
621 } else {
622 reg = PT1_P1_REG;
623 port_shift = port + 4;
624 }
625 break;
626 default:
627 return false;
628 }
629 pci_write_config_word(pdev, PT_ADDR_INDX, reg);
630 pci_read_config_byte(pdev, PT_READ_INDX, &value);
631
632 return !(value & BIT(port_shift));
633}
634EXPORT_SYMBOL_GPL(usb_amd_pt_check_port);
635
636/*
637 * Make sure the controller is completely inactive, unable to
638 * generate interrupts or do DMA.
639 */
640void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
641{
642 /* Turn off PIRQ enable and SMI enable. (This also turns off the
643 * BIOS's USB Legacy Support.) Turn off all the R/WC bits too.
644 */
645 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC);
646
647 /* Reset the HC - this will force us to get a
648 * new notification of any already connected
649 * ports due to the virtual disconnect that it
650 * implies.
651 */
652 outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
653 mb();
654 udelay(5);
655 if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
656 dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
657
658 /* Just to be safe, disable interrupt requests and
659 * make sure the controller is stopped.
660 */
661 outw(0, base + UHCI_USBINTR);
662 outw(0, base + UHCI_USBCMD);
663}
664EXPORT_SYMBOL_GPL(uhci_reset_hc);
665
666/*
667 * Initialize a controller that was newly discovered or has just been
668 * resumed. In either case we can't be sure of its previous state.
669 *
670 * Returns: 1 if the controller was reset, 0 otherwise.
671 */
672int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)
673{
674 u16 legsup;
675 unsigned int cmd, intr;
676
677 /*
678 * When restarting a suspended controller, we expect all the
679 * settings to be the same as we left them:
680 *
681 * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
682 * Controller is stopped and configured with EGSM set;
683 * No interrupts enabled except possibly Resume Detect.
684 *
685 * If any of these conditions are violated we do a complete reset.
686 */
687 pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup);
688 if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) {
689 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n",
690 __func__, legsup);
691 goto reset_needed;
692 }
693
694 cmd = inw(base + UHCI_USBCMD);
695 if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) ||
696 !(cmd & UHCI_USBCMD_EGSM)) {
697 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n",
698 __func__, cmd);
699 goto reset_needed;
700 }
701
702 intr = inw(base + UHCI_USBINTR);
703 if (intr & (~UHCI_USBINTR_RESUME)) {
704 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n",
705 __func__, intr);
706 goto reset_needed;
707 }
708 return 0;
709
710reset_needed:
711 dev_dbg(&pdev->dev, "Performing full reset\n");
712 uhci_reset_hc(pdev, base);
713 return 1;
714}
715EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);
716
717static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
718{
719 u16 cmd;
720 return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask);
721}
722
723#define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
724#define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
725
726static void quirk_usb_handoff_uhci(struct pci_dev *pdev)
727{
728 unsigned long base = 0;
729 int i;
730
731 if (!pio_enabled(pdev))
732 return;
733
734 for (i = 0; i < PCI_STD_NUM_BARS; i++)
735 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
736 base = pci_resource_start(pdev, i);
737 break;
738 }
739
740 if (base)
741 uhci_check_and_reset_hc(pdev, base);
742}
743
744static int mmio_resource_enabled(struct pci_dev *pdev, int idx)
745{
746 return pci_resource_start(pdev, idx) && mmio_enabled(pdev);
747}
748
749static void quirk_usb_handoff_ohci(struct pci_dev *pdev)
750{
751 void __iomem *base;
752 u32 control;
753 u32 fminterval = 0;
754 bool no_fminterval = false;
755 int cnt;
756
757 if (!mmio_resource_enabled(pdev, 0))
758 return;
759
760 base = pci_ioremap_bar(pdev, 0);
761 if (base == NULL)
762 return;
763
764 /*
765 * ULi M5237 OHCI controller locks the whole system when accessing
766 * the OHCI_FMINTERVAL offset.
767 */
768 if (pdev->vendor == PCI_VENDOR_ID_AL && pdev->device == 0x5237)
769 no_fminterval = true;
770
771 control = readl(base + OHCI_CONTROL);
772
773/* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
774#ifdef __hppa__
775#define OHCI_CTRL_MASK (OHCI_CTRL_RWC | OHCI_CTRL_IR)
776#else
777#define OHCI_CTRL_MASK OHCI_CTRL_RWC
778
779 if (control & OHCI_CTRL_IR) {
780 int wait_time = 500; /* arbitrary; 5 seconds */
781 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
782 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
783 while (wait_time > 0 &&
784 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
785 wait_time -= 10;
786 msleep(10);
787 }
788 if (wait_time <= 0)
789 dev_warn(&pdev->dev,
790 "OHCI: BIOS handoff failed (BIOS bug?) %08x\n",
791 readl(base + OHCI_CONTROL));
792 }
793#endif
794
795 /* disable interrupts */
796 writel((u32) ~0, base + OHCI_INTRDISABLE);
797
798 /* Go into the USB_RESET state, preserving RWC (and possibly IR) */
799 writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL);
800 readl(base + OHCI_CONTROL);
801
802 /* software reset of the controller, preserving HcFmInterval */
803 if (!no_fminterval)
804 fminterval = readl(base + OHCI_FMINTERVAL);
805
806 writel(OHCI_HCR, base + OHCI_CMDSTATUS);
807
808 /* reset requires max 10 us delay */
809 for (cnt = 30; cnt > 0; --cnt) { /* ... allow extra time */
810 if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0)
811 break;
812 udelay(1);
813 }
814
815 if (!no_fminterval)
816 writel(fminterval, base + OHCI_FMINTERVAL);
817
818 /* Now the controller is safely in SUSPEND and nothing can wake it up */
819 iounmap(base);
820}
821
822static const struct dmi_system_id ehci_dmi_nohandoff_table[] = {
823 {
824 /* Pegatron Lucid (ExoPC) */
825 .matches = {
826 DMI_MATCH(DMI_BOARD_NAME, "EXOPG06411"),
827 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-CE-133"),
828 },
829 },
830 {
831 /* Pegatron Lucid (Ordissimo AIRIS) */
832 .matches = {
833 DMI_MATCH(DMI_BOARD_NAME, "M11JB"),
834 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"),
835 },
836 },
837 {
838 /* Pegatron Lucid (Ordissimo) */
839 .matches = {
840 DMI_MATCH(DMI_BOARD_NAME, "Ordissimo"),
841 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"),
842 },
843 },
844 {
845 /* HASEE E200 */
846 .matches = {
847 DMI_MATCH(DMI_BOARD_VENDOR, "HASEE"),
848 DMI_MATCH(DMI_BOARD_NAME, "E210"),
849 DMI_MATCH(DMI_BIOS_VERSION, "6.00"),
850 },
851 },
852 { }
853};
854
855static void ehci_bios_handoff(struct pci_dev *pdev,
856 void __iomem *op_reg_base,
857 u32 cap, u8 offset)
858{
859 int try_handoff = 1, tried_handoff = 0;
860
861 /*
862 * The Pegatron Lucid tablet sporadically waits for 98 seconds trying
863 * the handoff on its unused controller. Skip it.
864 *
865 * The HASEE E200 hangs when the semaphore is set (bugzilla #77021).
866 */
867 if (pdev->vendor == 0x8086 && (pdev->device == 0x283a ||
868 pdev->device == 0x27cc)) {
869 if (dmi_check_system(ehci_dmi_nohandoff_table))
870 try_handoff = 0;
871 }
872
873 if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) {
874 dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
875
876#if 0
877/* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
878 * but that seems dubious in general (the BIOS left it off intentionally)
879 * and is known to prevent some systems from booting. so we won't do this
880 * unless maybe we can determine when we're on a system that needs SMI forced.
881 */
882 /* BIOS workaround (?): be sure the pre-Linux code
883 * receives the SMI
884 */
885 pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val);
886 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS,
887 val | EHCI_USBLEGCTLSTS_SOOE);
888#endif
889
890 /* some systems get upset if this semaphore is
891 * set for any other reason than forcing a BIOS
892 * handoff..
893 */
894 pci_write_config_byte(pdev, offset + 3, 1);
895 }
896
897 /* if boot firmware now owns EHCI, spin till it hands it over. */
898 if (try_handoff) {
899 int msec = 1000;
900 while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
901 tried_handoff = 1;
902 msleep(10);
903 msec -= 10;
904 pci_read_config_dword(pdev, offset, &cap);
905 }
906 }
907
908 if (cap & EHCI_USBLEGSUP_BIOS) {
909 /* well, possibly buggy BIOS... try to shut it down,
910 * and hope nothing goes too wrong
911 */
912 if (try_handoff)
913 dev_warn(&pdev->dev,
914 "EHCI: BIOS handoff failed (BIOS bug?) %08x\n",
915 cap);
916 pci_write_config_byte(pdev, offset + 2, 0);
917 }
918
919 /* just in case, always disable EHCI SMIs */
920 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0);
921
922 /* If the BIOS ever owned the controller then we can't expect
923 * any power sessions to remain intact.
924 */
925 if (tried_handoff)
926 writel(0, op_reg_base + EHCI_CONFIGFLAG);
927}
928
929static void quirk_usb_disable_ehci(struct pci_dev *pdev)
930{
931 void __iomem *base, *op_reg_base;
932 u32 hcc_params, cap, val;
933 u8 offset, cap_length;
934 int wait_time, count = 256/4;
935
936 if (!mmio_resource_enabled(pdev, 0))
937 return;
938
939 base = pci_ioremap_bar(pdev, 0);
940 if (base == NULL)
941 return;
942
943 cap_length = readb(base);
944 op_reg_base = base + cap_length;
945
946 /* EHCI 0.96 and later may have "extended capabilities"
947 * spec section 5.1 explains the bios handoff, e.g. for
948 * booting from USB disk or using a usb keyboard
949 */
950 hcc_params = readl(base + EHCI_HCC_PARAMS);
951 offset = (hcc_params >> 8) & 0xff;
952 while (offset && --count) {
953 pci_read_config_dword(pdev, offset, &cap);
954
955 switch (cap & 0xff) {
956 case 1:
957 ehci_bios_handoff(pdev, op_reg_base, cap, offset);
958 break;
959 case 0: /* Illegal reserved cap, set cap=0 so we exit */
960 cap = 0;
961 fallthrough;
962 default:
963 dev_warn(&pdev->dev,
964 "EHCI: unrecognized capability %02x\n",
965 cap & 0xff);
966 }
967 offset = (cap >> 8) & 0xff;
968 }
969 if (!count)
970 dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n");
971
972 /*
973 * halt EHCI & disable its interrupts in any case
974 */
975 val = readl(op_reg_base + EHCI_USBSTS);
976 if ((val & EHCI_USBSTS_HALTED) == 0) {
977 val = readl(op_reg_base + EHCI_USBCMD);
978 val &= ~EHCI_USBCMD_RUN;
979 writel(val, op_reg_base + EHCI_USBCMD);
980
981 wait_time = 2000;
982 do {
983 writel(0x3f, op_reg_base + EHCI_USBSTS);
984 udelay(100);
985 wait_time -= 100;
986 val = readl(op_reg_base + EHCI_USBSTS);
987 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
988 break;
989 }
990 } while (wait_time > 0);
991 }
992 writel(0, op_reg_base + EHCI_USBINTR);
993 writel(0x3f, op_reg_base + EHCI_USBSTS);
994
995 iounmap(base);
996}
997
998/*
999 * handshake - spin reading a register until handshake completes
1000 * @ptr: address of hc register to be read
1001 * @mask: bits to look at in result of read
1002 * @done: value of those bits when handshake succeeds
1003 * @wait_usec: timeout in microseconds
1004 * @delay_usec: delay in microseconds to wait between polling
1005 *
1006 * Polls a register every delay_usec microseconds.
1007 * Returns 0 when the mask bits have the value done.
1008 * Returns -ETIMEDOUT if this condition is not true after
1009 * wait_usec microseconds have passed.
1010 */
1011static int handshake(void __iomem *ptr, u32 mask, u32 done,
1012 int wait_usec, int delay_usec)
1013{
1014 u32 result;
1015
1016 do {
1017 result = readl(ptr);
1018 result &= mask;
1019 if (result == done)
1020 return 0;
1021 udelay(delay_usec);
1022 wait_usec -= delay_usec;
1023 } while (wait_usec > 0);
1024 return -ETIMEDOUT;
1025}
1026
1027/*
1028 * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that
1029 * share some number of ports. These ports can be switched between either
1030 * controller. Not all of the ports under the EHCI host controller may be
1031 * switchable.
1032 *
1033 * The ports should be switched over to xHCI before PCI probes for any device
1034 * start. This avoids active devices under EHCI being disconnected during the
1035 * port switchover, which could cause loss of data on USB storage devices, or
1036 * failed boot when the root file system is on a USB mass storage device and is
1037 * enumerated under EHCI first.
1038 *
1039 * We write into the xHC's PCI configuration space in some Intel-specific
1040 * registers to switch the ports over. The USB 3.0 terminations and the USB
1041 * 2.0 data wires are switched separately. We want to enable the SuperSpeed
1042 * terminations before switching the USB 2.0 wires over, so that USB 3.0
1043 * devices connect at SuperSpeed, rather than at USB 2.0 speeds.
1044 */
1045void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev)
1046{
1047 u32 ports_available;
1048 bool ehci_found = false;
1049 struct pci_dev *companion = NULL;
1050
1051 /* Sony VAIO t-series with subsystem device ID 90a8 is not capable of
1052 * switching ports from EHCI to xHCI
1053 */
1054 if (xhci_pdev->subsystem_vendor == PCI_VENDOR_ID_SONY &&
1055 xhci_pdev->subsystem_device == 0x90a8)
1056 return;
1057
1058 /* make sure an intel EHCI controller exists */
1059 for_each_pci_dev(companion) {
1060 if (companion->class == PCI_CLASS_SERIAL_USB_EHCI &&
1061 companion->vendor == PCI_VENDOR_ID_INTEL) {
1062 ehci_found = true;
1063 break;
1064 }
1065 }
1066
1067 if (!ehci_found)
1068 return;
1069
1070 /* Don't switchover the ports if the user hasn't compiled the xHCI
1071 * driver. Otherwise they will see "dead" USB ports that don't power
1072 * the devices.
1073 */
1074 if (!IS_ENABLED(CONFIG_USB_XHCI_HCD)) {
1075 dev_warn(&xhci_pdev->dev,
1076 "CONFIG_USB_XHCI_HCD is turned off, defaulting to EHCI.\n");
1077 dev_warn(&xhci_pdev->dev,
1078 "USB 3.0 devices will work at USB 2.0 speeds.\n");
1079 usb_disable_xhci_ports(xhci_pdev);
1080 return;
1081 }
1082
1083 /* Read USB3PRM, the USB 3.0 Port Routing Mask Register
1084 * Indicate the ports that can be changed from OS.
1085 */
1086 pci_read_config_dword(xhci_pdev, USB_INTEL_USB3PRM,
1087 &ports_available);
1088
1089 dev_dbg(&xhci_pdev->dev, "Configurable ports to enable SuperSpeed: 0x%x\n",
1090 ports_available);
1091
1092 /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable
1093 * Register, to turn on SuperSpeed terminations for the
1094 * switchable ports.
1095 */
1096 pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
1097 ports_available);
1098
1099 pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
1100 &ports_available);
1101 dev_dbg(&xhci_pdev->dev,
1102 "USB 3.0 ports that are now enabled under xHCI: 0x%x\n",
1103 ports_available);
1104
1105 /* Read XUSB2PRM, xHCI USB 2.0 Port Routing Mask Register
1106 * Indicate the USB 2.0 ports to be controlled by the xHCI host.
1107 */
1108
1109 pci_read_config_dword(xhci_pdev, USB_INTEL_USB2PRM,
1110 &ports_available);
1111
1112 dev_dbg(&xhci_pdev->dev, "Configurable USB 2.0 ports to hand over to xCHI: 0x%x\n",
1113 ports_available);
1114
1115 /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to
1116 * switch the USB 2.0 power and data lines over to the xHCI
1117 * host.
1118 */
1119 pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
1120 ports_available);
1121
1122 pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
1123 &ports_available);
1124 dev_dbg(&xhci_pdev->dev,
1125 "USB 2.0 ports that are now switched over to xHCI: 0x%x\n",
1126 ports_available);
1127}
1128EXPORT_SYMBOL_GPL(usb_enable_intel_xhci_ports);
1129
1130void usb_disable_xhci_ports(struct pci_dev *xhci_pdev)
1131{
1132 pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 0x0);
1133 pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 0x0);
1134}
1135EXPORT_SYMBOL_GPL(usb_disable_xhci_ports);
1136
1137/*
1138 * PCI Quirks for xHCI.
1139 *
1140 * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS.
1141 * It signals to the BIOS that the OS wants control of the host controller,
1142 * and then waits 1 second for the BIOS to hand over control.
1143 * If we timeout, assume the BIOS is broken and take control anyway.
1144 */
1145static void quirk_usb_handoff_xhci(struct pci_dev *pdev)
1146{
1147 void __iomem *base;
1148 int ext_cap_offset;
1149 void __iomem *op_reg_base;
1150 u32 val;
1151 int timeout;
1152 int len = pci_resource_len(pdev, 0);
1153
1154 if (!mmio_resource_enabled(pdev, 0))
1155 return;
1156
1157 base = ioremap(pci_resource_start(pdev, 0), len);
1158 if (base == NULL)
1159 return;
1160
1161 /*
1162 * Find the Legacy Support Capability register -
1163 * this is optional for xHCI host controllers.
1164 */
1165 ext_cap_offset = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_LEGACY);
1166
1167 if (!ext_cap_offset)
1168 goto hc_init;
1169
1170 if ((ext_cap_offset + sizeof(val)) > len) {
1171 /* We're reading garbage from the controller */
1172 dev_warn(&pdev->dev, "xHCI controller failing to respond");
1173 goto iounmap;
1174 }
1175 val = readl(base + ext_cap_offset);
1176
1177 /* Auto handoff never worked for these devices. Force it and continue */
1178 if ((pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) ||
1179 (pdev->vendor == PCI_VENDOR_ID_RENESAS
1180 && pdev->device == 0x0014)) {
1181 val = (val | XHCI_HC_OS_OWNED) & ~XHCI_HC_BIOS_OWNED;
1182 writel(val, base + ext_cap_offset);
1183 }
1184
1185 /* If the BIOS owns the HC, signal that the OS wants it, and wait */
1186 if (val & XHCI_HC_BIOS_OWNED) {
1187 writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset);
1188
1189 /* Wait for 1 second with 10 microsecond polling interval */
1190 timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED,
1191 0, 1000000, 10);
1192
1193 /* Assume a buggy BIOS and take HC ownership anyway */
1194 if (timeout) {
1195 dev_warn(&pdev->dev,
1196 "xHCI BIOS handoff failed (BIOS bug ?) %08x\n",
1197 val);
1198 writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset);
1199 }
1200 }
1201
1202 val = readl(base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
1203 /* Mask off (turn off) any enabled SMIs */
1204 val &= XHCI_LEGACY_DISABLE_SMI;
1205 /* Mask all SMI events bits, RW1C */
1206 val |= XHCI_LEGACY_SMI_EVENTS;
1207 /* Disable any BIOS SMIs and clear all SMI events*/
1208 writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
1209
1210hc_init:
1211 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
1212 usb_enable_intel_xhci_ports(pdev);
1213
1214 op_reg_base = base + XHCI_HC_LENGTH(readl(base));
1215
1216 /* Wait for the host controller to be ready before writing any
1217 * operational or runtime registers. Wait 5 seconds and no more.
1218 */
1219 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0,
1220 5000000, 10);
1221 /* Assume a buggy HC and start HC initialization anyway */
1222 if (timeout) {
1223 val = readl(op_reg_base + XHCI_STS_OFFSET);
1224 dev_warn(&pdev->dev,
1225 "xHCI HW not ready after 5 sec (HC bug?) status = 0x%x\n",
1226 val);
1227 }
1228
1229 /* Send the halt and disable interrupts command */
1230 val = readl(op_reg_base + XHCI_CMD_OFFSET);
1231 val &= ~(XHCI_CMD_RUN | XHCI_IRQS);
1232 writel(val, op_reg_base + XHCI_CMD_OFFSET);
1233
1234 /* Wait for the HC to halt - poll every 125 usec (one microframe). */
1235 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1,
1236 XHCI_MAX_HALT_USEC, 125);
1237 if (timeout) {
1238 val = readl(op_reg_base + XHCI_STS_OFFSET);
1239 dev_warn(&pdev->dev,
1240 "xHCI HW did not halt within %d usec status = 0x%x\n",
1241 XHCI_MAX_HALT_USEC, val);
1242 }
1243
1244iounmap:
1245 iounmap(base);
1246}
1247
1248static void quirk_usb_early_handoff(struct pci_dev *pdev)
1249{
1250 int ret;
1251
1252 /* Skip Netlogic mips SoC's internal PCI USB controller.
1253 * This device does not need/support EHCI/OHCI handoff
1254 */
1255 if (pdev->vendor == 0x184e) /* vendor Netlogic */
1256 return;
1257
1258 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
1259 ret = rpi_firmware_init_vl805(pdev);
1260 if (ret) {
1261 /* Firmware might be outdated, or something failed */
1262 dev_warn(&pdev->dev,
1263 "Failed to load VL805's firmware: %d. Will continue to attempt to work, but bad things might happen. You should fix this...\n",
1264 ret);
1265 }
1266 }
1267
1268 if (pdev->class != PCI_CLASS_SERIAL_USB_UHCI &&
1269 pdev->class != PCI_CLASS_SERIAL_USB_OHCI &&
1270 pdev->class != PCI_CLASS_SERIAL_USB_EHCI &&
1271 pdev->class != PCI_CLASS_SERIAL_USB_XHCI)
1272 return;
1273
1274 if (pci_enable_device(pdev) < 0) {
1275 dev_warn(&pdev->dev,
1276 "Can't enable PCI device, BIOS handoff failed.\n");
1277 return;
1278 }
1279 if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI)
1280 quirk_usb_handoff_uhci(pdev);
1281 else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI)
1282 quirk_usb_handoff_ohci(pdev);
1283 else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI)
1284 quirk_usb_disable_ehci(pdev);
1285 else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI)
1286 quirk_usb_handoff_xhci(pdev);
1287 pci_disable_device(pdev);
1288}
1289DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1290 PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff);