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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * SiFive UART driver
4 * Copyright (C) 2018 Paul Walmsley <paul@pwsan.com>
5 * Copyright (C) 2018-2019 SiFive
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * Based partially on:
18 * - drivers/tty/serial/pxa.c
19 * - drivers/tty/serial/amba-pl011.c
20 * - drivers/tty/serial/uartlite.c
21 * - drivers/tty/serial/omap-serial.c
22 * - drivers/pwm/pwm-sifive.c
23 *
24 * See the following sources for further documentation:
25 * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of
26 * SiFive FE310-G000 v2p3
27 * - The tree/master/src/main/scala/devices/uart directory of
28 * https://github.com/sifive/sifive-blocks/
29 *
30 * The SiFive UART design is not 8250-compatible. The following common
31 * features are not supported:
32 * - Word lengths other than 8 bits
33 * - Break handling
34 * - Parity
35 * - Flow control
36 * - Modem signals (DSR, RI, etc.)
37 * On the other hand, the design is free from the baggage of the 8250
38 * programming model.
39 */
40
41#include <linux/clk.h>
42#include <linux/console.h>
43#include <linux/delay.h>
44#include <linux/init.h>
45#include <linux/io.h>
46#include <linux/irq.h>
47#include <linux/module.h>
48#include <linux/of.h>
49#include <linux/of_irq.h>
50#include <linux/platform_device.h>
51#include <linux/serial_core.h>
52#include <linux/serial_reg.h>
53#include <linux/slab.h>
54#include <linux/tty.h>
55#include <linux/tty_flip.h>
56
57/*
58 * Register offsets
59 */
60
61/* TXDATA */
62#define SIFIVE_SERIAL_TXDATA_OFFS 0x0
63#define SIFIVE_SERIAL_TXDATA_FULL_SHIFT 31
64#define SIFIVE_SERIAL_TXDATA_FULL_MASK (1 << SIFIVE_SERIAL_TXDATA_FULL_SHIFT)
65#define SIFIVE_SERIAL_TXDATA_DATA_SHIFT 0
66#define SIFIVE_SERIAL_TXDATA_DATA_MASK (0xff << SIFIVE_SERIAL_TXDATA_DATA_SHIFT)
67
68/* RXDATA */
69#define SIFIVE_SERIAL_RXDATA_OFFS 0x4
70#define SIFIVE_SERIAL_RXDATA_EMPTY_SHIFT 31
71#define SIFIVE_SERIAL_RXDATA_EMPTY_MASK (1 << SIFIVE_SERIAL_RXDATA_EMPTY_SHIFT)
72#define SIFIVE_SERIAL_RXDATA_DATA_SHIFT 0
73#define SIFIVE_SERIAL_RXDATA_DATA_MASK (0xff << SIFIVE_SERIAL_RXDATA_DATA_SHIFT)
74
75/* TXCTRL */
76#define SIFIVE_SERIAL_TXCTRL_OFFS 0x8
77#define SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT 16
78#define SIFIVE_SERIAL_TXCTRL_TXCNT_MASK (0x7 << SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT)
79#define SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT 1
80#define SIFIVE_SERIAL_TXCTRL_NSTOP_MASK (1 << SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT)
81#define SIFIVE_SERIAL_TXCTRL_TXEN_SHIFT 0
82#define SIFIVE_SERIAL_TXCTRL_TXEN_MASK (1 << SIFIVE_SERIAL_TXCTRL_TXEN_SHIFT)
83
84/* RXCTRL */
85#define SIFIVE_SERIAL_RXCTRL_OFFS 0xC
86#define SIFIVE_SERIAL_RXCTRL_RXCNT_SHIFT 16
87#define SIFIVE_SERIAL_RXCTRL_RXCNT_MASK (0x7 << SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT)
88#define SIFIVE_SERIAL_RXCTRL_RXEN_SHIFT 0
89#define SIFIVE_SERIAL_RXCTRL_RXEN_MASK (1 << SIFIVE_SERIAL_RXCTRL_RXEN_SHIFT)
90
91/* IE */
92#define SIFIVE_SERIAL_IE_OFFS 0x10
93#define SIFIVE_SERIAL_IE_RXWM_SHIFT 1
94#define SIFIVE_SERIAL_IE_RXWM_MASK (1 << SIFIVE_SERIAL_IE_RXWM_SHIFT)
95#define SIFIVE_SERIAL_IE_TXWM_SHIFT 0
96#define SIFIVE_SERIAL_IE_TXWM_MASK (1 << SIFIVE_SERIAL_IE_TXWM_SHIFT)
97
98/* IP */
99#define SIFIVE_SERIAL_IP_OFFS 0x14
100#define SIFIVE_SERIAL_IP_RXWM_SHIFT 1
101#define SIFIVE_SERIAL_IP_RXWM_MASK (1 << SIFIVE_SERIAL_IP_RXWM_SHIFT)
102#define SIFIVE_SERIAL_IP_TXWM_SHIFT 0
103#define SIFIVE_SERIAL_IP_TXWM_MASK (1 << SIFIVE_SERIAL_IP_TXWM_SHIFT)
104
105/* DIV */
106#define SIFIVE_SERIAL_DIV_OFFS 0x18
107#define SIFIVE_SERIAL_DIV_DIV_SHIFT 0
108#define SIFIVE_SERIAL_DIV_DIV_MASK (0xffff << SIFIVE_SERIAL_IP_DIV_SHIFT)
109
110/*
111 * Config macros
112 */
113
114/*
115 * SIFIVE_SERIAL_MAX_PORTS: maximum number of UARTs on a device that can
116 * host a serial console
117 */
118#define SIFIVE_SERIAL_MAX_PORTS 8
119
120/*
121 * SIFIVE_DEFAULT_BAUD_RATE: default baud rate that the driver should
122 * configure itself to use
123 */
124#define SIFIVE_DEFAULT_BAUD_RATE 115200
125
126/* SIFIVE_SERIAL_NAME: our driver's name that we pass to the operating system */
127#define SIFIVE_SERIAL_NAME "sifive-serial"
128
129/* SIFIVE_TTY_PREFIX: tty name prefix for SiFive serial ports */
130#define SIFIVE_TTY_PREFIX "ttySIF"
131
132/* SIFIVE_TX_FIFO_DEPTH: depth of the TX FIFO (in bytes) */
133#define SIFIVE_TX_FIFO_DEPTH 8
134
135/* SIFIVE_RX_FIFO_DEPTH: depth of the TX FIFO (in bytes) */
136#define SIFIVE_RX_FIFO_DEPTH 8
137
138#if (SIFIVE_TX_FIFO_DEPTH != SIFIVE_RX_FIFO_DEPTH)
139#error Driver does not support configurations with different TX, RX FIFO sizes
140#endif
141
142/*
143 *
144 */
145
146/**
147 * sifive_serial_port - driver-specific data extension to struct uart_port
148 * @port: struct uart_port embedded in this struct
149 * @dev: struct device *
150 * @ier: shadowed copy of the interrupt enable register
151 * @clkin_rate: input clock to the UART IP block.
152 * @baud_rate: UART serial line rate (e.g., 115200 baud)
153 * @clk_notifier: clock rate change notifier for upstream clock changes
154 *
155 * Configuration data specific to this SiFive UART.
156 */
157struct sifive_serial_port {
158 struct uart_port port;
159 struct device *dev;
160 unsigned char ier;
161 unsigned long clkin_rate;
162 unsigned long baud_rate;
163 struct clk *clk;
164 struct notifier_block clk_notifier;
165};
166
167/*
168 * Structure container-of macros
169 */
170
171#define port_to_sifive_serial_port(p) (container_of((p), \
172 struct sifive_serial_port, \
173 port))
174
175#define notifier_to_sifive_serial_port(nb) (container_of((nb), \
176 struct sifive_serial_port, \
177 clk_notifier))
178
179/*
180 * Forward declarations
181 */
182static void sifive_serial_stop_tx(struct uart_port *port);
183
184/*
185 * Internal functions
186 */
187
188/**
189 * __ssp_early_writel() - write to a SiFive serial port register (early)
190 * @port: pointer to a struct uart_port record
191 * @offs: register address offset from the IP block base address
192 * @v: value to write to the register
193 *
194 * Given a pointer @port to a struct uart_port record, write the value
195 * @v to the IP block register address offset @offs. This function is
196 * intended for early console use.
197 *
198 * Context: Intended to be used only by the earlyconsole code.
199 */
200static void __ssp_early_writel(u32 v, u16 offs, struct uart_port *port)
201{
202 writel_relaxed(v, port->membase + offs);
203}
204
205/**
206 * __ssp_early_readl() - read from a SiFive serial port register (early)
207 * @port: pointer to a struct uart_port record
208 * @offs: register address offset from the IP block base address
209 *
210 * Given a pointer @port to a struct uart_port record, read the
211 * contents of the IP block register located at offset @offs from the
212 * IP block base and return it. This function is intended for early
213 * console use.
214 *
215 * Context: Intended to be called only by the earlyconsole code or by
216 * __ssp_readl() or __ssp_writel() (in this driver)
217 *
218 * Returns: the register value read from the UART.
219 */
220static u32 __ssp_early_readl(struct uart_port *port, u16 offs)
221{
222 return readl_relaxed(port->membase + offs);
223}
224
225/**
226 * __ssp_writel() - write to a SiFive serial port register
227 * @v: value to write to the register
228 * @offs: register address offset from the IP block base address
229 * @ssp: pointer to a struct sifive_serial_port record
230 *
231 * Write the value @v to the IP block register located at offset @offs from the
232 * IP block base, given a pointer @ssp to a struct sifive_serial_port record.
233 *
234 * Context: Any context.
235 */
236static void __ssp_writel(u32 v, u16 offs, struct sifive_serial_port *ssp)
237{
238 __ssp_early_writel(v, offs, &ssp->port);
239}
240
241/**
242 * __ssp_readl() - read from a SiFive serial port register
243 * @ssp: pointer to a struct sifive_serial_port record
244 * @offs: register address offset from the IP block base address
245 *
246 * Read the contents of the IP block register located at offset @offs from the
247 * IP block base, given a pointer @ssp to a struct sifive_serial_port record.
248 *
249 * Context: Any context.
250 *
251 * Returns: the value of the UART register
252 */
253static u32 __ssp_readl(struct sifive_serial_port *ssp, u16 offs)
254{
255 return __ssp_early_readl(&ssp->port, offs);
256}
257
258/**
259 * sifive_serial_is_txfifo_full() - is the TXFIFO full?
260 * @ssp: pointer to a struct sifive_serial_port
261 *
262 * Read the transmit FIFO "full" bit, returning a non-zero value if the
263 * TX FIFO is full, or zero if space remains. Intended to be used to prevent
264 * writes to the TX FIFO when it's full.
265 *
266 * Returns: SIFIVE_SERIAL_TXDATA_FULL_MASK (non-zero) if the transmit FIFO
267 * is full, or 0 if space remains.
268 */
269static int sifive_serial_is_txfifo_full(struct sifive_serial_port *ssp)
270{
271 return __ssp_readl(ssp, SIFIVE_SERIAL_TXDATA_OFFS) &
272 SIFIVE_SERIAL_TXDATA_FULL_MASK;
273}
274
275/**
276 * __ssp_transmit_char() - enqueue a byte to transmit onto the TX FIFO
277 * @ssp: pointer to a struct sifive_serial_port
278 * @ch: character to transmit
279 *
280 * Enqueue a byte @ch onto the transmit FIFO, given a pointer @ssp to the
281 * struct sifive_serial_port * to transmit on. Caller should first check to
282 * ensure that the TXFIFO has space; see sifive_serial_is_txfifo_full().
283 *
284 * Context: Any context.
285 */
286static void __ssp_transmit_char(struct sifive_serial_port *ssp, int ch)
287{
288 __ssp_writel(ch, SIFIVE_SERIAL_TXDATA_OFFS, ssp);
289}
290
291/**
292 * __ssp_transmit_chars() - enqueue multiple bytes onto the TX FIFO
293 * @ssp: pointer to a struct sifive_serial_port
294 *
295 * Transfer up to a TX FIFO size's worth of characters from the Linux serial
296 * transmit buffer to the SiFive UART TX FIFO.
297 *
298 * Context: Any context. Expects @ssp->port.lock to be held by caller.
299 */
300static void __ssp_transmit_chars(struct sifive_serial_port *ssp)
301{
302 struct circ_buf *xmit = &ssp->port.state->xmit;
303 int count;
304
305 if (ssp->port.x_char) {
306 __ssp_transmit_char(ssp, ssp->port.x_char);
307 ssp->port.icount.tx++;
308 ssp->port.x_char = 0;
309 return;
310 }
311 if (uart_circ_empty(xmit) || uart_tx_stopped(&ssp->port)) {
312 sifive_serial_stop_tx(&ssp->port);
313 return;
314 }
315 count = SIFIVE_TX_FIFO_DEPTH;
316 do {
317 __ssp_transmit_char(ssp, xmit->buf[xmit->tail]);
318 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
319 ssp->port.icount.tx++;
320 if (uart_circ_empty(xmit))
321 break;
322 } while (--count > 0);
323
324 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
325 uart_write_wakeup(&ssp->port);
326
327 if (uart_circ_empty(xmit))
328 sifive_serial_stop_tx(&ssp->port);
329}
330
331/**
332 * __ssp_enable_txwm() - enable transmit watermark interrupts
333 * @ssp: pointer to a struct sifive_serial_port
334 *
335 * Enable interrupt generation when the transmit FIFO watermark is reached
336 * on the SiFive UART referred to by @ssp.
337 */
338static void __ssp_enable_txwm(struct sifive_serial_port *ssp)
339{
340 if (ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK)
341 return;
342
343 ssp->ier |= SIFIVE_SERIAL_IE_TXWM_MASK;
344 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
345}
346
347/**
348 * __ssp_enable_rxwm() - enable receive watermark interrupts
349 * @ssp: pointer to a struct sifive_serial_port
350 *
351 * Enable interrupt generation when the receive FIFO watermark is reached
352 * on the SiFive UART referred to by @ssp.
353 */
354static void __ssp_enable_rxwm(struct sifive_serial_port *ssp)
355{
356 if (ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK)
357 return;
358
359 ssp->ier |= SIFIVE_SERIAL_IE_RXWM_MASK;
360 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
361}
362
363/**
364 * __ssp_disable_txwm() - disable transmit watermark interrupts
365 * @ssp: pointer to a struct sifive_serial_port
366 *
367 * Disable interrupt generation when the transmit FIFO watermark is reached
368 * on the UART referred to by @ssp.
369 */
370static void __ssp_disable_txwm(struct sifive_serial_port *ssp)
371{
372 if (!(ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK))
373 return;
374
375 ssp->ier &= ~SIFIVE_SERIAL_IE_TXWM_MASK;
376 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
377}
378
379/**
380 * __ssp_disable_rxwm() - disable receive watermark interrupts
381 * @ssp: pointer to a struct sifive_serial_port
382 *
383 * Disable interrupt generation when the receive FIFO watermark is reached
384 * on the UART referred to by @ssp.
385 */
386static void __ssp_disable_rxwm(struct sifive_serial_port *ssp)
387{
388 if (!(ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK))
389 return;
390
391 ssp->ier &= ~SIFIVE_SERIAL_IE_RXWM_MASK;
392 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
393}
394
395/**
396 * __ssp_receive_char() - receive a byte from the UART
397 * @ssp: pointer to a struct sifive_serial_port
398 * @is_empty: char pointer to return whether the RX FIFO is empty
399 *
400 * Try to read a byte from the SiFive UART RX FIFO, referenced by
401 * @ssp, and to return it. Also returns the RX FIFO empty bit in
402 * the char pointed to by @ch. The caller must pass the byte back to the
403 * Linux serial layer if needed.
404 *
405 * Returns: the byte read from the UART RX FIFO.
406 */
407static char __ssp_receive_char(struct sifive_serial_port *ssp, char *is_empty)
408{
409 u32 v;
410 u8 ch;
411
412 v = __ssp_readl(ssp, SIFIVE_SERIAL_RXDATA_OFFS);
413
414 if (!is_empty)
415 WARN_ON(1);
416 else
417 *is_empty = (v & SIFIVE_SERIAL_RXDATA_EMPTY_MASK) >>
418 SIFIVE_SERIAL_RXDATA_EMPTY_SHIFT;
419
420 ch = (v & SIFIVE_SERIAL_RXDATA_DATA_MASK) >>
421 SIFIVE_SERIAL_RXDATA_DATA_SHIFT;
422
423 return ch;
424}
425
426/**
427 * __ssp_receive_chars() - receive multiple bytes from the UART
428 * @ssp: pointer to a struct sifive_serial_port
429 *
430 * Receive up to an RX FIFO's worth of bytes from the SiFive UART referred
431 * to by @ssp and pass them up to the Linux serial layer.
432 *
433 * Context: Expects ssp->port.lock to be held by caller.
434 */
435static void __ssp_receive_chars(struct sifive_serial_port *ssp)
436{
437 unsigned char ch;
438 char is_empty;
439 int c;
440
441 for (c = SIFIVE_RX_FIFO_DEPTH; c > 0; --c) {
442 ch = __ssp_receive_char(ssp, &is_empty);
443 if (is_empty)
444 break;
445
446 ssp->port.icount.rx++;
447 uart_insert_char(&ssp->port, 0, 0, ch, TTY_NORMAL);
448 }
449
450 spin_unlock(&ssp->port.lock);
451 tty_flip_buffer_push(&ssp->port.state->port);
452 spin_lock(&ssp->port.lock);
453}
454
455/**
456 * __ssp_update_div() - calculate the divisor setting by the line rate
457 * @ssp: pointer to a struct sifive_serial_port
458 *
459 * Calculate the appropriate value of the clock divisor for the UART
460 * and target line rate referred to by @ssp and write it into the
461 * hardware.
462 */
463static void __ssp_update_div(struct sifive_serial_port *ssp)
464{
465 u16 div;
466
467 div = DIV_ROUND_UP(ssp->clkin_rate, ssp->baud_rate) - 1;
468
469 __ssp_writel(div, SIFIVE_SERIAL_DIV_OFFS, ssp);
470}
471
472/**
473 * __ssp_update_baud_rate() - set the UART "baud rate"
474 * @ssp: pointer to a struct sifive_serial_port
475 * @rate: new target bit rate
476 *
477 * Calculate the UART divisor value for the target bit rate @rate for the
478 * SiFive UART described by @ssp and program it into the UART. There may
479 * be some error between the target bit rate and the actual bit rate implemented
480 * by the UART due to clock ratio granularity.
481 */
482static void __ssp_update_baud_rate(struct sifive_serial_port *ssp,
483 unsigned int rate)
484{
485 if (ssp->baud_rate == rate)
486 return;
487
488 ssp->baud_rate = rate;
489 __ssp_update_div(ssp);
490}
491
492/**
493 * __ssp_set_stop_bits() - set the number of stop bits
494 * @ssp: pointer to a struct sifive_serial_port
495 * @nstop: 1 or 2 (stop bits)
496 *
497 * Program the SiFive UART referred to by @ssp to use @nstop stop bits.
498 */
499static void __ssp_set_stop_bits(struct sifive_serial_port *ssp, char nstop)
500{
501 u32 v;
502
503 if (nstop < 1 || nstop > 2) {
504 WARN_ON(1);
505 return;
506 }
507
508 v = __ssp_readl(ssp, SIFIVE_SERIAL_TXCTRL_OFFS);
509 v &= ~SIFIVE_SERIAL_TXCTRL_NSTOP_MASK;
510 v |= (nstop - 1) << SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT;
511 __ssp_writel(v, SIFIVE_SERIAL_TXCTRL_OFFS, ssp);
512}
513
514/**
515 * __ssp_wait_for_xmitr() - wait for an empty slot on the TX FIFO
516 * @ssp: pointer to a struct sifive_serial_port
517 *
518 * Delay while the UART TX FIFO referred to by @ssp is marked as full.
519 *
520 * Context: Any context.
521 */
522static void __maybe_unused __ssp_wait_for_xmitr(struct sifive_serial_port *ssp)
523{
524 while (sifive_serial_is_txfifo_full(ssp))
525 udelay(1); /* XXX Could probably be more intelligent here */
526}
527
528/*
529 * Linux serial API functions
530 */
531
532static void sifive_serial_stop_tx(struct uart_port *port)
533{
534 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
535
536 __ssp_disable_txwm(ssp);
537}
538
539static void sifive_serial_stop_rx(struct uart_port *port)
540{
541 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
542
543 __ssp_disable_rxwm(ssp);
544}
545
546static void sifive_serial_start_tx(struct uart_port *port)
547{
548 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
549
550 __ssp_enable_txwm(ssp);
551}
552
553static irqreturn_t sifive_serial_irq(int irq, void *dev_id)
554{
555 struct sifive_serial_port *ssp = dev_id;
556 u32 ip;
557
558 spin_lock(&ssp->port.lock);
559
560 ip = __ssp_readl(ssp, SIFIVE_SERIAL_IP_OFFS);
561 if (!ip) {
562 spin_unlock(&ssp->port.lock);
563 return IRQ_NONE;
564 }
565
566 if (ip & SIFIVE_SERIAL_IP_RXWM_MASK)
567 __ssp_receive_chars(ssp);
568 if (ip & SIFIVE_SERIAL_IP_TXWM_MASK)
569 __ssp_transmit_chars(ssp);
570
571 spin_unlock(&ssp->port.lock);
572
573 return IRQ_HANDLED;
574}
575
576static unsigned int sifive_serial_tx_empty(struct uart_port *port)
577{
578 return TIOCSER_TEMT;
579}
580
581static unsigned int sifive_serial_get_mctrl(struct uart_port *port)
582{
583 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
584}
585
586static void sifive_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
587{
588 /* IP block does not support these signals */
589}
590
591static void sifive_serial_break_ctl(struct uart_port *port, int break_state)
592{
593 /* IP block does not support sending a break */
594}
595
596static int sifive_serial_startup(struct uart_port *port)
597{
598 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
599
600 __ssp_enable_rxwm(ssp);
601
602 return 0;
603}
604
605static void sifive_serial_shutdown(struct uart_port *port)
606{
607 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
608
609 __ssp_disable_rxwm(ssp);
610 __ssp_disable_txwm(ssp);
611}
612
613/**
614 * sifive_serial_clk_notifier() - clock post-rate-change notifier
615 * @nb: pointer to the struct notifier_block, from the notifier code
616 * @event: event mask from the notifier code
617 * @data: pointer to the struct clk_notifier_data from the notifier code
618 *
619 * On the V0 SoC, the UART IP block is derived from the CPU clock source
620 * after a synchronous divide-by-two divider, so any CPU clock rate change
621 * requires the UART baud rate to be updated. This presumably corrupts any
622 * serial word currently being transmitted or received. In order to avoid
623 * corrupting the output data stream, we drain the transmit queue before
624 * allowing the clock's rate to be changed.
625 */
626static int sifive_serial_clk_notifier(struct notifier_block *nb,
627 unsigned long event, void *data)
628{
629 struct clk_notifier_data *cnd = data;
630 struct sifive_serial_port *ssp = notifier_to_sifive_serial_port(nb);
631
632 if (event == PRE_RATE_CHANGE) {
633 /*
634 * The TX watermark is always set to 1 by this driver, which
635 * means that the TX busy bit will lower when there are 0 bytes
636 * left in the TX queue -- in other words, when the TX FIFO is
637 * empty.
638 */
639 __ssp_wait_for_xmitr(ssp);
640 /*
641 * On the cycle the TX FIFO goes empty there is still a full
642 * UART frame left to be transmitted in the shift register.
643 * The UART provides no way for software to directly determine
644 * when that last frame has been transmitted, so we just sleep
645 * here instead. As we're not tracking the number of stop bits
646 * they're just worst cased here. The rest of the serial
647 * framing parameters aren't configurable by software.
648 */
649 udelay(DIV_ROUND_UP(12 * 1000 * 1000, ssp->baud_rate));
650 }
651
652 if (event == POST_RATE_CHANGE && ssp->clkin_rate != cnd->new_rate) {
653 ssp->clkin_rate = cnd->new_rate;
654 __ssp_update_div(ssp);
655 }
656
657 return NOTIFY_OK;
658}
659
660static void sifive_serial_set_termios(struct uart_port *port,
661 struct ktermios *termios,
662 struct ktermios *old)
663{
664 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
665 unsigned long flags;
666 u32 v, old_v;
667 int rate;
668 char nstop;
669
670 if ((termios->c_cflag & CSIZE) != CS8)
671 dev_err_once(ssp->port.dev, "only 8-bit words supported\n");
672 if (termios->c_iflag & (INPCK | PARMRK))
673 dev_err_once(ssp->port.dev, "parity checking not supported\n");
674 if (termios->c_iflag & BRKINT)
675 dev_err_once(ssp->port.dev, "BREAK detection not supported\n");
676
677 /* Set number of stop bits */
678 nstop = (termios->c_cflag & CSTOPB) ? 2 : 1;
679 __ssp_set_stop_bits(ssp, nstop);
680
681 /* Set line rate */
682 rate = uart_get_baud_rate(port, termios, old, 0, ssp->clkin_rate / 16);
683 __ssp_update_baud_rate(ssp, rate);
684
685 spin_lock_irqsave(&ssp->port.lock, flags);
686
687 /* Update the per-port timeout */
688 uart_update_timeout(port, termios->c_cflag, rate);
689
690 ssp->port.read_status_mask = 0;
691
692 /* Ignore all characters if CREAD is not set */
693 v = __ssp_readl(ssp, SIFIVE_SERIAL_RXCTRL_OFFS);
694 old_v = v;
695 if ((termios->c_cflag & CREAD) == 0)
696 v &= SIFIVE_SERIAL_RXCTRL_RXEN_MASK;
697 else
698 v |= SIFIVE_SERIAL_RXCTRL_RXEN_MASK;
699 if (v != old_v)
700 __ssp_writel(v, SIFIVE_SERIAL_RXCTRL_OFFS, ssp);
701
702 spin_unlock_irqrestore(&ssp->port.lock, flags);
703}
704
705static void sifive_serial_release_port(struct uart_port *port)
706{
707}
708
709static int sifive_serial_request_port(struct uart_port *port)
710{
711 return 0;
712}
713
714static void sifive_serial_config_port(struct uart_port *port, int flags)
715{
716 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
717
718 ssp->port.type = PORT_SIFIVE_V0;
719}
720
721static int sifive_serial_verify_port(struct uart_port *port,
722 struct serial_struct *ser)
723{
724 return -EINVAL;
725}
726
727static const char *sifive_serial_type(struct uart_port *port)
728{
729 return port->type == PORT_SIFIVE_V0 ? "SiFive UART v0" : NULL;
730}
731
732#ifdef CONFIG_CONSOLE_POLL
733static int sifive_serial_poll_get_char(struct uart_port *port)
734{
735 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
736 char is_empty, ch;
737
738 ch = __ssp_receive_char(ssp, &is_empty);
739 if (is_empty)
740 return NO_POLL_CHAR;
741
742 return ch;
743}
744
745static void sifive_serial_poll_put_char(struct uart_port *port,
746 unsigned char c)
747{
748 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
749
750 __ssp_wait_for_xmitr(ssp);
751 __ssp_transmit_char(ssp, c);
752}
753#endif /* CONFIG_CONSOLE_POLL */
754
755/*
756 * Early console support
757 */
758
759#ifdef CONFIG_SERIAL_EARLYCON
760static void early_sifive_serial_putc(struct uart_port *port, int c)
761{
762 while (__ssp_early_readl(port, SIFIVE_SERIAL_TXDATA_OFFS) &
763 SIFIVE_SERIAL_TXDATA_FULL_MASK)
764 cpu_relax();
765
766 __ssp_early_writel(c, SIFIVE_SERIAL_TXDATA_OFFS, port);
767}
768
769static void early_sifive_serial_write(struct console *con, const char *s,
770 unsigned int n)
771{
772 struct earlycon_device *dev = con->data;
773 struct uart_port *port = &dev->port;
774
775 uart_console_write(port, s, n, early_sifive_serial_putc);
776}
777
778static int __init early_sifive_serial_setup(struct earlycon_device *dev,
779 const char *options)
780{
781 struct uart_port *port = &dev->port;
782
783 if (!port->membase)
784 return -ENODEV;
785
786 dev->con->write = early_sifive_serial_write;
787
788 return 0;
789}
790
791OF_EARLYCON_DECLARE(sifive, "sifive,uart0", early_sifive_serial_setup);
792OF_EARLYCON_DECLARE(sifive, "sifive,fu540-c000-uart0",
793 early_sifive_serial_setup);
794#endif /* CONFIG_SERIAL_EARLYCON */
795
796/*
797 * Linux console interface
798 */
799
800#ifdef CONFIG_SERIAL_SIFIVE_CONSOLE
801
802static struct sifive_serial_port *sifive_serial_console_ports[SIFIVE_SERIAL_MAX_PORTS];
803
804static void sifive_serial_console_putchar(struct uart_port *port, int ch)
805{
806 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
807
808 __ssp_wait_for_xmitr(ssp);
809 __ssp_transmit_char(ssp, ch);
810}
811
812static void sifive_serial_console_write(struct console *co, const char *s,
813 unsigned int count)
814{
815 struct sifive_serial_port *ssp = sifive_serial_console_ports[co->index];
816 unsigned long flags;
817 unsigned int ier;
818 int locked = 1;
819
820 if (!ssp)
821 return;
822
823 local_irq_save(flags);
824 if (ssp->port.sysrq)
825 locked = 0;
826 else if (oops_in_progress)
827 locked = spin_trylock(&ssp->port.lock);
828 else
829 spin_lock(&ssp->port.lock);
830
831 ier = __ssp_readl(ssp, SIFIVE_SERIAL_IE_OFFS);
832 __ssp_writel(0, SIFIVE_SERIAL_IE_OFFS, ssp);
833
834 uart_console_write(&ssp->port, s, count, sifive_serial_console_putchar);
835
836 __ssp_writel(ier, SIFIVE_SERIAL_IE_OFFS, ssp);
837
838 if (locked)
839 spin_unlock(&ssp->port.lock);
840 local_irq_restore(flags);
841}
842
843static int __init sifive_serial_console_setup(struct console *co, char *options)
844{
845 struct sifive_serial_port *ssp;
846 int baud = SIFIVE_DEFAULT_BAUD_RATE;
847 int bits = 8;
848 int parity = 'n';
849 int flow = 'n';
850
851 if (co->index < 0 || co->index >= SIFIVE_SERIAL_MAX_PORTS)
852 return -ENODEV;
853
854 ssp = sifive_serial_console_ports[co->index];
855 if (!ssp)
856 return -ENODEV;
857
858 if (options)
859 uart_parse_options(options, &baud, &parity, &bits, &flow);
860
861 return uart_set_options(&ssp->port, co, baud, parity, bits, flow);
862}
863
864static struct uart_driver sifive_serial_uart_driver;
865
866static struct console sifive_serial_console = {
867 .name = SIFIVE_TTY_PREFIX,
868 .write = sifive_serial_console_write,
869 .device = uart_console_device,
870 .setup = sifive_serial_console_setup,
871 .flags = CON_PRINTBUFFER,
872 .index = -1,
873 .data = &sifive_serial_uart_driver,
874};
875
876static int __init sifive_console_init(void)
877{
878 register_console(&sifive_serial_console);
879 return 0;
880}
881
882console_initcall(sifive_console_init);
883
884static void __ssp_add_console_port(struct sifive_serial_port *ssp)
885{
886 sifive_serial_console_ports[ssp->port.line] = ssp;
887}
888
889static void __ssp_remove_console_port(struct sifive_serial_port *ssp)
890{
891 sifive_serial_console_ports[ssp->port.line] = 0;
892}
893
894#define SIFIVE_SERIAL_CONSOLE (&sifive_serial_console)
895
896#else
897
898#define SIFIVE_SERIAL_CONSOLE NULL
899
900static void __ssp_add_console_port(struct sifive_serial_port *ssp)
901{}
902static void __ssp_remove_console_port(struct sifive_serial_port *ssp)
903{}
904
905#endif
906
907static const struct uart_ops sifive_serial_uops = {
908 .tx_empty = sifive_serial_tx_empty,
909 .set_mctrl = sifive_serial_set_mctrl,
910 .get_mctrl = sifive_serial_get_mctrl,
911 .stop_tx = sifive_serial_stop_tx,
912 .start_tx = sifive_serial_start_tx,
913 .stop_rx = sifive_serial_stop_rx,
914 .break_ctl = sifive_serial_break_ctl,
915 .startup = sifive_serial_startup,
916 .shutdown = sifive_serial_shutdown,
917 .set_termios = sifive_serial_set_termios,
918 .type = sifive_serial_type,
919 .release_port = sifive_serial_release_port,
920 .request_port = sifive_serial_request_port,
921 .config_port = sifive_serial_config_port,
922 .verify_port = sifive_serial_verify_port,
923#ifdef CONFIG_CONSOLE_POLL
924 .poll_get_char = sifive_serial_poll_get_char,
925 .poll_put_char = sifive_serial_poll_put_char,
926#endif
927};
928
929static struct uart_driver sifive_serial_uart_driver = {
930 .owner = THIS_MODULE,
931 .driver_name = SIFIVE_SERIAL_NAME,
932 .dev_name = SIFIVE_TTY_PREFIX,
933 .nr = SIFIVE_SERIAL_MAX_PORTS,
934 .cons = SIFIVE_SERIAL_CONSOLE,
935};
936
937static int sifive_serial_probe(struct platform_device *pdev)
938{
939 struct sifive_serial_port *ssp;
940 struct resource *mem;
941 struct clk *clk;
942 void __iomem *base;
943 int irq, id, r;
944
945 irq = platform_get_irq(pdev, 0);
946 if (irq < 0)
947 return -EPROBE_DEFER;
948
949 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
950 base = devm_ioremap_resource(&pdev->dev, mem);
951 if (IS_ERR(base)) {
952 dev_err(&pdev->dev, "could not acquire device memory\n");
953 return PTR_ERR(base);
954 }
955
956 clk = devm_clk_get(&pdev->dev, NULL);
957 if (IS_ERR(clk)) {
958 dev_err(&pdev->dev, "unable to find controller clock\n");
959 return PTR_ERR(clk);
960 }
961
962 id = of_alias_get_id(pdev->dev.of_node, "serial");
963 if (id < 0) {
964 dev_err(&pdev->dev, "missing aliases entry\n");
965 return id;
966 }
967
968#ifdef CONFIG_SERIAL_SIFIVE_CONSOLE
969 if (id > SIFIVE_SERIAL_MAX_PORTS) {
970 dev_err(&pdev->dev, "too many UARTs (%d)\n", id);
971 return -EINVAL;
972 }
973#endif
974
975 ssp = devm_kzalloc(&pdev->dev, sizeof(*ssp), GFP_KERNEL);
976 if (!ssp)
977 return -ENOMEM;
978
979 ssp->port.dev = &pdev->dev;
980 ssp->port.type = PORT_SIFIVE_V0;
981 ssp->port.iotype = UPIO_MEM;
982 ssp->port.irq = irq;
983 ssp->port.fifosize = SIFIVE_TX_FIFO_DEPTH;
984 ssp->port.ops = &sifive_serial_uops;
985 ssp->port.line = id;
986 ssp->port.mapbase = mem->start;
987 ssp->port.membase = base;
988 ssp->dev = &pdev->dev;
989 ssp->clk = clk;
990 ssp->clk_notifier.notifier_call = sifive_serial_clk_notifier;
991
992 r = clk_notifier_register(ssp->clk, &ssp->clk_notifier);
993 if (r) {
994 dev_err(&pdev->dev, "could not register clock notifier: %d\n",
995 r);
996 goto probe_out1;
997 }
998
999 /* Set up clock divider */
1000 ssp->clkin_rate = clk_get_rate(ssp->clk);
1001 ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;
1002 __ssp_update_div(ssp);
1003
1004 platform_set_drvdata(pdev, ssp);
1005
1006 /* Enable transmits and set the watermark level to 1 */
1007 __ssp_writel((1 << SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT) |
1008 SIFIVE_SERIAL_TXCTRL_TXEN_MASK,
1009 SIFIVE_SERIAL_TXCTRL_OFFS, ssp);
1010
1011 /* Enable receives and set the watermark level to 0 */
1012 __ssp_writel((0 << SIFIVE_SERIAL_RXCTRL_RXCNT_SHIFT) |
1013 SIFIVE_SERIAL_RXCTRL_RXEN_MASK,
1014 SIFIVE_SERIAL_RXCTRL_OFFS, ssp);
1015
1016 r = request_irq(ssp->port.irq, sifive_serial_irq, ssp->port.irqflags,
1017 dev_name(&pdev->dev), ssp);
1018 if (r) {
1019 dev_err(&pdev->dev, "could not attach interrupt: %d\n", r);
1020 goto probe_out2;
1021 }
1022
1023 __ssp_add_console_port(ssp);
1024
1025 r = uart_add_one_port(&sifive_serial_uart_driver, &ssp->port);
1026 if (r != 0) {
1027 dev_err(&pdev->dev, "could not add uart: %d\n", r);
1028 goto probe_out3;
1029 }
1030
1031 return 0;
1032
1033probe_out3:
1034 __ssp_remove_console_port(ssp);
1035 free_irq(ssp->port.irq, ssp);
1036probe_out2:
1037 clk_notifier_unregister(ssp->clk, &ssp->clk_notifier);
1038probe_out1:
1039 return r;
1040}
1041
1042static int sifive_serial_remove(struct platform_device *dev)
1043{
1044 struct sifive_serial_port *ssp = platform_get_drvdata(dev);
1045
1046 __ssp_remove_console_port(ssp);
1047 uart_remove_one_port(&sifive_serial_uart_driver, &ssp->port);
1048 free_irq(ssp->port.irq, ssp);
1049 clk_notifier_unregister(ssp->clk, &ssp->clk_notifier);
1050
1051 return 0;
1052}
1053
1054static const struct of_device_id sifive_serial_of_match[] = {
1055 { .compatible = "sifive,fu540-c000-uart0" },
1056 { .compatible = "sifive,uart0" },
1057 {},
1058};
1059MODULE_DEVICE_TABLE(of, sifive_serial_of_match);
1060
1061static struct platform_driver sifive_serial_platform_driver = {
1062 .probe = sifive_serial_probe,
1063 .remove = sifive_serial_remove,
1064 .driver = {
1065 .name = SIFIVE_SERIAL_NAME,
1066 .of_match_table = of_match_ptr(sifive_serial_of_match),
1067 },
1068};
1069
1070static int __init sifive_serial_init(void)
1071{
1072 int r;
1073
1074 r = uart_register_driver(&sifive_serial_uart_driver);
1075 if (r)
1076 goto init_out1;
1077
1078 r = platform_driver_register(&sifive_serial_platform_driver);
1079 if (r)
1080 goto init_out2;
1081
1082 return 0;
1083
1084init_out2:
1085 uart_unregister_driver(&sifive_serial_uart_driver);
1086init_out1:
1087 return r;
1088}
1089
1090static void __exit sifive_serial_exit(void)
1091{
1092 platform_driver_unregister(&sifive_serial_platform_driver);
1093 uart_unregister_driver(&sifive_serial_uart_driver);
1094}
1095
1096module_init(sifive_serial_init);
1097module_exit(sifive_serial_exit);
1098
1099MODULE_DESCRIPTION("SiFive UART serial driver");
1100MODULE_LICENSE("GPL");
1101MODULE_AUTHOR("Paul Walmsley <paul@pwsan.com>");