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1/*
2 *Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
3 *
4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by
6 *the Free Software Foundation; version 2 of the License.
7 *
8 *This program is distributed in the hope that it will be useful,
9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 *GNU General Public License for more details.
12 *
13 *You should have received a copy of the GNU General Public License
14 *along with this program; if not, write to the Free Software
15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17#include <linux/kernel.h>
18#include <linux/serial_reg.h>
19#include <linux/slab.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/serial_core.h>
23#include <linux/interrupt.h>
24#include <linux/io.h>
25#include <linux/dmi.h>
26
27#include <linux/dmaengine.h>
28#include <linux/pch_dma.h>
29
30enum {
31 PCH_UART_HANDLED_RX_INT_SHIFT,
32 PCH_UART_HANDLED_TX_INT_SHIFT,
33 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
34 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
35 PCH_UART_HANDLED_MS_INT_SHIFT,
36};
37
38enum {
39 PCH_UART_8LINE,
40 PCH_UART_2LINE,
41};
42
43#define PCH_UART_DRIVER_DEVICE "ttyPCH"
44
45/* Set the max number of UART port
46 * Intel EG20T PCH: 4 port
47 * OKI SEMICONDUCTOR ML7213 IOH: 3 port
48 * OKI SEMICONDUCTOR ML7223 IOH: 2 port
49*/
50#define PCH_UART_NR 4
51
52#define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
53#define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
54#define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
55 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
56#define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
57 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
58#define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
59
60#define PCH_UART_RBR 0x00
61#define PCH_UART_THR 0x00
62
63#define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
64 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
65#define PCH_UART_IER_ERBFI 0x00000001
66#define PCH_UART_IER_ETBEI 0x00000002
67#define PCH_UART_IER_ELSI 0x00000004
68#define PCH_UART_IER_EDSSI 0x00000008
69
70#define PCH_UART_IIR_IP 0x00000001
71#define PCH_UART_IIR_IID 0x00000006
72#define PCH_UART_IIR_MSI 0x00000000
73#define PCH_UART_IIR_TRI 0x00000002
74#define PCH_UART_IIR_RRI 0x00000004
75#define PCH_UART_IIR_REI 0x00000006
76#define PCH_UART_IIR_TOI 0x00000008
77#define PCH_UART_IIR_FIFO256 0x00000020
78#define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
79#define PCH_UART_IIR_FE 0x000000C0
80
81#define PCH_UART_FCR_FIFOE 0x00000001
82#define PCH_UART_FCR_RFR 0x00000002
83#define PCH_UART_FCR_TFR 0x00000004
84#define PCH_UART_FCR_DMS 0x00000008
85#define PCH_UART_FCR_FIFO256 0x00000020
86#define PCH_UART_FCR_RFTL 0x000000C0
87
88#define PCH_UART_FCR_RFTL1 0x00000000
89#define PCH_UART_FCR_RFTL64 0x00000040
90#define PCH_UART_FCR_RFTL128 0x00000080
91#define PCH_UART_FCR_RFTL224 0x000000C0
92#define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
93#define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
94#define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
95#define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
96#define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
97#define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
98#define PCH_UART_FCR_RFTL_SHIFT 6
99
100#define PCH_UART_LCR_WLS 0x00000003
101#define PCH_UART_LCR_STB 0x00000004
102#define PCH_UART_LCR_PEN 0x00000008
103#define PCH_UART_LCR_EPS 0x00000010
104#define PCH_UART_LCR_SP 0x00000020
105#define PCH_UART_LCR_SB 0x00000040
106#define PCH_UART_LCR_DLAB 0x00000080
107#define PCH_UART_LCR_NP 0x00000000
108#define PCH_UART_LCR_OP PCH_UART_LCR_PEN
109#define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
110#define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
111#define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
112 PCH_UART_LCR_SP)
113
114#define PCH_UART_LCR_5BIT 0x00000000
115#define PCH_UART_LCR_6BIT 0x00000001
116#define PCH_UART_LCR_7BIT 0x00000002
117#define PCH_UART_LCR_8BIT 0x00000003
118
119#define PCH_UART_MCR_DTR 0x00000001
120#define PCH_UART_MCR_RTS 0x00000002
121#define PCH_UART_MCR_OUT 0x0000000C
122#define PCH_UART_MCR_LOOP 0x00000010
123#define PCH_UART_MCR_AFE 0x00000020
124
125#define PCH_UART_LSR_DR 0x00000001
126#define PCH_UART_LSR_ERR (1<<7)
127
128#define PCH_UART_MSR_DCTS 0x00000001
129#define PCH_UART_MSR_DDSR 0x00000002
130#define PCH_UART_MSR_TERI 0x00000004
131#define PCH_UART_MSR_DDCD 0x00000008
132#define PCH_UART_MSR_CTS 0x00000010
133#define PCH_UART_MSR_DSR 0x00000020
134#define PCH_UART_MSR_RI 0x00000040
135#define PCH_UART_MSR_DCD 0x00000080
136#define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
137 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
138
139#define PCH_UART_DLL 0x00
140#define PCH_UART_DLM 0x01
141
142#define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
143#define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
144#define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
145#define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
146#define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
147
148#define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
149#define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
150#define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
151#define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
152#define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
153#define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
154#define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
155#define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
156#define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
157#define PCH_UART_HAL_STB1 0
158#define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
159
160#define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
161#define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
162#define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
163 PCH_UART_HAL_CLR_RX_FIFO)
164
165#define PCH_UART_HAL_DMA_MODE0 0
166#define PCH_UART_HAL_FIFO_DIS 0
167#define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
168#define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
169 PCH_UART_FCR_FIFO256)
170#define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
171#define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
172#define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
173#define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
174#define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
175#define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
176#define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
177#define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
178#define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
179#define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
180#define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
181#define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
182#define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
183#define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
184
185#define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
186#define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
187#define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
188#define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
189#define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
190
191#define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
192#define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
193#define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
194#define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
195#define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
196
197#define PCI_VENDOR_ID_ROHM 0x10DB
198
199struct pch_uart_buffer {
200 unsigned char *buf;
201 int size;
202};
203
204struct eg20t_port {
205 struct uart_port port;
206 int port_type;
207 void __iomem *membase;
208 resource_size_t mapbase;
209 unsigned int iobase;
210 struct pci_dev *pdev;
211 int fifo_size;
212 int base_baud;
213 int start_tx;
214 int start_rx;
215 int tx_empty;
216 int int_dis_flag;
217 int trigger;
218 int trigger_level;
219 struct pch_uart_buffer rxbuf;
220 unsigned int dmsr;
221 unsigned int fcr;
222 unsigned int mcr;
223 unsigned int use_dma;
224 unsigned int use_dma_flag;
225 struct dma_async_tx_descriptor *desc_tx;
226 struct dma_async_tx_descriptor *desc_rx;
227 struct pch_dma_slave param_tx;
228 struct pch_dma_slave param_rx;
229 struct dma_chan *chan_tx;
230 struct dma_chan *chan_rx;
231 struct scatterlist *sg_tx_p;
232 int nent;
233 struct scatterlist sg_rx;
234 int tx_dma_use;
235 void *rx_buf_virt;
236 dma_addr_t rx_buf_dma;
237};
238
239/**
240 * struct pch_uart_driver_data - private data structure for UART-DMA
241 * @port_type: The number of DMA channel
242 * @line_no: UART port line number (0, 1, 2...)
243 */
244struct pch_uart_driver_data {
245 int port_type;
246 int line_no;
247};
248
249enum pch_uart_num_t {
250 pch_et20t_uart0 = 0,
251 pch_et20t_uart1,
252 pch_et20t_uart2,
253 pch_et20t_uart3,
254 pch_ml7213_uart0,
255 pch_ml7213_uart1,
256 pch_ml7213_uart2,
257 pch_ml7223_uart0,
258 pch_ml7223_uart1,
259};
260
261static struct pch_uart_driver_data drv_dat[] = {
262 [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
263 [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
264 [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
265 [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
266 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
267 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
268 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
269 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
270 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
271};
272
273static unsigned int default_baud = 9600;
274static const int trigger_level_256[4] = { 1, 64, 128, 224 };
275static const int trigger_level_64[4] = { 1, 16, 32, 56 };
276static const int trigger_level_16[4] = { 1, 4, 8, 14 };
277static const int trigger_level_1[4] = { 1, 1, 1, 1 };
278
279static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize,
280 int base_baud)
281{
282 struct eg20t_port *priv = pci_get_drvdata(pdev);
283
284 priv->trigger_level = 1;
285 priv->fcr = 0;
286}
287
288static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base)
289{
290 unsigned int msr = ioread8(base + UART_MSR);
291 priv->dmsr |= msr & PCH_UART_MSR_DELTA;
292
293 return msr;
294}
295
296static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
297 unsigned int flag)
298{
299 u8 ier = ioread8(priv->membase + UART_IER);
300 ier |= flag & PCH_UART_IER_MASK;
301 iowrite8(ier, priv->membase + UART_IER);
302}
303
304static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
305 unsigned int flag)
306{
307 u8 ier = ioread8(priv->membase + UART_IER);
308 ier &= ~(flag & PCH_UART_IER_MASK);
309 iowrite8(ier, priv->membase + UART_IER);
310}
311
312static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
313 unsigned int parity, unsigned int bits,
314 unsigned int stb)
315{
316 unsigned int dll, dlm, lcr;
317 int div;
318
319 div = DIV_ROUND_CLOSEST(priv->base_baud / 16, baud);
320 if (div < 0 || USHRT_MAX <= div) {
321 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
322 return -EINVAL;
323 }
324
325 dll = (unsigned int)div & 0x00FFU;
326 dlm = ((unsigned int)div >> 8) & 0x00FFU;
327
328 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
329 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
330 return -EINVAL;
331 }
332
333 if (bits & ~PCH_UART_LCR_WLS) {
334 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
335 return -EINVAL;
336 }
337
338 if (stb & ~PCH_UART_LCR_STB) {
339 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
340 return -EINVAL;
341 }
342
343 lcr = parity;
344 lcr |= bits;
345 lcr |= stb;
346
347 dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
348 __func__, baud, div, lcr, jiffies);
349 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
350 iowrite8(dll, priv->membase + PCH_UART_DLL);
351 iowrite8(dlm, priv->membase + PCH_UART_DLM);
352 iowrite8(lcr, priv->membase + UART_LCR);
353
354 return 0;
355}
356
357static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
358 unsigned int flag)
359{
360 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
361 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
362 __func__, flag);
363 return -EINVAL;
364 }
365
366 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
367 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
368 priv->membase + UART_FCR);
369 iowrite8(priv->fcr, priv->membase + UART_FCR);
370
371 return 0;
372}
373
374static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
375 unsigned int dmamode,
376 unsigned int fifo_size, unsigned int trigger)
377{
378 u8 fcr;
379
380 if (dmamode & ~PCH_UART_FCR_DMS) {
381 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
382 __func__, dmamode);
383 return -EINVAL;
384 }
385
386 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
387 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
388 __func__, fifo_size);
389 return -EINVAL;
390 }
391
392 if (trigger & ~PCH_UART_FCR_RFTL) {
393 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
394 __func__, trigger);
395 return -EINVAL;
396 }
397
398 switch (priv->fifo_size) {
399 case 256:
400 priv->trigger_level =
401 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
402 break;
403 case 64:
404 priv->trigger_level =
405 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
406 break;
407 case 16:
408 priv->trigger_level =
409 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
410 break;
411 default:
412 priv->trigger_level =
413 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
414 break;
415 }
416 fcr =
417 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
418 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
419 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
420 priv->membase + UART_FCR);
421 iowrite8(fcr, priv->membase + UART_FCR);
422 priv->fcr = fcr;
423
424 return 0;
425}
426
427static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
428{
429 priv->dmsr = 0;
430 return get_msr(priv, priv->membase);
431}
432
433static void pch_uart_hal_write(struct eg20t_port *priv,
434 const unsigned char *buf, int tx_size)
435{
436 int i;
437 unsigned int thr;
438
439 for (i = 0; i < tx_size;) {
440 thr = buf[i++];
441 iowrite8(thr, priv->membase + PCH_UART_THR);
442 }
443}
444
445static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
446 int rx_size)
447{
448 int i;
449 u8 rbr, lsr;
450
451 lsr = ioread8(priv->membase + UART_LSR);
452 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
453 i < rx_size && lsr & UART_LSR_DR;
454 lsr = ioread8(priv->membase + UART_LSR)) {
455 rbr = ioread8(priv->membase + PCH_UART_RBR);
456 buf[i++] = rbr;
457 }
458 return i;
459}
460
461static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
462{
463 unsigned int iir;
464 int ret;
465
466 iir = ioread8(priv->membase + UART_IIR);
467 ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
468 return ret;
469}
470
471static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
472{
473 return ioread8(priv->membase + UART_LSR);
474}
475
476static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
477{
478 unsigned int lcr;
479
480 lcr = ioread8(priv->membase + UART_LCR);
481 if (on)
482 lcr |= PCH_UART_LCR_SB;
483 else
484 lcr &= ~PCH_UART_LCR_SB;
485
486 iowrite8(lcr, priv->membase + UART_LCR);
487}
488
489static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
490 int size)
491{
492 struct uart_port *port;
493 struct tty_struct *tty;
494
495 port = &priv->port;
496 tty = tty_port_tty_get(&port->state->port);
497 if (!tty) {
498 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
499 return -EBUSY;
500 }
501
502 tty_insert_flip_string(tty, buf, size);
503 tty_flip_buffer_push(tty);
504 tty_kref_put(tty);
505
506 return 0;
507}
508
509static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
510{
511 int ret;
512 struct uart_port *port = &priv->port;
513
514 if (port->x_char) {
515 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
516 __func__, port->x_char, jiffies);
517 buf[0] = port->x_char;
518 port->x_char = 0;
519 ret = 1;
520 } else {
521 ret = 0;
522 }
523
524 return ret;
525}
526
527static int dma_push_rx(struct eg20t_port *priv, int size)
528{
529 struct tty_struct *tty;
530 int room;
531 struct uart_port *port = &priv->port;
532
533 port = &priv->port;
534 tty = tty_port_tty_get(&port->state->port);
535 if (!tty) {
536 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
537 return 0;
538 }
539
540 room = tty_buffer_request_room(tty, size);
541
542 if (room < size)
543 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
544 size - room);
545 if (!room)
546 return room;
547
548 tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
549
550 port->icount.rx += room;
551 tty_kref_put(tty);
552
553 return room;
554}
555
556static void pch_free_dma(struct uart_port *port)
557{
558 struct eg20t_port *priv;
559 priv = container_of(port, struct eg20t_port, port);
560
561 if (priv->chan_tx) {
562 dma_release_channel(priv->chan_tx);
563 priv->chan_tx = NULL;
564 }
565 if (priv->chan_rx) {
566 dma_release_channel(priv->chan_rx);
567 priv->chan_rx = NULL;
568 }
569 if (sg_dma_address(&priv->sg_rx))
570 dma_free_coherent(port->dev, port->fifosize,
571 sg_virt(&priv->sg_rx),
572 sg_dma_address(&priv->sg_rx));
573
574 return;
575}
576
577static bool filter(struct dma_chan *chan, void *slave)
578{
579 struct pch_dma_slave *param = slave;
580
581 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
582 chan->device->dev)) {
583 chan->private = param;
584 return true;
585 } else {
586 return false;
587 }
588}
589
590static void pch_request_dma(struct uart_port *port)
591{
592 dma_cap_mask_t mask;
593 struct dma_chan *chan;
594 struct pci_dev *dma_dev;
595 struct pch_dma_slave *param;
596 struct eg20t_port *priv =
597 container_of(port, struct eg20t_port, port);
598 dma_cap_zero(mask);
599 dma_cap_set(DMA_SLAVE, mask);
600
601 dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
602 PCI_DEVFN(0xa, 0)); /* Get DMA's dev
603 information */
604 /* Set Tx DMA */
605 param = &priv->param_tx;
606 param->dma_dev = &dma_dev->dev;
607 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
608
609 param->tx_reg = port->mapbase + UART_TX;
610 chan = dma_request_channel(mask, filter, param);
611 if (!chan) {
612 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
613 __func__);
614 return;
615 }
616 priv->chan_tx = chan;
617
618 /* Set Rx DMA */
619 param = &priv->param_rx;
620 param->dma_dev = &dma_dev->dev;
621 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
622
623 param->rx_reg = port->mapbase + UART_RX;
624 chan = dma_request_channel(mask, filter, param);
625 if (!chan) {
626 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
627 __func__);
628 dma_release_channel(priv->chan_tx);
629 return;
630 }
631
632 /* Get Consistent memory for DMA */
633 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
634 &priv->rx_buf_dma, GFP_KERNEL);
635 priv->chan_rx = chan;
636}
637
638static void pch_dma_rx_complete(void *arg)
639{
640 struct eg20t_port *priv = arg;
641 struct uart_port *port = &priv->port;
642 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
643 int count;
644
645 if (!tty) {
646 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
647 return;
648 }
649
650 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
651 count = dma_push_rx(priv, priv->trigger_level);
652 if (count)
653 tty_flip_buffer_push(tty);
654 tty_kref_put(tty);
655 async_tx_ack(priv->desc_rx);
656 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
657}
658
659static void pch_dma_tx_complete(void *arg)
660{
661 struct eg20t_port *priv = arg;
662 struct uart_port *port = &priv->port;
663 struct circ_buf *xmit = &port->state->xmit;
664 struct scatterlist *sg = priv->sg_tx_p;
665 int i;
666
667 for (i = 0; i < priv->nent; i++, sg++) {
668 xmit->tail += sg_dma_len(sg);
669 port->icount.tx += sg_dma_len(sg);
670 }
671 xmit->tail &= UART_XMIT_SIZE - 1;
672 async_tx_ack(priv->desc_tx);
673 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
674 priv->tx_dma_use = 0;
675 priv->nent = 0;
676 kfree(priv->sg_tx_p);
677 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
678}
679
680static int pop_tx(struct eg20t_port *priv, int size)
681{
682 int count = 0;
683 struct uart_port *port = &priv->port;
684 struct circ_buf *xmit = &port->state->xmit;
685
686 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
687 goto pop_tx_end;
688
689 do {
690 int cnt_to_end =
691 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
692 int sz = min(size - count, cnt_to_end);
693 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
694 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
695 count += sz;
696 } while (!uart_circ_empty(xmit) && count < size);
697
698pop_tx_end:
699 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
700 count, size - count, jiffies);
701
702 return count;
703}
704
705static int handle_rx_to(struct eg20t_port *priv)
706{
707 struct pch_uart_buffer *buf;
708 int rx_size;
709 int ret;
710 if (!priv->start_rx) {
711 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
712 return 0;
713 }
714 buf = &priv->rxbuf;
715 do {
716 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
717 ret = push_rx(priv, buf->buf, rx_size);
718 if (ret)
719 return 0;
720 } while (rx_size == buf->size);
721
722 return PCH_UART_HANDLED_RX_INT;
723}
724
725static int handle_rx(struct eg20t_port *priv)
726{
727 return handle_rx_to(priv);
728}
729
730static int dma_handle_rx(struct eg20t_port *priv)
731{
732 struct uart_port *port = &priv->port;
733 struct dma_async_tx_descriptor *desc;
734 struct scatterlist *sg;
735
736 priv = container_of(port, struct eg20t_port, port);
737 sg = &priv->sg_rx;
738
739 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
740
741 sg_dma_len(sg) = priv->trigger_level;
742
743 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
744 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
745 ~PAGE_MASK);
746
747 sg_dma_address(sg) = priv->rx_buf_dma;
748
749 desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
750 sg, 1, DMA_FROM_DEVICE,
751 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
752
753 if (!desc)
754 return 0;
755
756 priv->desc_rx = desc;
757 desc->callback = pch_dma_rx_complete;
758 desc->callback_param = priv;
759 desc->tx_submit(desc);
760 dma_async_issue_pending(priv->chan_rx);
761
762 return PCH_UART_HANDLED_RX_INT;
763}
764
765static unsigned int handle_tx(struct eg20t_port *priv)
766{
767 struct uart_port *port = &priv->port;
768 struct circ_buf *xmit = &port->state->xmit;
769 int fifo_size;
770 int tx_size;
771 int size;
772 int tx_empty;
773
774 if (!priv->start_tx) {
775 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
776 __func__, jiffies);
777 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
778 priv->tx_empty = 1;
779 return 0;
780 }
781
782 fifo_size = max(priv->fifo_size, 1);
783 tx_empty = 1;
784 if (pop_tx_x(priv, xmit->buf)) {
785 pch_uart_hal_write(priv, xmit->buf, 1);
786 port->icount.tx++;
787 tx_empty = 0;
788 fifo_size--;
789 }
790 size = min(xmit->head - xmit->tail, fifo_size);
791 if (size < 0)
792 size = fifo_size;
793
794 tx_size = pop_tx(priv, size);
795 if (tx_size > 0) {
796 port->icount.tx += tx_size;
797 tx_empty = 0;
798 }
799
800 priv->tx_empty = tx_empty;
801
802 if (tx_empty) {
803 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
804 uart_write_wakeup(port);
805 }
806
807 return PCH_UART_HANDLED_TX_INT;
808}
809
810static unsigned int dma_handle_tx(struct eg20t_port *priv)
811{
812 struct uart_port *port = &priv->port;
813 struct circ_buf *xmit = &port->state->xmit;
814 struct scatterlist *sg;
815 int nent;
816 int fifo_size;
817 int tx_empty;
818 struct dma_async_tx_descriptor *desc;
819 int num;
820 int i;
821 int bytes;
822 int size;
823 int rem;
824
825 if (!priv->start_tx) {
826 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
827 __func__, jiffies);
828 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
829 priv->tx_empty = 1;
830 return 0;
831 }
832
833 if (priv->tx_dma_use) {
834 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
835 __func__, jiffies);
836 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
837 priv->tx_empty = 1;
838 return 0;
839 }
840
841 fifo_size = max(priv->fifo_size, 1);
842 tx_empty = 1;
843 if (pop_tx_x(priv, xmit->buf)) {
844 pch_uart_hal_write(priv, xmit->buf, 1);
845 port->icount.tx++;
846 tx_empty = 0;
847 fifo_size--;
848 }
849
850 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
851 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
852 xmit->tail, UART_XMIT_SIZE));
853 if (!bytes) {
854 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
855 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
856 uart_write_wakeup(port);
857 return 0;
858 }
859
860 if (bytes > fifo_size) {
861 num = bytes / fifo_size + 1;
862 size = fifo_size;
863 rem = bytes % fifo_size;
864 } else {
865 num = 1;
866 size = bytes;
867 rem = bytes;
868 }
869
870 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
871 __func__, num, size, rem);
872
873 priv->tx_dma_use = 1;
874
875 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
876
877 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
878 sg = priv->sg_tx_p;
879
880 for (i = 0; i < num; i++, sg++) {
881 if (i == (num - 1))
882 sg_set_page(sg, virt_to_page(xmit->buf),
883 rem, fifo_size * i);
884 else
885 sg_set_page(sg, virt_to_page(xmit->buf),
886 size, fifo_size * i);
887 }
888
889 sg = priv->sg_tx_p;
890 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
891 if (!nent) {
892 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
893 return 0;
894 }
895 priv->nent = nent;
896
897 for (i = 0; i < nent; i++, sg++) {
898 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
899 fifo_size * i;
900 sg_dma_address(sg) = (sg_dma_address(sg) &
901 ~(UART_XMIT_SIZE - 1)) + sg->offset;
902 if (i == (nent - 1))
903 sg_dma_len(sg) = rem;
904 else
905 sg_dma_len(sg) = size;
906 }
907
908 desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
909 priv->sg_tx_p, nent, DMA_TO_DEVICE,
910 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
911 if (!desc) {
912 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
913 __func__);
914 return 0;
915 }
916 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
917 priv->desc_tx = desc;
918 desc->callback = pch_dma_tx_complete;
919 desc->callback_param = priv;
920
921 desc->tx_submit(desc);
922
923 dma_async_issue_pending(priv->chan_tx);
924
925 return PCH_UART_HANDLED_TX_INT;
926}
927
928static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
929{
930 u8 fcr = ioread8(priv->membase + UART_FCR);
931
932 /* Reset FIFO */
933 fcr |= UART_FCR_CLEAR_RCVR;
934 iowrite8(fcr, priv->membase + UART_FCR);
935
936 if (lsr & PCH_UART_LSR_ERR)
937 dev_err(&priv->pdev->dev, "Error data in FIFO\n");
938
939 if (lsr & UART_LSR_FE)
940 dev_err(&priv->pdev->dev, "Framing Error\n");
941
942 if (lsr & UART_LSR_PE)
943 dev_err(&priv->pdev->dev, "Parity Error\n");
944
945 if (lsr & UART_LSR_OE)
946 dev_err(&priv->pdev->dev, "Overrun Error\n");
947}
948
949static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
950{
951 struct eg20t_port *priv = dev_id;
952 unsigned int handled;
953 u8 lsr;
954 int ret = 0;
955 unsigned int iid;
956 unsigned long flags;
957
958 spin_lock_irqsave(&priv->port.lock, flags);
959 handled = 0;
960 while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
961 switch (iid) {
962 case PCH_UART_IID_RLS: /* Receiver Line Status */
963 lsr = pch_uart_hal_get_line_status(priv);
964 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
965 UART_LSR_PE | UART_LSR_OE)) {
966 pch_uart_err_ir(priv, lsr);
967 ret = PCH_UART_HANDLED_RX_ERR_INT;
968 }
969 break;
970 case PCH_UART_IID_RDR: /* Received Data Ready */
971 if (priv->use_dma) {
972 pch_uart_hal_disable_interrupt(priv,
973 PCH_UART_HAL_RX_INT);
974 ret = dma_handle_rx(priv);
975 if (!ret)
976 pch_uart_hal_enable_interrupt(priv,
977 PCH_UART_HAL_RX_INT);
978 } else {
979 ret = handle_rx(priv);
980 }
981 break;
982 case PCH_UART_IID_RDR_TO: /* Received Data Ready
983 (FIFO Timeout) */
984 ret = handle_rx_to(priv);
985 break;
986 case PCH_UART_IID_THRE: /* Transmitter Holding Register
987 Empty */
988 if (priv->use_dma)
989 ret = dma_handle_tx(priv);
990 else
991 ret = handle_tx(priv);
992 break;
993 case PCH_UART_IID_MS: /* Modem Status */
994 ret = PCH_UART_HANDLED_MS_INT;
995 break;
996 default: /* Never junp to this label */
997 dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__,
998 iid, jiffies);
999 ret = -1;
1000 break;
1001 }
1002 handled |= (unsigned int)ret;
1003 }
1004 if (handled == 0 && iid <= 1) {
1005 if (priv->int_dis_flag)
1006 priv->int_dis_flag = 0;
1007 }
1008
1009 spin_unlock_irqrestore(&priv->port.lock, flags);
1010 return IRQ_RETVAL(handled);
1011}
1012
1013/* This function tests whether the transmitter fifo and shifter for the port
1014 described by 'port' is empty. */
1015static unsigned int pch_uart_tx_empty(struct uart_port *port)
1016{
1017 struct eg20t_port *priv;
1018 int ret;
1019 priv = container_of(port, struct eg20t_port, port);
1020 if (priv->tx_empty)
1021 ret = TIOCSER_TEMT;
1022 else
1023 ret = 0;
1024
1025 return ret;
1026}
1027
1028/* Returns the current state of modem control inputs. */
1029static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1030{
1031 struct eg20t_port *priv;
1032 u8 modem;
1033 unsigned int ret = 0;
1034
1035 priv = container_of(port, struct eg20t_port, port);
1036 modem = pch_uart_hal_get_modem(priv);
1037
1038 if (modem & UART_MSR_DCD)
1039 ret |= TIOCM_CAR;
1040
1041 if (modem & UART_MSR_RI)
1042 ret |= TIOCM_RNG;
1043
1044 if (modem & UART_MSR_DSR)
1045 ret |= TIOCM_DSR;
1046
1047 if (modem & UART_MSR_CTS)
1048 ret |= TIOCM_CTS;
1049
1050 return ret;
1051}
1052
1053static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1054{
1055 u32 mcr = 0;
1056 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1057
1058 if (mctrl & TIOCM_DTR)
1059 mcr |= UART_MCR_DTR;
1060 if (mctrl & TIOCM_RTS)
1061 mcr |= UART_MCR_RTS;
1062 if (mctrl & TIOCM_LOOP)
1063 mcr |= UART_MCR_LOOP;
1064
1065 if (priv->mcr & UART_MCR_AFE)
1066 mcr |= UART_MCR_AFE;
1067
1068 if (mctrl)
1069 iowrite8(mcr, priv->membase + UART_MCR);
1070}
1071
1072static void pch_uart_stop_tx(struct uart_port *port)
1073{
1074 struct eg20t_port *priv;
1075 priv = container_of(port, struct eg20t_port, port);
1076 priv->start_tx = 0;
1077 priv->tx_dma_use = 0;
1078}
1079
1080static void pch_uart_start_tx(struct uart_port *port)
1081{
1082 struct eg20t_port *priv;
1083
1084 priv = container_of(port, struct eg20t_port, port);
1085
1086 if (priv->use_dma) {
1087 if (priv->tx_dma_use) {
1088 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1089 __func__);
1090 return;
1091 }
1092 }
1093
1094 priv->start_tx = 1;
1095 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1096}
1097
1098static void pch_uart_stop_rx(struct uart_port *port)
1099{
1100 struct eg20t_port *priv;
1101 priv = container_of(port, struct eg20t_port, port);
1102 priv->start_rx = 0;
1103 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
1104 priv->int_dis_flag = 1;
1105}
1106
1107/* Enable the modem status interrupts. */
1108static void pch_uart_enable_ms(struct uart_port *port)
1109{
1110 struct eg20t_port *priv;
1111 priv = container_of(port, struct eg20t_port, port);
1112 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1113}
1114
1115/* Control the transmission of a break signal. */
1116static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1117{
1118 struct eg20t_port *priv;
1119 unsigned long flags;
1120
1121 priv = container_of(port, struct eg20t_port, port);
1122 spin_lock_irqsave(&port->lock, flags);
1123 pch_uart_hal_set_break(priv, ctl);
1124 spin_unlock_irqrestore(&port->lock, flags);
1125}
1126
1127/* Grab any interrupt resources and initialise any low level driver state. */
1128static int pch_uart_startup(struct uart_port *port)
1129{
1130 struct eg20t_port *priv;
1131 int ret;
1132 int fifo_size;
1133 int trigger_level;
1134
1135 priv = container_of(port, struct eg20t_port, port);
1136 priv->tx_empty = 1;
1137
1138 if (port->uartclk)
1139 priv->base_baud = port->uartclk;
1140 else
1141 port->uartclk = priv->base_baud;
1142
1143 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1144 ret = pch_uart_hal_set_line(priv, default_baud,
1145 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1146 PCH_UART_HAL_STB1);
1147 if (ret)
1148 return ret;
1149
1150 switch (priv->fifo_size) {
1151 case 256:
1152 fifo_size = PCH_UART_HAL_FIFO256;
1153 break;
1154 case 64:
1155 fifo_size = PCH_UART_HAL_FIFO64;
1156 break;
1157 case 16:
1158 fifo_size = PCH_UART_HAL_FIFO16;
1159 case 1:
1160 default:
1161 fifo_size = PCH_UART_HAL_FIFO_DIS;
1162 break;
1163 }
1164
1165 switch (priv->trigger) {
1166 case PCH_UART_HAL_TRIGGER1:
1167 trigger_level = 1;
1168 break;
1169 case PCH_UART_HAL_TRIGGER_L:
1170 trigger_level = priv->fifo_size / 4;
1171 break;
1172 case PCH_UART_HAL_TRIGGER_M:
1173 trigger_level = priv->fifo_size / 2;
1174 break;
1175 case PCH_UART_HAL_TRIGGER_H:
1176 default:
1177 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1178 break;
1179 }
1180
1181 priv->trigger_level = trigger_level;
1182 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1183 fifo_size, priv->trigger);
1184 if (ret < 0)
1185 return ret;
1186
1187 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1188 KBUILD_MODNAME, priv);
1189 if (ret < 0)
1190 return ret;
1191
1192 if (priv->use_dma)
1193 pch_request_dma(port);
1194
1195 priv->start_rx = 1;
1196 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
1197 uart_update_timeout(port, CS8, default_baud);
1198
1199 return 0;
1200}
1201
1202static void pch_uart_shutdown(struct uart_port *port)
1203{
1204 struct eg20t_port *priv;
1205 int ret;
1206
1207 priv = container_of(port, struct eg20t_port, port);
1208 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1209 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1210 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1211 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1212 if (ret)
1213 dev_err(priv->port.dev,
1214 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1215
1216 if (priv->use_dma_flag)
1217 pch_free_dma(port);
1218
1219 free_irq(priv->port.irq, priv);
1220}
1221
1222/* Change the port parameters, including word length, parity, stop
1223 *bits. Update read_status_mask and ignore_status_mask to indicate
1224 *the types of events we are interested in receiving. */
1225static void pch_uart_set_termios(struct uart_port *port,
1226 struct ktermios *termios, struct ktermios *old)
1227{
1228 int baud;
1229 int rtn;
1230 unsigned int parity, bits, stb;
1231 struct eg20t_port *priv;
1232 unsigned long flags;
1233
1234 priv = container_of(port, struct eg20t_port, port);
1235 switch (termios->c_cflag & CSIZE) {
1236 case CS5:
1237 bits = PCH_UART_HAL_5BIT;
1238 break;
1239 case CS6:
1240 bits = PCH_UART_HAL_6BIT;
1241 break;
1242 case CS7:
1243 bits = PCH_UART_HAL_7BIT;
1244 break;
1245 default: /* CS8 */
1246 bits = PCH_UART_HAL_8BIT;
1247 break;
1248 }
1249 if (termios->c_cflag & CSTOPB)
1250 stb = PCH_UART_HAL_STB2;
1251 else
1252 stb = PCH_UART_HAL_STB1;
1253
1254 if (termios->c_cflag & PARENB) {
1255 if (!(termios->c_cflag & PARODD))
1256 parity = PCH_UART_HAL_PARITY_ODD;
1257 else
1258 parity = PCH_UART_HAL_PARITY_EVEN;
1259
1260 } else {
1261 parity = PCH_UART_HAL_PARITY_NONE;
1262 }
1263
1264 /* Only UART0 has auto hardware flow function */
1265 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1266 priv->mcr |= UART_MCR_AFE;
1267 else
1268 priv->mcr &= ~UART_MCR_AFE;
1269
1270 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1271
1272 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1273
1274 spin_lock_irqsave(&port->lock, flags);
1275
1276 uart_update_timeout(port, termios->c_cflag, baud);
1277 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1278 if (rtn)
1279 goto out;
1280
1281 /* Don't rewrite B0 */
1282 if (tty_termios_baud_rate(termios))
1283 tty_termios_encode_baud_rate(termios, baud, baud);
1284
1285out:
1286 spin_unlock_irqrestore(&port->lock, flags);
1287}
1288
1289static const char *pch_uart_type(struct uart_port *port)
1290{
1291 return KBUILD_MODNAME;
1292}
1293
1294static void pch_uart_release_port(struct uart_port *port)
1295{
1296 struct eg20t_port *priv;
1297
1298 priv = container_of(port, struct eg20t_port, port);
1299 pci_iounmap(priv->pdev, priv->membase);
1300 pci_release_regions(priv->pdev);
1301}
1302
1303static int pch_uart_request_port(struct uart_port *port)
1304{
1305 struct eg20t_port *priv;
1306 int ret;
1307 void __iomem *membase;
1308
1309 priv = container_of(port, struct eg20t_port, port);
1310 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1311 if (ret < 0)
1312 return -EBUSY;
1313
1314 membase = pci_iomap(priv->pdev, 1, 0);
1315 if (!membase) {
1316 pci_release_regions(priv->pdev);
1317 return -EBUSY;
1318 }
1319 priv->membase = port->membase = membase;
1320
1321 return 0;
1322}
1323
1324static void pch_uart_config_port(struct uart_port *port, int type)
1325{
1326 struct eg20t_port *priv;
1327
1328 priv = container_of(port, struct eg20t_port, port);
1329 if (type & UART_CONFIG_TYPE) {
1330 port->type = priv->port_type;
1331 pch_uart_request_port(port);
1332 }
1333}
1334
1335static int pch_uart_verify_port(struct uart_port *port,
1336 struct serial_struct *serinfo)
1337{
1338 struct eg20t_port *priv;
1339
1340 priv = container_of(port, struct eg20t_port, port);
1341 if (serinfo->flags & UPF_LOW_LATENCY) {
1342 dev_info(priv->port.dev,
1343 "PCH UART : Use PIO Mode (without DMA)\n");
1344 priv->use_dma = 0;
1345 serinfo->flags &= ~UPF_LOW_LATENCY;
1346 } else {
1347#ifndef CONFIG_PCH_DMA
1348 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1349 __func__);
1350 return -EOPNOTSUPP;
1351#endif
1352 priv->use_dma = 1;
1353 priv->use_dma_flag = 1;
1354 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1355 }
1356
1357 return 0;
1358}
1359
1360static struct uart_ops pch_uart_ops = {
1361 .tx_empty = pch_uart_tx_empty,
1362 .set_mctrl = pch_uart_set_mctrl,
1363 .get_mctrl = pch_uart_get_mctrl,
1364 .stop_tx = pch_uart_stop_tx,
1365 .start_tx = pch_uart_start_tx,
1366 .stop_rx = pch_uart_stop_rx,
1367 .enable_ms = pch_uart_enable_ms,
1368 .break_ctl = pch_uart_break_ctl,
1369 .startup = pch_uart_startup,
1370 .shutdown = pch_uart_shutdown,
1371 .set_termios = pch_uart_set_termios,
1372/* .pm = pch_uart_pm, Not supported yet */
1373/* .set_wake = pch_uart_set_wake, Not supported yet */
1374 .type = pch_uart_type,
1375 .release_port = pch_uart_release_port,
1376 .request_port = pch_uart_request_port,
1377 .config_port = pch_uart_config_port,
1378 .verify_port = pch_uart_verify_port
1379};
1380
1381static struct uart_driver pch_uart_driver = {
1382 .owner = THIS_MODULE,
1383 .driver_name = KBUILD_MODNAME,
1384 .dev_name = PCH_UART_DRIVER_DEVICE,
1385 .major = 0,
1386 .minor = 0,
1387 .nr = PCH_UART_NR,
1388};
1389
1390static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1391 const struct pci_device_id *id)
1392{
1393 struct eg20t_port *priv;
1394 int ret;
1395 unsigned int iobase;
1396 unsigned int mapbase;
1397 unsigned char *rxbuf;
1398 int fifosize, base_baud;
1399 int port_type;
1400 struct pch_uart_driver_data *board;
1401 const char *board_name;
1402
1403 board = &drv_dat[id->driver_data];
1404 port_type = board->port_type;
1405
1406 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1407 if (priv == NULL)
1408 goto init_port_alloc_err;
1409
1410 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1411 if (!rxbuf)
1412 goto init_port_free_txbuf;
1413
1414 base_baud = 1843200; /* 1.8432MHz */
1415
1416 /* quirk for CM-iTC board */
1417 board_name = dmi_get_system_info(DMI_BOARD_NAME);
1418 if (board_name && strstr(board_name, "CM-iTC"))
1419 base_baud = 192000000; /* 192.0MHz */
1420
1421 switch (port_type) {
1422 case PORT_UNKNOWN:
1423 fifosize = 256; /* EG20T/ML7213: UART0 */
1424 break;
1425 case PORT_8250:
1426 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1427 break;
1428 default:
1429 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1430 goto init_port_hal_free;
1431 }
1432
1433 pci_enable_msi(pdev);
1434
1435 iobase = pci_resource_start(pdev, 0);
1436 mapbase = pci_resource_start(pdev, 1);
1437 priv->mapbase = mapbase;
1438 priv->iobase = iobase;
1439 priv->pdev = pdev;
1440 priv->tx_empty = 1;
1441 priv->rxbuf.buf = rxbuf;
1442 priv->rxbuf.size = PAGE_SIZE;
1443
1444 priv->fifo_size = fifosize;
1445 priv->base_baud = base_baud;
1446 priv->port_type = PORT_MAX_8250 + port_type + 1;
1447 priv->port.dev = &pdev->dev;
1448 priv->port.iobase = iobase;
1449 priv->port.membase = NULL;
1450 priv->port.mapbase = mapbase;
1451 priv->port.irq = pdev->irq;
1452 priv->port.iotype = UPIO_PORT;
1453 priv->port.ops = &pch_uart_ops;
1454 priv->port.flags = UPF_BOOT_AUTOCONF;
1455 priv->port.fifosize = fifosize;
1456 priv->port.line = board->line_no;
1457 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1458
1459 spin_lock_init(&priv->port.lock);
1460
1461 pci_set_drvdata(pdev, priv);
1462 pch_uart_hal_request(pdev, fifosize, base_baud);
1463
1464 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1465 if (ret < 0)
1466 goto init_port_hal_free;
1467
1468 return priv;
1469
1470init_port_hal_free:
1471 free_page((unsigned long)rxbuf);
1472init_port_free_txbuf:
1473 kfree(priv);
1474init_port_alloc_err:
1475
1476 return NULL;
1477}
1478
1479static void pch_uart_exit_port(struct eg20t_port *priv)
1480{
1481 uart_remove_one_port(&pch_uart_driver, &priv->port);
1482 pci_set_drvdata(priv->pdev, NULL);
1483 free_page((unsigned long)priv->rxbuf.buf);
1484}
1485
1486static void pch_uart_pci_remove(struct pci_dev *pdev)
1487{
1488 struct eg20t_port *priv;
1489
1490 priv = (struct eg20t_port *)pci_get_drvdata(pdev);
1491
1492 pci_disable_msi(pdev);
1493 pch_uart_exit_port(priv);
1494 pci_disable_device(pdev);
1495 kfree(priv);
1496 return;
1497}
1498#ifdef CONFIG_PM
1499static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1500{
1501 struct eg20t_port *priv = pci_get_drvdata(pdev);
1502
1503 uart_suspend_port(&pch_uart_driver, &priv->port);
1504
1505 pci_save_state(pdev);
1506 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1507 return 0;
1508}
1509
1510static int pch_uart_pci_resume(struct pci_dev *pdev)
1511{
1512 struct eg20t_port *priv = pci_get_drvdata(pdev);
1513 int ret;
1514
1515 pci_set_power_state(pdev, PCI_D0);
1516 pci_restore_state(pdev);
1517
1518 ret = pci_enable_device(pdev);
1519 if (ret) {
1520 dev_err(&pdev->dev,
1521 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1522 return ret;
1523 }
1524
1525 uart_resume_port(&pch_uart_driver, &priv->port);
1526
1527 return 0;
1528}
1529#else
1530#define pch_uart_pci_suspend NULL
1531#define pch_uart_pci_resume NULL
1532#endif
1533
1534static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1535 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1536 .driver_data = pch_et20t_uart0},
1537 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1538 .driver_data = pch_et20t_uart1},
1539 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1540 .driver_data = pch_et20t_uart2},
1541 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1542 .driver_data = pch_et20t_uart3},
1543 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1544 .driver_data = pch_ml7213_uart0},
1545 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1546 .driver_data = pch_ml7213_uart1},
1547 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1548 .driver_data = pch_ml7213_uart2},
1549 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1550 .driver_data = pch_ml7223_uart0},
1551 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1552 .driver_data = pch_ml7223_uart1},
1553 {0,},
1554};
1555
1556static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1557 const struct pci_device_id *id)
1558{
1559 int ret;
1560 struct eg20t_port *priv;
1561
1562 ret = pci_enable_device(pdev);
1563 if (ret < 0)
1564 goto probe_error;
1565
1566 priv = pch_uart_init_port(pdev, id);
1567 if (!priv) {
1568 ret = -EBUSY;
1569 goto probe_disable_device;
1570 }
1571 pci_set_drvdata(pdev, priv);
1572
1573 return ret;
1574
1575probe_disable_device:
1576 pci_disable_msi(pdev);
1577 pci_disable_device(pdev);
1578probe_error:
1579 return ret;
1580}
1581
1582static struct pci_driver pch_uart_pci_driver = {
1583 .name = "pch_uart",
1584 .id_table = pch_uart_pci_id,
1585 .probe = pch_uart_pci_probe,
1586 .remove = __devexit_p(pch_uart_pci_remove),
1587 .suspend = pch_uart_pci_suspend,
1588 .resume = pch_uart_pci_resume,
1589};
1590
1591static int __init pch_uart_module_init(void)
1592{
1593 int ret;
1594
1595 /* register as UART driver */
1596 ret = uart_register_driver(&pch_uart_driver);
1597 if (ret < 0)
1598 return ret;
1599
1600 /* register as PCI driver */
1601 ret = pci_register_driver(&pch_uart_pci_driver);
1602 if (ret < 0)
1603 uart_unregister_driver(&pch_uart_driver);
1604
1605 return ret;
1606}
1607module_init(pch_uart_module_init);
1608
1609static void __exit pch_uart_module_exit(void)
1610{
1611 pci_unregister_driver(&pch_uart_pci_driver);
1612 uart_unregister_driver(&pch_uart_driver);
1613}
1614module_exit(pch_uart_module_exit);
1615
1616MODULE_LICENSE("GPL v2");
1617MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1618module_param(default_baud, uint, S_IRUGO);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 */
5#include <linux/kernel.h>
6#include <linux/serial_reg.h>
7#include <linux/slab.h>
8#include <linux/module.h>
9#include <linux/pci.h>
10#include <linux/console.h>
11#include <linux/serial_core.h>
12#include <linux/tty.h>
13#include <linux/tty_flip.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/dmi.h>
17#include <linux/nmi.h>
18#include <linux/delay.h>
19#include <linux/of.h>
20
21#include <linux/debugfs.h>
22#include <linux/dmaengine.h>
23#include <linux/pch_dma.h>
24
25enum {
26 PCH_UART_HANDLED_RX_INT_SHIFT,
27 PCH_UART_HANDLED_TX_INT_SHIFT,
28 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
29 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
30 PCH_UART_HANDLED_MS_INT_SHIFT,
31 PCH_UART_HANDLED_LS_INT_SHIFT,
32};
33
34#define PCH_UART_DRIVER_DEVICE "ttyPCH"
35
36/* Set the max number of UART port
37 * Intel EG20T PCH: 4 port
38 * LAPIS Semiconductor ML7213 IOH: 3 port
39 * LAPIS Semiconductor ML7223 IOH: 2 port
40*/
41#define PCH_UART_NR 4
42
43#define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
44#define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
45#define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
46 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
47#define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
48 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
49#define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
50
51#define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
52
53#define PCH_UART_RBR 0x00
54#define PCH_UART_THR 0x00
55
56#define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
57 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
58#define PCH_UART_IER_ERBFI 0x00000001
59#define PCH_UART_IER_ETBEI 0x00000002
60#define PCH_UART_IER_ELSI 0x00000004
61#define PCH_UART_IER_EDSSI 0x00000008
62
63#define PCH_UART_IIR_IP 0x00000001
64#define PCH_UART_IIR_IID 0x00000006
65#define PCH_UART_IIR_MSI 0x00000000
66#define PCH_UART_IIR_TRI 0x00000002
67#define PCH_UART_IIR_RRI 0x00000004
68#define PCH_UART_IIR_REI 0x00000006
69#define PCH_UART_IIR_TOI 0x00000008
70#define PCH_UART_IIR_FIFO256 0x00000020
71#define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
72#define PCH_UART_IIR_FE 0x000000C0
73
74#define PCH_UART_FCR_FIFOE 0x00000001
75#define PCH_UART_FCR_RFR 0x00000002
76#define PCH_UART_FCR_TFR 0x00000004
77#define PCH_UART_FCR_DMS 0x00000008
78#define PCH_UART_FCR_FIFO256 0x00000020
79#define PCH_UART_FCR_RFTL 0x000000C0
80
81#define PCH_UART_FCR_RFTL1 0x00000000
82#define PCH_UART_FCR_RFTL64 0x00000040
83#define PCH_UART_FCR_RFTL128 0x00000080
84#define PCH_UART_FCR_RFTL224 0x000000C0
85#define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
86#define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
87#define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
88#define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
89#define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
90#define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
91#define PCH_UART_FCR_RFTL_SHIFT 6
92
93#define PCH_UART_LCR_WLS 0x00000003
94#define PCH_UART_LCR_STB 0x00000004
95#define PCH_UART_LCR_PEN 0x00000008
96#define PCH_UART_LCR_EPS 0x00000010
97#define PCH_UART_LCR_SP 0x00000020
98#define PCH_UART_LCR_SB 0x00000040
99#define PCH_UART_LCR_DLAB 0x00000080
100#define PCH_UART_LCR_NP 0x00000000
101#define PCH_UART_LCR_OP PCH_UART_LCR_PEN
102#define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
103#define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
104#define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
105 PCH_UART_LCR_SP)
106
107#define PCH_UART_LCR_5BIT 0x00000000
108#define PCH_UART_LCR_6BIT 0x00000001
109#define PCH_UART_LCR_7BIT 0x00000002
110#define PCH_UART_LCR_8BIT 0x00000003
111
112#define PCH_UART_MCR_DTR 0x00000001
113#define PCH_UART_MCR_RTS 0x00000002
114#define PCH_UART_MCR_OUT 0x0000000C
115#define PCH_UART_MCR_LOOP 0x00000010
116#define PCH_UART_MCR_AFE 0x00000020
117
118#define PCH_UART_LSR_DR 0x00000001
119#define PCH_UART_LSR_ERR (1<<7)
120
121#define PCH_UART_MSR_DCTS 0x00000001
122#define PCH_UART_MSR_DDSR 0x00000002
123#define PCH_UART_MSR_TERI 0x00000004
124#define PCH_UART_MSR_DDCD 0x00000008
125#define PCH_UART_MSR_CTS 0x00000010
126#define PCH_UART_MSR_DSR 0x00000020
127#define PCH_UART_MSR_RI 0x00000040
128#define PCH_UART_MSR_DCD 0x00000080
129#define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
130 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
131
132#define PCH_UART_DLL 0x00
133#define PCH_UART_DLM 0x01
134
135#define PCH_UART_BRCSR 0x0E
136
137#define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
138#define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
139#define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
140#define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
141#define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
142
143#define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
144#define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
145#define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
146#define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
147#define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
148#define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
149#define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
150#define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
151#define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
152#define PCH_UART_HAL_STB1 0
153#define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
154
155#define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
156#define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
157#define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
158 PCH_UART_HAL_CLR_RX_FIFO)
159
160#define PCH_UART_HAL_DMA_MODE0 0
161#define PCH_UART_HAL_FIFO_DIS 0
162#define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
163#define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
164 PCH_UART_FCR_FIFO256)
165#define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
166#define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
167#define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
168#define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
169#define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
170#define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
171#define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
172#define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
173#define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
174#define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
175#define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
176#define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
177#define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
178#define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
179
180#define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
181#define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
182#define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
183#define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
184#define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
185
186#define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
187#define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
188#define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
189#define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
190#define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
191
192#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
193
194#define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */
195#define CMITC_UARTCLK 192000000 /* 192.0000 MHz */
196#define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */
197#define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */
198#define NTC1_UARTCLK 64000000 /* 64.0000 MHz */
199#define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */
200
201struct pch_uart_buffer {
202 unsigned char *buf;
203 int size;
204};
205
206struct eg20t_port {
207 struct uart_port port;
208 int port_type;
209 void __iomem *membase;
210 resource_size_t mapbase;
211 unsigned int iobase;
212 struct pci_dev *pdev;
213 int fifo_size;
214 unsigned int uartclk;
215 int start_tx;
216 int start_rx;
217 int tx_empty;
218 int trigger;
219 int trigger_level;
220 struct pch_uart_buffer rxbuf;
221 unsigned int dmsr;
222 unsigned int fcr;
223 unsigned int mcr;
224 unsigned int use_dma;
225 struct dma_async_tx_descriptor *desc_tx;
226 struct dma_async_tx_descriptor *desc_rx;
227 struct pch_dma_slave param_tx;
228 struct pch_dma_slave param_rx;
229 struct dma_chan *chan_tx;
230 struct dma_chan *chan_rx;
231 struct scatterlist *sg_tx_p;
232 int nent;
233 int orig_nent;
234 struct scatterlist sg_rx;
235 int tx_dma_use;
236 void *rx_buf_virt;
237 dma_addr_t rx_buf_dma;
238
239 struct dentry *debugfs;
240#define IRQ_NAME_SIZE 17
241 char irq_name[IRQ_NAME_SIZE];
242
243 /* protect the eg20t_port private structure and io access to membase */
244 spinlock_t lock;
245};
246
247/**
248 * struct pch_uart_driver_data - private data structure for UART-DMA
249 * @port_type: The type of UART port
250 * @line_no: UART port line number (0, 1, 2...)
251 */
252struct pch_uart_driver_data {
253 int port_type;
254 int line_no;
255};
256
257enum pch_uart_num_t {
258 pch_et20t_uart0 = 0,
259 pch_et20t_uart1,
260 pch_et20t_uart2,
261 pch_et20t_uart3,
262 pch_ml7213_uart0,
263 pch_ml7213_uart1,
264 pch_ml7213_uart2,
265 pch_ml7223_uart0,
266 pch_ml7223_uart1,
267 pch_ml7831_uart0,
268 pch_ml7831_uart1,
269};
270
271static struct pch_uart_driver_data drv_dat[] = {
272 [pch_et20t_uart0] = {PORT_PCH_8LINE, 0},
273 [pch_et20t_uart1] = {PORT_PCH_2LINE, 1},
274 [pch_et20t_uart2] = {PORT_PCH_2LINE, 2},
275 [pch_et20t_uart3] = {PORT_PCH_2LINE, 3},
276 [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0},
277 [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1},
278 [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2},
279 [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0},
280 [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1},
281 [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0},
282 [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1},
283};
284
285#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
286static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
287#endif
288static unsigned int default_baud = 9600;
289static unsigned int user_uartclk = 0;
290static const int trigger_level_256[4] = { 1, 64, 128, 224 };
291static const int trigger_level_64[4] = { 1, 16, 32, 56 };
292static const int trigger_level_16[4] = { 1, 4, 8, 14 };
293static const int trigger_level_1[4] = { 1, 1, 1, 1 };
294
295#ifdef CONFIG_DEBUG_FS
296
297#define PCH_REGS_BUFSIZE 1024
298
299
300static ssize_t port_show_regs(struct file *file, char __user *user_buf,
301 size_t count, loff_t *ppos)
302{
303 struct eg20t_port *priv = file->private_data;
304 char *buf;
305 u32 len = 0;
306 ssize_t ret;
307 unsigned char lcr;
308
309 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
310 if (!buf)
311 return 0;
312
313 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
314 "PCH EG20T port[%d] regs:\n", priv->port.line);
315
316 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
317 "=================================\n");
318 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
319 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
320 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
321 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
322 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
323 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
324 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
325 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
326 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
327 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
328 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
329 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
330 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
331 "BRCSR: \t0x%02x\n",
332 ioread8(priv->membase + PCH_UART_BRCSR));
333
334 lcr = ioread8(priv->membase + UART_LCR);
335 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
336 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
337 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
338 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
339 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
340 iowrite8(lcr, priv->membase + UART_LCR);
341
342 if (len > PCH_REGS_BUFSIZE)
343 len = PCH_REGS_BUFSIZE;
344
345 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
346 kfree(buf);
347 return ret;
348}
349
350static const struct file_operations port_regs_ops = {
351 .owner = THIS_MODULE,
352 .open = simple_open,
353 .read = port_show_regs,
354 .llseek = default_llseek,
355};
356#endif /* CONFIG_DEBUG_FS */
357
358static const struct dmi_system_id pch_uart_dmi_table[] = {
359 {
360 .ident = "CM-iTC",
361 {
362 DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
363 },
364 (void *)CMITC_UARTCLK,
365 },
366 {
367 .ident = "FRI2",
368 {
369 DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
370 },
371 (void *)FRI2_64_UARTCLK,
372 },
373 {
374 .ident = "Fish River Island II",
375 {
376 DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
377 },
378 (void *)FRI2_48_UARTCLK,
379 },
380 {
381 .ident = "COMe-mTT",
382 {
383 DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
384 },
385 (void *)NTC1_UARTCLK,
386 },
387 {
388 .ident = "nanoETXexpress-TT",
389 {
390 DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
391 },
392 (void *)NTC1_UARTCLK,
393 },
394 {
395 .ident = "MinnowBoard",
396 {
397 DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
398 },
399 (void *)MINNOW_UARTCLK,
400 },
401 { }
402};
403
404/* Return UART clock, checking for board specific clocks. */
405static unsigned int pch_uart_get_uartclk(void)
406{
407 const struct dmi_system_id *d;
408
409 if (user_uartclk)
410 return user_uartclk;
411
412 d = dmi_first_match(pch_uart_dmi_table);
413 if (d)
414 return (unsigned long)d->driver_data;
415
416 return DEFAULT_UARTCLK;
417}
418
419static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
420 unsigned int flag)
421{
422 u8 ier = ioread8(priv->membase + UART_IER);
423 ier |= flag & PCH_UART_IER_MASK;
424 iowrite8(ier, priv->membase + UART_IER);
425}
426
427static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
428 unsigned int flag)
429{
430 u8 ier = ioread8(priv->membase + UART_IER);
431 ier &= ~(flag & PCH_UART_IER_MASK);
432 iowrite8(ier, priv->membase + UART_IER);
433}
434
435static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
436 unsigned int parity, unsigned int bits,
437 unsigned int stb)
438{
439 unsigned int dll, dlm, lcr;
440 int div;
441
442 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
443 if (div < 0 || USHRT_MAX <= div) {
444 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
445 return -EINVAL;
446 }
447
448 dll = (unsigned int)div & 0x00FFU;
449 dlm = ((unsigned int)div >> 8) & 0x00FFU;
450
451 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
452 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
453 return -EINVAL;
454 }
455
456 if (bits & ~PCH_UART_LCR_WLS) {
457 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
458 return -EINVAL;
459 }
460
461 if (stb & ~PCH_UART_LCR_STB) {
462 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
463 return -EINVAL;
464 }
465
466 lcr = parity;
467 lcr |= bits;
468 lcr |= stb;
469
470 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
471 __func__, baud, div, lcr, jiffies);
472 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
473 iowrite8(dll, priv->membase + PCH_UART_DLL);
474 iowrite8(dlm, priv->membase + PCH_UART_DLM);
475 iowrite8(lcr, priv->membase + UART_LCR);
476
477 return 0;
478}
479
480static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
481 unsigned int flag)
482{
483 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
484 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
485 __func__, flag);
486 return -EINVAL;
487 }
488
489 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
490 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
491 priv->membase + UART_FCR);
492 iowrite8(priv->fcr, priv->membase + UART_FCR);
493
494 return 0;
495}
496
497static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
498 unsigned int dmamode,
499 unsigned int fifo_size, unsigned int trigger)
500{
501 u8 fcr;
502
503 if (dmamode & ~PCH_UART_FCR_DMS) {
504 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
505 __func__, dmamode);
506 return -EINVAL;
507 }
508
509 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
510 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
511 __func__, fifo_size);
512 return -EINVAL;
513 }
514
515 if (trigger & ~PCH_UART_FCR_RFTL) {
516 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
517 __func__, trigger);
518 return -EINVAL;
519 }
520
521 switch (priv->fifo_size) {
522 case 256:
523 priv->trigger_level =
524 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
525 break;
526 case 64:
527 priv->trigger_level =
528 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
529 break;
530 case 16:
531 priv->trigger_level =
532 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
533 break;
534 default:
535 priv->trigger_level =
536 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
537 break;
538 }
539 fcr =
540 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
541 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
542 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
543 priv->membase + UART_FCR);
544 iowrite8(fcr, priv->membase + UART_FCR);
545 priv->fcr = fcr;
546
547 return 0;
548}
549
550static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
551{
552 unsigned int msr = ioread8(priv->membase + UART_MSR);
553 priv->dmsr = msr & PCH_UART_MSR_DELTA;
554 return (u8)msr;
555}
556
557static void pch_uart_hal_write(struct eg20t_port *priv,
558 const unsigned char *buf, int tx_size)
559{
560 int i;
561 unsigned int thr;
562
563 for (i = 0; i < tx_size;) {
564 thr = buf[i++];
565 iowrite8(thr, priv->membase + PCH_UART_THR);
566 }
567}
568
569static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
570 int rx_size)
571{
572 int i;
573 u8 rbr, lsr;
574 struct uart_port *port = &priv->port;
575
576 lsr = ioread8(priv->membase + UART_LSR);
577 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
578 i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
579 lsr = ioread8(priv->membase + UART_LSR)) {
580 rbr = ioread8(priv->membase + PCH_UART_RBR);
581
582 if (lsr & UART_LSR_BI) {
583 port->icount.brk++;
584 if (uart_handle_break(port))
585 continue;
586 }
587 if (uart_handle_sysrq_char(port, rbr))
588 continue;
589
590 buf[i++] = rbr;
591 }
592 return i;
593}
594
595static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
596{
597 return ioread8(priv->membase + UART_IIR) &\
598 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
599}
600
601static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
602{
603 return ioread8(priv->membase + UART_LSR);
604}
605
606static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
607{
608 unsigned int lcr;
609
610 lcr = ioread8(priv->membase + UART_LCR);
611 if (on)
612 lcr |= PCH_UART_LCR_SB;
613 else
614 lcr &= ~PCH_UART_LCR_SB;
615
616 iowrite8(lcr, priv->membase + UART_LCR);
617}
618
619static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
620 int size)
621{
622 struct uart_port *port = &priv->port;
623 struct tty_port *tport = &port->state->port;
624
625 tty_insert_flip_string(tport, buf, size);
626 tty_flip_buffer_push(tport);
627
628 return 0;
629}
630
631static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
632{
633 int ret = 0;
634 struct uart_port *port = &priv->port;
635
636 if (port->x_char) {
637 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
638 __func__, port->x_char, jiffies);
639 buf[0] = port->x_char;
640 port->x_char = 0;
641 ret = 1;
642 }
643
644 return ret;
645}
646
647static int dma_push_rx(struct eg20t_port *priv, int size)
648{
649 int room;
650 struct uart_port *port = &priv->port;
651 struct tty_port *tport = &port->state->port;
652
653 room = tty_buffer_request_room(tport, size);
654
655 if (room < size)
656 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
657 size - room);
658 if (!room)
659 return 0;
660
661 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
662
663 port->icount.rx += room;
664
665 return room;
666}
667
668static void pch_free_dma(struct uart_port *port)
669{
670 struct eg20t_port *priv;
671 priv = container_of(port, struct eg20t_port, port);
672
673 if (priv->chan_tx) {
674 dma_release_channel(priv->chan_tx);
675 priv->chan_tx = NULL;
676 }
677 if (priv->chan_rx) {
678 dma_release_channel(priv->chan_rx);
679 priv->chan_rx = NULL;
680 }
681
682 if (priv->rx_buf_dma) {
683 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
684 priv->rx_buf_dma);
685 priv->rx_buf_virt = NULL;
686 priv->rx_buf_dma = 0;
687 }
688
689 return;
690}
691
692static bool filter(struct dma_chan *chan, void *slave)
693{
694 struct pch_dma_slave *param = slave;
695
696 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
697 chan->device->dev)) {
698 chan->private = param;
699 return true;
700 } else {
701 return false;
702 }
703}
704
705static void pch_request_dma(struct uart_port *port)
706{
707 dma_cap_mask_t mask;
708 struct dma_chan *chan;
709 struct pci_dev *dma_dev;
710 struct pch_dma_slave *param;
711 struct eg20t_port *priv =
712 container_of(port, struct eg20t_port, port);
713 dma_cap_zero(mask);
714 dma_cap_set(DMA_SLAVE, mask);
715
716 /* Get DMA's dev information */
717 dma_dev = pci_get_slot(priv->pdev->bus,
718 PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
719
720 /* Set Tx DMA */
721 param = &priv->param_tx;
722 param->dma_dev = &dma_dev->dev;
723 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
724
725 param->tx_reg = port->mapbase + UART_TX;
726 chan = dma_request_channel(mask, filter, param);
727 if (!chan) {
728 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
729 __func__);
730 return;
731 }
732 priv->chan_tx = chan;
733
734 /* Set Rx DMA */
735 param = &priv->param_rx;
736 param->dma_dev = &dma_dev->dev;
737 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
738
739 param->rx_reg = port->mapbase + UART_RX;
740 chan = dma_request_channel(mask, filter, param);
741 if (!chan) {
742 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
743 __func__);
744 dma_release_channel(priv->chan_tx);
745 priv->chan_tx = NULL;
746 return;
747 }
748
749 /* Get Consistent memory for DMA */
750 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
751 &priv->rx_buf_dma, GFP_KERNEL);
752 priv->chan_rx = chan;
753}
754
755static void pch_dma_rx_complete(void *arg)
756{
757 struct eg20t_port *priv = arg;
758 struct uart_port *port = &priv->port;
759 int count;
760
761 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
762 count = dma_push_rx(priv, priv->trigger_level);
763 if (count)
764 tty_flip_buffer_push(&port->state->port);
765 async_tx_ack(priv->desc_rx);
766 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
767 PCH_UART_HAL_RX_ERR_INT);
768}
769
770static void pch_dma_tx_complete(void *arg)
771{
772 struct eg20t_port *priv = arg;
773 struct uart_port *port = &priv->port;
774 struct circ_buf *xmit = &port->state->xmit;
775 struct scatterlist *sg = priv->sg_tx_p;
776 int i;
777
778 for (i = 0; i < priv->nent; i++, sg++) {
779 xmit->tail += sg_dma_len(sg);
780 port->icount.tx += sg_dma_len(sg);
781 }
782 xmit->tail &= UART_XMIT_SIZE - 1;
783 async_tx_ack(priv->desc_tx);
784 dma_unmap_sg(port->dev, sg, priv->orig_nent, DMA_TO_DEVICE);
785 priv->tx_dma_use = 0;
786 priv->nent = 0;
787 priv->orig_nent = 0;
788 kfree(priv->sg_tx_p);
789 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
790}
791
792static int pop_tx(struct eg20t_port *priv, int size)
793{
794 int count = 0;
795 struct uart_port *port = &priv->port;
796 struct circ_buf *xmit = &port->state->xmit;
797
798 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
799 goto pop_tx_end;
800
801 do {
802 int cnt_to_end =
803 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
804 int sz = min(size - count, cnt_to_end);
805 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
806 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
807 count += sz;
808 } while (!uart_circ_empty(xmit) && count < size);
809
810pop_tx_end:
811 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
812 count, size - count, jiffies);
813
814 return count;
815}
816
817static int handle_rx_to(struct eg20t_port *priv)
818{
819 struct pch_uart_buffer *buf;
820 int rx_size;
821 int ret;
822 if (!priv->start_rx) {
823 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
824 PCH_UART_HAL_RX_ERR_INT);
825 return 0;
826 }
827 buf = &priv->rxbuf;
828 do {
829 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
830 ret = push_rx(priv, buf->buf, rx_size);
831 if (ret)
832 return 0;
833 } while (rx_size == buf->size);
834
835 return PCH_UART_HANDLED_RX_INT;
836}
837
838static int handle_rx(struct eg20t_port *priv)
839{
840 return handle_rx_to(priv);
841}
842
843static int dma_handle_rx(struct eg20t_port *priv)
844{
845 struct uart_port *port = &priv->port;
846 struct dma_async_tx_descriptor *desc;
847 struct scatterlist *sg;
848
849 priv = container_of(port, struct eg20t_port, port);
850 sg = &priv->sg_rx;
851
852 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
853
854 sg_dma_len(sg) = priv->trigger_level;
855
856 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
857 sg_dma_len(sg), offset_in_page(priv->rx_buf_virt));
858
859 sg_dma_address(sg) = priv->rx_buf_dma;
860
861 desc = dmaengine_prep_slave_sg(priv->chan_rx,
862 sg, 1, DMA_DEV_TO_MEM,
863 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
864
865 if (!desc)
866 return 0;
867
868 priv->desc_rx = desc;
869 desc->callback = pch_dma_rx_complete;
870 desc->callback_param = priv;
871 desc->tx_submit(desc);
872 dma_async_issue_pending(priv->chan_rx);
873
874 return PCH_UART_HANDLED_RX_INT;
875}
876
877static unsigned int handle_tx(struct eg20t_port *priv)
878{
879 struct uart_port *port = &priv->port;
880 struct circ_buf *xmit = &port->state->xmit;
881 int fifo_size;
882 int tx_size;
883 int size;
884 int tx_empty;
885
886 if (!priv->start_tx) {
887 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
888 __func__, jiffies);
889 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
890 priv->tx_empty = 1;
891 return 0;
892 }
893
894 fifo_size = max(priv->fifo_size, 1);
895 tx_empty = 1;
896 if (pop_tx_x(priv, xmit->buf)) {
897 pch_uart_hal_write(priv, xmit->buf, 1);
898 port->icount.tx++;
899 tx_empty = 0;
900 fifo_size--;
901 }
902 size = min(xmit->head - xmit->tail, fifo_size);
903 if (size < 0)
904 size = fifo_size;
905
906 tx_size = pop_tx(priv, size);
907 if (tx_size > 0) {
908 port->icount.tx += tx_size;
909 tx_empty = 0;
910 }
911
912 priv->tx_empty = tx_empty;
913
914 if (tx_empty) {
915 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
916 uart_write_wakeup(port);
917 }
918
919 return PCH_UART_HANDLED_TX_INT;
920}
921
922static unsigned int dma_handle_tx(struct eg20t_port *priv)
923{
924 struct uart_port *port = &priv->port;
925 struct circ_buf *xmit = &port->state->xmit;
926 struct scatterlist *sg;
927 int nent;
928 int fifo_size;
929 struct dma_async_tx_descriptor *desc;
930 int num;
931 int i;
932 int bytes;
933 int size;
934 int rem;
935
936 if (!priv->start_tx) {
937 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
938 __func__, jiffies);
939 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
940 priv->tx_empty = 1;
941 return 0;
942 }
943
944 if (priv->tx_dma_use) {
945 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
946 __func__, jiffies);
947 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
948 priv->tx_empty = 1;
949 return 0;
950 }
951
952 fifo_size = max(priv->fifo_size, 1);
953 if (pop_tx_x(priv, xmit->buf)) {
954 pch_uart_hal_write(priv, xmit->buf, 1);
955 port->icount.tx++;
956 fifo_size--;
957 }
958
959 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
960 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
961 xmit->tail, UART_XMIT_SIZE));
962 if (!bytes) {
963 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
964 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
965 uart_write_wakeup(port);
966 return 0;
967 }
968
969 if (bytes > fifo_size) {
970 num = bytes / fifo_size + 1;
971 size = fifo_size;
972 rem = bytes % fifo_size;
973 } else {
974 num = 1;
975 size = bytes;
976 rem = bytes;
977 }
978
979 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
980 __func__, num, size, rem);
981
982 priv->tx_dma_use = 1;
983
984 priv->sg_tx_p = kcalloc(num, sizeof(struct scatterlist), GFP_ATOMIC);
985 if (!priv->sg_tx_p) {
986 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
987 return 0;
988 }
989
990 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
991 sg = priv->sg_tx_p;
992
993 for (i = 0; i < num; i++, sg++) {
994 if (i == (num - 1))
995 sg_set_page(sg, virt_to_page(xmit->buf),
996 rem, fifo_size * i);
997 else
998 sg_set_page(sg, virt_to_page(xmit->buf),
999 size, fifo_size * i);
1000 }
1001
1002 sg = priv->sg_tx_p;
1003 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
1004 if (!nent) {
1005 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1006 return 0;
1007 }
1008 priv->orig_nent = num;
1009 priv->nent = nent;
1010
1011 for (i = 0; i < nent; i++, sg++) {
1012 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1013 fifo_size * i;
1014 sg_dma_address(sg) = (sg_dma_address(sg) &
1015 ~(UART_XMIT_SIZE - 1)) + sg->offset;
1016 if (i == (nent - 1))
1017 sg_dma_len(sg) = rem;
1018 else
1019 sg_dma_len(sg) = size;
1020 }
1021
1022 desc = dmaengine_prep_slave_sg(priv->chan_tx,
1023 priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1024 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1025 if (!desc) {
1026 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
1027 __func__);
1028 return 0;
1029 }
1030 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1031 priv->desc_tx = desc;
1032 desc->callback = pch_dma_tx_complete;
1033 desc->callback_param = priv;
1034
1035 desc->tx_submit(desc);
1036
1037 dma_async_issue_pending(priv->chan_tx);
1038
1039 return PCH_UART_HANDLED_TX_INT;
1040}
1041
1042static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1043{
1044 struct uart_port *port = &priv->port;
1045 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1046 char *error_msg[5] = {};
1047 int i = 0;
1048
1049 if (lsr & PCH_UART_LSR_ERR)
1050 error_msg[i++] = "Error data in FIFO\n";
1051
1052 if (lsr & UART_LSR_FE) {
1053 port->icount.frame++;
1054 error_msg[i++] = " Framing Error\n";
1055 }
1056
1057 if (lsr & UART_LSR_PE) {
1058 port->icount.parity++;
1059 error_msg[i++] = " Parity Error\n";
1060 }
1061
1062 if (lsr & UART_LSR_OE) {
1063 port->icount.overrun++;
1064 error_msg[i++] = " Overrun Error\n";
1065 }
1066
1067 if (tty == NULL) {
1068 for (i = 0; error_msg[i] != NULL; i++)
1069 dev_err(&priv->pdev->dev, error_msg[i]);
1070 } else {
1071 tty_kref_put(tty);
1072 }
1073}
1074
1075static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1076{
1077 struct eg20t_port *priv = dev_id;
1078 unsigned int handled;
1079 u8 lsr;
1080 int ret = 0;
1081 unsigned char iid;
1082 unsigned long flags;
1083 int next = 1;
1084 u8 msr;
1085
1086 spin_lock_irqsave(&priv->lock, flags);
1087 handled = 0;
1088 while (next) {
1089 iid = pch_uart_hal_get_iid(priv);
1090 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1091 break;
1092 switch (iid) {
1093 case PCH_UART_IID_RLS: /* Receiver Line Status */
1094 lsr = pch_uart_hal_get_line_status(priv);
1095 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1096 UART_LSR_PE | UART_LSR_OE)) {
1097 pch_uart_err_ir(priv, lsr);
1098 ret = PCH_UART_HANDLED_RX_ERR_INT;
1099 } else {
1100 ret = PCH_UART_HANDLED_LS_INT;
1101 }
1102 break;
1103 case PCH_UART_IID_RDR: /* Received Data Ready */
1104 if (priv->use_dma) {
1105 pch_uart_hal_disable_interrupt(priv,
1106 PCH_UART_HAL_RX_INT |
1107 PCH_UART_HAL_RX_ERR_INT);
1108 ret = dma_handle_rx(priv);
1109 if (!ret)
1110 pch_uart_hal_enable_interrupt(priv,
1111 PCH_UART_HAL_RX_INT |
1112 PCH_UART_HAL_RX_ERR_INT);
1113 } else {
1114 ret = handle_rx(priv);
1115 }
1116 break;
1117 case PCH_UART_IID_RDR_TO: /* Received Data Ready
1118 (FIFO Timeout) */
1119 ret = handle_rx_to(priv);
1120 break;
1121 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1122 Empty */
1123 if (priv->use_dma)
1124 ret = dma_handle_tx(priv);
1125 else
1126 ret = handle_tx(priv);
1127 break;
1128 case PCH_UART_IID_MS: /* Modem Status */
1129 msr = pch_uart_hal_get_modem(priv);
1130 next = 0; /* MS ir prioirty is the lowest. So, MS ir
1131 means final interrupt */
1132 if ((msr & UART_MSR_ANY_DELTA) == 0)
1133 break;
1134 ret |= PCH_UART_HANDLED_MS_INT;
1135 break;
1136 default: /* Never junp to this label */
1137 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1138 iid, jiffies);
1139 ret = -1;
1140 next = 0;
1141 break;
1142 }
1143 handled |= (unsigned int)ret;
1144 }
1145
1146 spin_unlock_irqrestore(&priv->lock, flags);
1147 return IRQ_RETVAL(handled);
1148}
1149
1150/* This function tests whether the transmitter fifo and shifter for the port
1151 described by 'port' is empty. */
1152static unsigned int pch_uart_tx_empty(struct uart_port *port)
1153{
1154 struct eg20t_port *priv;
1155
1156 priv = container_of(port, struct eg20t_port, port);
1157 if (priv->tx_empty)
1158 return TIOCSER_TEMT;
1159 else
1160 return 0;
1161}
1162
1163/* Returns the current state of modem control inputs. */
1164static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1165{
1166 struct eg20t_port *priv;
1167 u8 modem;
1168 unsigned int ret = 0;
1169
1170 priv = container_of(port, struct eg20t_port, port);
1171 modem = pch_uart_hal_get_modem(priv);
1172
1173 if (modem & UART_MSR_DCD)
1174 ret |= TIOCM_CAR;
1175
1176 if (modem & UART_MSR_RI)
1177 ret |= TIOCM_RNG;
1178
1179 if (modem & UART_MSR_DSR)
1180 ret |= TIOCM_DSR;
1181
1182 if (modem & UART_MSR_CTS)
1183 ret |= TIOCM_CTS;
1184
1185 return ret;
1186}
1187
1188static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1189{
1190 u32 mcr = 0;
1191 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1192
1193 if (mctrl & TIOCM_DTR)
1194 mcr |= UART_MCR_DTR;
1195 if (mctrl & TIOCM_RTS)
1196 mcr |= UART_MCR_RTS;
1197 if (mctrl & TIOCM_LOOP)
1198 mcr |= UART_MCR_LOOP;
1199
1200 if (priv->mcr & UART_MCR_AFE)
1201 mcr |= UART_MCR_AFE;
1202
1203 if (mctrl)
1204 iowrite8(mcr, priv->membase + UART_MCR);
1205}
1206
1207static void pch_uart_stop_tx(struct uart_port *port)
1208{
1209 struct eg20t_port *priv;
1210 priv = container_of(port, struct eg20t_port, port);
1211 priv->start_tx = 0;
1212 priv->tx_dma_use = 0;
1213}
1214
1215static void pch_uart_start_tx(struct uart_port *port)
1216{
1217 struct eg20t_port *priv;
1218
1219 priv = container_of(port, struct eg20t_port, port);
1220
1221 if (priv->use_dma) {
1222 if (priv->tx_dma_use) {
1223 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1224 __func__);
1225 return;
1226 }
1227 }
1228
1229 priv->start_tx = 1;
1230 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1231}
1232
1233static void pch_uart_stop_rx(struct uart_port *port)
1234{
1235 struct eg20t_port *priv;
1236 priv = container_of(port, struct eg20t_port, port);
1237 priv->start_rx = 0;
1238 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1239 PCH_UART_HAL_RX_ERR_INT);
1240}
1241
1242/* Enable the modem status interrupts. */
1243static void pch_uart_enable_ms(struct uart_port *port)
1244{
1245 struct eg20t_port *priv;
1246 priv = container_of(port, struct eg20t_port, port);
1247 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1248}
1249
1250/* Control the transmission of a break signal. */
1251static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1252{
1253 struct eg20t_port *priv;
1254 unsigned long flags;
1255
1256 priv = container_of(port, struct eg20t_port, port);
1257 spin_lock_irqsave(&priv->lock, flags);
1258 pch_uart_hal_set_break(priv, ctl);
1259 spin_unlock_irqrestore(&priv->lock, flags);
1260}
1261
1262/* Grab any interrupt resources and initialise any low level driver state. */
1263static int pch_uart_startup(struct uart_port *port)
1264{
1265 struct eg20t_port *priv;
1266 int ret;
1267 int fifo_size;
1268 int trigger_level;
1269
1270 priv = container_of(port, struct eg20t_port, port);
1271 priv->tx_empty = 1;
1272
1273 if (port->uartclk)
1274 priv->uartclk = port->uartclk;
1275 else
1276 port->uartclk = priv->uartclk;
1277
1278 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1279 ret = pch_uart_hal_set_line(priv, default_baud,
1280 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1281 PCH_UART_HAL_STB1);
1282 if (ret)
1283 return ret;
1284
1285 switch (priv->fifo_size) {
1286 case 256:
1287 fifo_size = PCH_UART_HAL_FIFO256;
1288 break;
1289 case 64:
1290 fifo_size = PCH_UART_HAL_FIFO64;
1291 break;
1292 case 16:
1293 fifo_size = PCH_UART_HAL_FIFO16;
1294 break;
1295 case 1:
1296 default:
1297 fifo_size = PCH_UART_HAL_FIFO_DIS;
1298 break;
1299 }
1300
1301 switch (priv->trigger) {
1302 case PCH_UART_HAL_TRIGGER1:
1303 trigger_level = 1;
1304 break;
1305 case PCH_UART_HAL_TRIGGER_L:
1306 trigger_level = priv->fifo_size / 4;
1307 break;
1308 case PCH_UART_HAL_TRIGGER_M:
1309 trigger_level = priv->fifo_size / 2;
1310 break;
1311 case PCH_UART_HAL_TRIGGER_H:
1312 default:
1313 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1314 break;
1315 }
1316
1317 priv->trigger_level = trigger_level;
1318 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1319 fifo_size, priv->trigger);
1320 if (ret < 0)
1321 return ret;
1322
1323 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1324 priv->irq_name, priv);
1325 if (ret < 0)
1326 return ret;
1327
1328 if (priv->use_dma)
1329 pch_request_dma(port);
1330
1331 priv->start_rx = 1;
1332 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1333 PCH_UART_HAL_RX_ERR_INT);
1334 uart_update_timeout(port, CS8, default_baud);
1335
1336 return 0;
1337}
1338
1339static void pch_uart_shutdown(struct uart_port *port)
1340{
1341 struct eg20t_port *priv;
1342 int ret;
1343
1344 priv = container_of(port, struct eg20t_port, port);
1345 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1346 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1347 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1348 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1349 if (ret)
1350 dev_err(priv->port.dev,
1351 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1352
1353 pch_free_dma(port);
1354
1355 free_irq(priv->port.irq, priv);
1356}
1357
1358/* Change the port parameters, including word length, parity, stop
1359 *bits. Update read_status_mask and ignore_status_mask to indicate
1360 *the types of events we are interested in receiving. */
1361static void pch_uart_set_termios(struct uart_port *port,
1362 struct ktermios *termios, struct ktermios *old)
1363{
1364 int rtn;
1365 unsigned int baud, parity, bits, stb;
1366 struct eg20t_port *priv;
1367 unsigned long flags;
1368
1369 priv = container_of(port, struct eg20t_port, port);
1370 switch (termios->c_cflag & CSIZE) {
1371 case CS5:
1372 bits = PCH_UART_HAL_5BIT;
1373 break;
1374 case CS6:
1375 bits = PCH_UART_HAL_6BIT;
1376 break;
1377 case CS7:
1378 bits = PCH_UART_HAL_7BIT;
1379 break;
1380 default: /* CS8 */
1381 bits = PCH_UART_HAL_8BIT;
1382 break;
1383 }
1384 if (termios->c_cflag & CSTOPB)
1385 stb = PCH_UART_HAL_STB2;
1386 else
1387 stb = PCH_UART_HAL_STB1;
1388
1389 if (termios->c_cflag & PARENB) {
1390 if (termios->c_cflag & PARODD)
1391 parity = PCH_UART_HAL_PARITY_ODD;
1392 else
1393 parity = PCH_UART_HAL_PARITY_EVEN;
1394
1395 } else
1396 parity = PCH_UART_HAL_PARITY_NONE;
1397
1398 /* Only UART0 has auto hardware flow function */
1399 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1400 priv->mcr |= UART_MCR_AFE;
1401 else
1402 priv->mcr &= ~UART_MCR_AFE;
1403
1404 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1405
1406 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1407
1408 spin_lock_irqsave(&priv->lock, flags);
1409 spin_lock(&port->lock);
1410
1411 uart_update_timeout(port, termios->c_cflag, baud);
1412 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1413 if (rtn)
1414 goto out;
1415
1416 pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1417 /* Don't rewrite B0 */
1418 if (tty_termios_baud_rate(termios))
1419 tty_termios_encode_baud_rate(termios, baud, baud);
1420
1421out:
1422 spin_unlock(&port->lock);
1423 spin_unlock_irqrestore(&priv->lock, flags);
1424}
1425
1426static const char *pch_uart_type(struct uart_port *port)
1427{
1428 return KBUILD_MODNAME;
1429}
1430
1431static void pch_uart_release_port(struct uart_port *port)
1432{
1433 struct eg20t_port *priv;
1434
1435 priv = container_of(port, struct eg20t_port, port);
1436 pci_iounmap(priv->pdev, priv->membase);
1437 pci_release_regions(priv->pdev);
1438}
1439
1440static int pch_uart_request_port(struct uart_port *port)
1441{
1442 struct eg20t_port *priv;
1443 int ret;
1444 void __iomem *membase;
1445
1446 priv = container_of(port, struct eg20t_port, port);
1447 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1448 if (ret < 0)
1449 return -EBUSY;
1450
1451 membase = pci_iomap(priv->pdev, 1, 0);
1452 if (!membase) {
1453 pci_release_regions(priv->pdev);
1454 return -EBUSY;
1455 }
1456 priv->membase = port->membase = membase;
1457
1458 return 0;
1459}
1460
1461static void pch_uart_config_port(struct uart_port *port, int type)
1462{
1463 struct eg20t_port *priv;
1464
1465 priv = container_of(port, struct eg20t_port, port);
1466 if (type & UART_CONFIG_TYPE) {
1467 port->type = priv->port_type;
1468 pch_uart_request_port(port);
1469 }
1470}
1471
1472static int pch_uart_verify_port(struct uart_port *port,
1473 struct serial_struct *serinfo)
1474{
1475 struct eg20t_port *priv;
1476
1477 priv = container_of(port, struct eg20t_port, port);
1478 if (serinfo->flags & UPF_LOW_LATENCY) {
1479 dev_info(priv->port.dev,
1480 "PCH UART : Use PIO Mode (without DMA)\n");
1481 priv->use_dma = 0;
1482 serinfo->flags &= ~UPF_LOW_LATENCY;
1483 } else {
1484#ifndef CONFIG_PCH_DMA
1485 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1486 __func__);
1487 return -EOPNOTSUPP;
1488#endif
1489 if (!priv->use_dma) {
1490 pch_request_dma(port);
1491 if (priv->chan_rx)
1492 priv->use_dma = 1;
1493 }
1494 dev_info(priv->port.dev, "PCH UART: %s\n",
1495 priv->use_dma ?
1496 "Use DMA Mode" : "No DMA");
1497 }
1498
1499 return 0;
1500}
1501
1502#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1503/*
1504 * Wait for transmitter & holding register to empty
1505 */
1506static void wait_for_xmitr(struct eg20t_port *up, int bits)
1507{
1508 unsigned int status, tmout = 10000;
1509
1510 /* Wait up to 10ms for the character(s) to be sent. */
1511 for (;;) {
1512 status = ioread8(up->membase + UART_LSR);
1513
1514 if ((status & bits) == bits)
1515 break;
1516 if (--tmout == 0)
1517 break;
1518 udelay(1);
1519 }
1520
1521 /* Wait up to 1s for flow control if necessary */
1522 if (up->port.flags & UPF_CONS_FLOW) {
1523 unsigned int tmout;
1524 for (tmout = 1000000; tmout; tmout--) {
1525 unsigned int msr = ioread8(up->membase + UART_MSR);
1526 if (msr & UART_MSR_CTS)
1527 break;
1528 udelay(1);
1529 touch_nmi_watchdog();
1530 }
1531 }
1532}
1533#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1534
1535#ifdef CONFIG_CONSOLE_POLL
1536/*
1537 * Console polling routines for communicate via uart while
1538 * in an interrupt or debug context.
1539 */
1540static int pch_uart_get_poll_char(struct uart_port *port)
1541{
1542 struct eg20t_port *priv =
1543 container_of(port, struct eg20t_port, port);
1544 u8 lsr = ioread8(priv->membase + UART_LSR);
1545
1546 if (!(lsr & UART_LSR_DR))
1547 return NO_POLL_CHAR;
1548
1549 return ioread8(priv->membase + PCH_UART_RBR);
1550}
1551
1552
1553static void pch_uart_put_poll_char(struct uart_port *port,
1554 unsigned char c)
1555{
1556 unsigned int ier;
1557 struct eg20t_port *priv =
1558 container_of(port, struct eg20t_port, port);
1559
1560 /*
1561 * First save the IER then disable the interrupts
1562 */
1563 ier = ioread8(priv->membase + UART_IER);
1564 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1565
1566 wait_for_xmitr(priv, UART_LSR_THRE);
1567 /*
1568 * Send the character out.
1569 */
1570 iowrite8(c, priv->membase + PCH_UART_THR);
1571
1572 /*
1573 * Finally, wait for transmitter to become empty
1574 * and restore the IER
1575 */
1576 wait_for_xmitr(priv, BOTH_EMPTY);
1577 iowrite8(ier, priv->membase + UART_IER);
1578}
1579#endif /* CONFIG_CONSOLE_POLL */
1580
1581static const struct uart_ops pch_uart_ops = {
1582 .tx_empty = pch_uart_tx_empty,
1583 .set_mctrl = pch_uart_set_mctrl,
1584 .get_mctrl = pch_uart_get_mctrl,
1585 .stop_tx = pch_uart_stop_tx,
1586 .start_tx = pch_uart_start_tx,
1587 .stop_rx = pch_uart_stop_rx,
1588 .enable_ms = pch_uart_enable_ms,
1589 .break_ctl = pch_uart_break_ctl,
1590 .startup = pch_uart_startup,
1591 .shutdown = pch_uart_shutdown,
1592 .set_termios = pch_uart_set_termios,
1593/* .pm = pch_uart_pm, Not supported yet */
1594 .type = pch_uart_type,
1595 .release_port = pch_uart_release_port,
1596 .request_port = pch_uart_request_port,
1597 .config_port = pch_uart_config_port,
1598 .verify_port = pch_uart_verify_port,
1599#ifdef CONFIG_CONSOLE_POLL
1600 .poll_get_char = pch_uart_get_poll_char,
1601 .poll_put_char = pch_uart_put_poll_char,
1602#endif
1603};
1604
1605#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1606
1607static void pch_console_putchar(struct uart_port *port, int ch)
1608{
1609 struct eg20t_port *priv =
1610 container_of(port, struct eg20t_port, port);
1611
1612 wait_for_xmitr(priv, UART_LSR_THRE);
1613 iowrite8(ch, priv->membase + PCH_UART_THR);
1614}
1615
1616/*
1617 * Print a string to the serial port trying not to disturb
1618 * any possible real use of the port...
1619 *
1620 * The console_lock must be held when we get here.
1621 */
1622static void
1623pch_console_write(struct console *co, const char *s, unsigned int count)
1624{
1625 struct eg20t_port *priv;
1626 unsigned long flags;
1627 int priv_locked = 1;
1628 int port_locked = 1;
1629 u8 ier;
1630
1631 priv = pch_uart_ports[co->index];
1632
1633 touch_nmi_watchdog();
1634
1635 local_irq_save(flags);
1636 if (priv->port.sysrq) {
1637 /* call to uart_handle_sysrq_char already took the priv lock */
1638 priv_locked = 0;
1639 /* serial8250_handle_port() already took the port lock */
1640 port_locked = 0;
1641 } else if (oops_in_progress) {
1642 priv_locked = spin_trylock(&priv->lock);
1643 port_locked = spin_trylock(&priv->port.lock);
1644 } else {
1645 spin_lock(&priv->lock);
1646 spin_lock(&priv->port.lock);
1647 }
1648
1649 /*
1650 * First save the IER then disable the interrupts
1651 */
1652 ier = ioread8(priv->membase + UART_IER);
1653
1654 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1655
1656 uart_console_write(&priv->port, s, count, pch_console_putchar);
1657
1658 /*
1659 * Finally, wait for transmitter to become empty
1660 * and restore the IER
1661 */
1662 wait_for_xmitr(priv, BOTH_EMPTY);
1663 iowrite8(ier, priv->membase + UART_IER);
1664
1665 if (port_locked)
1666 spin_unlock(&priv->port.lock);
1667 if (priv_locked)
1668 spin_unlock(&priv->lock);
1669 local_irq_restore(flags);
1670}
1671
1672static int __init pch_console_setup(struct console *co, char *options)
1673{
1674 struct uart_port *port;
1675 int baud = default_baud;
1676 int bits = 8;
1677 int parity = 'n';
1678 int flow = 'n';
1679
1680 /*
1681 * Check whether an invalid uart number has been specified, and
1682 * if so, search for the first available port that does have
1683 * console support.
1684 */
1685 if (co->index >= PCH_UART_NR)
1686 co->index = 0;
1687 port = &pch_uart_ports[co->index]->port;
1688
1689 if (!port || (!port->iobase && !port->membase))
1690 return -ENODEV;
1691
1692 port->uartclk = pch_uart_get_uartclk();
1693
1694 if (options)
1695 uart_parse_options(options, &baud, &parity, &bits, &flow);
1696
1697 return uart_set_options(port, co, baud, parity, bits, flow);
1698}
1699
1700static struct uart_driver pch_uart_driver;
1701
1702static struct console pch_console = {
1703 .name = PCH_UART_DRIVER_DEVICE,
1704 .write = pch_console_write,
1705 .device = uart_console_device,
1706 .setup = pch_console_setup,
1707 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1708 .index = -1,
1709 .data = &pch_uart_driver,
1710};
1711
1712#define PCH_CONSOLE (&pch_console)
1713#else
1714#define PCH_CONSOLE NULL
1715#endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1716
1717static struct uart_driver pch_uart_driver = {
1718 .owner = THIS_MODULE,
1719 .driver_name = KBUILD_MODNAME,
1720 .dev_name = PCH_UART_DRIVER_DEVICE,
1721 .major = 0,
1722 .minor = 0,
1723 .nr = PCH_UART_NR,
1724 .cons = PCH_CONSOLE,
1725};
1726
1727static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1728 const struct pci_device_id *id)
1729{
1730 struct eg20t_port *priv;
1731 int ret;
1732 unsigned int iobase;
1733 unsigned int mapbase;
1734 unsigned char *rxbuf;
1735 int fifosize;
1736 int port_type;
1737 struct pch_uart_driver_data *board;
1738#ifdef CONFIG_DEBUG_FS
1739 char name[32]; /* for debugfs file name */
1740#endif
1741
1742 board = &drv_dat[id->driver_data];
1743 port_type = board->port_type;
1744
1745 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1746 if (priv == NULL)
1747 goto init_port_alloc_err;
1748
1749 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1750 if (!rxbuf)
1751 goto init_port_free_txbuf;
1752
1753 switch (port_type) {
1754 case PORT_PCH_8LINE:
1755 fifosize = 256; /* EG20T/ML7213: UART0 */
1756 break;
1757 case PORT_PCH_2LINE:
1758 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1759 break;
1760 default:
1761 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1762 goto init_port_hal_free;
1763 }
1764
1765 pci_enable_msi(pdev);
1766 pci_set_master(pdev);
1767
1768 spin_lock_init(&priv->lock);
1769
1770 iobase = pci_resource_start(pdev, 0);
1771 mapbase = pci_resource_start(pdev, 1);
1772 priv->mapbase = mapbase;
1773 priv->iobase = iobase;
1774 priv->pdev = pdev;
1775 priv->tx_empty = 1;
1776 priv->rxbuf.buf = rxbuf;
1777 priv->rxbuf.size = PAGE_SIZE;
1778
1779 priv->fifo_size = fifosize;
1780 priv->uartclk = pch_uart_get_uartclk();
1781 priv->port_type = port_type;
1782 priv->port.dev = &pdev->dev;
1783 priv->port.iobase = iobase;
1784 priv->port.membase = NULL;
1785 priv->port.mapbase = mapbase;
1786 priv->port.irq = pdev->irq;
1787 priv->port.iotype = UPIO_PORT;
1788 priv->port.ops = &pch_uart_ops;
1789 priv->port.flags = UPF_BOOT_AUTOCONF;
1790 priv->port.fifosize = fifosize;
1791 priv->port.line = board->line_no;
1792 priv->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PCH_UART_CONSOLE);
1793 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1794
1795 snprintf(priv->irq_name, IRQ_NAME_SIZE,
1796 KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1797 priv->port.line);
1798
1799 spin_lock_init(&priv->port.lock);
1800
1801 pci_set_drvdata(pdev, priv);
1802 priv->trigger_level = 1;
1803 priv->fcr = 0;
1804
1805 if (pdev->dev.of_node)
1806 of_property_read_u32(pdev->dev.of_node, "clock-frequency"
1807 , &user_uartclk);
1808
1809#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1810 pch_uart_ports[board->line_no] = priv;
1811#endif
1812 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1813 if (ret < 0)
1814 goto init_port_hal_free;
1815
1816#ifdef CONFIG_DEBUG_FS
1817 snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1818 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1819 NULL, priv, &port_regs_ops);
1820#endif
1821
1822 return priv;
1823
1824init_port_hal_free:
1825#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1826 pch_uart_ports[board->line_no] = NULL;
1827#endif
1828 free_page((unsigned long)rxbuf);
1829init_port_free_txbuf:
1830 kfree(priv);
1831init_port_alloc_err:
1832
1833 return NULL;
1834}
1835
1836static void pch_uart_exit_port(struct eg20t_port *priv)
1837{
1838
1839#ifdef CONFIG_DEBUG_FS
1840 debugfs_remove(priv->debugfs);
1841#endif
1842 uart_remove_one_port(&pch_uart_driver, &priv->port);
1843 free_page((unsigned long)priv->rxbuf.buf);
1844}
1845
1846static void pch_uart_pci_remove(struct pci_dev *pdev)
1847{
1848 struct eg20t_port *priv = pci_get_drvdata(pdev);
1849
1850 pci_disable_msi(pdev);
1851
1852#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1853 pch_uart_ports[priv->port.line] = NULL;
1854#endif
1855 pch_uart_exit_port(priv);
1856 pci_disable_device(pdev);
1857 kfree(priv);
1858 return;
1859}
1860
1861static int __maybe_unused pch_uart_pci_suspend(struct device *dev)
1862{
1863 struct eg20t_port *priv = dev_get_drvdata(dev);
1864
1865 uart_suspend_port(&pch_uart_driver, &priv->port);
1866
1867 return 0;
1868}
1869
1870static int __maybe_unused pch_uart_pci_resume(struct device *dev)
1871{
1872 struct eg20t_port *priv = dev_get_drvdata(dev);
1873
1874 uart_resume_port(&pch_uart_driver, &priv->port);
1875
1876 return 0;
1877}
1878
1879static const struct pci_device_id pch_uart_pci_id[] = {
1880 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1881 .driver_data = pch_et20t_uart0},
1882 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1883 .driver_data = pch_et20t_uart1},
1884 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1885 .driver_data = pch_et20t_uart2},
1886 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1887 .driver_data = pch_et20t_uart3},
1888 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1889 .driver_data = pch_ml7213_uart0},
1890 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1891 .driver_data = pch_ml7213_uart1},
1892 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1893 .driver_data = pch_ml7213_uart2},
1894 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1895 .driver_data = pch_ml7223_uart0},
1896 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1897 .driver_data = pch_ml7223_uart1},
1898 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1899 .driver_data = pch_ml7831_uart0},
1900 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1901 .driver_data = pch_ml7831_uart1},
1902 {0,},
1903};
1904
1905static int pch_uart_pci_probe(struct pci_dev *pdev,
1906 const struct pci_device_id *id)
1907{
1908 int ret;
1909 struct eg20t_port *priv;
1910
1911 ret = pci_enable_device(pdev);
1912 if (ret < 0)
1913 goto probe_error;
1914
1915 priv = pch_uart_init_port(pdev, id);
1916 if (!priv) {
1917 ret = -EBUSY;
1918 goto probe_disable_device;
1919 }
1920 pci_set_drvdata(pdev, priv);
1921
1922 return ret;
1923
1924probe_disable_device:
1925 pci_disable_msi(pdev);
1926 pci_disable_device(pdev);
1927probe_error:
1928 return ret;
1929}
1930
1931static SIMPLE_DEV_PM_OPS(pch_uart_pci_pm_ops,
1932 pch_uart_pci_suspend,
1933 pch_uart_pci_resume);
1934
1935static struct pci_driver pch_uart_pci_driver = {
1936 .name = "pch_uart",
1937 .id_table = pch_uart_pci_id,
1938 .probe = pch_uart_pci_probe,
1939 .remove = pch_uart_pci_remove,
1940 .driver.pm = &pch_uart_pci_pm_ops,
1941};
1942
1943static int __init pch_uart_module_init(void)
1944{
1945 int ret;
1946
1947 /* register as UART driver */
1948 ret = uart_register_driver(&pch_uart_driver);
1949 if (ret < 0)
1950 return ret;
1951
1952 /* register as PCI driver */
1953 ret = pci_register_driver(&pch_uart_pci_driver);
1954 if (ret < 0)
1955 uart_unregister_driver(&pch_uart_driver);
1956
1957 return ret;
1958}
1959module_init(pch_uart_module_init);
1960
1961static void __exit pch_uart_module_exit(void)
1962{
1963 pci_unregister_driver(&pch_uart_pci_driver);
1964 uart_unregister_driver(&pch_uart_driver);
1965}
1966module_exit(pch_uart_module_exit);
1967
1968MODULE_LICENSE("GPL v2");
1969MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1970MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
1971
1972module_param(default_baud, uint, S_IRUGO);
1973MODULE_PARM_DESC(default_baud,
1974 "Default BAUD for initial driver state and console (default 9600)");
1975module_param(user_uartclk, uint, S_IRUGO);
1976MODULE_PARM_DESC(user_uartclk,
1977 "Override UART default or board specific UART clock");