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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2011-2015, 2017, 2020, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/bitops.h>
7#include <linux/delay.h>
8#include <linux/err.h>
9#include <linux/iio/consumer.h>
10#include <linux/interrupt.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/of_device.h>
14#include <linux/platform_device.h>
15#include <linux/regmap.h>
16#include <linux/thermal.h>
17
18#include "../thermal_core.h"
19
20#define QPNP_TM_REG_TYPE 0x04
21#define QPNP_TM_REG_SUBTYPE 0x05
22#define QPNP_TM_REG_STATUS 0x08
23#define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40
24#define QPNP_TM_REG_ALARM_CTRL 0x46
25
26#define QPNP_TM_TYPE 0x09
27#define QPNP_TM_SUBTYPE_GEN1 0x08
28#define QPNP_TM_SUBTYPE_GEN2 0x09
29
30#define STATUS_GEN1_STAGE_MASK GENMASK(1, 0)
31#define STATUS_GEN2_STATE_MASK GENMASK(6, 4)
32#define STATUS_GEN2_STATE_SHIFT 4
33
34#define SHUTDOWN_CTRL1_OVERRIDE_S2 BIT(6)
35#define SHUTDOWN_CTRL1_THRESHOLD_MASK GENMASK(1, 0)
36
37#define SHUTDOWN_CTRL1_RATE_25HZ BIT(3)
38
39#define ALARM_CTRL_FORCE_ENABLE BIT(7)
40
41/*
42 * Trip point values based on threshold control
43 * 0 = {105 C, 125 C, 145 C}
44 * 1 = {110 C, 130 C, 150 C}
45 * 2 = {115 C, 135 C, 155 C}
46 * 3 = {120 C, 140 C, 160 C}
47*/
48#define TEMP_STAGE_STEP 20000 /* Stage step: 20.000 C */
49#define TEMP_STAGE_HYSTERESIS 2000
50
51#define TEMP_THRESH_MIN 105000 /* Threshold Min: 105 C */
52#define TEMP_THRESH_STEP 5000 /* Threshold step: 5 C */
53
54#define THRESH_MIN 0
55#define THRESH_MAX 3
56
57/* Stage 2 Threshold Min: 125 C */
58#define STAGE2_THRESHOLD_MIN 125000
59/* Stage 2 Threshold Max: 140 C */
60#define STAGE2_THRESHOLD_MAX 140000
61
62/* Temperature in Milli Celsius reported during stage 0 if no ADC is present */
63#define DEFAULT_TEMP 37000
64
65struct qpnp_tm_chip {
66 struct regmap *map;
67 struct device *dev;
68 struct thermal_zone_device *tz_dev;
69 unsigned int subtype;
70 long temp;
71 unsigned int thresh;
72 unsigned int stage;
73 unsigned int prev_stage;
74 unsigned int base;
75 /* protects .thresh, .stage and chip registers */
76 struct mutex lock;
77 bool initialized;
78
79 struct iio_channel *adc;
80};
81
82/* This array maps from GEN2 alarm state to GEN1 alarm stage */
83static const unsigned int alarm_state_map[8] = {0, 1, 1, 2, 2, 3, 3, 3};
84
85static int qpnp_tm_read(struct qpnp_tm_chip *chip, u16 addr, u8 *data)
86{
87 unsigned int val;
88 int ret;
89
90 ret = regmap_read(chip->map, chip->base + addr, &val);
91 if (ret < 0)
92 return ret;
93
94 *data = val;
95 return 0;
96}
97
98static int qpnp_tm_write(struct qpnp_tm_chip *chip, u16 addr, u8 data)
99{
100 return regmap_write(chip->map, chip->base + addr, data);
101}
102
103/**
104 * qpnp_tm_get_temp_stage() - return over-temperature stage
105 * @chip: Pointer to the qpnp_tm chip
106 *
107 * Return: stage (GEN1) or state (GEN2) on success, or errno on failure.
108 */
109static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip *chip)
110{
111 int ret;
112 u8 reg = 0;
113
114 ret = qpnp_tm_read(chip, QPNP_TM_REG_STATUS, ®);
115 if (ret < 0)
116 return ret;
117
118 if (chip->subtype == QPNP_TM_SUBTYPE_GEN1)
119 ret = reg & STATUS_GEN1_STAGE_MASK;
120 else
121 ret = (reg & STATUS_GEN2_STATE_MASK) >> STATUS_GEN2_STATE_SHIFT;
122
123 return ret;
124}
125
126/*
127 * This function updates the internal temp value based on the
128 * current thermal stage and threshold as well as the previous stage
129 */
130static int qpnp_tm_update_temp_no_adc(struct qpnp_tm_chip *chip)
131{
132 unsigned int stage, stage_new, stage_old;
133 int ret;
134
135 WARN_ON(!mutex_is_locked(&chip->lock));
136
137 ret = qpnp_tm_get_temp_stage(chip);
138 if (ret < 0)
139 return ret;
140 stage = ret;
141
142 if (chip->subtype == QPNP_TM_SUBTYPE_GEN1) {
143 stage_new = stage;
144 stage_old = chip->stage;
145 } else {
146 stage_new = alarm_state_map[stage];
147 stage_old = alarm_state_map[chip->stage];
148 }
149
150 if (stage_new > stage_old) {
151 /* increasing stage, use lower bound */
152 chip->temp = (stage_new - 1) * TEMP_STAGE_STEP +
153 chip->thresh * TEMP_THRESH_STEP +
154 TEMP_STAGE_HYSTERESIS + TEMP_THRESH_MIN;
155 } else if (stage_new < stage_old) {
156 /* decreasing stage, use upper bound */
157 chip->temp = stage_new * TEMP_STAGE_STEP +
158 chip->thresh * TEMP_THRESH_STEP -
159 TEMP_STAGE_HYSTERESIS + TEMP_THRESH_MIN;
160 }
161
162 chip->stage = stage;
163
164 return 0;
165}
166
167static int qpnp_tm_get_temp(void *data, int *temp)
168{
169 struct qpnp_tm_chip *chip = data;
170 int ret, mili_celsius;
171
172 if (!temp)
173 return -EINVAL;
174
175 if (!chip->initialized) {
176 *temp = DEFAULT_TEMP;
177 return 0;
178 }
179
180 if (!chip->adc) {
181 mutex_lock(&chip->lock);
182 ret = qpnp_tm_update_temp_no_adc(chip);
183 mutex_unlock(&chip->lock);
184 if (ret < 0)
185 return ret;
186 } else {
187 ret = iio_read_channel_processed(chip->adc, &mili_celsius);
188 if (ret < 0)
189 return ret;
190
191 chip->temp = mili_celsius;
192 }
193
194 *temp = chip->temp;
195
196 return 0;
197}
198
199static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip,
200 int temp)
201{
202 u8 reg;
203 bool disable_s2_shutdown = false;
204
205 WARN_ON(!mutex_is_locked(&chip->lock));
206
207 /*
208 * Default: S2 and S3 shutdown enabled, thresholds at
209 * 105C/125C/145C, monitoring at 25Hz
210 */
211 reg = SHUTDOWN_CTRL1_RATE_25HZ;
212
213 if (temp == THERMAL_TEMP_INVALID ||
214 temp < STAGE2_THRESHOLD_MIN) {
215 chip->thresh = THRESH_MIN;
216 goto skip;
217 }
218
219 if (temp <= STAGE2_THRESHOLD_MAX) {
220 chip->thresh = THRESH_MAX -
221 ((STAGE2_THRESHOLD_MAX - temp) /
222 TEMP_THRESH_STEP);
223 disable_s2_shutdown = true;
224 } else {
225 chip->thresh = THRESH_MAX;
226
227 if (chip->adc)
228 disable_s2_shutdown = true;
229 else
230 dev_warn(chip->dev,
231 "No ADC is configured and critical temperature is above the maximum stage 2 threshold of 140 C! Configuring stage 2 shutdown at 140 C.\n");
232 }
233
234skip:
235 reg |= chip->thresh;
236 if (disable_s2_shutdown)
237 reg |= SHUTDOWN_CTRL1_OVERRIDE_S2;
238
239 return qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg);
240}
241
242static int qpnp_tm_set_trip_temp(void *data, int trip, int temp)
243{
244 struct qpnp_tm_chip *chip = data;
245 const struct thermal_trip *trip_points;
246 int ret;
247
248 trip_points = of_thermal_get_trip_points(chip->tz_dev);
249 if (!trip_points)
250 return -EINVAL;
251
252 if (trip_points[trip].type != THERMAL_TRIP_CRITICAL)
253 return 0;
254
255 mutex_lock(&chip->lock);
256 ret = qpnp_tm_update_critical_trip_temp(chip, temp);
257 mutex_unlock(&chip->lock);
258
259 return ret;
260}
261
262static const struct thermal_zone_of_device_ops qpnp_tm_sensor_ops = {
263 .get_temp = qpnp_tm_get_temp,
264 .set_trip_temp = qpnp_tm_set_trip_temp,
265};
266
267static irqreturn_t qpnp_tm_isr(int irq, void *data)
268{
269 struct qpnp_tm_chip *chip = data;
270
271 thermal_zone_device_update(chip->tz_dev, THERMAL_EVENT_UNSPECIFIED);
272
273 return IRQ_HANDLED;
274}
275
276static int qpnp_tm_get_critical_trip_temp(struct qpnp_tm_chip *chip)
277{
278 int ntrips;
279 const struct thermal_trip *trips;
280 int i;
281
282 ntrips = of_thermal_get_ntrips(chip->tz_dev);
283 if (ntrips <= 0)
284 return THERMAL_TEMP_INVALID;
285
286 trips = of_thermal_get_trip_points(chip->tz_dev);
287 if (!trips)
288 return THERMAL_TEMP_INVALID;
289
290 for (i = 0; i < ntrips; i++) {
291 if (of_thermal_is_trip_valid(chip->tz_dev, i) &&
292 trips[i].type == THERMAL_TRIP_CRITICAL)
293 return trips[i].temperature;
294 }
295
296 return THERMAL_TEMP_INVALID;
297}
298
299/*
300 * This function initializes the internal temp value based on only the
301 * current thermal stage and threshold. Setup threshold control and
302 * disable shutdown override.
303 */
304static int qpnp_tm_init(struct qpnp_tm_chip *chip)
305{
306 unsigned int stage;
307 int ret;
308 u8 reg = 0;
309 int crit_temp;
310
311 mutex_lock(&chip->lock);
312
313 ret = qpnp_tm_read(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, ®);
314 if (ret < 0)
315 goto out;
316
317 chip->thresh = reg & SHUTDOWN_CTRL1_THRESHOLD_MASK;
318 chip->temp = DEFAULT_TEMP;
319
320 ret = qpnp_tm_get_temp_stage(chip);
321 if (ret < 0)
322 goto out;
323 chip->stage = ret;
324
325 stage = chip->subtype == QPNP_TM_SUBTYPE_GEN1
326 ? chip->stage : alarm_state_map[chip->stage];
327
328 if (stage)
329 chip->temp = chip->thresh * TEMP_THRESH_STEP +
330 (stage - 1) * TEMP_STAGE_STEP +
331 TEMP_THRESH_MIN;
332
333 crit_temp = qpnp_tm_get_critical_trip_temp(chip);
334 ret = qpnp_tm_update_critical_trip_temp(chip, crit_temp);
335 if (ret < 0)
336 goto out;
337
338 /* Enable the thermal alarm PMIC module in always-on mode. */
339 reg = ALARM_CTRL_FORCE_ENABLE;
340 ret = qpnp_tm_write(chip, QPNP_TM_REG_ALARM_CTRL, reg);
341
342 chip->initialized = true;
343
344out:
345 mutex_unlock(&chip->lock);
346 return ret;
347}
348
349static int qpnp_tm_probe(struct platform_device *pdev)
350{
351 struct qpnp_tm_chip *chip;
352 struct device_node *node;
353 u8 type, subtype;
354 u32 res;
355 int ret, irq;
356
357 node = pdev->dev.of_node;
358
359 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
360 if (!chip)
361 return -ENOMEM;
362
363 dev_set_drvdata(&pdev->dev, chip);
364 chip->dev = &pdev->dev;
365
366 mutex_init(&chip->lock);
367
368 chip->map = dev_get_regmap(pdev->dev.parent, NULL);
369 if (!chip->map)
370 return -ENXIO;
371
372 ret = of_property_read_u32(node, "reg", &res);
373 if (ret < 0)
374 return ret;
375
376 irq = platform_get_irq(pdev, 0);
377 if (irq < 0)
378 return irq;
379
380 /* ADC based measurements are optional */
381 chip->adc = devm_iio_channel_get(&pdev->dev, "thermal");
382 if (IS_ERR(chip->adc)) {
383 ret = PTR_ERR(chip->adc);
384 chip->adc = NULL;
385 if (ret == -EPROBE_DEFER)
386 return ret;
387 }
388
389 chip->base = res;
390
391 ret = qpnp_tm_read(chip, QPNP_TM_REG_TYPE, &type);
392 if (ret < 0) {
393 dev_err(&pdev->dev, "could not read type\n");
394 return ret;
395 }
396
397 ret = qpnp_tm_read(chip, QPNP_TM_REG_SUBTYPE, &subtype);
398 if (ret < 0) {
399 dev_err(&pdev->dev, "could not read subtype\n");
400 return ret;
401 }
402
403 if (type != QPNP_TM_TYPE || (subtype != QPNP_TM_SUBTYPE_GEN1
404 && subtype != QPNP_TM_SUBTYPE_GEN2)) {
405 dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n",
406 type, subtype);
407 return -ENODEV;
408 }
409
410 chip->subtype = subtype;
411
412 /*
413 * Register the sensor before initializing the hardware to be able to
414 * read the trip points. get_temp() returns the default temperature
415 * before the hardware initialization is completed.
416 */
417 chip->tz_dev = devm_thermal_zone_of_sensor_register(
418 &pdev->dev, 0, chip, &qpnp_tm_sensor_ops);
419 if (IS_ERR(chip->tz_dev)) {
420 dev_err(&pdev->dev, "failed to register sensor\n");
421 return PTR_ERR(chip->tz_dev);
422 }
423
424 ret = qpnp_tm_init(chip);
425 if (ret < 0) {
426 dev_err(&pdev->dev, "init failed\n");
427 return ret;
428 }
429
430 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, qpnp_tm_isr,
431 IRQF_ONESHOT, node->name, chip);
432 if (ret < 0)
433 return ret;
434
435 thermal_zone_device_update(chip->tz_dev, THERMAL_EVENT_UNSPECIFIED);
436
437 return 0;
438}
439
440static const struct of_device_id qpnp_tm_match_table[] = {
441 { .compatible = "qcom,spmi-temp-alarm" },
442 { }
443};
444MODULE_DEVICE_TABLE(of, qpnp_tm_match_table);
445
446static struct platform_driver qpnp_tm_driver = {
447 .driver = {
448 .name = "spmi-temp-alarm",
449 .of_match_table = qpnp_tm_match_table,
450 },
451 .probe = qpnp_tm_probe,
452};
453module_platform_driver(qpnp_tm_driver);
454
455MODULE_ALIAS("platform:spmi-temp-alarm");
456MODULE_DESCRIPTION("QPNP PMIC Temperature Alarm driver");
457MODULE_LICENSE("GPL v2");