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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2019 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 */
6
7#include <linux/of_address.h>
8#include <linux/platform_device.h>
9#include <linux/pm_domain.h>
10#include <linux/bitfield.h>
11#include <linux/regmap.h>
12#include <linux/mfd/syscon.h>
13#include <linux/of_device.h>
14#include <linux/reset-controller.h>
15#include <linux/reset.h>
16#include <linux/clk.h>
17#include <dt-bindings/power/meson8-power.h>
18#include <dt-bindings/power/meson-g12a-power.h>
19#include <dt-bindings/power/meson-gxbb-power.h>
20#include <dt-bindings/power/meson-sm1-power.h>
21
22/* AO Offsets */
23
24#define GX_AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2)
25#define GX_AO_RTI_GEN_PWR_ISO0 (0x3b << 2)
26
27/*
28 * Meson8/Meson8b/Meson8m2 only expose the power management registers of the
29 * AO-bus as syscon. 0x3a from GX translates to 0x02, 0x3b translates to 0x03
30 * and so on.
31 */
32#define MESON8_AO_RTI_GEN_PWR_SLEEP0 (0x02 << 2)
33#define MESON8_AO_RTI_GEN_PWR_ISO0 (0x03 << 2)
34
35/* HHI Offsets */
36
37#define HHI_MEM_PD_REG0 (0x40 << 2)
38#define HHI_VPU_MEM_PD_REG0 (0x41 << 2)
39#define HHI_VPU_MEM_PD_REG1 (0x42 << 2)
40#define HHI_VPU_MEM_PD_REG3 (0x43 << 2)
41#define HHI_VPU_MEM_PD_REG4 (0x44 << 2)
42#define HHI_AUDIO_MEM_PD_REG0 (0x45 << 2)
43#define HHI_NANOQ_MEM_PD_REG0 (0x46 << 2)
44#define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2)
45#define HHI_VPU_MEM_PD_REG2 (0x4d << 2)
46
47struct meson_ee_pwrc;
48struct meson_ee_pwrc_domain;
49
50struct meson_ee_pwrc_mem_domain {
51 unsigned int reg;
52 unsigned int mask;
53};
54
55struct meson_ee_pwrc_top_domain {
56 unsigned int sleep_reg;
57 unsigned int sleep_mask;
58 unsigned int iso_reg;
59 unsigned int iso_mask;
60};
61
62struct meson_ee_pwrc_domain_desc {
63 char *name;
64 unsigned int reset_names_count;
65 unsigned int clk_names_count;
66 struct meson_ee_pwrc_top_domain *top_pd;
67 unsigned int mem_pd_count;
68 struct meson_ee_pwrc_mem_domain *mem_pd;
69 bool (*get_power)(struct meson_ee_pwrc_domain *pwrc_domain);
70};
71
72struct meson_ee_pwrc_domain_data {
73 unsigned int count;
74 struct meson_ee_pwrc_domain_desc *domains;
75};
76
77/* TOP Power Domains */
78
79static struct meson_ee_pwrc_top_domain gx_pwrc_vpu = {
80 .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0,
81 .sleep_mask = BIT(8),
82 .iso_reg = GX_AO_RTI_GEN_PWR_SLEEP0,
83 .iso_mask = BIT(9),
84};
85
86static struct meson_ee_pwrc_top_domain meson8_pwrc_vpu = {
87 .sleep_reg = MESON8_AO_RTI_GEN_PWR_SLEEP0,
88 .sleep_mask = BIT(8),
89 .iso_reg = MESON8_AO_RTI_GEN_PWR_SLEEP0,
90 .iso_mask = BIT(9),
91};
92
93#define SM1_EE_PD(__bit) \
94 { \
95 .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, \
96 .sleep_mask = BIT(__bit), \
97 .iso_reg = GX_AO_RTI_GEN_PWR_ISO0, \
98 .iso_mask = BIT(__bit), \
99 }
100
101static struct meson_ee_pwrc_top_domain sm1_pwrc_vpu = SM1_EE_PD(8);
102static struct meson_ee_pwrc_top_domain sm1_pwrc_nna = SM1_EE_PD(16);
103static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17);
104static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18);
105static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19);
106
107/* Memory PD Domains */
108
109#define VPU_MEMPD(__reg) \
110 { __reg, GENMASK(1, 0) }, \
111 { __reg, GENMASK(3, 2) }, \
112 { __reg, GENMASK(5, 4) }, \
113 { __reg, GENMASK(7, 6) }, \
114 { __reg, GENMASK(9, 8) }, \
115 { __reg, GENMASK(11, 10) }, \
116 { __reg, GENMASK(13, 12) }, \
117 { __reg, GENMASK(15, 14) }, \
118 { __reg, GENMASK(17, 16) }, \
119 { __reg, GENMASK(19, 18) }, \
120 { __reg, GENMASK(21, 20) }, \
121 { __reg, GENMASK(23, 22) }, \
122 { __reg, GENMASK(25, 24) }, \
123 { __reg, GENMASK(27, 26) }, \
124 { __reg, GENMASK(29, 28) }, \
125 { __reg, GENMASK(31, 30) }
126
127#define VPU_HHI_MEMPD(__reg) \
128 { __reg, BIT(8) }, \
129 { __reg, BIT(9) }, \
130 { __reg, BIT(10) }, \
131 { __reg, BIT(11) }, \
132 { __reg, BIT(12) }, \
133 { __reg, BIT(13) }, \
134 { __reg, BIT(14) }, \
135 { __reg, BIT(15) }
136
137static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_vpu[] = {
138 VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
139 VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
140 VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
141 VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
142};
143
144static struct meson_ee_pwrc_mem_domain gxbb_pwrc_mem_vpu[] = {
145 VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
146 VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
147 VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
148};
149
150static struct meson_ee_pwrc_mem_domain meson_pwrc_mem_eth[] = {
151 { HHI_MEM_PD_REG0, GENMASK(3, 2) },
152};
153
154static struct meson_ee_pwrc_mem_domain meson8_pwrc_audio_dsp_mem[] = {
155 { HHI_MEM_PD_REG0, GENMASK(1, 0) },
156};
157
158static struct meson_ee_pwrc_mem_domain meson8_pwrc_mem_vpu[] = {
159 VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
160 VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
161 VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
162};
163
164static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_vpu[] = {
165 VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
166 VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
167 VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
168 VPU_MEMPD(HHI_VPU_MEM_PD_REG3),
169 { HHI_VPU_MEM_PD_REG4, GENMASK(1, 0) },
170 { HHI_VPU_MEM_PD_REG4, GENMASK(3, 2) },
171 { HHI_VPU_MEM_PD_REG4, GENMASK(5, 4) },
172 { HHI_VPU_MEM_PD_REG4, GENMASK(7, 6) },
173 VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
174};
175
176static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_nna[] = {
177 { HHI_NANOQ_MEM_PD_REG0, 0xff },
178 { HHI_NANOQ_MEM_PD_REG1, 0xff },
179};
180
181static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_usb[] = {
182 { HHI_MEM_PD_REG0, GENMASK(31, 30) },
183};
184
185static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_pcie[] = {
186 { HHI_MEM_PD_REG0, GENMASK(29, 26) },
187};
188
189static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_ge2d[] = {
190 { HHI_MEM_PD_REG0, GENMASK(25, 18) },
191};
192
193static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
194 { HHI_MEM_PD_REG0, GENMASK(5, 4) },
195 { HHI_AUDIO_MEM_PD_REG0, GENMASK(1, 0) },
196 { HHI_AUDIO_MEM_PD_REG0, GENMASK(3, 2) },
197 { HHI_AUDIO_MEM_PD_REG0, GENMASK(5, 4) },
198 { HHI_AUDIO_MEM_PD_REG0, GENMASK(7, 6) },
199 { HHI_AUDIO_MEM_PD_REG0, GENMASK(13, 12) },
200 { HHI_AUDIO_MEM_PD_REG0, GENMASK(15, 14) },
201 { HHI_AUDIO_MEM_PD_REG0, GENMASK(17, 16) },
202 { HHI_AUDIO_MEM_PD_REG0, GENMASK(19, 18) },
203 { HHI_AUDIO_MEM_PD_REG0, GENMASK(21, 20) },
204 { HHI_AUDIO_MEM_PD_REG0, GENMASK(23, 22) },
205 { HHI_AUDIO_MEM_PD_REG0, GENMASK(25, 24) },
206 { HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) },
207};
208
209#define VPU_PD(__name, __top_pd, __mem, __get_power, __resets, __clks) \
210 { \
211 .name = __name, \
212 .reset_names_count = __resets, \
213 .clk_names_count = __clks, \
214 .top_pd = __top_pd, \
215 .mem_pd_count = ARRAY_SIZE(__mem), \
216 .mem_pd = __mem, \
217 .get_power = __get_power, \
218 }
219
220#define TOP_PD(__name, __top_pd, __mem, __get_power) \
221 { \
222 .name = __name, \
223 .top_pd = __top_pd, \
224 .mem_pd_count = ARRAY_SIZE(__mem), \
225 .mem_pd = __mem, \
226 .get_power = __get_power, \
227 }
228
229#define MEM_PD(__name, __mem) \
230 TOP_PD(__name, NULL, __mem, NULL)
231
232static bool pwrc_ee_get_power(struct meson_ee_pwrc_domain *pwrc_domain);
233
234static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
235 [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu,
236 pwrc_ee_get_power, 11, 2),
237 [PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
238};
239
240static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = {
241 [PWRC_GXBB_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, gxbb_pwrc_mem_vpu,
242 pwrc_ee_get_power, 12, 2),
243 [PWRC_GXBB_ETHERNET_MEM_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
244};
245
246static struct meson_ee_pwrc_domain_desc meson8_pwrc_domains[] = {
247 [PWRC_MESON8_VPU_ID] = VPU_PD("VPU", &meson8_pwrc_vpu,
248 meson8_pwrc_mem_vpu, pwrc_ee_get_power,
249 0, 1),
250 [PWRC_MESON8_ETHERNET_MEM_ID] = MEM_PD("ETHERNET_MEM",
251 meson_pwrc_mem_eth),
252 [PWRC_MESON8_AUDIO_DSP_MEM_ID] = MEM_PD("AUDIO_DSP_MEM",
253 meson8_pwrc_audio_dsp_mem),
254};
255
256static struct meson_ee_pwrc_domain_desc meson8b_pwrc_domains[] = {
257 [PWRC_MESON8_VPU_ID] = VPU_PD("VPU", &meson8_pwrc_vpu,
258 meson8_pwrc_mem_vpu, pwrc_ee_get_power,
259 11, 1),
260 [PWRC_MESON8_ETHERNET_MEM_ID] = MEM_PD("ETHERNET_MEM",
261 meson_pwrc_mem_eth),
262 [PWRC_MESON8_AUDIO_DSP_MEM_ID] = MEM_PD("AUDIO_DSP_MEM",
263 meson8_pwrc_audio_dsp_mem),
264};
265
266static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = {
267 [PWRC_SM1_VPU_ID] = VPU_PD("VPU", &sm1_pwrc_vpu, sm1_pwrc_mem_vpu,
268 pwrc_ee_get_power, 11, 2),
269 [PWRC_SM1_NNA_ID] = TOP_PD("NNA", &sm1_pwrc_nna, sm1_pwrc_mem_nna,
270 pwrc_ee_get_power),
271 [PWRC_SM1_USB_ID] = TOP_PD("USB", &sm1_pwrc_usb, sm1_pwrc_mem_usb,
272 pwrc_ee_get_power),
273 [PWRC_SM1_PCIE_ID] = TOP_PD("PCI", &sm1_pwrc_pci, sm1_pwrc_mem_pcie,
274 pwrc_ee_get_power),
275 [PWRC_SM1_GE2D_ID] = TOP_PD("GE2D", &sm1_pwrc_ge2d, sm1_pwrc_mem_ge2d,
276 pwrc_ee_get_power),
277 [PWRC_SM1_AUDIO_ID] = MEM_PD("AUDIO", sm1_pwrc_mem_audio),
278 [PWRC_SM1_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
279};
280
281struct meson_ee_pwrc_domain {
282 struct generic_pm_domain base;
283 bool enabled;
284 struct meson_ee_pwrc *pwrc;
285 struct meson_ee_pwrc_domain_desc desc;
286 struct clk_bulk_data *clks;
287 int num_clks;
288 struct reset_control *rstc;
289 int num_rstc;
290};
291
292struct meson_ee_pwrc {
293 struct regmap *regmap_ao;
294 struct regmap *regmap_hhi;
295 struct meson_ee_pwrc_domain *domains;
296 struct genpd_onecell_data xlate;
297};
298
299static bool pwrc_ee_get_power(struct meson_ee_pwrc_domain *pwrc_domain)
300{
301 u32 reg;
302
303 regmap_read(pwrc_domain->pwrc->regmap_ao,
304 pwrc_domain->desc.top_pd->sleep_reg, ®);
305
306 return (reg & pwrc_domain->desc.top_pd->sleep_mask);
307}
308
309static int meson_ee_pwrc_off(struct generic_pm_domain *domain)
310{
311 struct meson_ee_pwrc_domain *pwrc_domain =
312 container_of(domain, struct meson_ee_pwrc_domain, base);
313 int i;
314
315 if (pwrc_domain->desc.top_pd)
316 regmap_update_bits(pwrc_domain->pwrc->regmap_ao,
317 pwrc_domain->desc.top_pd->sleep_reg,
318 pwrc_domain->desc.top_pd->sleep_mask,
319 pwrc_domain->desc.top_pd->sleep_mask);
320 udelay(20);
321
322 for (i = 0 ; i < pwrc_domain->desc.mem_pd_count ; ++i)
323 regmap_update_bits(pwrc_domain->pwrc->regmap_hhi,
324 pwrc_domain->desc.mem_pd[i].reg,
325 pwrc_domain->desc.mem_pd[i].mask,
326 pwrc_domain->desc.mem_pd[i].mask);
327
328 udelay(20);
329
330 if (pwrc_domain->desc.top_pd)
331 regmap_update_bits(pwrc_domain->pwrc->regmap_ao,
332 pwrc_domain->desc.top_pd->iso_reg,
333 pwrc_domain->desc.top_pd->iso_mask,
334 pwrc_domain->desc.top_pd->iso_mask);
335
336 if (pwrc_domain->num_clks) {
337 msleep(20);
338 clk_bulk_disable_unprepare(pwrc_domain->num_clks,
339 pwrc_domain->clks);
340 }
341
342 return 0;
343}
344
345static int meson_ee_pwrc_on(struct generic_pm_domain *domain)
346{
347 struct meson_ee_pwrc_domain *pwrc_domain =
348 container_of(domain, struct meson_ee_pwrc_domain, base);
349 int i, ret;
350
351 if (pwrc_domain->desc.top_pd)
352 regmap_update_bits(pwrc_domain->pwrc->regmap_ao,
353 pwrc_domain->desc.top_pd->sleep_reg,
354 pwrc_domain->desc.top_pd->sleep_mask, 0);
355 udelay(20);
356
357 for (i = 0 ; i < pwrc_domain->desc.mem_pd_count ; ++i)
358 regmap_update_bits(pwrc_domain->pwrc->regmap_hhi,
359 pwrc_domain->desc.mem_pd[i].reg,
360 pwrc_domain->desc.mem_pd[i].mask, 0);
361
362 udelay(20);
363
364 ret = reset_control_assert(pwrc_domain->rstc);
365 if (ret)
366 return ret;
367
368 if (pwrc_domain->desc.top_pd)
369 regmap_update_bits(pwrc_domain->pwrc->regmap_ao,
370 pwrc_domain->desc.top_pd->iso_reg,
371 pwrc_domain->desc.top_pd->iso_mask, 0);
372
373 ret = reset_control_deassert(pwrc_domain->rstc);
374 if (ret)
375 return ret;
376
377 return clk_bulk_prepare_enable(pwrc_domain->num_clks,
378 pwrc_domain->clks);
379}
380
381static int meson_ee_pwrc_init_domain(struct platform_device *pdev,
382 struct meson_ee_pwrc *pwrc,
383 struct meson_ee_pwrc_domain *dom)
384{
385 int ret;
386
387 dom->pwrc = pwrc;
388 dom->num_rstc = dom->desc.reset_names_count;
389 dom->num_clks = dom->desc.clk_names_count;
390
391 if (dom->num_rstc) {
392 int count = reset_control_get_count(&pdev->dev);
393
394 if (count != dom->num_rstc)
395 dev_warn(&pdev->dev, "Invalid resets count %d for domain %s\n",
396 count, dom->desc.name);
397
398 dom->rstc = devm_reset_control_array_get(&pdev->dev, false,
399 false);
400 if (IS_ERR(dom->rstc))
401 return PTR_ERR(dom->rstc);
402 }
403
404 if (dom->num_clks) {
405 int ret = devm_clk_bulk_get_all(&pdev->dev, &dom->clks);
406 if (ret < 0)
407 return ret;
408
409 if (dom->num_clks != ret) {
410 dev_warn(&pdev->dev, "Invalid clocks count %d for domain %s\n",
411 ret, dom->desc.name);
412 dom->num_clks = ret;
413 }
414 }
415
416 dom->base.name = dom->desc.name;
417 dom->base.power_on = meson_ee_pwrc_on;
418 dom->base.power_off = meson_ee_pwrc_off;
419
420 /*
421 * TOFIX: This is a special case for the VPU power domain, which can
422 * be enabled previously by the bootloader. In this case the VPU
423 * pipeline may be functional but no driver maybe never attach
424 * to this power domain, and if the domain is disabled it could
425 * cause system errors. This is why the pm_domain_always_on_gov
426 * is used here.
427 * For the same reason, the clocks should be enabled in case
428 * we need to power the domain off, otherwise the internal clocks
429 * prepare/enable counters won't be in sync.
430 */
431 if (dom->num_clks && dom->desc.get_power && !dom->desc.get_power(dom)) {
432 ret = clk_bulk_prepare_enable(dom->num_clks, dom->clks);
433 if (ret)
434 return ret;
435
436 ret = pm_genpd_init(&dom->base, &pm_domain_always_on_gov,
437 false);
438 if (ret)
439 return ret;
440 } else {
441 ret = pm_genpd_init(&dom->base, NULL,
442 (dom->desc.get_power ?
443 dom->desc.get_power(dom) : true));
444 if (ret)
445 return ret;
446 }
447
448 return 0;
449}
450
451static int meson_ee_pwrc_probe(struct platform_device *pdev)
452{
453 const struct meson_ee_pwrc_domain_data *match;
454 struct regmap *regmap_ao, *regmap_hhi;
455 struct meson_ee_pwrc *pwrc;
456 int i, ret;
457
458 match = of_device_get_match_data(&pdev->dev);
459 if (!match) {
460 dev_err(&pdev->dev, "failed to get match data\n");
461 return -ENODEV;
462 }
463
464 pwrc = devm_kzalloc(&pdev->dev, sizeof(*pwrc), GFP_KERNEL);
465 if (!pwrc)
466 return -ENOMEM;
467
468 pwrc->xlate.domains = devm_kcalloc(&pdev->dev, match->count,
469 sizeof(*pwrc->xlate.domains),
470 GFP_KERNEL);
471 if (!pwrc->xlate.domains)
472 return -ENOMEM;
473
474 pwrc->domains = devm_kcalloc(&pdev->dev, match->count,
475 sizeof(*pwrc->domains), GFP_KERNEL);
476 if (!pwrc->domains)
477 return -ENOMEM;
478
479 pwrc->xlate.num_domains = match->count;
480
481 regmap_hhi = syscon_node_to_regmap(of_get_parent(pdev->dev.of_node));
482 if (IS_ERR(regmap_hhi)) {
483 dev_err(&pdev->dev, "failed to get HHI regmap\n");
484 return PTR_ERR(regmap_hhi);
485 }
486
487 regmap_ao = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
488 "amlogic,ao-sysctrl");
489 if (IS_ERR(regmap_ao)) {
490 dev_err(&pdev->dev, "failed to get AO regmap\n");
491 return PTR_ERR(regmap_ao);
492 }
493
494 pwrc->regmap_ao = regmap_ao;
495 pwrc->regmap_hhi = regmap_hhi;
496
497 platform_set_drvdata(pdev, pwrc);
498
499 for (i = 0 ; i < match->count ; ++i) {
500 struct meson_ee_pwrc_domain *dom = &pwrc->domains[i];
501
502 memcpy(&dom->desc, &match->domains[i], sizeof(dom->desc));
503
504 ret = meson_ee_pwrc_init_domain(pdev, pwrc, dom);
505 if (ret)
506 return ret;
507
508 pwrc->xlate.domains[i] = &dom->base;
509 }
510
511 return of_genpd_add_provider_onecell(pdev->dev.of_node, &pwrc->xlate);
512}
513
514static void meson_ee_pwrc_shutdown(struct platform_device *pdev)
515{
516 struct meson_ee_pwrc *pwrc = platform_get_drvdata(pdev);
517 int i;
518
519 for (i = 0 ; i < pwrc->xlate.num_domains ; ++i) {
520 struct meson_ee_pwrc_domain *dom = &pwrc->domains[i];
521
522 if (dom->desc.get_power && !dom->desc.get_power(dom))
523 meson_ee_pwrc_off(&dom->base);
524 }
525}
526
527static struct meson_ee_pwrc_domain_data meson_ee_g12a_pwrc_data = {
528 .count = ARRAY_SIZE(g12a_pwrc_domains),
529 .domains = g12a_pwrc_domains,
530};
531
532static struct meson_ee_pwrc_domain_data meson_ee_gxbb_pwrc_data = {
533 .count = ARRAY_SIZE(gxbb_pwrc_domains),
534 .domains = gxbb_pwrc_domains,
535};
536
537static struct meson_ee_pwrc_domain_data meson_ee_m8_pwrc_data = {
538 .count = ARRAY_SIZE(meson8_pwrc_domains),
539 .domains = meson8_pwrc_domains,
540};
541
542static struct meson_ee_pwrc_domain_data meson_ee_m8b_pwrc_data = {
543 .count = ARRAY_SIZE(meson8b_pwrc_domains),
544 .domains = meson8b_pwrc_domains,
545};
546
547static struct meson_ee_pwrc_domain_data meson_ee_sm1_pwrc_data = {
548 .count = ARRAY_SIZE(sm1_pwrc_domains),
549 .domains = sm1_pwrc_domains,
550};
551
552static const struct of_device_id meson_ee_pwrc_match_table[] = {
553 {
554 .compatible = "amlogic,meson8-pwrc",
555 .data = &meson_ee_m8_pwrc_data,
556 },
557 {
558 .compatible = "amlogic,meson8b-pwrc",
559 .data = &meson_ee_m8b_pwrc_data,
560 },
561 {
562 .compatible = "amlogic,meson8m2-pwrc",
563 .data = &meson_ee_m8b_pwrc_data,
564 },
565 {
566 .compatible = "amlogic,meson-gxbb-pwrc",
567 .data = &meson_ee_gxbb_pwrc_data,
568 },
569 {
570 .compatible = "amlogic,meson-g12a-pwrc",
571 .data = &meson_ee_g12a_pwrc_data,
572 },
573 {
574 .compatible = "amlogic,meson-sm1-pwrc",
575 .data = &meson_ee_sm1_pwrc_data,
576 },
577 { /* sentinel */ }
578};
579
580static struct platform_driver meson_ee_pwrc_driver = {
581 .probe = meson_ee_pwrc_probe,
582 .shutdown = meson_ee_pwrc_shutdown,
583 .driver = {
584 .name = "meson_ee_pwrc",
585 .of_match_table = meson_ee_pwrc_match_table,
586 },
587};
588builtin_platform_driver(meson_ee_pwrc_driver);