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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
4 */
5
6#include <linux/acpi.h>
7#include <linux/time.h>
8#include <linux/of.h>
9#include <linux/platform_device.h>
10#include <linux/phy/phy.h>
11#include <linux/gpio/consumer.h>
12#include <linux/reset-controller.h>
13#include <linux/devfreq.h>
14
15#include "ufshcd.h"
16#include "ufshcd-pltfrm.h"
17#include "unipro.h"
18#include "ufs-qcom.h"
19#include "ufshci.h"
20#include "ufs_quirks.h"
21#define UFS_QCOM_DEFAULT_DBG_PRINT_EN \
22 (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
23
24enum {
25 TSTBUS_UAWM,
26 TSTBUS_UARM,
27 TSTBUS_TXUC,
28 TSTBUS_RXUC,
29 TSTBUS_DFC,
30 TSTBUS_TRLUT,
31 TSTBUS_TMRLUT,
32 TSTBUS_OCSC,
33 TSTBUS_UTP_HCI,
34 TSTBUS_COMBINED,
35 TSTBUS_WRAPPER,
36 TSTBUS_UNIPRO,
37 TSTBUS_MAX,
38};
39
40static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
41
42static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
43static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
44 u32 clk_cycles);
45
46static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
47{
48 return container_of(rcd, struct ufs_qcom_host, rcdev);
49}
50
51static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,
52 const char *prefix, void *priv)
53{
54 ufshcd_dump_regs(hba, offset, len * 4, prefix);
55}
56
57static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
58{
59 int err = 0;
60
61 err = ufshcd_dme_get(hba,
62 UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes);
63 if (err)
64 dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n",
65 __func__, err);
66
67 return err;
68}
69
70static int ufs_qcom_host_clk_get(struct device *dev,
71 const char *name, struct clk **clk_out, bool optional)
72{
73 struct clk *clk;
74 int err = 0;
75
76 clk = devm_clk_get(dev, name);
77 if (!IS_ERR(clk)) {
78 *clk_out = clk;
79 return 0;
80 }
81
82 err = PTR_ERR(clk);
83
84 if (optional && err == -ENOENT) {
85 *clk_out = NULL;
86 return 0;
87 }
88
89 if (err != -EPROBE_DEFER)
90 dev_err(dev, "failed to get %s err %d\n", name, err);
91
92 return err;
93}
94
95static int ufs_qcom_host_clk_enable(struct device *dev,
96 const char *name, struct clk *clk)
97{
98 int err = 0;
99
100 err = clk_prepare_enable(clk);
101 if (err)
102 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err);
103
104 return err;
105}
106
107static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
108{
109 if (!host->is_lane_clks_enabled)
110 return;
111
112 clk_disable_unprepare(host->tx_l1_sync_clk);
113 clk_disable_unprepare(host->tx_l0_sync_clk);
114 clk_disable_unprepare(host->rx_l1_sync_clk);
115 clk_disable_unprepare(host->rx_l0_sync_clk);
116
117 host->is_lane_clks_enabled = false;
118}
119
120static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
121{
122 int err = 0;
123 struct device *dev = host->hba->dev;
124
125 if (host->is_lane_clks_enabled)
126 return 0;
127
128 err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
129 host->rx_l0_sync_clk);
130 if (err)
131 goto out;
132
133 err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
134 host->tx_l0_sync_clk);
135 if (err)
136 goto disable_rx_l0;
137
138 err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
139 host->rx_l1_sync_clk);
140 if (err)
141 goto disable_tx_l0;
142
143 err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
144 host->tx_l1_sync_clk);
145 if (err)
146 goto disable_rx_l1;
147
148 host->is_lane_clks_enabled = true;
149 goto out;
150
151disable_rx_l1:
152 clk_disable_unprepare(host->rx_l1_sync_clk);
153disable_tx_l0:
154 clk_disable_unprepare(host->tx_l0_sync_clk);
155disable_rx_l0:
156 clk_disable_unprepare(host->rx_l0_sync_clk);
157out:
158 return err;
159}
160
161static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
162{
163 int err = 0;
164 struct device *dev = host->hba->dev;
165
166 if (has_acpi_companion(dev))
167 return 0;
168
169 err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk",
170 &host->rx_l0_sync_clk, false);
171 if (err)
172 goto out;
173
174 err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk",
175 &host->tx_l0_sync_clk, false);
176 if (err)
177 goto out;
178
179 /* In case of single lane per direction, don't read lane1 clocks */
180 if (host->hba->lanes_per_direction > 1) {
181 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
182 &host->rx_l1_sync_clk, false);
183 if (err)
184 goto out;
185
186 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
187 &host->tx_l1_sync_clk, true);
188 }
189out:
190 return err;
191}
192
193static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
194{
195 u32 tx_lanes;
196
197 return ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);
198}
199
200static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
201{
202 int err;
203 u32 tx_fsm_val = 0;
204 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
205
206 do {
207 err = ufshcd_dme_get(hba,
208 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
209 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
210 &tx_fsm_val);
211 if (err || tx_fsm_val == TX_FSM_HIBERN8)
212 break;
213
214 /* sleep for max. 200us */
215 usleep_range(100, 200);
216 } while (time_before(jiffies, timeout));
217
218 /*
219 * we might have scheduled out for long during polling so
220 * check the state again.
221 */
222 if (time_after(jiffies, timeout))
223 err = ufshcd_dme_get(hba,
224 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
225 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
226 &tx_fsm_val);
227
228 if (err) {
229 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
230 __func__, err);
231 } else if (tx_fsm_val != TX_FSM_HIBERN8) {
232 err = tx_fsm_val;
233 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
234 __func__, err);
235 }
236
237 return err;
238}
239
240static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
241{
242 ufshcd_rmwl(host->hba, QUNIPRO_SEL,
243 ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0,
244 REG_UFS_CFG1);
245 /* make sure above configuration is applied before we return */
246 mb();
247}
248
249/*
250 * ufs_qcom_host_reset - reset host controller and PHY
251 */
252static int ufs_qcom_host_reset(struct ufs_hba *hba)
253{
254 int ret = 0;
255 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
256
257 if (!host->core_reset) {
258 dev_warn(hba->dev, "%s: reset control not set\n", __func__);
259 goto out;
260 }
261
262 ret = reset_control_assert(host->core_reset);
263 if (ret) {
264 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",
265 __func__, ret);
266 goto out;
267 }
268
269 /*
270 * The hardware requirement for delay between assert/deassert
271 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
272 * ~125us (4/32768). To be on the safe side add 200us delay.
273 */
274 usleep_range(200, 210);
275
276 ret = reset_control_deassert(host->core_reset);
277 if (ret)
278 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n",
279 __func__, ret);
280
281 usleep_range(1000, 1100);
282
283out:
284 return ret;
285}
286
287static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
288{
289 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
290 struct phy *phy = host->generic_phy;
291 int ret = 0;
292 bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B)
293 ? true : false;
294
295 /* Reset UFS Host Controller and PHY */
296 ret = ufs_qcom_host_reset(hba);
297 if (ret)
298 dev_warn(hba->dev, "%s: host reset returned %d\n",
299 __func__, ret);
300
301 if (is_rate_B)
302 phy_set_mode(phy, PHY_MODE_UFS_HS_B);
303
304 /* phy initialization - calibrate the phy */
305 ret = phy_init(phy);
306 if (ret) {
307 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
308 __func__, ret);
309 goto out;
310 }
311
312 /* power on phy - start serdes and phy's power and clocks */
313 ret = phy_power_on(phy);
314 if (ret) {
315 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
316 __func__, ret);
317 goto out_disable_phy;
318 }
319
320 ufs_qcom_select_unipro_mode(host);
321
322 return 0;
323
324out_disable_phy:
325 phy_exit(phy);
326out:
327 return ret;
328}
329
330/*
331 * The UTP controller has a number of internal clock gating cells (CGCs).
332 * Internal hardware sub-modules within the UTP controller control the CGCs.
333 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
334 * in a specific operation, UTP controller CGCs are by default disabled and
335 * this function enables them (after every UFS link startup) to save some power
336 * leakage.
337 */
338static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
339{
340 ufshcd_writel(hba,
341 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
342 REG_UFS_CFG2);
343
344 /* Ensure that HW clock gating is enabled before next operations */
345 mb();
346}
347
348static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
349 enum ufs_notify_change_status status)
350{
351 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
352 int err = 0;
353
354 switch (status) {
355 case PRE_CHANGE:
356 ufs_qcom_power_up_sequence(hba);
357 /*
358 * The PHY PLL output is the source of tx/rx lane symbol
359 * clocks, hence, enable the lane clocks only after PHY
360 * is initialized.
361 */
362 err = ufs_qcom_enable_lane_clks(host);
363 break;
364 case POST_CHANGE:
365 /* check if UFS PHY moved from DISABLED to HIBERN8 */
366 err = ufs_qcom_check_hibern8(hba);
367 ufs_qcom_enable_hw_clk_gating(hba);
368 ufs_qcom_ice_enable(host);
369 break;
370 default:
371 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
372 err = -EINVAL;
373 break;
374 }
375 return err;
376}
377
378/*
379 * Returns zero for success and non-zero in case of a failure
380 */
381static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
382 u32 hs, u32 rate, bool update_link_startup_timer)
383{
384 int ret = 0;
385 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
386 struct ufs_clk_info *clki;
387 u32 core_clk_period_in_ns;
388 u32 tx_clk_cycles_per_us = 0;
389 unsigned long core_clk_rate = 0;
390 u32 core_clk_cycles_per_us = 0;
391
392 static u32 pwm_fr_table[][2] = {
393 {UFS_PWM_G1, 0x1},
394 {UFS_PWM_G2, 0x1},
395 {UFS_PWM_G3, 0x1},
396 {UFS_PWM_G4, 0x1},
397 };
398
399 static u32 hs_fr_table_rA[][2] = {
400 {UFS_HS_G1, 0x1F},
401 {UFS_HS_G2, 0x3e},
402 {UFS_HS_G3, 0x7D},
403 };
404
405 static u32 hs_fr_table_rB[][2] = {
406 {UFS_HS_G1, 0x24},
407 {UFS_HS_G2, 0x49},
408 {UFS_HS_G3, 0x92},
409 };
410
411 /*
412 * The Qunipro controller does not use following registers:
413 * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
414 * UFS_REG_PA_LINK_STARTUP_TIMER
415 * But UTP controller uses SYS1CLK_1US_REG register for Interrupt
416 * Aggregation logic.
417 */
418 if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
419 goto out;
420
421 if (gear == 0) {
422 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
423 goto out_error;
424 }
425
426 list_for_each_entry(clki, &hba->clk_list_head, list) {
427 if (!strcmp(clki->name, "core_clk"))
428 core_clk_rate = clk_get_rate(clki->clk);
429 }
430
431 /* If frequency is smaller than 1MHz, set to 1MHz */
432 if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
433 core_clk_rate = DEFAULT_CLK_RATE_HZ;
434
435 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
436 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
437 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
438 /*
439 * make sure above write gets applied before we return from
440 * this function.
441 */
442 mb();
443 }
444
445 if (ufs_qcom_cap_qunipro(host))
446 goto out;
447
448 core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
449 core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
450 core_clk_period_in_ns &= MASK_CLK_NS_REG;
451
452 switch (hs) {
453 case FASTAUTO_MODE:
454 case FAST_MODE:
455 if (rate == PA_HS_MODE_A) {
456 if (gear > ARRAY_SIZE(hs_fr_table_rA)) {
457 dev_err(hba->dev,
458 "%s: index %d exceeds table size %zu\n",
459 __func__, gear,
460 ARRAY_SIZE(hs_fr_table_rA));
461 goto out_error;
462 }
463 tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
464 } else if (rate == PA_HS_MODE_B) {
465 if (gear > ARRAY_SIZE(hs_fr_table_rB)) {
466 dev_err(hba->dev,
467 "%s: index %d exceeds table size %zu\n",
468 __func__, gear,
469 ARRAY_SIZE(hs_fr_table_rB));
470 goto out_error;
471 }
472 tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
473 } else {
474 dev_err(hba->dev, "%s: invalid rate = %d\n",
475 __func__, rate);
476 goto out_error;
477 }
478 break;
479 case SLOWAUTO_MODE:
480 case SLOW_MODE:
481 if (gear > ARRAY_SIZE(pwm_fr_table)) {
482 dev_err(hba->dev,
483 "%s: index %d exceeds table size %zu\n",
484 __func__, gear,
485 ARRAY_SIZE(pwm_fr_table));
486 goto out_error;
487 }
488 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
489 break;
490 case UNCHANGED:
491 default:
492 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
493 goto out_error;
494 }
495
496 if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=
497 (core_clk_period_in_ns | tx_clk_cycles_per_us)) {
498 /* this register 2 fields shall be written at once */
499 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,
500 REG_UFS_TX_SYMBOL_CLK_NS_US);
501 /*
502 * make sure above write gets applied before we return from
503 * this function.
504 */
505 mb();
506 }
507
508 if (update_link_startup_timer) {
509 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100),
510 REG_UFS_PA_LINK_STARTUP_TIMER);
511 /*
512 * make sure that this configuration is applied before
513 * we return
514 */
515 mb();
516 }
517 goto out;
518
519out_error:
520 ret = -EINVAL;
521out:
522 return ret;
523}
524
525static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
526 enum ufs_notify_change_status status)
527{
528 int err = 0;
529 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
530
531 switch (status) {
532 case PRE_CHANGE:
533 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
534 0, true)) {
535 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
536 __func__);
537 err = -EINVAL;
538 goto out;
539 }
540
541 if (ufs_qcom_cap_qunipro(host))
542 /*
543 * set unipro core clock cycles to 150 & clear clock
544 * divider
545 */
546 err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba,
547 150);
548
549 /*
550 * Some UFS devices (and may be host) have issues if LCC is
551 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
552 * before link startup which will make sure that both host
553 * and device TX LCC are disabled once link startup is
554 * completed.
555 */
556 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41)
557 err = ufshcd_disable_host_tx_lcc(hba);
558
559 break;
560 case POST_CHANGE:
561 ufs_qcom_link_startup_post_change(hba);
562 break;
563 default:
564 break;
565 }
566
567out:
568 return err;
569}
570
571static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
572{
573 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
574 struct phy *phy = host->generic_phy;
575
576 if (ufs_qcom_is_link_off(hba)) {
577 /*
578 * Disable the tx/rx lane symbol clocks before PHY is
579 * powered down as the PLL source should be disabled
580 * after downstream clocks are disabled.
581 */
582 ufs_qcom_disable_lane_clks(host);
583 phy_power_off(phy);
584
585 } else if (!ufs_qcom_is_link_active(hba)) {
586 ufs_qcom_disable_lane_clks(host);
587 }
588
589 return 0;
590}
591
592static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
593{
594 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
595 struct phy *phy = host->generic_phy;
596 int err;
597
598 if (ufs_qcom_is_link_off(hba)) {
599 err = phy_power_on(phy);
600 if (err) {
601 dev_err(hba->dev, "%s: failed PHY power on: %d\n",
602 __func__, err);
603 return err;
604 }
605
606 err = ufs_qcom_enable_lane_clks(host);
607 if (err)
608 return err;
609
610 } else if (!ufs_qcom_is_link_active(hba)) {
611 err = ufs_qcom_enable_lane_clks(host);
612 if (err)
613 return err;
614 }
615
616 err = ufs_qcom_ice_resume(host);
617 if (err)
618 return err;
619
620 hba->is_sys_suspended = false;
621 return 0;
622}
623
624#ifdef CONFIG_MSM_BUS_SCALING
625static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host,
626 const char *speed_mode)
627{
628 struct device *dev = host->hba->dev;
629 struct device_node *np = dev->of_node;
630 int err;
631 const char *key = "qcom,bus-vector-names";
632
633 if (!speed_mode) {
634 err = -EINVAL;
635 goto out;
636 }
637
638 if (host->bus_vote.is_max_bw_needed && !!strcmp(speed_mode, "MIN"))
639 err = of_property_match_string(np, key, "MAX");
640 else
641 err = of_property_match_string(np, key, speed_mode);
642
643out:
644 if (err < 0)
645 dev_err(dev, "%s: Invalid %s mode %d\n",
646 __func__, speed_mode, err);
647 return err;
648}
649
650static void ufs_qcom_get_speed_mode(struct ufs_pa_layer_attr *p, char *result)
651{
652 int gear = max_t(u32, p->gear_rx, p->gear_tx);
653 int lanes = max_t(u32, p->lane_rx, p->lane_tx);
654 int pwr;
655
656 /* default to PWM Gear 1, Lane 1 if power mode is not initialized */
657 if (!gear)
658 gear = 1;
659
660 if (!lanes)
661 lanes = 1;
662
663 if (!p->pwr_rx && !p->pwr_tx) {
664 pwr = SLOWAUTO_MODE;
665 snprintf(result, BUS_VECTOR_NAME_LEN, "MIN");
666 } else if (p->pwr_rx == FAST_MODE || p->pwr_rx == FASTAUTO_MODE ||
667 p->pwr_tx == FAST_MODE || p->pwr_tx == FASTAUTO_MODE) {
668 pwr = FAST_MODE;
669 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_R%s_G%d_L%d", "HS",
670 p->hs_rate == PA_HS_MODE_B ? "B" : "A", gear, lanes);
671 } else {
672 pwr = SLOW_MODE;
673 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_G%d_L%d",
674 "PWM", gear, lanes);
675 }
676}
677
678static int __ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
679{
680 int err = 0;
681
682 if (vote != host->bus_vote.curr_vote) {
683 err = msm_bus_scale_client_update_request(
684 host->bus_vote.client_handle, vote);
685 if (err) {
686 dev_err(host->hba->dev,
687 "%s: msm_bus_scale_client_update_request() failed: bus_client_handle=0x%x, vote=%d, err=%d\n",
688 __func__, host->bus_vote.client_handle,
689 vote, err);
690 goto out;
691 }
692
693 host->bus_vote.curr_vote = vote;
694 }
695out:
696 return err;
697}
698
699static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
700{
701 int vote;
702 int err = 0;
703 char mode[BUS_VECTOR_NAME_LEN];
704
705 ufs_qcom_get_speed_mode(&host->dev_req_params, mode);
706
707 vote = ufs_qcom_get_bus_vote(host, mode);
708 if (vote >= 0)
709 err = __ufs_qcom_set_bus_vote(host, vote);
710 else
711 err = vote;
712
713 if (err)
714 dev_err(host->hba->dev, "%s: failed %d\n", __func__, err);
715 else
716 host->bus_vote.saved_vote = vote;
717 return err;
718}
719
720static int ufs_qcom_set_bus_vote(struct ufs_hba *hba, bool on)
721{
722 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
723 int vote, err;
724
725 /*
726 * In case ufs_qcom_init() is not yet done, simply ignore.
727 * This ufs_qcom_set_bus_vote() shall be called from
728 * ufs_qcom_init() after init is done.
729 */
730 if (!host)
731 return 0;
732
733 if (on) {
734 vote = host->bus_vote.saved_vote;
735 if (vote == host->bus_vote.min_bw_vote)
736 ufs_qcom_update_bus_bw_vote(host);
737 } else {
738 vote = host->bus_vote.min_bw_vote;
739 }
740
741 err = __ufs_qcom_set_bus_vote(host, vote);
742 if (err)
743 dev_err(hba->dev, "%s: set bus vote failed %d\n",
744 __func__, err);
745
746 return err;
747}
748
749static ssize_t
750show_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
751 char *buf)
752{
753 struct ufs_hba *hba = dev_get_drvdata(dev);
754 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
755
756 return snprintf(buf, PAGE_SIZE, "%u\n",
757 host->bus_vote.is_max_bw_needed);
758}
759
760static ssize_t
761store_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
762 const char *buf, size_t count)
763{
764 struct ufs_hba *hba = dev_get_drvdata(dev);
765 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
766 uint32_t value;
767
768 if (!kstrtou32(buf, 0, &value)) {
769 host->bus_vote.is_max_bw_needed = !!value;
770 ufs_qcom_update_bus_bw_vote(host);
771 }
772
773 return count;
774}
775
776static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
777{
778 int err;
779 struct msm_bus_scale_pdata *bus_pdata;
780 struct device *dev = host->hba->dev;
781 struct platform_device *pdev = to_platform_device(dev);
782 struct device_node *np = dev->of_node;
783
784 bus_pdata = msm_bus_cl_get_pdata(pdev);
785 if (!bus_pdata) {
786 dev_err(dev, "%s: failed to get bus vectors\n", __func__);
787 err = -ENODATA;
788 goto out;
789 }
790
791 err = of_property_count_strings(np, "qcom,bus-vector-names");
792 if (err < 0 || err != bus_pdata->num_usecases) {
793 dev_err(dev, "%s: qcom,bus-vector-names not specified correctly %d\n",
794 __func__, err);
795 goto out;
796 }
797
798 host->bus_vote.client_handle = msm_bus_scale_register_client(bus_pdata);
799 if (!host->bus_vote.client_handle) {
800 dev_err(dev, "%s: msm_bus_scale_register_client failed\n",
801 __func__);
802 err = -EFAULT;
803 goto out;
804 }
805
806 /* cache the vote index for minimum and maximum bandwidth */
807 host->bus_vote.min_bw_vote = ufs_qcom_get_bus_vote(host, "MIN");
808 host->bus_vote.max_bw_vote = ufs_qcom_get_bus_vote(host, "MAX");
809
810 host->bus_vote.max_bus_bw.show = show_ufs_to_mem_max_bus_bw;
811 host->bus_vote.max_bus_bw.store = store_ufs_to_mem_max_bus_bw;
812 sysfs_attr_init(&host->bus_vote.max_bus_bw.attr);
813 host->bus_vote.max_bus_bw.attr.name = "max_bus_bw";
814 host->bus_vote.max_bus_bw.attr.mode = S_IRUGO | S_IWUSR;
815 err = device_create_file(dev, &host->bus_vote.max_bus_bw);
816out:
817 return err;
818}
819#else /* CONFIG_MSM_BUS_SCALING */
820static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
821{
822 return 0;
823}
824
825static int ufs_qcom_set_bus_vote(struct ufs_hba *host, bool on)
826{
827 return 0;
828}
829
830static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
831{
832 return 0;
833}
834#endif /* CONFIG_MSM_BUS_SCALING */
835
836static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
837{
838 if (host->dev_ref_clk_ctrl_mmio &&
839 (enable ^ host->is_dev_ref_clk_enabled)) {
840 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
841
842 if (enable)
843 temp |= host->dev_ref_clk_en_mask;
844 else
845 temp &= ~host->dev_ref_clk_en_mask;
846
847 /*
848 * If we are here to disable this clock it might be immediately
849 * after entering into hibern8 in which case we need to make
850 * sure that device ref_clk is active for specific time after
851 * hibern8 enter.
852 */
853 if (!enable) {
854 unsigned long gating_wait;
855
856 gating_wait = host->hba->dev_info.clk_gating_wait_us;
857 if (!gating_wait) {
858 udelay(1);
859 } else {
860 /*
861 * bRefClkGatingWaitTime defines the minimum
862 * time for which the reference clock is
863 * required by device during transition from
864 * HS-MODE to LS-MODE or HIBERN8 state. Give it
865 * more delay to be on the safe side.
866 */
867 gating_wait += 10;
868 usleep_range(gating_wait, gating_wait + 10);
869 }
870 }
871
872 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
873
874 /* ensure that ref_clk is enabled/disabled before we return */
875 wmb();
876
877 /*
878 * If we call hibern8 exit after this, we need to make sure that
879 * device ref_clk is stable for at least 1us before the hibern8
880 * exit command.
881 */
882 if (enable)
883 udelay(1);
884
885 host->is_dev_ref_clk_enabled = enable;
886 }
887}
888
889static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
890 enum ufs_notify_change_status status,
891 struct ufs_pa_layer_attr *dev_max_params,
892 struct ufs_pa_layer_attr *dev_req_params)
893{
894 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
895 struct ufs_dev_params ufs_qcom_cap;
896 int ret = 0;
897
898 if (!dev_req_params) {
899 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
900 ret = -EINVAL;
901 goto out;
902 }
903
904 switch (status) {
905 case PRE_CHANGE:
906 ufs_qcom_cap.tx_lanes = UFS_QCOM_LIMIT_NUM_LANES_TX;
907 ufs_qcom_cap.rx_lanes = UFS_QCOM_LIMIT_NUM_LANES_RX;
908 ufs_qcom_cap.hs_rx_gear = UFS_QCOM_LIMIT_HSGEAR_RX;
909 ufs_qcom_cap.hs_tx_gear = UFS_QCOM_LIMIT_HSGEAR_TX;
910 ufs_qcom_cap.pwm_rx_gear = UFS_QCOM_LIMIT_PWMGEAR_RX;
911 ufs_qcom_cap.pwm_tx_gear = UFS_QCOM_LIMIT_PWMGEAR_TX;
912 ufs_qcom_cap.rx_pwr_pwm = UFS_QCOM_LIMIT_RX_PWR_PWM;
913 ufs_qcom_cap.tx_pwr_pwm = UFS_QCOM_LIMIT_TX_PWR_PWM;
914 ufs_qcom_cap.rx_pwr_hs = UFS_QCOM_LIMIT_RX_PWR_HS;
915 ufs_qcom_cap.tx_pwr_hs = UFS_QCOM_LIMIT_TX_PWR_HS;
916 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
917 ufs_qcom_cap.desired_working_mode =
918 UFS_QCOM_LIMIT_DESIRED_MODE;
919
920 if (host->hw_ver.major == 0x1) {
921 /*
922 * HS-G3 operations may not reliably work on legacy QCOM
923 * UFS host controller hardware even though capability
924 * exchange during link startup phase may end up
925 * negotiating maximum supported gear as G3.
926 * Hence downgrade the maximum supported gear to HS-G2.
927 */
928 if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2)
929 ufs_qcom_cap.hs_tx_gear = UFS_HS_G2;
930 if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2)
931 ufs_qcom_cap.hs_rx_gear = UFS_HS_G2;
932 }
933
934 ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap,
935 dev_max_params,
936 dev_req_params);
937 if (ret) {
938 pr_err("%s: failed to determine capabilities\n",
939 __func__);
940 goto out;
941 }
942
943 /* enable the device ref clock before changing to HS mode */
944 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
945 ufshcd_is_hs_mode(dev_req_params))
946 ufs_qcom_dev_ref_clk_ctrl(host, true);
947
948 if (host->hw_ver.major >= 0x4) {
949 if (dev_req_params->gear_tx == UFS_HS_G4) {
950 /* INITIAL ADAPT */
951 ufshcd_dme_set(hba,
952 UIC_ARG_MIB(PA_TXHSADAPTTYPE),
953 PA_INITIAL_ADAPT);
954 } else {
955 /* NO ADAPT */
956 ufshcd_dme_set(hba,
957 UIC_ARG_MIB(PA_TXHSADAPTTYPE),
958 PA_NO_ADAPT);
959 }
960 }
961 break;
962 case POST_CHANGE:
963 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
964 dev_req_params->pwr_rx,
965 dev_req_params->hs_rate, false)) {
966 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
967 __func__);
968 /*
969 * we return error code at the end of the routine,
970 * but continue to configure UFS_PHY_TX_LANE_ENABLE
971 * and bus voting as usual
972 */
973 ret = -EINVAL;
974 }
975
976 /* cache the power mode parameters to use internally */
977 memcpy(&host->dev_req_params,
978 dev_req_params, sizeof(*dev_req_params));
979 ufs_qcom_update_bus_bw_vote(host);
980
981 /* disable the device ref clock if entered PWM mode */
982 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
983 !ufshcd_is_hs_mode(dev_req_params))
984 ufs_qcom_dev_ref_clk_ctrl(host, false);
985 break;
986 default:
987 ret = -EINVAL;
988 break;
989 }
990out:
991 return ret;
992}
993
994static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
995{
996 int err;
997 u32 pa_vs_config_reg1;
998
999 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
1000 &pa_vs_config_reg1);
1001 if (err)
1002 goto out;
1003
1004 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
1005 err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
1006 (pa_vs_config_reg1 | (1 << 12)));
1007
1008out:
1009 return err;
1010}
1011
1012static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
1013{
1014 int err = 0;
1015
1016 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
1017 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
1018
1019 if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC)
1020 hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE;
1021
1022 return err;
1023}
1024
1025static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
1026{
1027 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1028
1029 if (host->hw_ver.major == 0x1)
1030 return UFSHCI_VERSION_11;
1031 else
1032 return UFSHCI_VERSION_20;
1033}
1034
1035/**
1036 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
1037 * @hba: host controller instance
1038 *
1039 * QCOM UFS host controller might have some non standard behaviours (quirks)
1040 * than what is specified by UFSHCI specification. Advertise all such
1041 * quirks to standard UFS host controller driver so standard takes them into
1042 * account.
1043 */
1044static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
1045{
1046 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1047
1048 if (host->hw_ver.major == 0x01) {
1049 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1050 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
1051 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE;
1052
1053 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)
1054 hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR;
1055
1056 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
1057 }
1058
1059 if (host->hw_ver.major == 0x2) {
1060 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
1061
1062 if (!ufs_qcom_cap_qunipro(host))
1063 /* Legacy UniPro mode still need following quirks */
1064 hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1065 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
1066 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP);
1067 }
1068}
1069
1070static void ufs_qcom_set_caps(struct ufs_hba *hba)
1071{
1072 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1073
1074 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1075 hba->caps |= UFSHCD_CAP_CLK_SCALING;
1076 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1077 hba->caps |= UFSHCD_CAP_WB_EN;
1078 hba->caps |= UFSHCD_CAP_CRYPTO;
1079
1080 if (host->hw_ver.major >= 0x2) {
1081 host->caps = UFS_QCOM_CAP_QUNIPRO |
1082 UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE;
1083 }
1084}
1085
1086/**
1087 * ufs_qcom_setup_clocks - enables/disable clocks
1088 * @hba: host controller instance
1089 * @on: If true, enable clocks else disable them.
1090 * @status: PRE_CHANGE or POST_CHANGE notify
1091 *
1092 * Returns 0 on success, non-zero on failure.
1093 */
1094static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
1095 enum ufs_notify_change_status status)
1096{
1097 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1098 int err = 0;
1099
1100 /*
1101 * In case ufs_qcom_init() is not yet done, simply ignore.
1102 * This ufs_qcom_setup_clocks() shall be called from
1103 * ufs_qcom_init() after init is done.
1104 */
1105 if (!host)
1106 return 0;
1107
1108 switch (status) {
1109 case PRE_CHANGE:
1110 if (on) {
1111 err = ufs_qcom_set_bus_vote(hba, true);
1112 } else {
1113 if (!ufs_qcom_is_link_active(hba)) {
1114 /* disable device ref_clk */
1115 ufs_qcom_dev_ref_clk_ctrl(host, false);
1116 }
1117 }
1118 break;
1119 case POST_CHANGE:
1120 if (on) {
1121 /* enable the device ref clock for HS mode*/
1122 if (ufshcd_is_hs_mode(&hba->pwr_info))
1123 ufs_qcom_dev_ref_clk_ctrl(host, true);
1124 } else {
1125 err = ufs_qcom_set_bus_vote(hba, false);
1126 }
1127 break;
1128 }
1129
1130 return err;
1131}
1132
1133static int
1134ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
1135{
1136 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1137
1138 /* Currently this code only knows about a single reset. */
1139 WARN_ON(id);
1140 ufs_qcom_assert_reset(host->hba);
1141 /* provide 1ms delay to let the reset pulse propagate. */
1142 usleep_range(1000, 1100);
1143 return 0;
1144}
1145
1146static int
1147ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
1148{
1149 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1150
1151 /* Currently this code only knows about a single reset. */
1152 WARN_ON(id);
1153 ufs_qcom_deassert_reset(host->hba);
1154
1155 /*
1156 * after reset deassertion, phy will need all ref clocks,
1157 * voltage, current to settle down before starting serdes.
1158 */
1159 usleep_range(1000, 1100);
1160 return 0;
1161}
1162
1163static const struct reset_control_ops ufs_qcom_reset_ops = {
1164 .assert = ufs_qcom_reset_assert,
1165 .deassert = ufs_qcom_reset_deassert,
1166};
1167
1168#define ANDROID_BOOT_DEV_MAX 30
1169static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
1170
1171#ifndef MODULE
1172static int __init get_android_boot_dev(char *str)
1173{
1174 strlcpy(android_boot_dev, str, ANDROID_BOOT_DEV_MAX);
1175 return 1;
1176}
1177__setup("androidboot.bootdevice=", get_android_boot_dev);
1178#endif
1179
1180/**
1181 * ufs_qcom_init - bind phy with controller
1182 * @hba: host controller instance
1183 *
1184 * Binds PHY with controller and powers up PHY enabling clocks
1185 * and regulators.
1186 *
1187 * Returns -EPROBE_DEFER if binding fails, returns negative error
1188 * on phy power up failure and returns zero on success.
1189 */
1190static int ufs_qcom_init(struct ufs_hba *hba)
1191{
1192 int err;
1193 struct device *dev = hba->dev;
1194 struct platform_device *pdev = to_platform_device(dev);
1195 struct ufs_qcom_host *host;
1196 struct resource *res;
1197
1198 if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev)))
1199 return -ENODEV;
1200
1201 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1202 if (!host) {
1203 err = -ENOMEM;
1204 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
1205 goto out;
1206 }
1207
1208 /* Make a two way bind between the qcom host and the hba */
1209 host->hba = hba;
1210 ufshcd_set_variant(hba, host);
1211
1212 /* Setup the reset control of HCI */
1213 host->core_reset = devm_reset_control_get(hba->dev, "rst");
1214 if (IS_ERR(host->core_reset)) {
1215 err = PTR_ERR(host->core_reset);
1216 dev_warn(dev, "Failed to get reset control %d\n", err);
1217 host->core_reset = NULL;
1218 err = 0;
1219 }
1220
1221 /* Fire up the reset controller. Failure here is non-fatal. */
1222 host->rcdev.of_node = dev->of_node;
1223 host->rcdev.ops = &ufs_qcom_reset_ops;
1224 host->rcdev.owner = dev->driver->owner;
1225 host->rcdev.nr_resets = 1;
1226 err = devm_reset_controller_register(dev, &host->rcdev);
1227 if (err) {
1228 dev_warn(dev, "Failed to register reset controller\n");
1229 err = 0;
1230 }
1231
1232 /*
1233 * voting/devoting device ref_clk source is time consuming hence
1234 * skip devoting it during aggressive clock gating. This clock
1235 * will still be gated off during runtime suspend.
1236 */
1237 host->generic_phy = devm_phy_get(dev, "ufsphy");
1238
1239 if (host->generic_phy == ERR_PTR(-EPROBE_DEFER)) {
1240 /*
1241 * UFS driver might be probed before the phy driver does.
1242 * In that case we would like to return EPROBE_DEFER code.
1243 */
1244 err = -EPROBE_DEFER;
1245 dev_warn(dev, "%s: required phy device. hasn't probed yet. err = %d\n",
1246 __func__, err);
1247 goto out_variant_clear;
1248 } else if (IS_ERR(host->generic_phy)) {
1249 if (has_acpi_companion(dev)) {
1250 host->generic_phy = NULL;
1251 } else {
1252 err = PTR_ERR(host->generic_phy);
1253 dev_err(dev, "%s: PHY get failed %d\n", __func__, err);
1254 goto out_variant_clear;
1255 }
1256 }
1257
1258 host->device_reset = devm_gpiod_get_optional(dev, "reset",
1259 GPIOD_OUT_HIGH);
1260 if (IS_ERR(host->device_reset)) {
1261 err = PTR_ERR(host->device_reset);
1262 if (err != -EPROBE_DEFER)
1263 dev_err(dev, "failed to acquire reset gpio: %d\n", err);
1264 goto out_variant_clear;
1265 }
1266
1267 err = ufs_qcom_bus_register(host);
1268 if (err)
1269 goto out_variant_clear;
1270
1271 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1272 &host->hw_ver.minor, &host->hw_ver.step);
1273
1274 /*
1275 * for newer controllers, device reference clock control bit has
1276 * moved inside UFS controller register address space itself.
1277 */
1278 if (host->hw_ver.major >= 0x02) {
1279 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1280 host->dev_ref_clk_en_mask = BIT(26);
1281 } else {
1282 /* "dev_ref_clk_ctrl_mem" is optional resource */
1283 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1284 "dev_ref_clk_ctrl_mem");
1285 if (res) {
1286 host->dev_ref_clk_ctrl_mmio =
1287 devm_ioremap_resource(dev, res);
1288 if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) {
1289 dev_warn(dev,
1290 "%s: could not map dev_ref_clk_ctrl_mmio, err %ld\n",
1291 __func__,
1292 PTR_ERR(host->dev_ref_clk_ctrl_mmio));
1293 host->dev_ref_clk_ctrl_mmio = NULL;
1294 }
1295 host->dev_ref_clk_en_mask = BIT(5);
1296 }
1297 }
1298
1299 err = ufs_qcom_init_lane_clks(host);
1300 if (err)
1301 goto out_variant_clear;
1302
1303 ufs_qcom_set_caps(hba);
1304 ufs_qcom_advertise_quirks(hba);
1305
1306 err = ufs_qcom_ice_init(host);
1307 if (err)
1308 goto out_variant_clear;
1309
1310 ufs_qcom_set_bus_vote(hba, true);
1311 ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1312
1313 if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
1314 ufs_qcom_hosts[hba->dev->id] = host;
1315
1316 host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
1317 ufs_qcom_get_default_testbus_cfg(host);
1318 err = ufs_qcom_testbus_config(host);
1319 if (err) {
1320 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1321 __func__, err);
1322 err = 0;
1323 }
1324
1325 goto out;
1326
1327out_variant_clear:
1328 ufshcd_set_variant(hba, NULL);
1329out:
1330 return err;
1331}
1332
1333static void ufs_qcom_exit(struct ufs_hba *hba)
1334{
1335 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1336
1337 ufs_qcom_disable_lane_clks(host);
1338 phy_power_off(host->generic_phy);
1339 phy_exit(host->generic_phy);
1340}
1341
1342static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
1343 u32 clk_cycles)
1344{
1345 int err;
1346 u32 core_clk_ctrl_reg;
1347
1348 if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
1349 return -EINVAL;
1350
1351 err = ufshcd_dme_get(hba,
1352 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1353 &core_clk_ctrl_reg);
1354 if (err)
1355 goto out;
1356
1357 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
1358 core_clk_ctrl_reg |= clk_cycles;
1359
1360 /* Clear CORE_CLK_DIV_EN */
1361 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1362
1363 err = ufshcd_dme_set(hba,
1364 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1365 core_clk_ctrl_reg);
1366out:
1367 return err;
1368}
1369
1370static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1371{
1372 /* nothing to do as of now */
1373 return 0;
1374}
1375
1376static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1377{
1378 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1379
1380 if (!ufs_qcom_cap_qunipro(host))
1381 return 0;
1382
1383 /* set unipro core clock cycles to 150 and clear clock divider */
1384 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150);
1385}
1386
1387static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1388{
1389 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1390 int err;
1391 u32 core_clk_ctrl_reg;
1392
1393 if (!ufs_qcom_cap_qunipro(host))
1394 return 0;
1395
1396 err = ufshcd_dme_get(hba,
1397 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1398 &core_clk_ctrl_reg);
1399
1400 /* make sure CORE_CLK_DIV_EN is cleared */
1401 if (!err &&
1402 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1403 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1404 err = ufshcd_dme_set(hba,
1405 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1406 core_clk_ctrl_reg);
1407 }
1408
1409 return err;
1410}
1411
1412static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1413{
1414 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1415
1416 if (!ufs_qcom_cap_qunipro(host))
1417 return 0;
1418
1419 /* set unipro core clock cycles to 75 and clear clock divider */
1420 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75);
1421}
1422
1423static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1424 bool scale_up, enum ufs_notify_change_status status)
1425{
1426 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1427 struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
1428 int err = 0;
1429
1430 if (status == PRE_CHANGE) {
1431 if (scale_up)
1432 err = ufs_qcom_clk_scale_up_pre_change(hba);
1433 else
1434 err = ufs_qcom_clk_scale_down_pre_change(hba);
1435 } else {
1436 if (scale_up)
1437 err = ufs_qcom_clk_scale_up_post_change(hba);
1438 else
1439 err = ufs_qcom_clk_scale_down_post_change(hba);
1440
1441 if (err || !dev_req_params)
1442 goto out;
1443
1444 ufs_qcom_cfg_timers(hba,
1445 dev_req_params->gear_rx,
1446 dev_req_params->pwr_rx,
1447 dev_req_params->hs_rate,
1448 false);
1449 ufs_qcom_update_bus_bw_vote(host);
1450 }
1451
1452out:
1453 return err;
1454}
1455
1456static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
1457 void *priv, void (*print_fn)(struct ufs_hba *hba,
1458 int offset, int num_regs, const char *str, void *priv))
1459{
1460 u32 reg;
1461 struct ufs_qcom_host *host;
1462
1463 if (unlikely(!hba)) {
1464 pr_err("%s: hba is NULL\n", __func__);
1465 return;
1466 }
1467 if (unlikely(!print_fn)) {
1468 dev_err(hba->dev, "%s: print_fn is NULL\n", __func__);
1469 return;
1470 }
1471
1472 host = ufshcd_get_variant(hba);
1473 if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))
1474 return;
1475
1476 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1477 print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv);
1478
1479 reg = ufshcd_readl(hba, REG_UFS_CFG1);
1480 reg |= UTP_DBG_RAMS_EN;
1481 ufshcd_writel(hba, reg, REG_UFS_CFG1);
1482
1483 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1484 print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv);
1485
1486 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1487 print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv);
1488
1489 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1490 print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv);
1491
1492 /* clear bit 17 - UTP_DBG_RAMS_EN */
1493 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1494
1495 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1496 print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv);
1497
1498 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1499 print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv);
1500
1501 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1502 print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv);
1503
1504 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1505 print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv);
1506
1507 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1508 print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv);
1509
1510 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1511 print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv);
1512
1513 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1514 print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv);
1515}
1516
1517static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1518{
1519 if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) {
1520 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1521 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1522 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1523 } else {
1524 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1);
1525 ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);
1526 }
1527}
1528
1529static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1530{
1531 /* provide a legal default configuration */
1532 host->testbus.select_major = TSTBUS_UNIPRO;
1533 host->testbus.select_minor = 37;
1534}
1535
1536static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1537{
1538 if (host->testbus.select_major >= TSTBUS_MAX) {
1539 dev_err(host->hba->dev,
1540 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1541 __func__, host->testbus.select_major);
1542 return false;
1543 }
1544
1545 return true;
1546}
1547
1548int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1549{
1550 int reg;
1551 int offset;
1552 u32 mask = TEST_BUS_SUB_SEL_MASK;
1553
1554 if (!host)
1555 return -EINVAL;
1556
1557 if (!ufs_qcom_testbus_cfg_is_ok(host))
1558 return -EPERM;
1559
1560 switch (host->testbus.select_major) {
1561 case TSTBUS_UAWM:
1562 reg = UFS_TEST_BUS_CTRL_0;
1563 offset = 24;
1564 break;
1565 case TSTBUS_UARM:
1566 reg = UFS_TEST_BUS_CTRL_0;
1567 offset = 16;
1568 break;
1569 case TSTBUS_TXUC:
1570 reg = UFS_TEST_BUS_CTRL_0;
1571 offset = 8;
1572 break;
1573 case TSTBUS_RXUC:
1574 reg = UFS_TEST_BUS_CTRL_0;
1575 offset = 0;
1576 break;
1577 case TSTBUS_DFC:
1578 reg = UFS_TEST_BUS_CTRL_1;
1579 offset = 24;
1580 break;
1581 case TSTBUS_TRLUT:
1582 reg = UFS_TEST_BUS_CTRL_1;
1583 offset = 16;
1584 break;
1585 case TSTBUS_TMRLUT:
1586 reg = UFS_TEST_BUS_CTRL_1;
1587 offset = 8;
1588 break;
1589 case TSTBUS_OCSC:
1590 reg = UFS_TEST_BUS_CTRL_1;
1591 offset = 0;
1592 break;
1593 case TSTBUS_WRAPPER:
1594 reg = UFS_TEST_BUS_CTRL_2;
1595 offset = 16;
1596 break;
1597 case TSTBUS_COMBINED:
1598 reg = UFS_TEST_BUS_CTRL_2;
1599 offset = 8;
1600 break;
1601 case TSTBUS_UTP_HCI:
1602 reg = UFS_TEST_BUS_CTRL_2;
1603 offset = 0;
1604 break;
1605 case TSTBUS_UNIPRO:
1606 reg = UFS_UNIPRO_CFG;
1607 offset = 20;
1608 mask = 0xFFF;
1609 break;
1610 /*
1611 * No need for a default case, since
1612 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1613 * is legal
1614 */
1615 }
1616 mask <<= offset;
1617
1618 pm_runtime_get_sync(host->hba->dev);
1619 ufshcd_hold(host->hba, false);
1620 ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1621 (u32)host->testbus.select_major << 19,
1622 REG_UFS_CFG1);
1623 ufshcd_rmwl(host->hba, mask,
1624 (u32)host->testbus.select_minor << offset,
1625 reg);
1626 ufs_qcom_enable_test_bus(host);
1627 /*
1628 * Make sure the test bus configuration is
1629 * committed before returning.
1630 */
1631 mb();
1632 ufshcd_release(host->hba);
1633 pm_runtime_put_sync(host->hba->dev);
1634
1635 return 0;
1636}
1637
1638static void ufs_qcom_testbus_read(struct ufs_hba *hba)
1639{
1640 ufshcd_dump_regs(hba, UFS_TEST_BUS, 4, "UFS_TEST_BUS ");
1641}
1642
1643static void ufs_qcom_print_unipro_testbus(struct ufs_hba *hba)
1644{
1645 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1646 u32 *testbus = NULL;
1647 int i, nminor = 256, testbus_len = nminor * sizeof(u32);
1648
1649 testbus = kmalloc(testbus_len, GFP_KERNEL);
1650 if (!testbus)
1651 return;
1652
1653 host->testbus.select_major = TSTBUS_UNIPRO;
1654 for (i = 0; i < nminor; i++) {
1655 host->testbus.select_minor = i;
1656 ufs_qcom_testbus_config(host);
1657 testbus[i] = ufshcd_readl(hba, UFS_TEST_BUS);
1658 }
1659 print_hex_dump(KERN_ERR, "UNIPRO_TEST_BUS ", DUMP_PREFIX_OFFSET,
1660 16, 4, testbus, testbus_len, false);
1661 kfree(testbus);
1662}
1663
1664static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1665{
1666 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1667 "HCI Vendor Specific Registers ");
1668
1669 /* sleep a bit intermittently as we are dumping too much data */
1670 ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper);
1671 udelay(1000);
1672 ufs_qcom_testbus_read(hba);
1673 udelay(1000);
1674 ufs_qcom_print_unipro_testbus(hba);
1675 udelay(1000);
1676}
1677
1678/**
1679 * ufs_qcom_device_reset() - toggle the (optional) device reset line
1680 * @hba: per-adapter instance
1681 *
1682 * Toggles the (optional) reset line to reset the attached device.
1683 */
1684static void ufs_qcom_device_reset(struct ufs_hba *hba)
1685{
1686 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1687
1688 /* reset gpio is optional */
1689 if (!host->device_reset)
1690 return;
1691
1692 /*
1693 * The UFS device shall detect reset pulses of 1us, sleep for 10us to
1694 * be on the safe side.
1695 */
1696 gpiod_set_value_cansleep(host->device_reset, 1);
1697 usleep_range(10, 15);
1698
1699 gpiod_set_value_cansleep(host->device_reset, 0);
1700 usleep_range(10, 15);
1701}
1702
1703#if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND)
1704static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1705 struct devfreq_dev_profile *p,
1706 void *data)
1707{
1708 static struct devfreq_simple_ondemand_data *d;
1709
1710 if (!data)
1711 return;
1712
1713 d = (struct devfreq_simple_ondemand_data *)data;
1714 p->polling_ms = 60;
1715 d->upthreshold = 70;
1716 d->downdifferential = 5;
1717}
1718#else
1719static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1720 struct devfreq_dev_profile *p,
1721 void *data)
1722{
1723}
1724#endif
1725
1726/*
1727 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1728 *
1729 * The variant operations configure the necessary controller and PHY
1730 * handshake during initialization.
1731 */
1732static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1733 .name = "qcom",
1734 .init = ufs_qcom_init,
1735 .exit = ufs_qcom_exit,
1736 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version,
1737 .clk_scale_notify = ufs_qcom_clk_scale_notify,
1738 .setup_clocks = ufs_qcom_setup_clocks,
1739 .hce_enable_notify = ufs_qcom_hce_enable_notify,
1740 .link_startup_notify = ufs_qcom_link_startup_notify,
1741 .pwr_change_notify = ufs_qcom_pwr_change_notify,
1742 .apply_dev_quirks = ufs_qcom_apply_dev_quirks,
1743 .suspend = ufs_qcom_suspend,
1744 .resume = ufs_qcom_resume,
1745 .dbg_register_dump = ufs_qcom_dump_dbg_regs,
1746 .device_reset = ufs_qcom_device_reset,
1747 .config_scaling_param = ufs_qcom_config_scaling_param,
1748 .program_key = ufs_qcom_ice_program_key,
1749};
1750
1751/**
1752 * ufs_qcom_probe - probe routine of the driver
1753 * @pdev: pointer to Platform device handle
1754 *
1755 * Return zero for success and non-zero for failure
1756 */
1757static int ufs_qcom_probe(struct platform_device *pdev)
1758{
1759 int err;
1760 struct device *dev = &pdev->dev;
1761
1762 /* Perform generic probe */
1763 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1764 if (err)
1765 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1766
1767 return err;
1768}
1769
1770/**
1771 * ufs_qcom_remove - set driver_data of the device to NULL
1772 * @pdev: pointer to platform device handle
1773 *
1774 * Always returns 0
1775 */
1776static int ufs_qcom_remove(struct platform_device *pdev)
1777{
1778 struct ufs_hba *hba = platform_get_drvdata(pdev);
1779
1780 pm_runtime_get_sync(&(pdev)->dev);
1781 ufshcd_remove(hba);
1782 return 0;
1783}
1784
1785static const struct of_device_id ufs_qcom_of_match[] = {
1786 { .compatible = "qcom,ufshc"},
1787 {},
1788};
1789MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1790
1791#ifdef CONFIG_ACPI
1792static const struct acpi_device_id ufs_qcom_acpi_match[] = {
1793 { "QCOM24A5" },
1794 { },
1795};
1796MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match);
1797#endif
1798
1799static const struct dev_pm_ops ufs_qcom_pm_ops = {
1800 .suspend = ufshcd_pltfrm_suspend,
1801 .resume = ufshcd_pltfrm_resume,
1802 .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
1803 .runtime_resume = ufshcd_pltfrm_runtime_resume,
1804 .runtime_idle = ufshcd_pltfrm_runtime_idle,
1805};
1806
1807static struct platform_driver ufs_qcom_pltform = {
1808 .probe = ufs_qcom_probe,
1809 .remove = ufs_qcom_remove,
1810 .shutdown = ufshcd_pltfrm_shutdown,
1811 .driver = {
1812 .name = "ufshcd-qcom",
1813 .pm = &ufs_qcom_pm_ops,
1814 .of_match_table = of_match_ptr(ufs_qcom_of_match),
1815 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match),
1816 },
1817};
1818module_platform_driver(ufs_qcom_pltform);
1819
1820MODULE_LICENSE("GPL v2");