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1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include <linux/vmalloc.h>
31
32#include "../wifi.h"
33#include "../core.h"
34#include "../pci.h"
35#include "reg.h"
36#include "def.h"
37#include "phy.h"
38#include "dm.h"
39#include "hw.h"
40#include "rf.h"
41#include "sw.h"
42#include "trx.h"
43#include "led.h"
44
45static void rtl92c_init_aspm_vars(struct ieee80211_hw *hw)
46{
47 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
48
49 /*close ASPM for AMD defaultly */
50 rtlpci->const_amdpci_aspm = 0;
51
52 /*
53 * ASPM PS mode.
54 * 0 - Disable ASPM,
55 * 1 - Enable ASPM without Clock Req,
56 * 2 - Enable ASPM with Clock Req,
57 * 3 - Alwyas Enable ASPM with Clock Req,
58 * 4 - Always Enable ASPM without Clock Req.
59 * set defult to RTL8192CE:3 RTL8192E:2
60 * */
61 rtlpci->const_pci_aspm = 3;
62
63 /*Setting for PCI-E device */
64 rtlpci->const_devicepci_aspm_setting = 0x03;
65
66 /*Setting for PCI-E bridge */
67 rtlpci->const_hostpci_aspm_setting = 0x02;
68
69 /*
70 * In Hw/Sw Radio Off situation.
71 * 0 - Default,
72 * 1 - From ASPM setting without low Mac Pwr,
73 * 2 - From ASPM setting with low Mac Pwr,
74 * 3 - Bus D3
75 * set default to RTL8192CE:0 RTL8192SE:2
76 */
77 rtlpci->const_hwsw_rfoff_d3 = 0;
78
79 /*
80 * This setting works for those device with
81 * backdoor ASPM setting such as EPHY setting.
82 * 0 - Not support ASPM,
83 * 1 - Support ASPM,
84 * 2 - According to chipset.
85 */
86 rtlpci->const_support_pciaspm = 1;
87}
88
89int rtl92c_init_sw_vars(struct ieee80211_hw *hw)
90{
91 int err;
92 struct rtl_priv *rtlpriv = rtl_priv(hw);
93 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
94 const struct firmware *firmware;
95
96 rtl8192ce_bt_reg_init(hw);
97
98 rtlpriv->dm.dm_initialgain_enable = 1;
99 rtlpriv->dm.dm_flag = 0;
100 rtlpriv->dm.disable_framebursting = 0;
101 rtlpriv->dm.thermalvalue = 0;
102 rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
103
104 /* compatible 5G band 88ce just 2.4G band & smsp */
105 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
106 rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
107 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
108
109 rtlpci->receive_config = (RCR_APPFCS |
110 RCR_AMF |
111 RCR_ADF |
112 RCR_APP_MIC |
113 RCR_APP_ICV |
114 RCR_AICV |
115 RCR_ACRC32 |
116 RCR_AB |
117 RCR_AM |
118 RCR_APM |
119 RCR_APP_PHYST_RXFF | RCR_HTC_LOC_CTRL | 0);
120
121 rtlpci->irq_mask[0] =
122 (u32) (IMR_ROK |
123 IMR_VODOK |
124 IMR_VIDOK |
125 IMR_BEDOK |
126 IMR_BKDOK |
127 IMR_MGNTDOK |
128 IMR_HIGHDOK | IMR_BDOK | IMR_RDU | IMR_RXFOVW | 0);
129
130 rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD | 0);
131
132 /* for LPS & IPS */
133 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
134 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
135 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
136 rtlpriv->psc.reg_fwctrl_lps = 3;
137 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
138 /* for ASPM, you can close aspm through
139 * set const_support_pciaspm = 0 */
140 rtl92c_init_aspm_vars(hw);
141
142 if (rtlpriv->psc.reg_fwctrl_lps == 1)
143 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
144 else if (rtlpriv->psc.reg_fwctrl_lps == 2)
145 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
146 else if (rtlpriv->psc.reg_fwctrl_lps == 3)
147 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
148
149 /* for firmware buf */
150 rtlpriv->rtlhal.pfirmware = vzalloc(0x4000);
151 if (!rtlpriv->rtlhal.pfirmware) {
152 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
153 ("Can't alloc buffer for fw.\n"));
154 return 1;
155 }
156
157 /* request fw */
158 err = request_firmware(&firmware, rtlpriv->cfg->fw_name,
159 rtlpriv->io.dev);
160 if (err) {
161 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
162 ("Failed to request firmware!\n"));
163 return 1;
164 }
165 if (firmware->size > 0x4000) {
166 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
167 ("Firmware is too big!\n"));
168 release_firmware(firmware);
169 return 1;
170 }
171 memcpy(rtlpriv->rtlhal.pfirmware, firmware->data, firmware->size);
172 rtlpriv->rtlhal.fwsize = firmware->size;
173 release_firmware(firmware);
174
175 return 0;
176}
177
178void rtl92c_deinit_sw_vars(struct ieee80211_hw *hw)
179{
180 struct rtl_priv *rtlpriv = rtl_priv(hw);
181
182 if (rtlpriv->rtlhal.pfirmware) {
183 vfree(rtlpriv->rtlhal.pfirmware);
184 rtlpriv->rtlhal.pfirmware = NULL;
185 }
186}
187
188static struct rtl_hal_ops rtl8192ce_hal_ops = {
189 .init_sw_vars = rtl92c_init_sw_vars,
190 .deinit_sw_vars = rtl92c_deinit_sw_vars,
191 .read_eeprom_info = rtl92ce_read_eeprom_info,
192 .interrupt_recognized = rtl92ce_interrupt_recognized,
193 .hw_init = rtl92ce_hw_init,
194 .hw_disable = rtl92ce_card_disable,
195 .hw_suspend = rtl92ce_suspend,
196 .hw_resume = rtl92ce_resume,
197 .enable_interrupt = rtl92ce_enable_interrupt,
198 .disable_interrupt = rtl92ce_disable_interrupt,
199 .set_network_type = rtl92ce_set_network_type,
200 .set_chk_bssid = rtl92ce_set_check_bssid,
201 .set_qos = rtl92ce_set_qos,
202 .set_bcn_reg = rtl92ce_set_beacon_related_registers,
203 .set_bcn_intv = rtl92ce_set_beacon_interval,
204 .update_interrupt_mask = rtl92ce_update_interrupt_mask,
205 .get_hw_reg = rtl92ce_get_hw_reg,
206 .set_hw_reg = rtl92ce_set_hw_reg,
207 .update_rate_tbl = rtl92ce_update_hal_rate_tbl,
208 .fill_tx_desc = rtl92ce_tx_fill_desc,
209 .fill_tx_cmddesc = rtl92ce_tx_fill_cmddesc,
210 .query_rx_desc = rtl92ce_rx_query_desc,
211 .set_channel_access = rtl92ce_update_channel_access_setting,
212 .radio_onoff_checking = rtl92ce_gpio_radio_on_off_checking,
213 .set_bw_mode = rtl92c_phy_set_bw_mode,
214 .switch_channel = rtl92c_phy_sw_chnl,
215 .dm_watchdog = rtl92c_dm_watchdog,
216 .scan_operation_backup = rtl92c_phy_scan_operation_backup,
217 .set_rf_power_state = rtl92c_phy_set_rf_power_state,
218 .led_control = rtl92ce_led_control,
219 .set_desc = rtl92ce_set_desc,
220 .get_desc = rtl92ce_get_desc,
221 .tx_polling = rtl92ce_tx_polling,
222 .enable_hw_sec = rtl92ce_enable_hw_security_config,
223 .set_key = rtl92ce_set_key,
224 .init_sw_leds = rtl92ce_init_sw_leds,
225 .get_bbreg = rtl92c_phy_query_bb_reg,
226 .set_bbreg = rtl92c_phy_set_bb_reg,
227 .set_rfreg = rtl92ce_phy_set_rf_reg,
228 .get_rfreg = rtl92c_phy_query_rf_reg,
229 .phy_rf6052_config = rtl92ce_phy_rf6052_config,
230 .phy_rf6052_set_cck_txpower = rtl92ce_phy_rf6052_set_cck_txpower,
231 .phy_rf6052_set_ofdm_txpower = rtl92ce_phy_rf6052_set_ofdm_txpower,
232 .config_bb_with_headerfile = _rtl92ce_phy_config_bb_with_headerfile,
233 .config_bb_with_pgheaderfile = _rtl92ce_phy_config_bb_with_pgheaderfile,
234 .phy_lc_calibrate = _rtl92ce_phy_lc_calibrate,
235 .phy_set_bw_mode_callback = rtl92ce_phy_set_bw_mode_callback,
236 .dm_dynamic_txpower = rtl92ce_dm_dynamic_txpower,
237};
238
239static struct rtl_mod_params rtl92ce_mod_params = {
240 .sw_crypto = false,
241 .inactiveps = true,
242 .swctrl_lps = false,
243 .fwctrl_lps = true,
244};
245
246static struct rtl_hal_cfg rtl92ce_hal_cfg = {
247 .bar_id = 2,
248 .write_readback = true,
249 .name = "rtl92c_pci",
250 .fw_name = "rtlwifi/rtl8192cfw.bin",
251 .ops = &rtl8192ce_hal_ops,
252 .mod_params = &rtl92ce_mod_params,
253
254 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
255 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
256 .maps[SYS_CLK] = REG_SYS_CLKR,
257 .maps[MAC_RCR_AM] = AM,
258 .maps[MAC_RCR_AB] = AB,
259 .maps[MAC_RCR_ACRC32] = ACRC32,
260 .maps[MAC_RCR_ACF] = ACF,
261 .maps[MAC_RCR_AAP] = AAP,
262
263 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
264 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
265 .maps[EFUSE_CLK] = 0,
266 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
267 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
268 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
269 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
270 .maps[EFUSE_ANA8M] = EFUSE_ANA8M,
271 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
272 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
273 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
274
275 .maps[RWCAM] = REG_CAMCMD,
276 .maps[WCAMI] = REG_CAMWRITE,
277 .maps[RCAMO] = REG_CAMREAD,
278 .maps[CAMDBG] = REG_CAMDBG,
279 .maps[SECR] = REG_SECCFG,
280 .maps[SEC_CAM_NONE] = CAM_NONE,
281 .maps[SEC_CAM_WEP40] = CAM_WEP40,
282 .maps[SEC_CAM_TKIP] = CAM_TKIP,
283 .maps[SEC_CAM_AES] = CAM_AES,
284 .maps[SEC_CAM_WEP104] = CAM_WEP104,
285
286 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
287 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
288 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
289 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
290 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
291 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
292 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
293 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
294 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
295 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
296 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
297 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
298 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
299 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
300 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
301 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
302
303 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
304 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
305 .maps[RTL_IMR_BcnInt] = IMR_BCNINT,
306 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
307 .maps[RTL_IMR_RDU] = IMR_RDU,
308 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
309 .maps[RTL_IMR_BDOK] = IMR_BDOK,
310 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
311 .maps[RTL_IMR_TBDER] = IMR_TBDER,
312 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
313 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
314 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
315 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
316 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
317 .maps[RTL_IMR_VODOK] = IMR_VODOK,
318 .maps[RTL_IMR_ROK] = IMR_ROK,
319 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
320
321 .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
322 .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
323 .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
324 .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
325 .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
326 .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
327 .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
328 .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
329 .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
330 .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
331 .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
332 .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
333
334 .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
335 .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
336};
337
338DEFINE_PCI_DEVICE_TABLE(rtl92ce_pci_ids) = {
339 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8191, rtl92ce_hal_cfg)},
340 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8178, rtl92ce_hal_cfg)},
341 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8177, rtl92ce_hal_cfg)},
342 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8176, rtl92ce_hal_cfg)},
343 {},
344};
345
346MODULE_DEVICE_TABLE(pci, rtl92ce_pci_ids);
347
348MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
349MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
350MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
351MODULE_LICENSE("GPL");
352MODULE_DESCRIPTION("Realtek 8192C/8188C 802.11n PCI wireless");
353MODULE_FIRMWARE("rtlwifi/rtl8192cfw.bin");
354
355module_param_named(swenc, rtl92ce_mod_params.sw_crypto, bool, 0444);
356module_param_named(ips, rtl92ce_mod_params.inactiveps, bool, 0444);
357module_param_named(swlps, rtl92ce_mod_params.swctrl_lps, bool, 0444);
358module_param_named(fwlps, rtl92ce_mod_params.fwctrl_lps, bool, 0444);
359MODULE_PARM_DESC(swenc, "using hardware crypto (default 0 [hardware])\n");
360MODULE_PARM_DESC(ips, "using no link power save (default 1 is open)\n");
361MODULE_PARM_DESC(fwlps, "using linked fw control power save "
362 "(default 1 is open)\n");
363
364static struct pci_driver rtl92ce_driver = {
365 .name = KBUILD_MODNAME,
366 .id_table = rtl92ce_pci_ids,
367 .probe = rtl_pci_probe,
368 .remove = rtl_pci_disconnect,
369
370#ifdef CONFIG_PM
371 .suspend = rtl_pci_suspend,
372 .resume = rtl_pci_resume,
373#endif
374
375};
376
377static int __init rtl92ce_module_init(void)
378{
379 int ret;
380
381 ret = pci_register_driver(&rtl92ce_driver);
382 if (ret)
383 RT_ASSERT(false, (": No device found\n"));
384
385 return ret;
386}
387
388static void __exit rtl92ce_module_exit(void)
389{
390 pci_unregister_driver(&rtl92ce_driver);
391}
392
393module_init(rtl92ce_module_init);
394module_exit(rtl92ce_module_exit);