1/**
  2 * Copyright (c) 2017 Redpine Signals Inc.
  3 *
  4 * Permission to use, copy, modify, and/or distribute this software for any
  5 * purpose with or without fee is hereby granted, provided that the above
  6 * copyright notice and this permission notice appear in all copies.
  7 *
  8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 15 */
 16
 17#ifndef __RSI_HAL_H__
 18#define __RSI_HAL_H__
 19
 20/* Device Operating modes */
 21#define DEV_OPMODE_WIFI_ALONE		1
 22#define DEV_OPMODE_BT_ALONE		4
 23#define DEV_OPMODE_BT_LE_ALONE		8
 24#define DEV_OPMODE_BT_DUAL		12
 25#define DEV_OPMODE_STA_BT		5
 26#define DEV_OPMODE_STA_BT_LE		9
 27#define DEV_OPMODE_STA_BT_DUAL		13
 28#define DEV_OPMODE_AP_BT		6
 29#define DEV_OPMODE_AP_BT_DUAL		14
 30
 31#define FLASH_WRITE_CHUNK_SIZE		(4 * 1024)
 32#define FLASH_SECTOR_SIZE		(4 * 1024)
 33
 34#define FLASH_SIZE_ADDR			0x04000016
 35#define PING_BUFFER_ADDRESS		0x19000
 36#define PONG_BUFFER_ADDRESS		0x1a000
 37#define SWBL_REGIN			0x41050034
 38#define SWBL_REGOUT			0x4105003c
 39#define PING_WRITE			0x1
 40#define PONG_WRITE			0x2
 41
 42#define BL_CMD_TIMEOUT			2000
 43#define BL_BURN_TIMEOUT			(50 * 1000)
 44
 45#define REGIN_VALID			0xA
 46#define REGIN_INPUT			0xA0
 47#define REGOUT_VALID			0xAB
 48#define REGOUT_INVALID			(~0xAB)
 49#define CMD_PASS			0xAA
 50#define CMD_FAIL			0xCC
 51
 52#define LOAD_HOSTED_FW			'A'
 53#define BURN_HOSTED_FW			'B'
 54#define PING_VALID			'I'
 55#define PONG_VALID			'O'
 56#define PING_AVAIL			'I'
 57#define PONG_AVAIL			'O'
 58#define EOF_REACHED			'E'
 59#define CHECK_CRC			'K'
 60#define POLLING_MODE			'P'
 61#define CONFIG_AUTO_READ_MODE		'R'
 62#define JUMP_TO_ZERO_PC			'J'
 63#define FW_LOADING_SUCCESSFUL		'S'
 64#define LOADING_INITIATED		'1'
 65
 66#define RSI_ULP_RESET_REG		0x161
 67#define RSI_WATCH_DOG_TIMER_1		0x16c
 68#define RSI_WATCH_DOG_TIMER_2		0x16d
 69#define RSI_WATCH_DOG_DELAY_TIMER_1		0x16e
 70#define RSI_WATCH_DOG_DELAY_TIMER_2		0x16f
 71#define RSI_WATCH_DOG_TIMER_ENABLE		0x170
 72
 73/* Watchdog timer addresses for 9116 */
 74#define NWP_AHB_BASE_ADDR		0x41300000
 75#define NWP_WWD_INTERRUPT_TIMER		(NWP_AHB_BASE_ADDR + 0x300)
 76#define NWP_WWD_SYSTEM_RESET_TIMER	(NWP_AHB_BASE_ADDR + 0x304)
 77#define NWP_WWD_WINDOW_TIMER		(NWP_AHB_BASE_ADDR + 0x308)
 78#define NWP_WWD_TIMER_SETTINGS		(NWP_AHB_BASE_ADDR + 0x30C)
 79#define NWP_WWD_MODE_AND_RSTART		(NWP_AHB_BASE_ADDR + 0x310)
 80#define NWP_WWD_RESET_BYPASS		(NWP_AHB_BASE_ADDR + 0x314)
 81#define NWP_FSM_INTR_MASK_REG		(NWP_AHB_BASE_ADDR + 0x104)
 82
 83/* Watchdog timer values */
 84#define NWP_WWD_INT_TIMER_CLKS		5
 85#define NWP_WWD_SYS_RESET_TIMER_CLKS	4
 86#define NWP_WWD_TIMER_DISABLE		0xAA0001
 87
 88#define RSI_ULP_WRITE_0			00
 89#define RSI_ULP_WRITE_2			02
 90#define RSI_ULP_WRITE_50		50
 91
 92#define RSI_RESTART_WDT			BIT(11)
 93#define RSI_BYPASS_ULP_ON_WDT		BIT(1)
 94
 95#define RSI_ULP_TIMER_ENABLE		((0xaa000) | RSI_RESTART_WDT |	\
 96					 RSI_BYPASS_ULP_ON_WDT)
 97#define RSI_RF_SPI_PROG_REG_BASE_ADDR	0x40080000
 98
 99#define RSI_GSPI_CTRL_REG0		(RSI_RF_SPI_PROG_REG_BASE_ADDR)
100#define RSI_GSPI_CTRL_REG1		(RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x2)
101#define RSI_GSPI_DATA_REG0		(RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x4)
102#define RSI_GSPI_DATA_REG1		(RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x6)
103#define RSI_GSPI_DATA_REG2		(RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x8)
104
105#define RSI_GSPI_CTRL_REG0_VALUE		0x340
106
107#define RSI_GSPI_DMA_MODE			BIT(13)
108
109#define RSI_GSPI_2_ULP			BIT(12)
110#define RSI_GSPI_TRIG			BIT(7)
111#define RSI_GSPI_READ			BIT(6)
112#define RSI_GSPI_RF_SPI_ACTIVE		BIT(8)
113
114/* Boot loader commands */
115#define SEND_RPS_FILE			'2'
116
117#define FW_IMAGE_MIN_ADDRESS		(68 * 1024)
118#define MAX_FLASH_FILE_SIZE		(400 * 1024) //400K
119#define FLASH_START_ADDRESS		16
120
121#define COMMON_HAL_CARD_READY_IND	0x0
122
123#define COMMAN_HAL_WAIT_FOR_CARD_READY	1
124
125#define RSI_DEV_OPMODE_WIFI_ALONE	1
126#define RSI_DEV_COEX_MODE_WIFI_ALONE	1
127
128#define BBP_INFO_40MHZ 0x6
129
130#define FW_FLASH_OFFSET			0x820
131#define LMAC_VER_OFFSET_9113		(FW_FLASH_OFFSET + 0x200)
132#define LMAC_VER_OFFSET_9116		0x22C2
133#define MAX_DWORD_ALIGN_BYTES		64
134#define RSI_COMMON_REG_SIZE		2
135#define RSI_9116_REG_SIZE		4
136#define FW_ALIGN_SIZE			4
137#define RSI_9116_FW_MAGIC_WORD		0x5aa5
138
139#define MEM_ACCESS_CTRL_FROM_HOST	0x41300000
140#define RAM_384K_ACCESS_FROM_TA		(BIT(2) | BIT(3) | BIT(4) | BIT(5) | \
141					 BIT(20) | BIT(21) | BIT(22) | \
142					 BIT(23) | BIT(24) | BIT(25))
143
144struct bl_header {
145	__le32 flags;
146	__le32 image_no;
147	__le32 check_sum;
148	__le32 flash_start_address;
149	__le32 flash_len;
150} __packed;
151
152struct ta_metadata {
153	char *name;
154	unsigned int address;
155};
156
157#define RSI_BL_CTRL_LEN_MASK			0xFFFFFF
158#define RSI_BL_CTRL_SPI_32BIT_MODE		BIT(27)
159#define RSI_BL_CTRL_REL_TA_SOFTRESET		BIT(28)
160#define RSI_BL_CTRL_START_FROM_ROM_PC		BIT(29)
161#define RSI_BL_CTRL_SPI_8BIT_MODE		BIT(30)
162#define RSI_BL_CTRL_LAST_ENTRY			BIT(31)
163struct bootload_entry {
164	__le32 control;
165	__le32 dst_addr;
166} __packed;
167
168struct bootload_ds {
169	__le16 fixed_pattern;
170	__le16 offset;
171	__le32 reserved;
172	struct bootload_entry bl_entry[7];
173} __packed;
174
175struct rsi_mgmt_desc {
176	__le16 len_qno;
177	u8 frame_type;
178	u8 misc_flags;
179	u8 xtend_desc_size;
180	u8 header_len;
181	__le16 frame_info;
182	__le16 rate_info;
183	__le16 bbp_info;
184	__le16 seq_ctrl;
185	u8 reserved2;
186	u8 sta_id;
187} __packed;
188
189struct rsi_data_desc {
190	__le16 len_qno;
191	u8 cfm_frame_type;
192	u8 misc_flags;
193	u8 xtend_desc_size;
194	u8 header_len;
195	__le16 frame_info;
196	__le16 rate_info;
197	__le16 bbp_info;
198	__le16 mac_flags;
199	u8 qid_tid;
200	u8 sta_id;
201} __packed;
202
203struct rsi_bt_desc {
204	__le16 len_qno;
205	__le16 reserved1;
206	__le32 reserved2;
207	__le32 reserved3;
208	__le16 reserved4;
209	__le16 bt_pkt_type;
210} __packed;
211
212int rsi_hal_device_init(struct rsi_hw *adapter);
213int rsi_prepare_mgmt_desc(struct rsi_common *common, struct sk_buff *skb);
214int rsi_prepare_data_desc(struct rsi_common *common, struct sk_buff *skb);
215int rsi_prepare_beacon(struct rsi_common *common, struct sk_buff *skb);
216int rsi_send_pkt_to_bus(struct rsi_common *common, struct sk_buff *skb);
217int rsi_send_bt_pkt(struct rsi_common *common, struct sk_buff *skb);
218
219#endif