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1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright (C) 2018 - 2020 Intel Corporation
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program.
21 *
22 * The full GNU General Public License is included in this distribution
23 * in the file called COPYING.
24 *
25 * Contact Information:
26 * Intel Linux Wireless <linuxwifi@intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *
29 * BSD LICENSE
30 *
31 * Copyright (C) 2018 - 2020 Intel Corporation
32 * All rights reserved.
33 *
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
36 * are met:
37 *
38 * * Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * * Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in
42 * the documentation and/or other materials provided with the
43 * distribution.
44 * * Neither the name Intel Corporation nor the names of its
45 * contributors may be used to endorse or promote products derived
46 * from this software without specific prior written permission.
47 *
48 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
49 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
50 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
51 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
52 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
53 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
54 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
55 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
56 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
57 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
58 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
59 *
60 *****************************************************************************/
61
62#include <linux/firmware.h>
63#include "iwl-drv.h"
64#include "iwl-trans.h"
65#include "iwl-dbg-tlv.h"
66#include "fw/dbg.h"
67#include "fw/runtime.h"
68
69/**
70 * enum iwl_dbg_tlv_type - debug TLV types
71 * @IWL_DBG_TLV_TYPE_DEBUG_INFO: debug info TLV
72 * @IWL_DBG_TLV_TYPE_BUF_ALLOC: buffer allocation TLV
73 * @IWL_DBG_TLV_TYPE_HCMD: host command TLV
74 * @IWL_DBG_TLV_TYPE_REGION: region TLV
75 * @IWL_DBG_TLV_TYPE_TRIGGER: trigger TLV
76 * @IWL_DBG_TLV_TYPE_NUM: number of debug TLVs
77 */
78enum iwl_dbg_tlv_type {
79 IWL_DBG_TLV_TYPE_DEBUG_INFO =
80 IWL_UCODE_TLV_TYPE_DEBUG_INFO - IWL_UCODE_TLV_DEBUG_BASE,
81 IWL_DBG_TLV_TYPE_BUF_ALLOC,
82 IWL_DBG_TLV_TYPE_HCMD,
83 IWL_DBG_TLV_TYPE_REGION,
84 IWL_DBG_TLV_TYPE_TRIGGER,
85 IWL_DBG_TLV_TYPE_NUM,
86};
87
88/**
89 * struct iwl_dbg_tlv_ver_data - debug TLV version struct
90 * @min_ver: min version supported
91 * @max_ver: max version supported
92 */
93struct iwl_dbg_tlv_ver_data {
94 int min_ver;
95 int max_ver;
96};
97
98/**
99 * struct iwl_dbg_tlv_timer_node - timer node struct
100 * @list: list of &struct iwl_dbg_tlv_timer_node
101 * @timer: timer
102 * @fwrt: &struct iwl_fw_runtime
103 * @tlv: TLV attach to the timer node
104 */
105struct iwl_dbg_tlv_timer_node {
106 struct list_head list;
107 struct timer_list timer;
108 struct iwl_fw_runtime *fwrt;
109 struct iwl_ucode_tlv *tlv;
110};
111
112static const struct iwl_dbg_tlv_ver_data
113dbg_ver_table[IWL_DBG_TLV_TYPE_NUM] = {
114 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = {.min_ver = 1, .max_ver = 1,},
115 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = {.min_ver = 1, .max_ver = 1,},
116 [IWL_DBG_TLV_TYPE_HCMD] = {.min_ver = 1, .max_ver = 1,},
117 [IWL_DBG_TLV_TYPE_REGION] = {.min_ver = 1, .max_ver = 1,},
118 [IWL_DBG_TLV_TYPE_TRIGGER] = {.min_ver = 1, .max_ver = 1,},
119};
120
121static int iwl_dbg_tlv_add(struct iwl_ucode_tlv *tlv, struct list_head *list)
122{
123 u32 len = le32_to_cpu(tlv->length);
124 struct iwl_dbg_tlv_node *node;
125
126 node = kzalloc(sizeof(*node) + len, GFP_KERNEL);
127 if (!node)
128 return -ENOMEM;
129
130 memcpy(&node->tlv, tlv, sizeof(node->tlv) + len);
131 list_add_tail(&node->list, list);
132
133 return 0;
134}
135
136static bool iwl_dbg_tlv_ver_support(struct iwl_ucode_tlv *tlv)
137{
138 struct iwl_fw_ini_header *hdr = (void *)&tlv->data[0];
139 u32 type = le32_to_cpu(tlv->type);
140 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE;
141 u32 ver = le32_to_cpu(hdr->version);
142
143 if (ver < dbg_ver_table[tlv_idx].min_ver ||
144 ver > dbg_ver_table[tlv_idx].max_ver)
145 return false;
146
147 return true;
148}
149
150static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans,
151 struct iwl_ucode_tlv *tlv)
152{
153 struct iwl_fw_ini_debug_info_tlv *debug_info = (void *)tlv->data;
154
155 if (le32_to_cpu(tlv->length) != sizeof(*debug_info))
156 return -EINVAL;
157
158 IWL_DEBUG_FW(trans, "WRT: Loading debug cfg: %s\n",
159 debug_info->debug_cfg_name);
160
161 return iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list);
162}
163
164static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans,
165 struct iwl_ucode_tlv *tlv)
166{
167 struct iwl_fw_ini_allocation_tlv *alloc = (void *)tlv->data;
168 u32 buf_location;
169 u32 alloc_id;
170
171 if (le32_to_cpu(tlv->length) != sizeof(*alloc))
172 return -EINVAL;
173
174 buf_location = le32_to_cpu(alloc->buf_location);
175 alloc_id = le32_to_cpu(alloc->alloc_id);
176
177 if (buf_location == IWL_FW_INI_LOCATION_INVALID ||
178 buf_location >= IWL_FW_INI_LOCATION_NUM)
179 goto err;
180
181 if (alloc_id == IWL_FW_INI_ALLOCATION_INVALID ||
182 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
183 goto err;
184
185 if ((buf_location == IWL_FW_INI_LOCATION_SRAM_PATH ||
186 buf_location == IWL_FW_INI_LOCATION_NPK_PATH) &&
187 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1)
188 goto err;
189
190 trans->dbg.fw_mon_cfg[alloc_id] = *alloc;
191
192 return 0;
193err:
194 IWL_ERR(trans,
195 "WRT: Invalid allocation id %u and/or location id %u for allocation TLV\n",
196 alloc_id, buf_location);
197 return -EINVAL;
198}
199
200static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans,
201 struct iwl_ucode_tlv *tlv)
202{
203 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)tlv->data;
204 u32 tp = le32_to_cpu(hcmd->time_point);
205
206 if (le32_to_cpu(tlv->length) <= sizeof(*hcmd))
207 return -EINVAL;
208
209 /* Host commands can not be sent in early time point since the FW
210 * is not ready
211 */
212 if (tp == IWL_FW_INI_TIME_POINT_INVALID ||
213 tp >= IWL_FW_INI_TIME_POINT_NUM ||
214 tp == IWL_FW_INI_TIME_POINT_EARLY) {
215 IWL_ERR(trans,
216 "WRT: Invalid time point %u for host command TLV\n",
217 tp);
218 return -EINVAL;
219 }
220
221 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list);
222}
223
224static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans,
225 struct iwl_ucode_tlv *tlv)
226{
227 struct iwl_fw_ini_region_tlv *reg = (void *)tlv->data;
228 struct iwl_ucode_tlv **active_reg;
229 u32 id = le32_to_cpu(reg->id);
230 u32 type = le32_to_cpu(reg->type);
231 u32 tlv_len = sizeof(*tlv) + le32_to_cpu(tlv->length);
232
233 if (le32_to_cpu(tlv->length) < sizeof(*reg))
234 return -EINVAL;
235
236 if (id >= IWL_FW_INI_MAX_REGION_ID) {
237 IWL_ERR(trans, "WRT: Invalid region id %u\n", id);
238 return -EINVAL;
239 }
240
241 if (type <= IWL_FW_INI_REGION_INVALID ||
242 type >= IWL_FW_INI_REGION_NUM) {
243 IWL_ERR(trans, "WRT: Invalid region type %u\n", type);
244 return -EINVAL;
245 }
246
247 if (type == IWL_FW_INI_REGION_PCI_IOSF_CONFIG &&
248 !trans->ops->read_config32) {
249 IWL_ERR(trans, "WRT: Unsupported region type %u\n", type);
250 return -EOPNOTSUPP;
251 }
252
253 active_reg = &trans->dbg.active_regions[id];
254 if (*active_reg) {
255 IWL_WARN(trans, "WRT: Overriding region id %u\n", id);
256
257 kfree(*active_reg);
258 }
259
260 *active_reg = kmemdup(tlv, tlv_len, GFP_KERNEL);
261 if (!*active_reg)
262 return -ENOMEM;
263
264 IWL_DEBUG_FW(trans, "WRT: Enabling region id %u type %u\n", id, type);
265
266 return 0;
267}
268
269static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans,
270 struct iwl_ucode_tlv *tlv)
271{
272 struct iwl_fw_ini_trigger_tlv *trig = (void *)tlv->data;
273 u32 tp = le32_to_cpu(trig->time_point);
274 struct iwl_ucode_tlv *dup = NULL;
275 int ret;
276
277 if (le32_to_cpu(tlv->length) < sizeof(*trig))
278 return -EINVAL;
279
280 if (tp <= IWL_FW_INI_TIME_POINT_INVALID ||
281 tp >= IWL_FW_INI_TIME_POINT_NUM) {
282 IWL_ERR(trans,
283 "WRT: Invalid time point %u for trigger TLV\n",
284 tp);
285 return -EINVAL;
286 }
287
288 if (!le32_to_cpu(trig->occurrences)) {
289 dup = kmemdup(tlv, sizeof(*tlv) + le32_to_cpu(tlv->length),
290 GFP_KERNEL);
291 if (!dup)
292 return -ENOMEM;
293 trig = (void *)dup->data;
294 trig->occurrences = cpu_to_le32(-1);
295 tlv = dup;
296 }
297
298 ret = iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list);
299 kfree(dup);
300
301 return ret;
302}
303
304static int (*dbg_tlv_alloc[])(struct iwl_trans *trans,
305 struct iwl_ucode_tlv *tlv) = {
306 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = iwl_dbg_tlv_alloc_debug_info,
307 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = iwl_dbg_tlv_alloc_buf_alloc,
308 [IWL_DBG_TLV_TYPE_HCMD] = iwl_dbg_tlv_alloc_hcmd,
309 [IWL_DBG_TLV_TYPE_REGION] = iwl_dbg_tlv_alloc_region,
310 [IWL_DBG_TLV_TYPE_TRIGGER] = iwl_dbg_tlv_alloc_trigger,
311};
312
313void iwl_dbg_tlv_alloc(struct iwl_trans *trans, struct iwl_ucode_tlv *tlv,
314 bool ext)
315{
316 struct iwl_fw_ini_header *hdr = (void *)&tlv->data[0];
317 u32 type = le32_to_cpu(tlv->type);
318 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE;
319 u32 domain = le32_to_cpu(hdr->domain);
320 enum iwl_ini_cfg_state *cfg_state = ext ?
321 &trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg;
322 int ret;
323
324 if (domain != IWL_FW_INI_DOMAIN_ALWAYS_ON &&
325 !(domain & trans->dbg.domains_bitmap)) {
326 IWL_DEBUG_FW(trans,
327 "WRT: Skipping TLV with disabled domain 0x%0x (0x%0x)\n",
328 domain, trans->dbg.domains_bitmap);
329 return;
330 }
331
332 if (tlv_idx >= ARRAY_SIZE(dbg_tlv_alloc) || !dbg_tlv_alloc[tlv_idx]) {
333 IWL_ERR(trans, "WRT: Unsupported TLV type 0x%x\n", type);
334 goto out_err;
335 }
336
337 if (!iwl_dbg_tlv_ver_support(tlv)) {
338 IWL_ERR(trans, "WRT: Unsupported TLV 0x%x version %u\n", type,
339 le32_to_cpu(hdr->version));
340 goto out_err;
341 }
342
343 ret = dbg_tlv_alloc[tlv_idx](trans, tlv);
344 if (ret) {
345 IWL_ERR(trans,
346 "WRT: Failed to allocate TLV 0x%x, ret %d, (ext=%d)\n",
347 type, ret, ext);
348 goto out_err;
349 }
350
351 if (*cfg_state == IWL_INI_CFG_STATE_NOT_LOADED)
352 *cfg_state = IWL_INI_CFG_STATE_LOADED;
353
354 return;
355
356out_err:
357 *cfg_state = IWL_INI_CFG_STATE_CORRUPTED;
358}
359
360void iwl_dbg_tlv_del_timers(struct iwl_trans *trans)
361{
362 struct list_head *timer_list = &trans->dbg.periodic_trig_list;
363 struct iwl_dbg_tlv_timer_node *node, *tmp;
364
365 list_for_each_entry_safe(node, tmp, timer_list, list) {
366 del_timer(&node->timer);
367 list_del(&node->list);
368 kfree(node);
369 }
370}
371IWL_EXPORT_SYMBOL(iwl_dbg_tlv_del_timers);
372
373static void iwl_dbg_tlv_fragments_free(struct iwl_trans *trans,
374 enum iwl_fw_ini_allocation_id alloc_id)
375{
376 struct iwl_fw_mon *fw_mon;
377 int i;
378
379 if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID ||
380 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
381 return;
382
383 fw_mon = &trans->dbg.fw_mon_ini[alloc_id];
384
385 for (i = 0; i < fw_mon->num_frags; i++) {
386 struct iwl_dram_data *frag = &fw_mon->frags[i];
387
388 dma_free_coherent(trans->dev, frag->size, frag->block,
389 frag->physical);
390
391 frag->physical = 0;
392 frag->block = NULL;
393 frag->size = 0;
394 }
395
396 kfree(fw_mon->frags);
397 fw_mon->frags = NULL;
398 fw_mon->num_frags = 0;
399}
400
401void iwl_dbg_tlv_free(struct iwl_trans *trans)
402{
403 struct iwl_dbg_tlv_node *tlv_node, *tlv_node_tmp;
404 int i;
405
406 iwl_dbg_tlv_del_timers(trans);
407
408 for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) {
409 struct iwl_ucode_tlv **active_reg =
410 &trans->dbg.active_regions[i];
411
412 kfree(*active_reg);
413 *active_reg = NULL;
414 }
415
416 list_for_each_entry_safe(tlv_node, tlv_node_tmp,
417 &trans->dbg.debug_info_tlv_list, list) {
418 list_del(&tlv_node->list);
419 kfree(tlv_node);
420 }
421
422 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) {
423 struct iwl_dbg_tlv_time_point_data *tp =
424 &trans->dbg.time_point[i];
425
426 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->trig_list,
427 list) {
428 list_del(&tlv_node->list);
429 kfree(tlv_node);
430 }
431
432 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->hcmd_list,
433 list) {
434 list_del(&tlv_node->list);
435 kfree(tlv_node);
436 }
437
438 list_for_each_entry_safe(tlv_node, tlv_node_tmp,
439 &tp->active_trig_list, list) {
440 list_del(&tlv_node->list);
441 kfree(tlv_node);
442 }
443 }
444
445 for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++)
446 iwl_dbg_tlv_fragments_free(trans, i);
447}
448
449static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data,
450 size_t len)
451{
452 struct iwl_ucode_tlv *tlv;
453 u32 tlv_len;
454
455 while (len >= sizeof(*tlv)) {
456 len -= sizeof(*tlv);
457 tlv = (void *)data;
458
459 tlv_len = le32_to_cpu(tlv->length);
460
461 if (len < tlv_len) {
462 IWL_ERR(trans, "invalid TLV len: %zd/%u\n",
463 len, tlv_len);
464 return -EINVAL;
465 }
466 len -= ALIGN(tlv_len, 4);
467 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
468
469 iwl_dbg_tlv_alloc(trans, tlv, true);
470 }
471
472 return 0;
473}
474
475void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans)
476{
477 const struct firmware *fw;
478 int res;
479
480 if (!iwlwifi_mod_params.enable_ini)
481 return;
482
483 res = firmware_request_nowarn(&fw, "iwl-debug-yoyo.bin", dev);
484 if (res)
485 return;
486
487 iwl_dbg_tlv_parse_bin(trans, fw->data, fw->size);
488
489 release_firmware(fw);
490}
491
492void iwl_dbg_tlv_init(struct iwl_trans *trans)
493{
494 int i;
495
496 INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list);
497 INIT_LIST_HEAD(&trans->dbg.periodic_trig_list);
498
499 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) {
500 struct iwl_dbg_tlv_time_point_data *tp =
501 &trans->dbg.time_point[i];
502
503 INIT_LIST_HEAD(&tp->trig_list);
504 INIT_LIST_HEAD(&tp->hcmd_list);
505 INIT_LIST_HEAD(&tp->active_trig_list);
506 }
507}
508
509static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt,
510 struct iwl_dram_data *frag, u32 pages)
511{
512 void *block = NULL;
513 dma_addr_t physical;
514
515 if (!frag || frag->size || !pages)
516 return -EIO;
517
518 /*
519 * We try to allocate as many pages as we can, starting with
520 * the requested amount and going down until we can allocate
521 * something. Because of DIV_ROUND_UP(), pages will never go
522 * down to 0 and stop the loop, so stop when pages reaches 1,
523 * which is too small anyway.
524 */
525 while (pages > 1) {
526 block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE,
527 &physical,
528 GFP_KERNEL | __GFP_NOWARN);
529 if (block)
530 break;
531
532 IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n",
533 pages * PAGE_SIZE);
534
535 pages = DIV_ROUND_UP(pages, 2);
536 }
537
538 if (!block)
539 return -ENOMEM;
540
541 frag->physical = physical;
542 frag->block = block;
543 frag->size = pages * PAGE_SIZE;
544
545 return pages;
546}
547
548static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt,
549 enum iwl_fw_ini_allocation_id alloc_id)
550{
551 struct iwl_fw_mon *fw_mon;
552 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg;
553 u32 num_frags, remain_pages, frag_pages;
554 int i;
555
556 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID ||
557 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
558 return -EIO;
559
560 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id];
561 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
562
563 if (fw_mon->num_frags ||
564 fw_mon_cfg->buf_location !=
565 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH))
566 return 0;
567
568 num_frags = le32_to_cpu(fw_mon_cfg->max_frags_num);
569 if (!fw_has_capa(&fwrt->fw->ucode_capa,
570 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) {
571 if (alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1)
572 return -EIO;
573 num_frags = 1;
574 }
575
576 remain_pages = DIV_ROUND_UP(le32_to_cpu(fw_mon_cfg->req_size),
577 PAGE_SIZE);
578 num_frags = min_t(u32, num_frags, BUF_ALLOC_MAX_NUM_FRAGS);
579 num_frags = min_t(u32, num_frags, remain_pages);
580 frag_pages = DIV_ROUND_UP(remain_pages, num_frags);
581
582 fw_mon->frags = kcalloc(num_frags, sizeof(*fw_mon->frags), GFP_KERNEL);
583 if (!fw_mon->frags)
584 return -ENOMEM;
585
586 for (i = 0; i < num_frags; i++) {
587 int pages = min_t(u32, frag_pages, remain_pages);
588
589 IWL_DEBUG_FW(fwrt,
590 "WRT: Allocating DRAM buffer (alloc_id=%u, fragment=%u, size=0x%lx)\n",
591 alloc_id, i, pages * PAGE_SIZE);
592
593 pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i],
594 pages);
595 if (pages < 0) {
596 u32 alloc_size = le32_to_cpu(fw_mon_cfg->req_size) -
597 (remain_pages * PAGE_SIZE);
598
599 if (alloc_size < le32_to_cpu(fw_mon_cfg->min_size)) {
600 iwl_dbg_tlv_fragments_free(fwrt->trans,
601 alloc_id);
602 return pages;
603 }
604 break;
605 }
606
607 remain_pages -= pages;
608 fw_mon->num_frags++;
609 }
610
611 return 0;
612}
613
614static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt,
615 enum iwl_fw_ini_allocation_id alloc_id)
616{
617 struct iwl_fw_mon *fw_mon;
618 u32 remain_frags, num_commands;
619 int i, fw_mon_idx = 0;
620
621 if (!fw_has_capa(&fwrt->fw->ucode_capa,
622 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP))
623 return 0;
624
625 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID ||
626 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
627 return -EIO;
628
629 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
630 IWL_FW_INI_LOCATION_DRAM_PATH)
631 return 0;
632
633 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
634
635 /* the first fragment of DBGC1 is given to the FW via register
636 * or context info
637 */
638 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1)
639 fw_mon_idx++;
640
641 remain_frags = fw_mon->num_frags - fw_mon_idx;
642 if (!remain_frags)
643 return 0;
644
645 num_commands = DIV_ROUND_UP(remain_frags, BUF_ALLOC_MAX_NUM_FRAGS);
646
647 IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n",
648 alloc_id);
649
650 for (i = 0; i < num_commands; i++) {
651 u32 num_frags = min_t(u32, remain_frags,
652 BUF_ALLOC_MAX_NUM_FRAGS);
653 struct iwl_buf_alloc_cmd data = {
654 .alloc_id = cpu_to_le32(alloc_id),
655 .num_frags = cpu_to_le32(num_frags),
656 .buf_location =
657 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH),
658 };
659 struct iwl_host_cmd hcmd = {
660 .id = WIDE_ID(DEBUG_GROUP, BUFFER_ALLOCATION),
661 .data[0] = &data,
662 .len[0] = sizeof(data),
663 };
664 int ret, j;
665
666 for (j = 0; j < num_frags; j++) {
667 struct iwl_buf_alloc_frag *frag = &data.frags[j];
668 struct iwl_dram_data *fw_mon_frag =
669 &fw_mon->frags[fw_mon_idx++];
670
671 frag->addr = cpu_to_le64(fw_mon_frag->physical);
672 frag->size = cpu_to_le32(fw_mon_frag->size);
673 }
674 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
675 if (ret)
676 return ret;
677
678 remain_frags -= num_frags;
679 }
680
681 return 0;
682}
683
684static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt)
685{
686 int ret, i;
687
688 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) {
689 ret = iwl_dbg_tlv_apply_buffer(fwrt, i);
690 if (ret)
691 IWL_WARN(fwrt,
692 "WRT: Failed to apply DRAM buffer for allocation id %d, ret=%d\n",
693 i, ret);
694 }
695}
696
697static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt,
698 struct list_head *hcmd_list)
699{
700 struct iwl_dbg_tlv_node *node;
701
702 list_for_each_entry(node, hcmd_list, list) {
703 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)node->tlv.data;
704 struct iwl_fw_ini_hcmd *hcmd_data = &hcmd->hcmd;
705 u16 hcmd_len = le32_to_cpu(node->tlv.length) - sizeof(*hcmd);
706 struct iwl_host_cmd cmd = {
707 .id = WIDE_ID(hcmd_data->group, hcmd_data->id),
708 .len = { hcmd_len, },
709 .data = { hcmd_data->data, },
710 };
711
712 iwl_trans_send_cmd(fwrt->trans, &cmd);
713 }
714}
715
716static void iwl_dbg_tlv_periodic_trig_handler(struct timer_list *t)
717{
718 struct iwl_dbg_tlv_timer_node *timer_node =
719 from_timer(timer_node, t, timer);
720 struct iwl_fwrt_dump_data dump_data = {
721 .trig = (void *)timer_node->tlv->data,
722 };
723 int ret;
724
725 ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data);
726 if (!ret || ret == -EBUSY) {
727 u32 occur = le32_to_cpu(dump_data.trig->occurrences);
728 u32 collect_interval = le32_to_cpu(dump_data.trig->data[0]);
729
730 if (!occur)
731 return;
732
733 mod_timer(t, jiffies + msecs_to_jiffies(collect_interval));
734 }
735}
736
737static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt)
738{
739 struct iwl_dbg_tlv_node *node;
740 struct list_head *trig_list =
741 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list;
742
743 list_for_each_entry(node, trig_list, list) {
744 struct iwl_fw_ini_trigger_tlv *trig = (void *)node->tlv.data;
745 struct iwl_dbg_tlv_timer_node *timer_node;
746 u32 occur = le32_to_cpu(trig->occurrences), collect_interval;
747 u32 min_interval = 100;
748
749 if (!occur)
750 continue;
751
752 /* make sure there is at least one dword of data for the
753 * interval value
754 */
755 if (le32_to_cpu(node->tlv.length) <
756 sizeof(*trig) + sizeof(__le32)) {
757 IWL_ERR(fwrt,
758 "WRT: Invalid periodic trigger data was not given\n");
759 continue;
760 }
761
762 if (le32_to_cpu(trig->data[0]) < min_interval) {
763 IWL_WARN(fwrt,
764 "WRT: Override min interval from %u to %u msec\n",
765 le32_to_cpu(trig->data[0]), min_interval);
766 trig->data[0] = cpu_to_le32(min_interval);
767 }
768
769 collect_interval = le32_to_cpu(trig->data[0]);
770
771 timer_node = kzalloc(sizeof(*timer_node), GFP_KERNEL);
772 if (!timer_node) {
773 IWL_ERR(fwrt,
774 "WRT: Failed to allocate periodic trigger\n");
775 continue;
776 }
777
778 timer_node->fwrt = fwrt;
779 timer_node->tlv = &node->tlv;
780 timer_setup(&timer_node->timer,
781 iwl_dbg_tlv_periodic_trig_handler, 0);
782
783 list_add_tail(&timer_node->list,
784 &fwrt->trans->dbg.periodic_trig_list);
785
786 IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n");
787
788 mod_timer(&timer_node->timer,
789 jiffies + msecs_to_jiffies(collect_interval));
790 }
791}
792
793static bool is_trig_data_contained(struct iwl_ucode_tlv *new,
794 struct iwl_ucode_tlv *old)
795{
796 struct iwl_fw_ini_trigger_tlv *new_trig = (void *)new->data;
797 struct iwl_fw_ini_trigger_tlv *old_trig = (void *)old->data;
798 __le32 *new_data = new_trig->data, *old_data = old_trig->data;
799 u32 new_dwords_num = iwl_tlv_array_len(new, new_trig, data);
800 u32 old_dwords_num = iwl_tlv_array_len(new, new_trig, data);
801 int i, j;
802
803 for (i = 0; i < new_dwords_num; i++) {
804 bool match = false;
805
806 for (j = 0; j < old_dwords_num; j++) {
807 if (new_data[i] == old_data[j]) {
808 match = true;
809 break;
810 }
811 }
812 if (!match)
813 return false;
814 }
815
816 return true;
817}
818
819static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt,
820 struct iwl_ucode_tlv *trig_tlv,
821 struct iwl_dbg_tlv_node *node)
822{
823 struct iwl_ucode_tlv *node_tlv = &node->tlv;
824 struct iwl_fw_ini_trigger_tlv *node_trig = (void *)node_tlv->data;
825 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data;
826 u32 policy = le32_to_cpu(trig->apply_policy);
827 u32 size = le32_to_cpu(trig_tlv->length);
828 u32 trig_data_len = size - sizeof(*trig);
829 u32 offset = 0;
830
831 if (!(policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_DATA)) {
832 u32 data_len = le32_to_cpu(node_tlv->length) -
833 sizeof(*node_trig);
834
835 IWL_DEBUG_FW(fwrt,
836 "WRT: Appending trigger data (time point %u)\n",
837 le32_to_cpu(trig->time_point));
838
839 offset += data_len;
840 size += data_len;
841 } else {
842 IWL_DEBUG_FW(fwrt,
843 "WRT: Overriding trigger data (time point %u)\n",
844 le32_to_cpu(trig->time_point));
845 }
846
847 if (size != le32_to_cpu(node_tlv->length)) {
848 struct list_head *prev = node->list.prev;
849 struct iwl_dbg_tlv_node *tmp;
850
851 list_del(&node->list);
852
853 tmp = krealloc(node, sizeof(*node) + size, GFP_KERNEL);
854 if (!tmp) {
855 IWL_WARN(fwrt,
856 "WRT: No memory to override trigger (time point %u)\n",
857 le32_to_cpu(trig->time_point));
858
859 list_add(&node->list, prev);
860
861 return -ENOMEM;
862 }
863
864 list_add(&tmp->list, prev);
865 node_tlv = &tmp->tlv;
866 node_trig = (void *)node_tlv->data;
867 }
868
869 memcpy(node_trig->data + offset, trig->data, trig_data_len);
870 node_tlv->length = cpu_to_le32(size);
871
872 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_CFG) {
873 IWL_DEBUG_FW(fwrt,
874 "WRT: Overriding trigger configuration (time point %u)\n",
875 le32_to_cpu(trig->time_point));
876
877 /* the first 11 dwords are configuration related */
878 memcpy(node_trig, trig, sizeof(__le32) * 11);
879 }
880
881 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_REGIONS) {
882 IWL_DEBUG_FW(fwrt,
883 "WRT: Overriding trigger regions (time point %u)\n",
884 le32_to_cpu(trig->time_point));
885
886 node_trig->regions_mask = trig->regions_mask;
887 } else {
888 IWL_DEBUG_FW(fwrt,
889 "WRT: Appending trigger regions (time point %u)\n",
890 le32_to_cpu(trig->time_point));
891
892 node_trig->regions_mask |= trig->regions_mask;
893 }
894
895 return 0;
896}
897
898static int
899iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt,
900 struct list_head *trig_list,
901 struct iwl_ucode_tlv *trig_tlv)
902{
903 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data;
904 struct iwl_dbg_tlv_node *node, *match = NULL;
905 u32 policy = le32_to_cpu(trig->apply_policy);
906
907 list_for_each_entry(node, trig_list, list) {
908 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_TIME_POINT))
909 break;
910
911 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_DATA) ||
912 is_trig_data_contained(trig_tlv, &node->tlv)) {
913 match = node;
914 break;
915 }
916 }
917
918 if (!match) {
919 IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n",
920 le32_to_cpu(trig->time_point));
921 return iwl_dbg_tlv_add(trig_tlv, trig_list);
922 }
923
924 return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match);
925}
926
927static void
928iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt,
929 struct iwl_dbg_tlv_time_point_data *tp)
930{
931 struct iwl_dbg_tlv_node *node;
932 struct list_head *trig_list = &tp->trig_list;
933 struct list_head *active_trig_list = &tp->active_trig_list;
934
935 list_for_each_entry(node, trig_list, list) {
936 struct iwl_ucode_tlv *tlv = &node->tlv;
937
938 iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv);
939 }
940}
941
942static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt,
943 struct iwl_fwrt_dump_data *dump_data,
944 union iwl_dbg_tlv_tp_data *tp_data,
945 u32 trig_data)
946{
947 struct iwl_rx_packet *pkt = tp_data->fw_pkt;
948 struct iwl_cmd_header *wanted_hdr = (void *)&trig_data;
949
950 if (pkt && ((wanted_hdr->cmd == 0 && wanted_hdr->group_id == 0) ||
951 (pkt->hdr.cmd == wanted_hdr->cmd &&
952 pkt->hdr.group_id == wanted_hdr->group_id))) {
953 struct iwl_rx_packet *fw_pkt =
954 kmemdup(pkt,
955 sizeof(*pkt) + iwl_rx_packet_payload_len(pkt),
956 GFP_ATOMIC);
957
958 if (!fw_pkt)
959 return false;
960
961 dump_data->fw_pkt = fw_pkt;
962
963 return true;
964 }
965
966 return false;
967}
968
969static int
970iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt,
971 struct list_head *active_trig_list,
972 union iwl_dbg_tlv_tp_data *tp_data,
973 bool (*data_check)(struct iwl_fw_runtime *fwrt,
974 struct iwl_fwrt_dump_data *dump_data,
975 union iwl_dbg_tlv_tp_data *tp_data,
976 u32 trig_data))
977{
978 struct iwl_dbg_tlv_node *node;
979
980 list_for_each_entry(node, active_trig_list, list) {
981 struct iwl_fwrt_dump_data dump_data = {
982 .trig = (void *)node->tlv.data,
983 };
984 u32 num_data = iwl_tlv_array_len(&node->tlv, dump_data.trig,
985 data);
986 int ret, i;
987
988 if (!num_data) {
989 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data);
990 if (ret)
991 return ret;
992 }
993
994 for (i = 0; i < num_data; i++) {
995 if (!data_check ||
996 data_check(fwrt, &dump_data, tp_data,
997 le32_to_cpu(dump_data.trig->data[i]))) {
998 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data);
999 if (ret)
1000 return ret;
1001
1002 break;
1003 }
1004 }
1005 }
1006
1007 return 0;
1008}
1009
1010static void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt)
1011{
1012 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest;
1013 int ret, i;
1014
1015 IWL_DEBUG_FW(fwrt,
1016 "WRT: Generating active triggers list, domain 0x%x\n",
1017 fwrt->trans->dbg.domains_bitmap);
1018
1019 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) {
1020 struct iwl_dbg_tlv_time_point_data *tp =
1021 &fwrt->trans->dbg.time_point[i];
1022
1023 iwl_dbg_tlv_gen_active_trig_list(fwrt, tp);
1024 }
1025
1026 *ini_dest = IWL_FW_INI_LOCATION_INVALID;
1027 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) {
1028 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
1029 &fwrt->trans->dbg.fw_mon_cfg[i];
1030 u32 dest = le32_to_cpu(fw_mon_cfg->buf_location);
1031
1032 if (dest == IWL_FW_INI_LOCATION_INVALID)
1033 continue;
1034
1035 if (*ini_dest == IWL_FW_INI_LOCATION_INVALID)
1036 *ini_dest = dest;
1037
1038 if (dest != *ini_dest)
1039 continue;
1040
1041 ret = iwl_dbg_tlv_alloc_fragments(fwrt, i);
1042 if (ret)
1043 IWL_WARN(fwrt,
1044 "WRT: Failed to allocate DRAM buffer for allocation id %d, ret=%d\n",
1045 i, ret);
1046 }
1047}
1048
1049void iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt,
1050 enum iwl_fw_ini_time_point tp_id,
1051 union iwl_dbg_tlv_tp_data *tp_data)
1052{
1053 struct list_head *hcmd_list, *trig_list;
1054
1055 if (!iwl_trans_dbg_ini_valid(fwrt->trans) ||
1056 tp_id == IWL_FW_INI_TIME_POINT_INVALID ||
1057 tp_id >= IWL_FW_INI_TIME_POINT_NUM)
1058 return;
1059
1060 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list;
1061 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list;
1062
1063 switch (tp_id) {
1064 case IWL_FW_INI_TIME_POINT_EARLY:
1065 iwl_dbg_tlv_init_cfg(fwrt);
1066 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL);
1067 break;
1068 case IWL_FW_INI_TIME_POINT_AFTER_ALIVE:
1069 iwl_dbg_tlv_apply_buffers(fwrt);
1070 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1071 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL);
1072 break;
1073 case IWL_FW_INI_TIME_POINT_PERIODIC:
1074 iwl_dbg_tlv_set_periodic_trigs(fwrt);
1075 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1076 break;
1077 case IWL_FW_INI_TIME_POINT_FW_RSP_OR_NOTIF:
1078 case IWL_FW_INI_TIME_POINT_MISSED_BEACONS:
1079 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1080 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data,
1081 iwl_dbg_tlv_check_fw_pkt);
1082 break;
1083 default:
1084 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1085 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL);
1086 break;
1087 }
1088}
1089IWL_EXPORT_SYMBOL(iwl_dbg_tlv_time_point);