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1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/*
3 * Driver for Microsemi VSC85xx PHYs
4 *
5 * Copyright (c) 2016 Microsemi Corporation
6 */
7
8#ifndef _MSCC_PHY_H_
9#define _MSCC_PHY_H_
10
11#if IS_ENABLED(CONFIG_MACSEC)
12#include "mscc_macsec.h"
13#endif
14
15enum rgmii_clock_delay {
16 RGMII_CLK_DELAY_0_2_NS = 0,
17 RGMII_CLK_DELAY_0_8_NS = 1,
18 RGMII_CLK_DELAY_1_1_NS = 2,
19 RGMII_CLK_DELAY_1_7_NS = 3,
20 RGMII_CLK_DELAY_2_0_NS = 4,
21 RGMII_CLK_DELAY_2_3_NS = 5,
22 RGMII_CLK_DELAY_2_6_NS = 6,
23 RGMII_CLK_DELAY_3_4_NS = 7
24};
25
26/* Microsemi VSC85xx PHY registers */
27/* IEEE 802. Std Registers */
28#define MSCC_PHY_BYPASS_CONTROL 18
29#define DISABLE_HP_AUTO_MDIX_MASK 0x0080
30#define DISABLE_PAIR_SWAP_CORR_MASK 0x0020
31#define DISABLE_POLARITY_CORR_MASK 0x0010
32#define PARALLEL_DET_IGNORE_ADVERTISED 0x0008
33
34#define MSCC_PHY_EXT_CNTL_STATUS 22
35#define SMI_BROADCAST_WR_EN 0x0001
36
37#define MSCC_PHY_ERR_RX_CNT 19
38#define MSCC_PHY_ERR_FALSE_CARRIER_CNT 20
39#define MSCC_PHY_ERR_LINK_DISCONNECT_CNT 21
40#define ERR_CNT_MASK GENMASK(7, 0)
41
42#define MSCC_PHY_EXT_PHY_CNTL_1 23
43#define MAC_IF_SELECTION_MASK 0x1800
44#define MAC_IF_SELECTION_GMII 0
45#define MAC_IF_SELECTION_RMII 1
46#define MAC_IF_SELECTION_RGMII 2
47#define MAC_IF_SELECTION_POS 11
48#define VSC8584_MAC_IF_SELECTION_MASK 0x1000
49#define VSC8584_MAC_IF_SELECTION_SGMII 0
50#define VSC8584_MAC_IF_SELECTION_1000BASEX 1
51#define VSC8584_MAC_IF_SELECTION_POS 12
52#define FAR_END_LOOPBACK_MODE_MASK 0x0008
53#define MEDIA_OP_MODE_MASK 0x0700
54#define MEDIA_OP_MODE_COPPER 0
55#define MEDIA_OP_MODE_SERDES 1
56#define MEDIA_OP_MODE_1000BASEX 2
57#define MEDIA_OP_MODE_100BASEFX 3
58#define MEDIA_OP_MODE_AMS_COPPER_SERDES 5
59#define MEDIA_OP_MODE_AMS_COPPER_1000BASEX 6
60#define MEDIA_OP_MODE_AMS_COPPER_100BASEFX 7
61#define MEDIA_OP_MODE_POS 8
62
63#define MSCC_PHY_EXT_PHY_CNTL_2 24
64
65#define MII_VSC85XX_INT_MASK 25
66#define MII_VSC85XX_INT_MASK_MDINT BIT(15)
67#define MII_VSC85XX_INT_MASK_LINK_CHG BIT(13)
68#define MII_VSC85XX_INT_MASK_WOL BIT(6)
69#define MII_VSC85XX_INT_MASK_EXT BIT(5)
70#define MII_VSC85XX_INT_STATUS 26
71
72#define MII_VSC85XX_INT_MASK_MASK (MII_VSC85XX_INT_MASK_MDINT | \
73 MII_VSC85XX_INT_MASK_LINK_CHG | \
74 MII_VSC85XX_INT_MASK_EXT)
75
76#define MSCC_PHY_WOL_MAC_CONTROL 27
77#define EDGE_RATE_CNTL_POS 5
78#define EDGE_RATE_CNTL_MASK 0x00E0
79
80#define MSCC_PHY_DEV_AUX_CNTL 28
81#define HP_AUTO_MDIX_X_OVER_IND_MASK 0x2000
82
83#define MSCC_PHY_LED_MODE_SEL 29
84#define LED_MODE_SEL_POS(x) ((x) * 4)
85#define LED_MODE_SEL_MASK(x) (GENMASK(3, 0) << LED_MODE_SEL_POS(x))
86#define LED_MODE_SEL(x, mode) (((mode) << LED_MODE_SEL_POS(x)) & LED_MODE_SEL_MASK(x))
87
88#define MSCC_EXT_PAGE_CSR_CNTL_17 17
89#define MSCC_EXT_PAGE_CSR_CNTL_18 18
90
91#define MSCC_EXT_PAGE_CSR_CNTL_19 19
92#define MSCC_PHY_CSR_CNTL_19_REG_ADDR(x) (x)
93#define MSCC_PHY_CSR_CNTL_19_TARGET(x) ((x) << 12)
94#define MSCC_PHY_CSR_CNTL_19_READ BIT(14)
95#define MSCC_PHY_CSR_CNTL_19_CMD BIT(15)
96
97#define MSCC_EXT_PAGE_CSR_CNTL_20 20
98#define MSCC_PHY_CSR_CNTL_20_TARGET(x) (x)
99
100#define PHY_MCB_TARGET 0x07
101#define PHY_MCB_S6G_WRITE BIT(31)
102#define PHY_MCB_S6G_READ BIT(30)
103
104#define PHY_S6G_PLL5G_CFG0 0x06
105#define PHY_S6G_LCPLL_CFG 0x11
106#define PHY_S6G_PLL_CFG 0x2b
107#define PHY_S6G_COMMON_CFG 0x2c
108#define PHY_S6G_GPC_CFG 0x2e
109#define PHY_S6G_MISC_CFG 0x3b
110#define PHY_MCB_S6G_CFG 0x3f
111#define PHY_S6G_DFT_CFG2 0x3e
112#define PHY_S6G_PLL_STATUS 0x31
113#define PHY_S6G_IB_STATUS0 0x2f
114
115#define PHY_S6G_SYS_RST_POS 31
116#define PHY_S6G_ENA_LANE_POS 18
117#define PHY_S6G_ENA_LOOP_POS 8
118#define PHY_S6G_QRATE_POS 6
119#define PHY_S6G_IF_MODE_POS 4
120#define PHY_S6G_PLL_ENA_OFFS_POS 21
121#define PHY_S6G_PLL_FSM_CTRL_DATA_POS 8
122#define PHY_S6G_PLL_FSM_ENA_POS 7
123
124#define MSCC_EXT_PAGE_ACCESS 31
125#define MSCC_PHY_PAGE_STANDARD 0x0000 /* Standard registers */
126#define MSCC_PHY_PAGE_EXTENDED 0x0001 /* Extended registers */
127#define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */
128#define MSCC_PHY_PAGE_EXTENDED_3 0x0003 /* Extended reg - page 3 */
129#define MSCC_PHY_PAGE_EXTENDED_4 0x0004 /* Extended reg - page 4 */
130#define MSCC_PHY_PAGE_CSR_CNTL MSCC_PHY_PAGE_EXTENDED_4
131#define MSCC_PHY_PAGE_MACSEC MSCC_PHY_PAGE_EXTENDED_4
132/* Extended reg - GPIO; this is a bank of registers that are shared for all PHYs
133 * in the same package.
134 */
135#define MSCC_PHY_PAGE_EXTENDED_GPIO 0x0010 /* Extended reg - GPIO */
136#define MSCC_PHY_PAGE_1588 0x1588 /* PTP (1588) */
137#define MSCC_PHY_PAGE_TEST 0x2a30 /* Test reg */
138#define MSCC_PHY_PAGE_TR 0x52b5 /* Token ring registers */
139
140/* Extended Page 1 Registers */
141#define MSCC_PHY_CU_MEDIA_CRC_VALID_CNT 18
142#define VALID_CRC_CNT_CRC_MASK GENMASK(13, 0)
143
144#define MSCC_PHY_EXT_MODE_CNTL 19
145#define FORCE_MDI_CROSSOVER_MASK 0x000C
146#define FORCE_MDI_CROSSOVER_MDIX 0x000C
147#define FORCE_MDI_CROSSOVER_MDI 0x0008
148
149#define MSCC_PHY_ACTIPHY_CNTL 20
150#define PHY_ADDR_REVERSED 0x0200
151#define DOWNSHIFT_CNTL_MASK 0x001C
152#define DOWNSHIFT_EN 0x0010
153#define DOWNSHIFT_CNTL_POS 2
154
155#define MSCC_PHY_EXT_PHY_CNTL_4 23
156#define PHY_CNTL_4_ADDR_POS 11
157
158#define MSCC_PHY_VERIPHY_CNTL_2 25
159
160#define MSCC_PHY_VERIPHY_CNTL_3 26
161
162/* Extended Page 2 Registers */
163#define MSCC_PHY_CU_PMD_TX_CNTL 16
164
165/* RGMII setting controls at address 18E2, for VSC8572 and similar */
166#define VSC8572_RGMII_CNTL 18
167#define VSC8572_RGMII_RX_DELAY_MASK 0x000E
168#define VSC8572_RGMII_TX_DELAY_MASK 0x0070
169
170/* RGMII controls at address 20E2, for VSC8502 and similar */
171#define VSC8502_RGMII_CNTL 20
172#define VSC8502_RGMII_RX_DELAY_MASK 0x0070
173#define VSC8502_RGMII_TX_DELAY_MASK 0x0007
174
175#define MSCC_PHY_WOL_LOWER_MAC_ADDR 21
176#define MSCC_PHY_WOL_MID_MAC_ADDR 22
177#define MSCC_PHY_WOL_UPPER_MAC_ADDR 23
178#define MSCC_PHY_WOL_LOWER_PASSWD 24
179#define MSCC_PHY_WOL_MID_PASSWD 25
180#define MSCC_PHY_WOL_UPPER_PASSWD 26
181
182#define MSCC_PHY_WOL_MAC_CONTROL 27
183#define SECURE_ON_ENABLE 0x8000
184#define SECURE_ON_PASSWD_LEN_4 0x4000
185
186#define MSCC_PHY_EXTENDED_INT 28
187#define MSCC_PHY_EXTENDED_INT_MS_EGR BIT(9)
188
189/* Extended Page 3 Registers */
190#define MSCC_PHY_SERDES_TX_VALID_CNT 21
191#define MSCC_PHY_SERDES_TX_CRC_ERR_CNT 22
192#define MSCC_PHY_SERDES_RX_VALID_CNT 28
193#define MSCC_PHY_SERDES_RX_CRC_ERR_CNT 29
194
195/* Extended page GPIO Registers */
196#define MSCC_DW8051_CNTL_STATUS 0
197#define MICRO_NSOFT_RESET 0x8000
198#define RUN_FROM_INT_ROM 0x4000
199#define AUTOINC_ADDR 0x2000
200#define PATCH_RAM_CLK 0x1000
201#define MICRO_PATCH_EN 0x0080
202#define DW8051_CLK_EN 0x0010
203#define MICRO_CLK_EN 0x0008
204#define MICRO_CLK_DIVIDE(x) ((x) >> 1)
205#define MSCC_DW8051_VLD_MASK 0xf1ff
206
207/* x Address in range 1-4 */
208#define MSCC_TRAP_ROM_ADDR(x) ((x) * 2 + 1)
209#define MSCC_PATCH_RAM_ADDR(x) (((x) + 1) * 2)
210#define MSCC_INT_MEM_ADDR 11
211
212#define MSCC_INT_MEM_CNTL 12
213#define READ_SFR 0x6000
214#define READ_PRAM 0x4000
215#define READ_ROM 0x2000
216#define READ_RAM 0x0000
217#define INT_MEM_WRITE_EN 0x1000
218#define EN_PATCH_RAM_TRAP_ADDR(x) (0x0100 << ((x) - 1))
219#define INT_MEM_DATA_M 0x00ff
220#define INT_MEM_DATA(x) (INT_MEM_DATA_M & (x))
221
222#define MSCC_PHY_PROC_CMD 18
223#define PROC_CMD_NCOMPLETED 0x8000
224#define PROC_CMD_FAILED 0x4000
225#define PROC_CMD_SGMII_PORT(x) ((x) << 8)
226#define PROC_CMD_FIBER_PORT(x) (0x0100 << (x) % 4)
227#define PROC_CMD_QSGMII_PORT 0x0c00
228#define PROC_CMD_RST_CONF_PORT 0x0080
229#define PROC_CMD_RECONF_PORT 0x0000
230#define PROC_CMD_READ_MOD_WRITE_PORT 0x0040
231#define PROC_CMD_WRITE 0x0040
232#define PROC_CMD_READ 0x0000
233#define PROC_CMD_FIBER_DISABLE 0x0020
234#define PROC_CMD_FIBER_100BASE_FX 0x0010
235#define PROC_CMD_FIBER_1000BASE_X 0x0000
236#define PROC_CMD_SGMII_MAC 0x0030
237#define PROC_CMD_QSGMII_MAC 0x0020
238#define PROC_CMD_NO_MAC_CONF 0x0000
239#define PROC_CMD_1588_DEFAULT_INIT 0x0010
240#define PROC_CMD_NOP 0x000f
241#define PROC_CMD_PHY_INIT 0x000a
242#define PROC_CMD_CRC16 0x0008
243#define PROC_CMD_FIBER_MEDIA_CONF 0x0001
244#define PROC_CMD_MCB_ACCESS_MAC_CONF 0x0000
245#define PROC_CMD_NCOMPLETED_TIMEOUT_MS 500
246
247#define MSCC_PHY_MAC_CFG_FASTLINK 19
248#define MAC_CFG_MASK 0xc000
249#define MAC_CFG_SGMII 0x0000
250#define MAC_CFG_QSGMII 0x4000
251#define MAC_CFG_RGMII 0x8000
252
253/* Test page Registers */
254#define MSCC_PHY_TEST_PAGE_5 5
255#define MSCC_PHY_TEST_PAGE_8 8
256#define TR_CLK_DISABLE 0x8000
257#define MSCC_PHY_TEST_PAGE_9 9
258#define MSCC_PHY_TEST_PAGE_20 20
259#define MSCC_PHY_TEST_PAGE_24 24
260
261/* Token ring page Registers */
262#define MSCC_PHY_TR_CNTL 16
263#define TR_WRITE 0x8000
264#define TR_ADDR(x) (0x7fff & (x))
265#define MSCC_PHY_TR_LSB 17
266#define MSCC_PHY_TR_MSB 18
267
268/* Microsemi PHY ID's
269 * Code assumes lowest nibble is 0
270 */
271#define PHY_ID_VSC8502 0x00070630
272#define PHY_ID_VSC8504 0x000704c0
273#define PHY_ID_VSC8514 0x00070670
274#define PHY_ID_VSC8530 0x00070560
275#define PHY_ID_VSC8531 0x00070570
276#define PHY_ID_VSC8540 0x00070760
277#define PHY_ID_VSC8541 0x00070770
278#define PHY_ID_VSC8552 0x000704e0
279#define PHY_ID_VSC856X 0x000707e0
280#define PHY_ID_VSC8572 0x000704d0
281#define PHY_ID_VSC8574 0x000704a0
282#define PHY_ID_VSC8575 0x000707d0
283#define PHY_ID_VSC8582 0x000707b0
284#define PHY_ID_VSC8584 0x000707c0
285
286#define MSCC_VDDMAC_1500 1500
287#define MSCC_VDDMAC_1800 1800
288#define MSCC_VDDMAC_2500 2500
289#define MSCC_VDDMAC_3300 3300
290
291#define DOWNSHIFT_COUNT_MAX 5
292
293#define MAX_LEDS 4
294
295#define VSC8584_SUPP_LED_MODES (BIT(VSC8531_LINK_ACTIVITY) | \
296 BIT(VSC8531_LINK_1000_ACTIVITY) | \
297 BIT(VSC8531_LINK_100_ACTIVITY) | \
298 BIT(VSC8531_LINK_10_ACTIVITY) | \
299 BIT(VSC8531_LINK_100_1000_ACTIVITY) | \
300 BIT(VSC8531_LINK_10_1000_ACTIVITY) | \
301 BIT(VSC8531_LINK_10_100_ACTIVITY) | \
302 BIT(VSC8584_LINK_100FX_1000X_ACTIVITY) | \
303 BIT(VSC8531_DUPLEX_COLLISION) | \
304 BIT(VSC8531_COLLISION) | \
305 BIT(VSC8531_ACTIVITY) | \
306 BIT(VSC8584_100FX_1000X_ACTIVITY) | \
307 BIT(VSC8531_AUTONEG_FAULT) | \
308 BIT(VSC8531_SERIAL_MODE) | \
309 BIT(VSC8531_FORCE_LED_OFF) | \
310 BIT(VSC8531_FORCE_LED_ON))
311
312#define VSC85XX_SUPP_LED_MODES (BIT(VSC8531_LINK_ACTIVITY) | \
313 BIT(VSC8531_LINK_1000_ACTIVITY) | \
314 BIT(VSC8531_LINK_100_ACTIVITY) | \
315 BIT(VSC8531_LINK_10_ACTIVITY) | \
316 BIT(VSC8531_LINK_100_1000_ACTIVITY) | \
317 BIT(VSC8531_LINK_10_1000_ACTIVITY) | \
318 BIT(VSC8531_LINK_10_100_ACTIVITY) | \
319 BIT(VSC8531_DUPLEX_COLLISION) | \
320 BIT(VSC8531_COLLISION) | \
321 BIT(VSC8531_ACTIVITY) | \
322 BIT(VSC8531_AUTONEG_FAULT) | \
323 BIT(VSC8531_SERIAL_MODE) | \
324 BIT(VSC8531_FORCE_LED_OFF) | \
325 BIT(VSC8531_FORCE_LED_ON))
326
327#define MSCC_VSC8584_REVB_INT8051_FW "microchip/mscc_vsc8584_revb_int8051_fb48.bin"
328#define MSCC_VSC8584_REVB_INT8051_FW_START_ADDR 0xe800
329#define MSCC_VSC8584_REVB_INT8051_FW_CRC 0xfb48
330
331#define MSCC_VSC8574_REVB_INT8051_FW "microchip/mscc_vsc8574_revb_int8051_29e8.bin"
332#define MSCC_VSC8574_REVB_INT8051_FW_START_ADDR 0x4000
333#define MSCC_VSC8574_REVB_INT8051_FW_CRC 0x29e8
334
335#define VSC8584_REVB 0x0001
336#define MSCC_DEV_REV_MASK GENMASK(3, 0)
337
338struct reg_val {
339 u16 reg;
340 u32 val;
341};
342
343struct vsc85xx_hw_stat {
344 const char *string;
345 u8 reg;
346 u16 page;
347 u16 mask;
348};
349
350struct vsc8531_private {
351 int rate_magic;
352 u16 supp_led_modes;
353 u32 leds_mode[MAX_LEDS];
354 u8 nleds;
355 const struct vsc85xx_hw_stat *hw_stats;
356 u64 *stats;
357 int nstats;
358 /* PHY address within the package. */
359 u8 addr;
360 /* For multiple port PHYs; the MDIO address of the base PHY in the
361 * package.
362 */
363 unsigned int base_addr;
364
365#if IS_ENABLED(CONFIG_MACSEC)
366 /* MACsec fields:
367 * - One SecY per device (enforced at the s/w implementation level)
368 * - macsec_flows: list of h/w flows
369 * - ingr_flows: bitmap of ingress flows
370 * - egr_flows: bitmap of egress flows
371 */
372 struct macsec_secy *secy;
373 struct list_head macsec_flows;
374 unsigned long ingr_flows;
375 unsigned long egr_flows;
376#endif
377
378 struct mii_timestamper mii_ts;
379
380 bool input_clk_init;
381 struct vsc85xx_ptp *ptp;
382 /* LOAD/SAVE GPIO pin, used for retrieving or setting time to the PHC. */
383 struct gpio_desc *load_save;
384
385 /* For multiple port PHYs; the MDIO address of the base PHY in the
386 * pair of two PHYs that share a 1588 engine. PHY0 and PHY2 are coupled.
387 * PHY1 and PHY3 as well. PHY0 and PHY1 are base PHYs for their
388 * respective pair.
389 */
390 unsigned int ts_base_addr;
391 u8 ts_base_phy;
392
393 /* ts_lock: used for per-PHY timestamping operations.
394 * phc_lock: used for per-PHY PHC opertations.
395 */
396 struct mutex ts_lock;
397 struct mutex phc_lock;
398};
399
400/* Shared structure between the PHYs of the same package.
401 * gpio_lock: used for PHC operations. Common for all PHYs as the load/save GPIO
402 * is shared.
403 */
404struct vsc85xx_shared_private {
405 struct mutex gpio_lock;
406};
407
408#if IS_ENABLED(CONFIG_OF_MDIO)
409struct vsc8531_edge_rate_table {
410 u32 vddmac;
411 u32 slowdown[8];
412};
413#endif /* CONFIG_OF_MDIO */
414
415#if IS_ENABLED(CONFIG_MACSEC)
416int vsc8584_macsec_init(struct phy_device *phydev);
417void vsc8584_handle_macsec_interrupt(struct phy_device *phydev);
418void vsc8584_config_macsec_intr(struct phy_device *phydev);
419#else
420static inline int vsc8584_macsec_init(struct phy_device *phydev)
421{
422 return 0;
423}
424static inline void vsc8584_handle_macsec_interrupt(struct phy_device *phydev)
425{
426}
427static inline void vsc8584_config_macsec_intr(struct phy_device *phydev)
428{
429}
430#endif
431
432#if IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING)
433void vsc85xx_link_change_notify(struct phy_device *phydev);
434void vsc8584_config_ts_intr(struct phy_device *phydev);
435int vsc8584_ptp_init(struct phy_device *phydev);
436int vsc8584_ptp_probe_once(struct phy_device *phydev);
437int vsc8584_ptp_probe(struct phy_device *phydev);
438irqreturn_t vsc8584_handle_ts_interrupt(struct phy_device *phydev);
439#else
440static inline void vsc85xx_link_change_notify(struct phy_device *phydev)
441{
442}
443static inline void vsc8584_config_ts_intr(struct phy_device *phydev)
444{
445}
446static inline int vsc8584_ptp_init(struct phy_device *phydev)
447{
448 return 0;
449}
450static inline int vsc8584_ptp_probe_once(struct phy_device *phydev)
451{
452 return 0;
453}
454static inline int vsc8584_ptp_probe(struct phy_device *phydev)
455{
456 return 0;
457}
458static inline irqreturn_t vsc8584_handle_ts_interrupt(struct phy_device *phydev)
459{
460 return IRQ_NONE;
461}
462#endif
463
464#endif /* _MSCC_PHY_H_ */