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1/*
2 * drivers/net/phy/micrel.c
3 *
4 * Driver for Micrel PHYs
5 *
6 * Author: David J. Choi
7 *
8 * Copyright (c) 2010 Micrel, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * Support : ksz9021 1000/100/10 phy from Micrel
16 * ks8001, ks8737, ks8721, ks8041, ks8051 100/10 phy
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/phy.h>
22#include <linux/micrel_phy.h>
23
24/* general Interrupt control/status reg in vendor specific block. */
25#define MII_KSZPHY_INTCS 0x1B
26#define KSZPHY_INTCS_JABBER (1 << 15)
27#define KSZPHY_INTCS_RECEIVE_ERR (1 << 14)
28#define KSZPHY_INTCS_PAGE_RECEIVE (1 << 13)
29#define KSZPHY_INTCS_PARELLEL (1 << 12)
30#define KSZPHY_INTCS_LINK_PARTNER_ACK (1 << 11)
31#define KSZPHY_INTCS_LINK_DOWN (1 << 10)
32#define KSZPHY_INTCS_REMOTE_FAULT (1 << 9)
33#define KSZPHY_INTCS_LINK_UP (1 << 8)
34#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
35 KSZPHY_INTCS_LINK_DOWN)
36
37/* general PHY control reg in vendor specific block. */
38#define MII_KSZPHY_CTRL 0x1F
39/* bitmap of PHY register to set interrupt mode */
40#define KSZPHY_CTRL_INT_ACTIVE_HIGH (1 << 9)
41#define KSZ9021_CTRL_INT_ACTIVE_HIGH (1 << 14)
42#define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14)
43#define KSZ8051_RMII_50MHZ_CLK (1 << 7)
44
45static int kszphy_ack_interrupt(struct phy_device *phydev)
46{
47 /* bit[7..0] int status, which is a read and clear register. */
48 int rc;
49
50 rc = phy_read(phydev, MII_KSZPHY_INTCS);
51
52 return (rc < 0) ? rc : 0;
53}
54
55static int kszphy_set_interrupt(struct phy_device *phydev)
56{
57 int temp;
58 temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ?
59 KSZPHY_INTCS_ALL : 0;
60 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
61}
62
63static int kszphy_config_intr(struct phy_device *phydev)
64{
65 int temp, rc;
66
67 /* set the interrupt pin active low */
68 temp = phy_read(phydev, MII_KSZPHY_CTRL);
69 temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
70 phy_write(phydev, MII_KSZPHY_CTRL, temp);
71 rc = kszphy_set_interrupt(phydev);
72 return rc < 0 ? rc : 0;
73}
74
75static int ksz9021_config_intr(struct phy_device *phydev)
76{
77 int temp, rc;
78
79 /* set the interrupt pin active low */
80 temp = phy_read(phydev, MII_KSZPHY_CTRL);
81 temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
82 phy_write(phydev, MII_KSZPHY_CTRL, temp);
83 rc = kszphy_set_interrupt(phydev);
84 return rc < 0 ? rc : 0;
85}
86
87static int ks8737_config_intr(struct phy_device *phydev)
88{
89 int temp, rc;
90
91 /* set the interrupt pin active low */
92 temp = phy_read(phydev, MII_KSZPHY_CTRL);
93 temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH;
94 phy_write(phydev, MII_KSZPHY_CTRL, temp);
95 rc = kszphy_set_interrupt(phydev);
96 return rc < 0 ? rc : 0;
97}
98
99static int kszphy_config_init(struct phy_device *phydev)
100{
101 return 0;
102}
103
104static int ks8051_config_init(struct phy_device *phydev)
105{
106 int regval;
107
108 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
109 regval = phy_read(phydev, MII_KSZPHY_CTRL);
110 regval |= KSZ8051_RMII_50MHZ_CLK;
111 phy_write(phydev, MII_KSZPHY_CTRL, regval);
112 }
113
114 return 0;
115}
116
117static struct phy_driver ks8737_driver = {
118 .phy_id = PHY_ID_KS8737,
119 .phy_id_mask = 0x00fffff0,
120 .name = "Micrel KS8737",
121 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
122 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
123 .config_init = kszphy_config_init,
124 .config_aneg = genphy_config_aneg,
125 .read_status = genphy_read_status,
126 .ack_interrupt = kszphy_ack_interrupt,
127 .config_intr = ks8737_config_intr,
128 .driver = { .owner = THIS_MODULE,},
129};
130
131static struct phy_driver ks8041_driver = {
132 .phy_id = PHY_ID_KS8041,
133 .phy_id_mask = 0x00fffff0,
134 .name = "Micrel KS8041",
135 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
136 | SUPPORTED_Asym_Pause),
137 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
138 .config_init = kszphy_config_init,
139 .config_aneg = genphy_config_aneg,
140 .read_status = genphy_read_status,
141 .ack_interrupt = kszphy_ack_interrupt,
142 .config_intr = kszphy_config_intr,
143 .driver = { .owner = THIS_MODULE,},
144};
145
146static struct phy_driver ks8051_driver = {
147 .phy_id = PHY_ID_KS8051,
148 .phy_id_mask = 0x00fffff0,
149 .name = "Micrel KS8051",
150 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
151 | SUPPORTED_Asym_Pause),
152 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
153 .config_init = ks8051_config_init,
154 .config_aneg = genphy_config_aneg,
155 .read_status = genphy_read_status,
156 .ack_interrupt = kszphy_ack_interrupt,
157 .config_intr = kszphy_config_intr,
158 .driver = { .owner = THIS_MODULE,},
159};
160
161static struct phy_driver ks8001_driver = {
162 .phy_id = PHY_ID_KS8001,
163 .name = "Micrel KS8001 or KS8721",
164 .phy_id_mask = 0x00fffff0,
165 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
166 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
167 .config_init = kszphy_config_init,
168 .config_aneg = genphy_config_aneg,
169 .read_status = genphy_read_status,
170 .ack_interrupt = kszphy_ack_interrupt,
171 .config_intr = kszphy_config_intr,
172 .driver = { .owner = THIS_MODULE,},
173};
174
175static struct phy_driver ksz9021_driver = {
176 .phy_id = PHY_ID_KSZ9021,
177 .phy_id_mask = 0x000fff10,
178 .name = "Micrel KSZ9021 Gigabit PHY",
179 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause
180 | SUPPORTED_Asym_Pause),
181 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
182 .config_init = kszphy_config_init,
183 .config_aneg = genphy_config_aneg,
184 .read_status = genphy_read_status,
185 .ack_interrupt = kszphy_ack_interrupt,
186 .config_intr = ksz9021_config_intr,
187 .driver = { .owner = THIS_MODULE, },
188};
189
190static int __init ksphy_init(void)
191{
192 int ret;
193
194 ret = phy_driver_register(&ks8001_driver);
195 if (ret)
196 goto err1;
197
198 ret = phy_driver_register(&ksz9021_driver);
199 if (ret)
200 goto err2;
201
202 ret = phy_driver_register(&ks8737_driver);
203 if (ret)
204 goto err3;
205 ret = phy_driver_register(&ks8041_driver);
206 if (ret)
207 goto err4;
208 ret = phy_driver_register(&ks8051_driver);
209 if (ret)
210 goto err5;
211
212 return 0;
213
214err5:
215 phy_driver_unregister(&ks8041_driver);
216err4:
217 phy_driver_unregister(&ks8737_driver);
218err3:
219 phy_driver_unregister(&ksz9021_driver);
220err2:
221 phy_driver_unregister(&ks8001_driver);
222err1:
223 return ret;
224}
225
226static void __exit ksphy_exit(void)
227{
228 phy_driver_unregister(&ks8001_driver);
229 phy_driver_unregister(&ks8737_driver);
230 phy_driver_unregister(&ksz9021_driver);
231 phy_driver_unregister(&ks8041_driver);
232 phy_driver_unregister(&ks8051_driver);
233}
234
235module_init(ksphy_init);
236module_exit(ksphy_exit);
237
238MODULE_DESCRIPTION("Micrel PHY driver");
239MODULE_AUTHOR("David J. Choi");
240MODULE_LICENSE("GPL");
241
242static struct mdio_device_id __maybe_unused micrel_tbl[] = {
243 { PHY_ID_KSZ9021, 0x000fff10 },
244 { PHY_ID_KS8001, 0x00fffff0 },
245 { PHY_ID_KS8737, 0x00fffff0 },
246 { PHY_ID_KS8041, 0x00fffff0 },
247 { PHY_ID_KS8051, 0x00fffff0 },
248 { }
249};
250
251MODULE_DEVICE_TABLE(mdio, micrel_tbl);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/micrel.c
4 *
5 * Driver for Micrel PHYs
6 *
7 * Author: David J. Choi
8 *
9 * Copyright (c) 2010-2013 Micrel, Inc.
10 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
11 *
12 * Support : Micrel Phys:
13 * Giga phys: ksz9021, ksz9031, ksz9131
14 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
15 * ksz8021, ksz8031, ksz8051,
16 * ksz8081, ksz8091,
17 * ksz8061,
18 * Switch : ksz8873, ksz886x
19 * ksz9477
20 */
21
22#include <linux/bitfield.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/phy.h>
26#include <linux/micrel_phy.h>
27#include <linux/of.h>
28#include <linux/clk.h>
29#include <linux/delay.h>
30
31/* Operation Mode Strap Override */
32#define MII_KSZPHY_OMSO 0x16
33#define KSZPHY_OMSO_FACTORY_TEST BIT(15)
34#define KSZPHY_OMSO_B_CAST_OFF BIT(9)
35#define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
36#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
37#define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
38
39/* general Interrupt control/status reg in vendor specific block. */
40#define MII_KSZPHY_INTCS 0x1B
41#define KSZPHY_INTCS_JABBER BIT(15)
42#define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
43#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
44#define KSZPHY_INTCS_PARELLEL BIT(12)
45#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
46#define KSZPHY_INTCS_LINK_DOWN BIT(10)
47#define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
48#define KSZPHY_INTCS_LINK_UP BIT(8)
49#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
50 KSZPHY_INTCS_LINK_DOWN)
51
52/* PHY Control 1 */
53#define MII_KSZPHY_CTRL_1 0x1e
54
55/* PHY Control 2 / PHY Control (if no PHY Control 1) */
56#define MII_KSZPHY_CTRL_2 0x1f
57#define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
58/* bitmap of PHY register to set interrupt mode */
59#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
60#define KSZPHY_RMII_REF_CLK_SEL BIT(7)
61
62/* Write/read to/from extended registers */
63#define MII_KSZPHY_EXTREG 0x0b
64#define KSZPHY_EXTREG_WRITE 0x8000
65
66#define MII_KSZPHY_EXTREG_WRITE 0x0c
67#define MII_KSZPHY_EXTREG_READ 0x0d
68
69/* Extended registers */
70#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
71#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
72#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
73
74#define PS_TO_REG 200
75
76struct kszphy_hw_stat {
77 const char *string;
78 u8 reg;
79 u8 bits;
80};
81
82static struct kszphy_hw_stat kszphy_hw_stats[] = {
83 { "phy_receive_errors", 21, 16},
84 { "phy_idle_errors", 10, 8 },
85};
86
87struct kszphy_type {
88 u32 led_mode_reg;
89 u16 interrupt_level_mask;
90 bool has_broadcast_disable;
91 bool has_nand_tree_disable;
92 bool has_rmii_ref_clk_sel;
93};
94
95struct kszphy_priv {
96 const struct kszphy_type *type;
97 int led_mode;
98 bool rmii_ref_clk_sel;
99 bool rmii_ref_clk_sel_val;
100 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
101};
102
103static const struct kszphy_type ksz8021_type = {
104 .led_mode_reg = MII_KSZPHY_CTRL_2,
105 .has_broadcast_disable = true,
106 .has_nand_tree_disable = true,
107 .has_rmii_ref_clk_sel = true,
108};
109
110static const struct kszphy_type ksz8041_type = {
111 .led_mode_reg = MII_KSZPHY_CTRL_1,
112};
113
114static const struct kszphy_type ksz8051_type = {
115 .led_mode_reg = MII_KSZPHY_CTRL_2,
116 .has_nand_tree_disable = true,
117};
118
119static const struct kszphy_type ksz8081_type = {
120 .led_mode_reg = MII_KSZPHY_CTRL_2,
121 .has_broadcast_disable = true,
122 .has_nand_tree_disable = true,
123 .has_rmii_ref_clk_sel = true,
124};
125
126static const struct kszphy_type ks8737_type = {
127 .interrupt_level_mask = BIT(14),
128};
129
130static const struct kszphy_type ksz9021_type = {
131 .interrupt_level_mask = BIT(14),
132};
133
134static int kszphy_extended_write(struct phy_device *phydev,
135 u32 regnum, u16 val)
136{
137 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
138 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
139}
140
141static int kszphy_extended_read(struct phy_device *phydev,
142 u32 regnum)
143{
144 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
145 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
146}
147
148static int kszphy_ack_interrupt(struct phy_device *phydev)
149{
150 /* bit[7..0] int status, which is a read and clear register. */
151 int rc;
152
153 rc = phy_read(phydev, MII_KSZPHY_INTCS);
154
155 return (rc < 0) ? rc : 0;
156}
157
158static int kszphy_config_intr(struct phy_device *phydev)
159{
160 const struct kszphy_type *type = phydev->drv->driver_data;
161 int temp;
162 u16 mask;
163
164 if (type && type->interrupt_level_mask)
165 mask = type->interrupt_level_mask;
166 else
167 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
168
169 /* set the interrupt pin active low */
170 temp = phy_read(phydev, MII_KSZPHY_CTRL);
171 if (temp < 0)
172 return temp;
173 temp &= ~mask;
174 phy_write(phydev, MII_KSZPHY_CTRL, temp);
175
176 /* enable / disable interrupts */
177 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
178 temp = KSZPHY_INTCS_ALL;
179 else
180 temp = 0;
181
182 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
183}
184
185static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
186{
187 int ctrl;
188
189 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
190 if (ctrl < 0)
191 return ctrl;
192
193 if (val)
194 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
195 else
196 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
197
198 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
199}
200
201static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
202{
203 int rc, temp, shift;
204
205 switch (reg) {
206 case MII_KSZPHY_CTRL_1:
207 shift = 14;
208 break;
209 case MII_KSZPHY_CTRL_2:
210 shift = 4;
211 break;
212 default:
213 return -EINVAL;
214 }
215
216 temp = phy_read(phydev, reg);
217 if (temp < 0) {
218 rc = temp;
219 goto out;
220 }
221
222 temp &= ~(3 << shift);
223 temp |= val << shift;
224 rc = phy_write(phydev, reg, temp);
225out:
226 if (rc < 0)
227 phydev_err(phydev, "failed to set led mode\n");
228
229 return rc;
230}
231
232/* Disable PHY address 0 as the broadcast address, so that it can be used as a
233 * unique (non-broadcast) address on a shared bus.
234 */
235static int kszphy_broadcast_disable(struct phy_device *phydev)
236{
237 int ret;
238
239 ret = phy_read(phydev, MII_KSZPHY_OMSO);
240 if (ret < 0)
241 goto out;
242
243 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
244out:
245 if (ret)
246 phydev_err(phydev, "failed to disable broadcast address\n");
247
248 return ret;
249}
250
251static int kszphy_nand_tree_disable(struct phy_device *phydev)
252{
253 int ret;
254
255 ret = phy_read(phydev, MII_KSZPHY_OMSO);
256 if (ret < 0)
257 goto out;
258
259 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
260 return 0;
261
262 ret = phy_write(phydev, MII_KSZPHY_OMSO,
263 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
264out:
265 if (ret)
266 phydev_err(phydev, "failed to disable NAND tree mode\n");
267
268 return ret;
269}
270
271/* Some config bits need to be set again on resume, handle them here. */
272static int kszphy_config_reset(struct phy_device *phydev)
273{
274 struct kszphy_priv *priv = phydev->priv;
275 int ret;
276
277 if (priv->rmii_ref_clk_sel) {
278 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
279 if (ret) {
280 phydev_err(phydev,
281 "failed to set rmii reference clock\n");
282 return ret;
283 }
284 }
285
286 if (priv->led_mode >= 0)
287 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
288
289 return 0;
290}
291
292static int kszphy_config_init(struct phy_device *phydev)
293{
294 struct kszphy_priv *priv = phydev->priv;
295 const struct kszphy_type *type;
296
297 if (!priv)
298 return 0;
299
300 type = priv->type;
301
302 if (type->has_broadcast_disable)
303 kszphy_broadcast_disable(phydev);
304
305 if (type->has_nand_tree_disable)
306 kszphy_nand_tree_disable(phydev);
307
308 return kszphy_config_reset(phydev);
309}
310
311static int ksz8041_config_init(struct phy_device *phydev)
312{
313 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
314
315 struct device_node *of_node = phydev->mdio.dev.of_node;
316
317 /* Limit supported and advertised modes in fiber mode */
318 if (of_property_read_bool(of_node, "micrel,fiber-mode")) {
319 phydev->dev_flags |= MICREL_PHY_FXEN;
320 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
321 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
322
323 linkmode_and(phydev->supported, phydev->supported, mask);
324 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
325 phydev->supported);
326 linkmode_and(phydev->advertising, phydev->advertising, mask);
327 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
328 phydev->advertising);
329 phydev->autoneg = AUTONEG_DISABLE;
330 }
331
332 return kszphy_config_init(phydev);
333}
334
335static int ksz8041_config_aneg(struct phy_device *phydev)
336{
337 /* Skip auto-negotiation in fiber mode */
338 if (phydev->dev_flags & MICREL_PHY_FXEN) {
339 phydev->speed = SPEED_100;
340 return 0;
341 }
342
343 return genphy_config_aneg(phydev);
344}
345
346static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
347 const u32 ksz_phy_id)
348{
349 int ret;
350
351 if ((phydev->phy_id & MICREL_PHY_ID_MASK) != ksz_phy_id)
352 return 0;
353
354 ret = phy_read(phydev, MII_BMSR);
355 if (ret < 0)
356 return ret;
357
358 /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
359 * exact PHY ID. However, they can be told apart by the extended
360 * capability registers presence. The KSZ8051 PHY has them while
361 * the switch does not.
362 */
363 ret &= BMSR_ERCAP;
364 if (ksz_phy_id == PHY_ID_KSZ8051)
365 return ret;
366 else
367 return !ret;
368}
369
370static int ksz8051_match_phy_device(struct phy_device *phydev)
371{
372 return ksz8051_ksz8795_match_phy_device(phydev, PHY_ID_KSZ8051);
373}
374
375static int ksz8081_config_init(struct phy_device *phydev)
376{
377 /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
378 * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
379 * pull-down is missing, the factory test mode should be cleared by
380 * manually writing a 0.
381 */
382 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
383
384 return kszphy_config_init(phydev);
385}
386
387static int ksz8061_config_init(struct phy_device *phydev)
388{
389 int ret;
390
391 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
392 if (ret)
393 return ret;
394
395 return kszphy_config_init(phydev);
396}
397
398static int ksz8795_match_phy_device(struct phy_device *phydev)
399{
400 return ksz8051_ksz8795_match_phy_device(phydev, PHY_ID_KSZ87XX);
401}
402
403static int ksz9021_load_values_from_of(struct phy_device *phydev,
404 const struct device_node *of_node,
405 u16 reg,
406 const char *field1, const char *field2,
407 const char *field3, const char *field4)
408{
409 int val1 = -1;
410 int val2 = -2;
411 int val3 = -3;
412 int val4 = -4;
413 int newval;
414 int matches = 0;
415
416 if (!of_property_read_u32(of_node, field1, &val1))
417 matches++;
418
419 if (!of_property_read_u32(of_node, field2, &val2))
420 matches++;
421
422 if (!of_property_read_u32(of_node, field3, &val3))
423 matches++;
424
425 if (!of_property_read_u32(of_node, field4, &val4))
426 matches++;
427
428 if (!matches)
429 return 0;
430
431 if (matches < 4)
432 newval = kszphy_extended_read(phydev, reg);
433 else
434 newval = 0;
435
436 if (val1 != -1)
437 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
438
439 if (val2 != -2)
440 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
441
442 if (val3 != -3)
443 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
444
445 if (val4 != -4)
446 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
447
448 return kszphy_extended_write(phydev, reg, newval);
449}
450
451static int ksz9021_config_init(struct phy_device *phydev)
452{
453 const struct device *dev = &phydev->mdio.dev;
454 const struct device_node *of_node = dev->of_node;
455 const struct device *dev_walker;
456
457 /* The Micrel driver has a deprecated option to place phy OF
458 * properties in the MAC node. Walk up the tree of devices to
459 * find a device with an OF node.
460 */
461 dev_walker = &phydev->mdio.dev;
462 do {
463 of_node = dev_walker->of_node;
464 dev_walker = dev_walker->parent;
465
466 } while (!of_node && dev_walker);
467
468 if (of_node) {
469 ksz9021_load_values_from_of(phydev, of_node,
470 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
471 "txen-skew-ps", "txc-skew-ps",
472 "rxdv-skew-ps", "rxc-skew-ps");
473 ksz9021_load_values_from_of(phydev, of_node,
474 MII_KSZPHY_RX_DATA_PAD_SKEW,
475 "rxd0-skew-ps", "rxd1-skew-ps",
476 "rxd2-skew-ps", "rxd3-skew-ps");
477 ksz9021_load_values_from_of(phydev, of_node,
478 MII_KSZPHY_TX_DATA_PAD_SKEW,
479 "txd0-skew-ps", "txd1-skew-ps",
480 "txd2-skew-ps", "txd3-skew-ps");
481 }
482 return 0;
483}
484
485#define KSZ9031_PS_TO_REG 60
486
487/* Extended registers */
488/* MMD Address 0x0 */
489#define MII_KSZ9031RN_FLP_BURST_TX_LO 3
490#define MII_KSZ9031RN_FLP_BURST_TX_HI 4
491
492/* MMD Address 0x2 */
493#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
494#define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4)
495#define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0)
496
497#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
498#define MII_KSZ9031RN_RXD3 GENMASK(15, 12)
499#define MII_KSZ9031RN_RXD2 GENMASK(11, 8)
500#define MII_KSZ9031RN_RXD1 GENMASK(7, 4)
501#define MII_KSZ9031RN_RXD0 GENMASK(3, 0)
502
503#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
504#define MII_KSZ9031RN_TXD3 GENMASK(15, 12)
505#define MII_KSZ9031RN_TXD2 GENMASK(11, 8)
506#define MII_KSZ9031RN_TXD1 GENMASK(7, 4)
507#define MII_KSZ9031RN_TXD0 GENMASK(3, 0)
508
509#define MII_KSZ9031RN_CLK_PAD_SKEW 8
510#define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5)
511#define MII_KSZ9031RN_RX_CLK GENMASK(4, 0)
512
513/* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To
514 * provide different RGMII options we need to configure delay offset
515 * for each pad relative to build in delay.
516 */
517/* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
518 * 1.80ns
519 */
520#define RX_ID 0x7
521#define RX_CLK_ID 0x19
522
523/* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
524 * internal 1.2ns delay.
525 */
526#define RX_ND 0xc
527#define RX_CLK_ND 0x0
528
529/* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
530#define TX_ID 0x0
531#define TX_CLK_ID 0x1f
532
533/* set tx and tx_clk to "No delay adjustment" to keep 0ns
534 * dealy
535 */
536#define TX_ND 0x7
537#define TX_CLK_ND 0xf
538
539/* MMD Address 0x1C */
540#define MII_KSZ9031RN_EDPD 0x23
541#define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
542
543static int ksz9031_of_load_skew_values(struct phy_device *phydev,
544 const struct device_node *of_node,
545 u16 reg, size_t field_sz,
546 const char *field[], u8 numfields,
547 bool *update)
548{
549 int val[4] = {-1, -2, -3, -4};
550 int matches = 0;
551 u16 mask;
552 u16 maxval;
553 u16 newval;
554 int i;
555
556 for (i = 0; i < numfields; i++)
557 if (!of_property_read_u32(of_node, field[i], val + i))
558 matches++;
559
560 if (!matches)
561 return 0;
562
563 *update |= true;
564
565 if (matches < numfields)
566 newval = phy_read_mmd(phydev, 2, reg);
567 else
568 newval = 0;
569
570 maxval = (field_sz == 4) ? 0xf : 0x1f;
571 for (i = 0; i < numfields; i++)
572 if (val[i] != -(i + 1)) {
573 mask = 0xffff;
574 mask ^= maxval << (field_sz * i);
575 newval = (newval & mask) |
576 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
577 << (field_sz * i));
578 }
579
580 return phy_write_mmd(phydev, 2, reg, newval);
581}
582
583/* Center KSZ9031RNX FLP timing at 16ms. */
584static int ksz9031_center_flp_timing(struct phy_device *phydev)
585{
586 int result;
587
588 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
589 0x0006);
590 if (result)
591 return result;
592
593 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
594 0x1A80);
595 if (result)
596 return result;
597
598 return genphy_restart_aneg(phydev);
599}
600
601/* Enable energy-detect power-down mode */
602static int ksz9031_enable_edpd(struct phy_device *phydev)
603{
604 int reg;
605
606 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
607 if (reg < 0)
608 return reg;
609 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
610 reg | MII_KSZ9031RN_EDPD_ENABLE);
611}
612
613static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
614{
615 u16 rx, tx, rx_clk, tx_clk;
616 int ret;
617
618 switch (phydev->interface) {
619 case PHY_INTERFACE_MODE_RGMII:
620 tx = TX_ND;
621 tx_clk = TX_CLK_ND;
622 rx = RX_ND;
623 rx_clk = RX_CLK_ND;
624 break;
625 case PHY_INTERFACE_MODE_RGMII_ID:
626 tx = TX_ID;
627 tx_clk = TX_CLK_ID;
628 rx = RX_ID;
629 rx_clk = RX_CLK_ID;
630 break;
631 case PHY_INTERFACE_MODE_RGMII_RXID:
632 tx = TX_ND;
633 tx_clk = TX_CLK_ND;
634 rx = RX_ID;
635 rx_clk = RX_CLK_ID;
636 break;
637 case PHY_INTERFACE_MODE_RGMII_TXID:
638 tx = TX_ID;
639 tx_clk = TX_CLK_ID;
640 rx = RX_ND;
641 rx_clk = RX_CLK_ND;
642 break;
643 default:
644 return 0;
645 }
646
647 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
648 FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |
649 FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
650 if (ret < 0)
651 return ret;
652
653 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
654 FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |
655 FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |
656 FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |
657 FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
658 if (ret < 0)
659 return ret;
660
661 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
662 FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |
663 FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |
664 FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |
665 FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
666 if (ret < 0)
667 return ret;
668
669 return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW,
670 FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |
671 FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
672}
673
674static int ksz9031_config_init(struct phy_device *phydev)
675{
676 const struct device *dev = &phydev->mdio.dev;
677 const struct device_node *of_node = dev->of_node;
678 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
679 static const char *rx_data_skews[4] = {
680 "rxd0-skew-ps", "rxd1-skew-ps",
681 "rxd2-skew-ps", "rxd3-skew-ps"
682 };
683 static const char *tx_data_skews[4] = {
684 "txd0-skew-ps", "txd1-skew-ps",
685 "txd2-skew-ps", "txd3-skew-ps"
686 };
687 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
688 const struct device *dev_walker;
689 int result;
690
691 result = ksz9031_enable_edpd(phydev);
692 if (result < 0)
693 return result;
694
695 /* The Micrel driver has a deprecated option to place phy OF
696 * properties in the MAC node. Walk up the tree of devices to
697 * find a device with an OF node.
698 */
699 dev_walker = &phydev->mdio.dev;
700 do {
701 of_node = dev_walker->of_node;
702 dev_walker = dev_walker->parent;
703 } while (!of_node && dev_walker);
704
705 if (of_node) {
706 bool update = false;
707
708 if (phy_interface_is_rgmii(phydev)) {
709 result = ksz9031_config_rgmii_delay(phydev);
710 if (result < 0)
711 return result;
712 }
713
714 ksz9031_of_load_skew_values(phydev, of_node,
715 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
716 clk_skews, 2, &update);
717
718 ksz9031_of_load_skew_values(phydev, of_node,
719 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
720 control_skews, 2, &update);
721
722 ksz9031_of_load_skew_values(phydev, of_node,
723 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
724 rx_data_skews, 4, &update);
725
726 ksz9031_of_load_skew_values(phydev, of_node,
727 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
728 tx_data_skews, 4, &update);
729
730 if (update && phydev->interface != PHY_INTERFACE_MODE_RGMII)
731 phydev_warn(phydev,
732 "*-skew-ps values should be used only with phy-mode = \"rgmii\"\n");
733
734 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
735 * When the device links in the 1000BASE-T slave mode only,
736 * the optional 125MHz reference output clock (CLK125_NDO)
737 * has wide duty cycle variation.
738 *
739 * The optional CLK125_NDO clock does not meet the RGMII
740 * 45/55 percent (min/max) duty cycle requirement and therefore
741 * cannot be used directly by the MAC side for clocking
742 * applications that have setup/hold time requirements on
743 * rising and falling clock edges.
744 *
745 * Workaround:
746 * Force the phy to be the master to receive a stable clock
747 * which meets the duty cycle requirement.
748 */
749 if (of_property_read_bool(of_node, "micrel,force-master")) {
750 result = phy_read(phydev, MII_CTRL1000);
751 if (result < 0)
752 goto err_force_master;
753
754 /* enable master mode, config & prefer master */
755 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
756 result = phy_write(phydev, MII_CTRL1000, result);
757 if (result < 0)
758 goto err_force_master;
759 }
760 }
761
762 return ksz9031_center_flp_timing(phydev);
763
764err_force_master:
765 phydev_err(phydev, "failed to force the phy to master mode\n");
766 return result;
767}
768
769#define KSZ9131_SKEW_5BIT_MAX 2400
770#define KSZ9131_SKEW_4BIT_MAX 800
771#define KSZ9131_OFFSET 700
772#define KSZ9131_STEP 100
773
774static int ksz9131_of_load_skew_values(struct phy_device *phydev,
775 struct device_node *of_node,
776 u16 reg, size_t field_sz,
777 char *field[], u8 numfields)
778{
779 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
780 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
781 int skewval, skewmax = 0;
782 int matches = 0;
783 u16 maxval;
784 u16 newval;
785 u16 mask;
786 int i;
787
788 /* psec properties in dts should mean x pico seconds */
789 if (field_sz == 5)
790 skewmax = KSZ9131_SKEW_5BIT_MAX;
791 else
792 skewmax = KSZ9131_SKEW_4BIT_MAX;
793
794 for (i = 0; i < numfields; i++)
795 if (!of_property_read_s32(of_node, field[i], &skewval)) {
796 if (skewval < -KSZ9131_OFFSET)
797 skewval = -KSZ9131_OFFSET;
798 else if (skewval > skewmax)
799 skewval = skewmax;
800
801 val[i] = skewval + KSZ9131_OFFSET;
802 matches++;
803 }
804
805 if (!matches)
806 return 0;
807
808 if (matches < numfields)
809 newval = phy_read_mmd(phydev, 2, reg);
810 else
811 newval = 0;
812
813 maxval = (field_sz == 4) ? 0xf : 0x1f;
814 for (i = 0; i < numfields; i++)
815 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
816 mask = 0xffff;
817 mask ^= maxval << (field_sz * i);
818 newval = (newval & mask) |
819 (((val[i] / KSZ9131_STEP) & maxval)
820 << (field_sz * i));
821 }
822
823 return phy_write_mmd(phydev, 2, reg, newval);
824}
825
826#define KSZ9131RN_MMD_COMMON_CTRL_REG 2
827#define KSZ9131RN_RXC_DLL_CTRL 76
828#define KSZ9131RN_TXC_DLL_CTRL 77
829#define KSZ9131RN_DLL_CTRL_BYPASS BIT_MASK(12)
830#define KSZ9131RN_DLL_ENABLE_DELAY 0
831#define KSZ9131RN_DLL_DISABLE_DELAY BIT(12)
832
833static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
834{
835 u16 rxcdll_val, txcdll_val;
836 int ret;
837
838 switch (phydev->interface) {
839 case PHY_INTERFACE_MODE_RGMII:
840 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
841 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
842 break;
843 case PHY_INTERFACE_MODE_RGMII_ID:
844 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
845 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
846 break;
847 case PHY_INTERFACE_MODE_RGMII_RXID:
848 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
849 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
850 break;
851 case PHY_INTERFACE_MODE_RGMII_TXID:
852 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
853 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
854 break;
855 default:
856 return 0;
857 }
858
859 ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
860 KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
861 rxcdll_val);
862 if (ret < 0)
863 return ret;
864
865 return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
866 KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
867 txcdll_val);
868}
869
870static int ksz9131_config_init(struct phy_device *phydev)
871{
872 const struct device *dev = &phydev->mdio.dev;
873 struct device_node *of_node = dev->of_node;
874 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
875 char *rx_data_skews[4] = {
876 "rxd0-skew-psec", "rxd1-skew-psec",
877 "rxd2-skew-psec", "rxd3-skew-psec"
878 };
879 char *tx_data_skews[4] = {
880 "txd0-skew-psec", "txd1-skew-psec",
881 "txd2-skew-psec", "txd3-skew-psec"
882 };
883 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
884 const struct device *dev_walker;
885 int ret;
886
887 dev_walker = &phydev->mdio.dev;
888 do {
889 of_node = dev_walker->of_node;
890 dev_walker = dev_walker->parent;
891 } while (!of_node && dev_walker);
892
893 if (!of_node)
894 return 0;
895
896 if (phy_interface_is_rgmii(phydev)) {
897 ret = ksz9131_config_rgmii_delay(phydev);
898 if (ret < 0)
899 return ret;
900 }
901
902 ret = ksz9131_of_load_skew_values(phydev, of_node,
903 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
904 clk_skews, 2);
905 if (ret < 0)
906 return ret;
907
908 ret = ksz9131_of_load_skew_values(phydev, of_node,
909 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
910 control_skews, 2);
911 if (ret < 0)
912 return ret;
913
914 ret = ksz9131_of_load_skew_values(phydev, of_node,
915 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
916 rx_data_skews, 4);
917 if (ret < 0)
918 return ret;
919
920 ret = ksz9131_of_load_skew_values(phydev, of_node,
921 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
922 tx_data_skews, 4);
923 if (ret < 0)
924 return ret;
925
926 return 0;
927}
928
929#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
930#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
931#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
932static int ksz8873mll_read_status(struct phy_device *phydev)
933{
934 int regval;
935
936 /* dummy read */
937 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
938
939 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
940
941 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
942 phydev->duplex = DUPLEX_HALF;
943 else
944 phydev->duplex = DUPLEX_FULL;
945
946 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
947 phydev->speed = SPEED_10;
948 else
949 phydev->speed = SPEED_100;
950
951 phydev->link = 1;
952 phydev->pause = phydev->asym_pause = 0;
953
954 return 0;
955}
956
957static int ksz9031_get_features(struct phy_device *phydev)
958{
959 int ret;
960
961 ret = genphy_read_abilities(phydev);
962 if (ret < 0)
963 return ret;
964
965 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
966 * Whenever the device's Asymmetric Pause capability is set to 1,
967 * link-up may fail after a link-up to link-down transition.
968 *
969 * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
970 *
971 * Workaround:
972 * Do not enable the Asymmetric Pause capability bit.
973 */
974 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
975
976 /* We force setting the Pause capability as the core will force the
977 * Asymmetric Pause capability to 1 otherwise.
978 */
979 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
980
981 return 0;
982}
983
984static int ksz9031_read_status(struct phy_device *phydev)
985{
986 int err;
987 int regval;
988
989 err = genphy_read_status(phydev);
990 if (err)
991 return err;
992
993 /* Make sure the PHY is not broken. Read idle error count,
994 * and reset the PHY if it is maxed out.
995 */
996 regval = phy_read(phydev, MII_STAT1000);
997 if ((regval & 0xFF) == 0xFF) {
998 phy_init_hw(phydev);
999 phydev->link = 0;
1000 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
1001 phydev->drv->config_intr(phydev);
1002 return genphy_config_aneg(phydev);
1003 }
1004
1005 return 0;
1006}
1007
1008static int ksz8873mll_config_aneg(struct phy_device *phydev)
1009{
1010 return 0;
1011}
1012
1013static int kszphy_get_sset_count(struct phy_device *phydev)
1014{
1015 return ARRAY_SIZE(kszphy_hw_stats);
1016}
1017
1018static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
1019{
1020 int i;
1021
1022 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
1023 strlcpy(data + i * ETH_GSTRING_LEN,
1024 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
1025 }
1026}
1027
1028static u64 kszphy_get_stat(struct phy_device *phydev, int i)
1029{
1030 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
1031 struct kszphy_priv *priv = phydev->priv;
1032 int val;
1033 u64 ret;
1034
1035 val = phy_read(phydev, stat.reg);
1036 if (val < 0) {
1037 ret = U64_MAX;
1038 } else {
1039 val = val & ((1 << stat.bits) - 1);
1040 priv->stats[i] += val;
1041 ret = priv->stats[i];
1042 }
1043
1044 return ret;
1045}
1046
1047static void kszphy_get_stats(struct phy_device *phydev,
1048 struct ethtool_stats *stats, u64 *data)
1049{
1050 int i;
1051
1052 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
1053 data[i] = kszphy_get_stat(phydev, i);
1054}
1055
1056static int kszphy_suspend(struct phy_device *phydev)
1057{
1058 /* Disable PHY Interrupts */
1059 if (phy_interrupt_is_valid(phydev)) {
1060 phydev->interrupts = PHY_INTERRUPT_DISABLED;
1061 if (phydev->drv->config_intr)
1062 phydev->drv->config_intr(phydev);
1063 }
1064
1065 return genphy_suspend(phydev);
1066}
1067
1068static int kszphy_resume(struct phy_device *phydev)
1069{
1070 int ret;
1071
1072 genphy_resume(phydev);
1073
1074 /* After switching from power-down to normal mode, an internal global
1075 * reset is automatically generated. Wait a minimum of 1 ms before
1076 * read/write access to the PHY registers.
1077 */
1078 usleep_range(1000, 2000);
1079
1080 ret = kszphy_config_reset(phydev);
1081 if (ret)
1082 return ret;
1083
1084 /* Enable PHY Interrupts */
1085 if (phy_interrupt_is_valid(phydev)) {
1086 phydev->interrupts = PHY_INTERRUPT_ENABLED;
1087 if (phydev->drv->config_intr)
1088 phydev->drv->config_intr(phydev);
1089 }
1090
1091 return 0;
1092}
1093
1094static int kszphy_probe(struct phy_device *phydev)
1095{
1096 const struct kszphy_type *type = phydev->drv->driver_data;
1097 const struct device_node *np = phydev->mdio.dev.of_node;
1098 struct kszphy_priv *priv;
1099 struct clk *clk;
1100 int ret;
1101
1102 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1103 if (!priv)
1104 return -ENOMEM;
1105
1106 phydev->priv = priv;
1107
1108 priv->type = type;
1109
1110 if (type->led_mode_reg) {
1111 ret = of_property_read_u32(np, "micrel,led-mode",
1112 &priv->led_mode);
1113 if (ret)
1114 priv->led_mode = -1;
1115
1116 if (priv->led_mode > 3) {
1117 phydev_err(phydev, "invalid led mode: 0x%02x\n",
1118 priv->led_mode);
1119 priv->led_mode = -1;
1120 }
1121 } else {
1122 priv->led_mode = -1;
1123 }
1124
1125 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
1126 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
1127 if (!IS_ERR_OR_NULL(clk)) {
1128 unsigned long rate = clk_get_rate(clk);
1129 bool rmii_ref_clk_sel_25_mhz;
1130
1131 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
1132 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
1133 "micrel,rmii-reference-clock-select-25-mhz");
1134
1135 if (rate > 24500000 && rate < 25500000) {
1136 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
1137 } else if (rate > 49500000 && rate < 50500000) {
1138 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
1139 } else {
1140 phydev_err(phydev, "Clock rate out of range: %ld\n",
1141 rate);
1142 return -EINVAL;
1143 }
1144 }
1145
1146 /* Support legacy board-file configuration */
1147 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
1148 priv->rmii_ref_clk_sel = true;
1149 priv->rmii_ref_clk_sel_val = true;
1150 }
1151
1152 return 0;
1153}
1154
1155static struct phy_driver ksphy_driver[] = {
1156{
1157 .phy_id = PHY_ID_KS8737,
1158 .phy_id_mask = MICREL_PHY_ID_MASK,
1159 .name = "Micrel KS8737",
1160 /* PHY_BASIC_FEATURES */
1161 .driver_data = &ks8737_type,
1162 .config_init = kszphy_config_init,
1163 .ack_interrupt = kszphy_ack_interrupt,
1164 .config_intr = kszphy_config_intr,
1165 .suspend = genphy_suspend,
1166 .resume = genphy_resume,
1167}, {
1168 .phy_id = PHY_ID_KSZ8021,
1169 .phy_id_mask = 0x00ffffff,
1170 .name = "Micrel KSZ8021 or KSZ8031",
1171 /* PHY_BASIC_FEATURES */
1172 .driver_data = &ksz8021_type,
1173 .probe = kszphy_probe,
1174 .config_init = kszphy_config_init,
1175 .ack_interrupt = kszphy_ack_interrupt,
1176 .config_intr = kszphy_config_intr,
1177 .get_sset_count = kszphy_get_sset_count,
1178 .get_strings = kszphy_get_strings,
1179 .get_stats = kszphy_get_stats,
1180 .suspend = genphy_suspend,
1181 .resume = genphy_resume,
1182}, {
1183 .phy_id = PHY_ID_KSZ8031,
1184 .phy_id_mask = 0x00ffffff,
1185 .name = "Micrel KSZ8031",
1186 /* PHY_BASIC_FEATURES */
1187 .driver_data = &ksz8021_type,
1188 .probe = kszphy_probe,
1189 .config_init = kszphy_config_init,
1190 .ack_interrupt = kszphy_ack_interrupt,
1191 .config_intr = kszphy_config_intr,
1192 .get_sset_count = kszphy_get_sset_count,
1193 .get_strings = kszphy_get_strings,
1194 .get_stats = kszphy_get_stats,
1195 .suspend = genphy_suspend,
1196 .resume = genphy_resume,
1197}, {
1198 .phy_id = PHY_ID_KSZ8041,
1199 .phy_id_mask = MICREL_PHY_ID_MASK,
1200 .name = "Micrel KSZ8041",
1201 /* PHY_BASIC_FEATURES */
1202 .driver_data = &ksz8041_type,
1203 .probe = kszphy_probe,
1204 .config_init = ksz8041_config_init,
1205 .config_aneg = ksz8041_config_aneg,
1206 .ack_interrupt = kszphy_ack_interrupt,
1207 .config_intr = kszphy_config_intr,
1208 .get_sset_count = kszphy_get_sset_count,
1209 .get_strings = kszphy_get_strings,
1210 .get_stats = kszphy_get_stats,
1211 .suspend = genphy_suspend,
1212 .resume = genphy_resume,
1213}, {
1214 .phy_id = PHY_ID_KSZ8041RNLI,
1215 .phy_id_mask = MICREL_PHY_ID_MASK,
1216 .name = "Micrel KSZ8041RNLI",
1217 /* PHY_BASIC_FEATURES */
1218 .driver_data = &ksz8041_type,
1219 .probe = kszphy_probe,
1220 .config_init = kszphy_config_init,
1221 .ack_interrupt = kszphy_ack_interrupt,
1222 .config_intr = kszphy_config_intr,
1223 .get_sset_count = kszphy_get_sset_count,
1224 .get_strings = kszphy_get_strings,
1225 .get_stats = kszphy_get_stats,
1226 .suspend = genphy_suspend,
1227 .resume = genphy_resume,
1228}, {
1229 .name = "Micrel KSZ8051",
1230 /* PHY_BASIC_FEATURES */
1231 .driver_data = &ksz8051_type,
1232 .probe = kszphy_probe,
1233 .config_init = kszphy_config_init,
1234 .ack_interrupt = kszphy_ack_interrupt,
1235 .config_intr = kszphy_config_intr,
1236 .get_sset_count = kszphy_get_sset_count,
1237 .get_strings = kszphy_get_strings,
1238 .get_stats = kszphy_get_stats,
1239 .match_phy_device = ksz8051_match_phy_device,
1240 .suspend = genphy_suspend,
1241 .resume = genphy_resume,
1242}, {
1243 .phy_id = PHY_ID_KSZ8001,
1244 .name = "Micrel KSZ8001 or KS8721",
1245 .phy_id_mask = 0x00fffffc,
1246 /* PHY_BASIC_FEATURES */
1247 .driver_data = &ksz8041_type,
1248 .probe = kszphy_probe,
1249 .config_init = kszphy_config_init,
1250 .ack_interrupt = kszphy_ack_interrupt,
1251 .config_intr = kszphy_config_intr,
1252 .get_sset_count = kszphy_get_sset_count,
1253 .get_strings = kszphy_get_strings,
1254 .get_stats = kszphy_get_stats,
1255 .suspend = genphy_suspend,
1256 .resume = genphy_resume,
1257}, {
1258 .phy_id = PHY_ID_KSZ8081,
1259 .name = "Micrel KSZ8081 or KSZ8091",
1260 .phy_id_mask = MICREL_PHY_ID_MASK,
1261 /* PHY_BASIC_FEATURES */
1262 .driver_data = &ksz8081_type,
1263 .probe = kszphy_probe,
1264 .config_init = ksz8081_config_init,
1265 .ack_interrupt = kszphy_ack_interrupt,
1266 .config_intr = kszphy_config_intr,
1267 .get_sset_count = kszphy_get_sset_count,
1268 .get_strings = kszphy_get_strings,
1269 .get_stats = kszphy_get_stats,
1270 .suspend = kszphy_suspend,
1271 .resume = kszphy_resume,
1272}, {
1273 .phy_id = PHY_ID_KSZ8061,
1274 .name = "Micrel KSZ8061",
1275 .phy_id_mask = MICREL_PHY_ID_MASK,
1276 /* PHY_BASIC_FEATURES */
1277 .config_init = ksz8061_config_init,
1278 .ack_interrupt = kszphy_ack_interrupt,
1279 .config_intr = kszphy_config_intr,
1280 .suspend = genphy_suspend,
1281 .resume = genphy_resume,
1282}, {
1283 .phy_id = PHY_ID_KSZ9021,
1284 .phy_id_mask = 0x000ffffe,
1285 .name = "Micrel KSZ9021 Gigabit PHY",
1286 /* PHY_GBIT_FEATURES */
1287 .driver_data = &ksz9021_type,
1288 .probe = kszphy_probe,
1289 .get_features = ksz9031_get_features,
1290 .config_init = ksz9021_config_init,
1291 .ack_interrupt = kszphy_ack_interrupt,
1292 .config_intr = kszphy_config_intr,
1293 .get_sset_count = kszphy_get_sset_count,
1294 .get_strings = kszphy_get_strings,
1295 .get_stats = kszphy_get_stats,
1296 .suspend = genphy_suspend,
1297 .resume = genphy_resume,
1298 .read_mmd = genphy_read_mmd_unsupported,
1299 .write_mmd = genphy_write_mmd_unsupported,
1300}, {
1301 .phy_id = PHY_ID_KSZ9031,
1302 .phy_id_mask = MICREL_PHY_ID_MASK,
1303 .name = "Micrel KSZ9031 Gigabit PHY",
1304 .driver_data = &ksz9021_type,
1305 .probe = kszphy_probe,
1306 .get_features = ksz9031_get_features,
1307 .config_init = ksz9031_config_init,
1308 .soft_reset = genphy_soft_reset,
1309 .read_status = ksz9031_read_status,
1310 .ack_interrupt = kszphy_ack_interrupt,
1311 .config_intr = kszphy_config_intr,
1312 .get_sset_count = kszphy_get_sset_count,
1313 .get_strings = kszphy_get_strings,
1314 .get_stats = kszphy_get_stats,
1315 .suspend = genphy_suspend,
1316 .resume = kszphy_resume,
1317}, {
1318 .phy_id = PHY_ID_KSZ9131,
1319 .phy_id_mask = MICREL_PHY_ID_MASK,
1320 .name = "Microchip KSZ9131 Gigabit PHY",
1321 /* PHY_GBIT_FEATURES */
1322 .driver_data = &ksz9021_type,
1323 .probe = kszphy_probe,
1324 .config_init = ksz9131_config_init,
1325 .read_status = genphy_read_status,
1326 .ack_interrupt = kszphy_ack_interrupt,
1327 .config_intr = kszphy_config_intr,
1328 .get_sset_count = kszphy_get_sset_count,
1329 .get_strings = kszphy_get_strings,
1330 .get_stats = kszphy_get_stats,
1331 .suspend = genphy_suspend,
1332 .resume = kszphy_resume,
1333}, {
1334 .phy_id = PHY_ID_KSZ8873MLL,
1335 .phy_id_mask = MICREL_PHY_ID_MASK,
1336 .name = "Micrel KSZ8873MLL Switch",
1337 /* PHY_BASIC_FEATURES */
1338 .config_init = kszphy_config_init,
1339 .config_aneg = ksz8873mll_config_aneg,
1340 .read_status = ksz8873mll_read_status,
1341 .suspend = genphy_suspend,
1342 .resume = genphy_resume,
1343}, {
1344 .phy_id = PHY_ID_KSZ886X,
1345 .phy_id_mask = MICREL_PHY_ID_MASK,
1346 .name = "Micrel KSZ886X Switch",
1347 /* PHY_BASIC_FEATURES */
1348 .config_init = kszphy_config_init,
1349 .suspend = genphy_suspend,
1350 .resume = genphy_resume,
1351}, {
1352 .name = "Micrel KSZ87XX Switch",
1353 /* PHY_BASIC_FEATURES */
1354 .config_init = kszphy_config_init,
1355 .config_aneg = ksz8873mll_config_aneg,
1356 .read_status = ksz8873mll_read_status,
1357 .match_phy_device = ksz8795_match_phy_device,
1358 .suspend = genphy_suspend,
1359 .resume = genphy_resume,
1360}, {
1361 .phy_id = PHY_ID_KSZ9477,
1362 .phy_id_mask = MICREL_PHY_ID_MASK,
1363 .name = "Microchip KSZ9477",
1364 /* PHY_GBIT_FEATURES */
1365 .config_init = kszphy_config_init,
1366 .suspend = genphy_suspend,
1367 .resume = genphy_resume,
1368} };
1369
1370module_phy_driver(ksphy_driver);
1371
1372MODULE_DESCRIPTION("Micrel PHY driver");
1373MODULE_AUTHOR("David J. Choi");
1374MODULE_LICENSE("GPL");
1375
1376static struct mdio_device_id __maybe_unused micrel_tbl[] = {
1377 { PHY_ID_KSZ9021, 0x000ffffe },
1378 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
1379 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
1380 { PHY_ID_KSZ8001, 0x00fffffc },
1381 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
1382 { PHY_ID_KSZ8021, 0x00ffffff },
1383 { PHY_ID_KSZ8031, 0x00ffffff },
1384 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
1385 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
1386 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
1387 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1388 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1389 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
1390 { }
1391};
1392
1393MODULE_DEVICE_TABLE(mdio, micrel_tbl);