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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#include <linux/pci.h>
5#include <linux/delay.h>
6#include <linux/iopoll.h>
7#include <linux/sched.h>
8
9#include "ixgbe.h"
10#include "ixgbe_phy.h"
11
12static void ixgbe_i2c_start(struct ixgbe_hw *hw);
13static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
14static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
15static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
16static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
17static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
18static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
19static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
20static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
21static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
22static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
23static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
24static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
25static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
26static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
27
28/**
29 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
30 * @hw: pointer to the hardware structure
31 * @byte: byte to send
32 *
33 * Returns an error code on error.
34 **/
35static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
36{
37 s32 status;
38
39 status = ixgbe_clock_out_i2c_byte(hw, byte);
40 if (status)
41 return status;
42 return ixgbe_get_i2c_ack(hw);
43}
44
45/**
46 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
47 * @hw: pointer to the hardware structure
48 * @byte: pointer to a u8 to receive the byte
49 *
50 * Returns an error code on error.
51 **/
52static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
53{
54 s32 status;
55
56 status = ixgbe_clock_in_i2c_byte(hw, byte);
57 if (status)
58 return status;
59 /* ACK */
60 return ixgbe_clock_out_i2c_bit(hw, false);
61}
62
63/**
64 * ixgbe_ones_comp_byte_add - Perform one's complement addition
65 * @add1: addend 1
66 * @add2: addend 2
67 *
68 * Returns one's complement 8-bit sum.
69 **/
70static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
71{
72 u16 sum = add1 + add2;
73
74 sum = (sum & 0xFF) + (sum >> 8);
75 return sum & 0xFF;
76}
77
78/**
79 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
80 * @hw: pointer to the hardware structure
81 * @addr: I2C bus address to read from
82 * @reg: I2C device register to read from
83 * @val: pointer to location to receive read value
84 * @lock: true if to take and release semaphore
85 *
86 * Returns an error code on error.
87 */
88s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
89 u16 reg, u16 *val, bool lock)
90{
91 u32 swfw_mask = hw->phy.phy_semaphore_mask;
92 int max_retry = 3;
93 int retry = 0;
94 u8 csum_byte;
95 u8 high_bits;
96 u8 low_bits;
97 u8 reg_high;
98 u8 csum;
99
100 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
101 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
102 csum = ~csum;
103 do {
104 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
105 return IXGBE_ERR_SWFW_SYNC;
106 ixgbe_i2c_start(hw);
107 /* Device Address and write indication */
108 if (ixgbe_out_i2c_byte_ack(hw, addr))
109 goto fail;
110 /* Write bits 14:8 */
111 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
112 goto fail;
113 /* Write bits 7:0 */
114 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
115 goto fail;
116 /* Write csum */
117 if (ixgbe_out_i2c_byte_ack(hw, csum))
118 goto fail;
119 /* Re-start condition */
120 ixgbe_i2c_start(hw);
121 /* Device Address and read indication */
122 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
123 goto fail;
124 /* Get upper bits */
125 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
126 goto fail;
127 /* Get low bits */
128 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
129 goto fail;
130 /* Get csum */
131 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
132 goto fail;
133 /* NACK */
134 if (ixgbe_clock_out_i2c_bit(hw, false))
135 goto fail;
136 ixgbe_i2c_stop(hw);
137 if (lock)
138 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
139 *val = (high_bits << 8) | low_bits;
140 return 0;
141
142fail:
143 ixgbe_i2c_bus_clear(hw);
144 if (lock)
145 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
146 retry++;
147 if (retry < max_retry)
148 hw_dbg(hw, "I2C byte read combined error - Retry.\n");
149 else
150 hw_dbg(hw, "I2C byte read combined error.\n");
151 } while (retry < max_retry);
152
153 return IXGBE_ERR_I2C;
154}
155
156/**
157 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
158 * @hw: pointer to the hardware structure
159 * @addr: I2C bus address to write to
160 * @reg: I2C device register to write to
161 * @val: value to write
162 * @lock: true if to take and release semaphore
163 *
164 * Returns an error code on error.
165 */
166s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
167 u16 reg, u16 val, bool lock)
168{
169 u32 swfw_mask = hw->phy.phy_semaphore_mask;
170 int max_retry = 1;
171 int retry = 0;
172 u8 reg_high;
173 u8 csum;
174
175 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
176 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
177 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
178 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
179 csum = ~csum;
180 do {
181 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
182 return IXGBE_ERR_SWFW_SYNC;
183 ixgbe_i2c_start(hw);
184 /* Device Address and write indication */
185 if (ixgbe_out_i2c_byte_ack(hw, addr))
186 goto fail;
187 /* Write bits 14:8 */
188 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
189 goto fail;
190 /* Write bits 7:0 */
191 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
192 goto fail;
193 /* Write data 15:8 */
194 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
195 goto fail;
196 /* Write data 7:0 */
197 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
198 goto fail;
199 /* Write csum */
200 if (ixgbe_out_i2c_byte_ack(hw, csum))
201 goto fail;
202 ixgbe_i2c_stop(hw);
203 if (lock)
204 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
205 return 0;
206
207fail:
208 ixgbe_i2c_bus_clear(hw);
209 if (lock)
210 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
211 retry++;
212 if (retry < max_retry)
213 hw_dbg(hw, "I2C byte write combined error - Retry.\n");
214 else
215 hw_dbg(hw, "I2C byte write combined error.\n");
216 } while (retry < max_retry);
217
218 return IXGBE_ERR_I2C;
219}
220
221/**
222 * ixgbe_probe_phy - Probe a single address for a PHY
223 * @hw: pointer to hardware structure
224 * @phy_addr: PHY address to probe
225 *
226 * Returns true if PHY found
227 **/
228static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
229{
230 u16 ext_ability = 0;
231
232 hw->phy.mdio.prtad = phy_addr;
233 if (mdio45_probe(&hw->phy.mdio, phy_addr) != 0)
234 return false;
235
236 if (ixgbe_get_phy_id(hw))
237 return false;
238
239 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
240
241 if (hw->phy.type == ixgbe_phy_unknown) {
242 hw->phy.ops.read_reg(hw,
243 MDIO_PMA_EXTABLE,
244 MDIO_MMD_PMAPMD,
245 &ext_ability);
246 if (ext_ability &
247 (MDIO_PMA_EXTABLE_10GBT |
248 MDIO_PMA_EXTABLE_1000BT))
249 hw->phy.type = ixgbe_phy_cu_unknown;
250 else
251 hw->phy.type = ixgbe_phy_generic;
252 }
253
254 return true;
255}
256
257/**
258 * ixgbe_identify_phy_generic - Get physical layer module
259 * @hw: pointer to hardware structure
260 *
261 * Determines the physical layer module found on the current adapter.
262 **/
263s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
264{
265 u32 phy_addr;
266 u32 status = IXGBE_ERR_PHY_ADDR_INVALID;
267
268 if (!hw->phy.phy_semaphore_mask) {
269 if (hw->bus.lan_id)
270 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
271 else
272 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
273 }
274
275 if (hw->phy.type != ixgbe_phy_unknown)
276 return 0;
277
278 if (hw->phy.nw_mng_if_sel) {
279 phy_addr = (hw->phy.nw_mng_if_sel &
280 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
281 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
282 if (ixgbe_probe_phy(hw, phy_addr))
283 return 0;
284 else
285 return IXGBE_ERR_PHY_ADDR_INVALID;
286 }
287
288 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
289 if (ixgbe_probe_phy(hw, phy_addr)) {
290 status = 0;
291 break;
292 }
293 }
294
295 /* Certain media types do not have a phy so an address will not
296 * be found and the code will take this path. Caller has to
297 * decide if it is an error or not.
298 */
299 if (status)
300 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
301
302 return status;
303}
304
305/**
306 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
307 * @hw: pointer to the hardware structure
308 *
309 * This function checks the MMNGC.MNG_VETO bit to see if there are
310 * any constraints on link from manageability. For MAC's that don't
311 * have this bit just return false since the link can not be blocked
312 * via this method.
313 **/
314bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
315{
316 u32 mmngc;
317
318 /* If we don't have this bit, it can't be blocking */
319 if (hw->mac.type == ixgbe_mac_82598EB)
320 return false;
321
322 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
323 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
324 hw_dbg(hw, "MNG_VETO bit detected.\n");
325 return true;
326 }
327
328 return false;
329}
330
331/**
332 * ixgbe_get_phy_id - Get the phy type
333 * @hw: pointer to hardware structure
334 *
335 **/
336static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
337{
338 s32 status;
339 u16 phy_id_high = 0;
340 u16 phy_id_low = 0;
341
342 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
343 &phy_id_high);
344
345 if (!status) {
346 hw->phy.id = (u32)(phy_id_high << 16);
347 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
348 &phy_id_low);
349 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
350 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
351 }
352 return status;
353}
354
355/**
356 * ixgbe_get_phy_type_from_id - Get the phy type
357 * @phy_id: hardware phy id
358 *
359 **/
360static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
361{
362 enum ixgbe_phy_type phy_type;
363
364 switch (phy_id) {
365 case TN1010_PHY_ID:
366 phy_type = ixgbe_phy_tn;
367 break;
368 case X550_PHY_ID2:
369 case X550_PHY_ID3:
370 case X540_PHY_ID:
371 phy_type = ixgbe_phy_aq;
372 break;
373 case QT2022_PHY_ID:
374 phy_type = ixgbe_phy_qt;
375 break;
376 case ATH_PHY_ID:
377 phy_type = ixgbe_phy_nl;
378 break;
379 case X557_PHY_ID:
380 case X557_PHY_ID2:
381 phy_type = ixgbe_phy_x550em_ext_t;
382 break;
383 default:
384 phy_type = ixgbe_phy_unknown;
385 break;
386 }
387
388 return phy_type;
389}
390
391/**
392 * ixgbe_reset_phy_generic - Performs a PHY reset
393 * @hw: pointer to hardware structure
394 **/
395s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
396{
397 u32 i;
398 u16 ctrl = 0;
399 s32 status = 0;
400
401 if (hw->phy.type == ixgbe_phy_unknown)
402 status = ixgbe_identify_phy_generic(hw);
403
404 if (status != 0 || hw->phy.type == ixgbe_phy_none)
405 return status;
406
407 /* Don't reset PHY if it's shut down due to overtemp. */
408 if (!hw->phy.reset_if_overtemp &&
409 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
410 return 0;
411
412 /* Blocked by MNG FW so bail */
413 if (ixgbe_check_reset_blocked(hw))
414 return 0;
415
416 /*
417 * Perform soft PHY reset to the PHY_XS.
418 * This will cause a soft reset to the PHY
419 */
420 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
421 MDIO_MMD_PHYXS,
422 MDIO_CTRL1_RESET);
423
424 /*
425 * Poll for reset bit to self-clear indicating reset is complete.
426 * Some PHYs could take up to 3 seconds to complete and need about
427 * 1.7 usec delay after the reset is complete.
428 */
429 for (i = 0; i < 30; i++) {
430 msleep(100);
431 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
432 status = hw->phy.ops.read_reg(hw,
433 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
434 MDIO_MMD_PMAPMD, &ctrl);
435 if (status)
436 return status;
437
438 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
439 udelay(2);
440 break;
441 }
442 } else {
443 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1,
444 MDIO_MMD_PHYXS, &ctrl);
445 if (status)
446 return status;
447
448 if (!(ctrl & MDIO_CTRL1_RESET)) {
449 udelay(2);
450 break;
451 }
452 }
453 }
454
455 if (ctrl & MDIO_CTRL1_RESET) {
456 hw_dbg(hw, "PHY reset polling failed to complete.\n");
457 return IXGBE_ERR_RESET_FAILED;
458 }
459
460 return 0;
461}
462
463/**
464 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
465 * the SWFW lock
466 * @hw: pointer to hardware structure
467 * @reg_addr: 32 bit address of PHY register to read
468 * @device_type: 5 bit device type
469 * @phy_data: Pointer to read data from PHY register
470 **/
471s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
472 u16 *phy_data)
473{
474 u32 i, data, command;
475
476 /* Setup and write the address cycle command */
477 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
478 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
479 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
480 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
481
482 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
483
484 /* Check every 10 usec to see if the address cycle completed.
485 * The MDI Command bit will clear when the operation is
486 * complete
487 */
488 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
489 udelay(10);
490
491 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
492 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
493 break;
494 }
495
496
497 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
498 hw_dbg(hw, "PHY address command did not complete.\n");
499 return IXGBE_ERR_PHY;
500 }
501
502 /* Address cycle complete, setup and write the read
503 * command
504 */
505 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
506 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
507 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
508 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
509
510 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
511
512 /* Check every 10 usec to see if the address cycle
513 * completed. The MDI Command bit will clear when the
514 * operation is complete
515 */
516 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
517 udelay(10);
518
519 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
520 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
521 break;
522 }
523
524 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
525 hw_dbg(hw, "PHY read command didn't complete\n");
526 return IXGBE_ERR_PHY;
527 }
528
529 /* Read operation is complete. Get the data
530 * from MSRWD
531 */
532 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
533 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
534 *phy_data = (u16)(data);
535
536 return 0;
537}
538
539/**
540 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
541 * using the SWFW lock - this function is needed in most cases
542 * @hw: pointer to hardware structure
543 * @reg_addr: 32 bit address of PHY register to read
544 * @device_type: 5 bit device type
545 * @phy_data: Pointer to read data from PHY register
546 **/
547s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
548 u32 device_type, u16 *phy_data)
549{
550 s32 status;
551 u32 gssr = hw->phy.phy_semaphore_mask;
552
553 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
554 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
555 phy_data);
556 hw->mac.ops.release_swfw_sync(hw, gssr);
557 } else {
558 return IXGBE_ERR_SWFW_SYNC;
559 }
560
561 return status;
562}
563
564/**
565 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
566 * without SWFW lock
567 * @hw: pointer to hardware structure
568 * @reg_addr: 32 bit PHY register to write
569 * @device_type: 5 bit device type
570 * @phy_data: Data to write to the PHY register
571 **/
572s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
573 u32 device_type, u16 phy_data)
574{
575 u32 i, command;
576
577 /* Put the data in the MDI single read and write data register*/
578 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
579
580 /* Setup and write the address cycle command */
581 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
582 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
583 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
584 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
585
586 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
587
588 /*
589 * Check every 10 usec to see if the address cycle completed.
590 * The MDI Command bit will clear when the operation is
591 * complete
592 */
593 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
594 udelay(10);
595
596 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
597 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
598 break;
599 }
600
601 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
602 hw_dbg(hw, "PHY address cmd didn't complete\n");
603 return IXGBE_ERR_PHY;
604 }
605
606 /*
607 * Address cycle complete, setup and write the write
608 * command
609 */
610 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
611 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
612 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
613 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
614
615 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
616
617 /* Check every 10 usec to see if the address cycle
618 * completed. The MDI Command bit will clear when the
619 * operation is complete
620 */
621 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
622 udelay(10);
623
624 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
625 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
626 break;
627 }
628
629 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
630 hw_dbg(hw, "PHY write cmd didn't complete\n");
631 return IXGBE_ERR_PHY;
632 }
633
634 return 0;
635}
636
637/**
638 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
639 * using SWFW lock- this function is needed in most cases
640 * @hw: pointer to hardware structure
641 * @reg_addr: 32 bit PHY register to write
642 * @device_type: 5 bit device type
643 * @phy_data: Data to write to the PHY register
644 **/
645s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
646 u32 device_type, u16 phy_data)
647{
648 s32 status;
649 u32 gssr = hw->phy.phy_semaphore_mask;
650
651 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
652 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
653 phy_data);
654 hw->mac.ops.release_swfw_sync(hw, gssr);
655 } else {
656 return IXGBE_ERR_SWFW_SYNC;
657 }
658
659 return status;
660}
661
662#define IXGBE_HW_READ_REG(addr) IXGBE_READ_REG(hw, addr)
663
664/**
665 * ixgbe_msca_cmd - Write the command register and poll for completion/timeout
666 * @hw: pointer to hardware structure
667 * @cmd: command register value to write
668 **/
669static s32 ixgbe_msca_cmd(struct ixgbe_hw *hw, u32 cmd)
670{
671 IXGBE_WRITE_REG(hw, IXGBE_MSCA, cmd);
672
673 return readx_poll_timeout(IXGBE_HW_READ_REG, IXGBE_MSCA, cmd,
674 !(cmd & IXGBE_MSCA_MDI_COMMAND), 10,
675 10 * IXGBE_MDIO_COMMAND_TIMEOUT);
676}
677
678/**
679 * ixgbe_mii_bus_read_generic - Read a clause 22/45 register with gssr flags
680 * @hw: pointer to hardware structure
681 * @addr: address
682 * @regnum: register number
683 * @gssr: semaphore flags to acquire
684 **/
685static s32 ixgbe_mii_bus_read_generic(struct ixgbe_hw *hw, int addr,
686 int regnum, u32 gssr)
687{
688 u32 hwaddr, cmd;
689 s32 data;
690
691 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
692 return -EBUSY;
693
694 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
695 if (regnum & MII_ADDR_C45) {
696 hwaddr |= regnum & GENMASK(21, 0);
697 cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
698 } else {
699 hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
700 cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL |
701 IXGBE_MSCA_READ_AUTOINC | IXGBE_MSCA_MDI_COMMAND;
702 }
703
704 data = ixgbe_msca_cmd(hw, cmd);
705 if (data < 0)
706 goto mii_bus_read_done;
707
708 /* For a clause 45 access the address cycle just completed, we still
709 * need to do the read command, otherwise just get the data
710 */
711 if (!(regnum & MII_ADDR_C45))
712 goto do_mii_bus_read;
713
714 cmd = hwaddr | IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND;
715 data = ixgbe_msca_cmd(hw, cmd);
716 if (data < 0)
717 goto mii_bus_read_done;
718
719do_mii_bus_read:
720 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
721 data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0);
722
723mii_bus_read_done:
724 hw->mac.ops.release_swfw_sync(hw, gssr);
725 return data;
726}
727
728/**
729 * ixgbe_mii_bus_write_generic - Write a clause 22/45 register with gssr flags
730 * @hw: pointer to hardware structure
731 * @addr: address
732 * @regnum: register number
733 * @val: value to write
734 * @gssr: semaphore flags to acquire
735 **/
736static s32 ixgbe_mii_bus_write_generic(struct ixgbe_hw *hw, int addr,
737 int regnum, u16 val, u32 gssr)
738{
739 u32 hwaddr, cmd;
740 s32 err;
741
742 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
743 return -EBUSY;
744
745 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val);
746
747 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
748 if (regnum & MII_ADDR_C45) {
749 hwaddr |= regnum & GENMASK(21, 0);
750 cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
751 } else {
752 hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
753 cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
754 IXGBE_MSCA_MDI_COMMAND;
755 }
756
757 /* For clause 45 this is an address cycle, for clause 22 this is the
758 * entire transaction
759 */
760 err = ixgbe_msca_cmd(hw, cmd);
761 if (err < 0 || !(regnum & MII_ADDR_C45))
762 goto mii_bus_write_done;
763
764 cmd = hwaddr | IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND;
765 err = ixgbe_msca_cmd(hw, cmd);
766
767mii_bus_write_done:
768 hw->mac.ops.release_swfw_sync(hw, gssr);
769 return err;
770}
771
772/**
773 * ixgbe_mii_bus_read - Read a clause 22/45 register
774 * @hw: pointer to hardware structure
775 * @addr: address
776 * @regnum: register number
777 **/
778static s32 ixgbe_mii_bus_read(struct mii_bus *bus, int addr, int regnum)
779{
780 struct ixgbe_adapter *adapter = bus->priv;
781 struct ixgbe_hw *hw = &adapter->hw;
782 u32 gssr = hw->phy.phy_semaphore_mask;
783
784 return ixgbe_mii_bus_read_generic(hw, addr, regnum, gssr);
785}
786
787/**
788 * ixgbe_mii_bus_write - Write a clause 22/45 register
789 * @hw: pointer to hardware structure
790 * @addr: address
791 * @regnum: register number
792 * @val: value to write
793 **/
794static s32 ixgbe_mii_bus_write(struct mii_bus *bus, int addr, int regnum,
795 u16 val)
796{
797 struct ixgbe_adapter *adapter = bus->priv;
798 struct ixgbe_hw *hw = &adapter->hw;
799 u32 gssr = hw->phy.phy_semaphore_mask;
800
801 return ixgbe_mii_bus_write_generic(hw, addr, regnum, val, gssr);
802}
803
804/**
805 * ixgbe_x550em_a_mii_bus_read - Read a clause 22/45 register on x550em_a
806 * @hw: pointer to hardware structure
807 * @addr: address
808 * @regnum: register number
809 **/
810static s32 ixgbe_x550em_a_mii_bus_read(struct mii_bus *bus, int addr,
811 int regnum)
812{
813 struct ixgbe_adapter *adapter = bus->priv;
814 struct ixgbe_hw *hw = &adapter->hw;
815 u32 gssr = hw->phy.phy_semaphore_mask;
816
817 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
818 return ixgbe_mii_bus_read_generic(hw, addr, regnum, gssr);
819}
820
821/**
822 * ixgbe_x550em_a_mii_bus_write - Write a clause 22/45 register on x550em_a
823 * @hw: pointer to hardware structure
824 * @addr: address
825 * @regnum: register number
826 * @val: value to write
827 **/
828static s32 ixgbe_x550em_a_mii_bus_write(struct mii_bus *bus, int addr,
829 int regnum, u16 val)
830{
831 struct ixgbe_adapter *adapter = bus->priv;
832 struct ixgbe_hw *hw = &adapter->hw;
833 u32 gssr = hw->phy.phy_semaphore_mask;
834
835 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
836 return ixgbe_mii_bus_write_generic(hw, addr, regnum, val, gssr);
837}
838
839/**
840 * ixgbe_get_first_secondary_devfn - get first device downstream of root port
841 * @devfn: PCI_DEVFN of root port on domain 0, bus 0
842 *
843 * Returns pci_dev pointer to PCI_DEVFN(0, 0) on subordinate side of root
844 * on domain 0, bus 0, devfn = 'devfn'
845 **/
846static struct pci_dev *ixgbe_get_first_secondary_devfn(unsigned int devfn)
847{
848 struct pci_dev *rp_pdev;
849 int bus;
850
851 rp_pdev = pci_get_domain_bus_and_slot(0, 0, devfn);
852 if (rp_pdev && rp_pdev->subordinate) {
853 bus = rp_pdev->subordinate->number;
854 return pci_get_domain_bus_and_slot(0, bus, 0);
855 }
856
857 return NULL;
858}
859
860/**
861 * ixgbe_x550em_a_has_mii - is this the first ixgbe x550em_a PCI function?
862 * @hw: pointer to hardware structure
863 *
864 * Returns true if hw points to lowest numbered PCI B:D.F x550_em_a device in
865 * the SoC. There are up to 4 MACs sharing a single MDIO bus on the x550em_a,
866 * but we only want to register one MDIO bus.
867 **/
868static bool ixgbe_x550em_a_has_mii(struct ixgbe_hw *hw)
869{
870 struct ixgbe_adapter *adapter = hw->back;
871 struct pci_dev *pdev = adapter->pdev;
872 struct pci_dev *func0_pdev;
873
874 /* For the C3000 family of SoCs (x550em_a) the internal ixgbe devices
875 * are always downstream of root ports @ 0000:00:16.0 & 0000:00:17.0
876 * It's not valid for function 0 to be disabled and function 1 is up,
877 * so the lowest numbered ixgbe dev will be device 0 function 0 on one
878 * of those two root ports
879 */
880 func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x16, 0));
881 if (func0_pdev) {
882 if (func0_pdev == pdev)
883 return true;
884 else
885 return false;
886 }
887 func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x17, 0));
888 if (func0_pdev == pdev)
889 return true;
890
891 return false;
892}
893
894/**
895 * ixgbe_mii_bus_init - mii_bus structure setup
896 * @hw: pointer to hardware structure
897 *
898 * Returns 0 on success, negative on failure
899 *
900 * ixgbe_mii_bus_init initializes a mii_bus structure in adapter
901 **/
902s32 ixgbe_mii_bus_init(struct ixgbe_hw *hw)
903{
904 struct ixgbe_adapter *adapter = hw->back;
905 struct pci_dev *pdev = adapter->pdev;
906 struct device *dev = &adapter->netdev->dev;
907 struct mii_bus *bus;
908
909 bus = devm_mdiobus_alloc(dev);
910 if (!bus)
911 return -ENOMEM;
912
913 switch (hw->device_id) {
914 /* C3000 SoCs */
915 case IXGBE_DEV_ID_X550EM_A_KR:
916 case IXGBE_DEV_ID_X550EM_A_KR_L:
917 case IXGBE_DEV_ID_X550EM_A_SFP_N:
918 case IXGBE_DEV_ID_X550EM_A_SGMII:
919 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
920 case IXGBE_DEV_ID_X550EM_A_10G_T:
921 case IXGBE_DEV_ID_X550EM_A_SFP:
922 case IXGBE_DEV_ID_X550EM_A_1G_T:
923 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
924 if (!ixgbe_x550em_a_has_mii(hw))
925 return -ENODEV;
926 bus->read = &ixgbe_x550em_a_mii_bus_read;
927 bus->write = &ixgbe_x550em_a_mii_bus_write;
928 break;
929 default:
930 bus->read = &ixgbe_mii_bus_read;
931 bus->write = &ixgbe_mii_bus_write;
932 break;
933 }
934
935 /* Use the position of the device in the PCI hierarchy as the id */
936 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mdio-%s", ixgbe_driver_name,
937 pci_name(pdev));
938
939 bus->name = "ixgbe-mdio";
940 bus->priv = adapter;
941 bus->parent = dev;
942 bus->phy_mask = GENMASK(31, 0);
943
944 /* Support clause 22/45 natively. ixgbe_probe() sets MDIO_EMULATE_C22
945 * unfortunately that causes some clause 22 frames to be sent with
946 * clause 45 addressing. We don't want that.
947 */
948 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_SUPPORTS_C22;
949
950 adapter->mii_bus = bus;
951 return mdiobus_register(bus);
952}
953
954/**
955 * ixgbe_setup_phy_link_generic - Set and restart autoneg
956 * @hw: pointer to hardware structure
957 *
958 * Restart autonegotiation and PHY and waits for completion.
959 **/
960s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
961{
962 s32 status = 0;
963 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
964 bool autoneg = false;
965 ixgbe_link_speed speed;
966
967 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
968
969 /* Set or unset auto-negotiation 10G advertisement */
970 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg);
971
972 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
973 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
974 (speed & IXGBE_LINK_SPEED_10GB_FULL))
975 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
976
977 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg);
978
979 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
980 MDIO_MMD_AN, &autoneg_reg);
981
982 if (hw->mac.type == ixgbe_mac_X550) {
983 /* Set or unset auto-negotiation 5G advertisement */
984 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
985 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
986 (speed & IXGBE_LINK_SPEED_5GB_FULL))
987 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
988
989 /* Set or unset auto-negotiation 2.5G advertisement */
990 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
991 if ((hw->phy.autoneg_advertised &
992 IXGBE_LINK_SPEED_2_5GB_FULL) &&
993 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
994 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
995 }
996
997 /* Set or unset auto-negotiation 1G advertisement */
998 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
999 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
1000 (speed & IXGBE_LINK_SPEED_1GB_FULL))
1001 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
1002
1003 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1004 MDIO_MMD_AN, autoneg_reg);
1005
1006 /* Set or unset auto-negotiation 100M advertisement */
1007 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
1008
1009 autoneg_reg &= ~(ADVERTISE_100FULL | ADVERTISE_100HALF);
1010 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
1011 (speed & IXGBE_LINK_SPEED_100_FULL))
1012 autoneg_reg |= ADVERTISE_100FULL;
1013
1014 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
1015
1016 /* Blocked by MNG FW so don't reset PHY */
1017 if (ixgbe_check_reset_blocked(hw))
1018 return 0;
1019
1020 /* Restart PHY autonegotiation and wait for completion */
1021 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1022 MDIO_MMD_AN, &autoneg_reg);
1023
1024 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1025
1026 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1027 MDIO_MMD_AN, autoneg_reg);
1028
1029 return status;
1030}
1031
1032/**
1033 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
1034 * @hw: pointer to hardware structure
1035 * @speed: new link speed
1036 * @autoneg_wait_to_complete: unused
1037 **/
1038s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
1039 ixgbe_link_speed speed,
1040 bool autoneg_wait_to_complete)
1041{
1042 /* Clear autoneg_advertised and set new values based on input link
1043 * speed.
1044 */
1045 hw->phy.autoneg_advertised = 0;
1046
1047 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1048 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
1049
1050 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
1051 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
1052
1053 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
1054 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
1055
1056 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1057 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
1058
1059 if (speed & IXGBE_LINK_SPEED_100_FULL)
1060 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
1061
1062 if (speed & IXGBE_LINK_SPEED_10_FULL)
1063 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
1064
1065 /* Setup link based on the new speed settings */
1066 if (hw->phy.ops.setup_link)
1067 hw->phy.ops.setup_link(hw);
1068
1069 return 0;
1070}
1071
1072/**
1073 * ixgbe_get_copper_speeds_supported - Get copper link speed from phy
1074 * @hw: pointer to hardware structure
1075 *
1076 * Determines the supported link capabilities by reading the PHY auto
1077 * negotiation register.
1078 */
1079static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
1080{
1081 u16 speed_ability;
1082 s32 status;
1083
1084 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
1085 &speed_ability);
1086 if (status)
1087 return status;
1088
1089 if (speed_ability & MDIO_SPEED_10G)
1090 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
1091 if (speed_ability & MDIO_PMA_SPEED_1000)
1092 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
1093 if (speed_ability & MDIO_PMA_SPEED_100)
1094 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
1095
1096 switch (hw->mac.type) {
1097 case ixgbe_mac_X550:
1098 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
1099 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
1100 break;
1101 case ixgbe_mac_X550EM_x:
1102 case ixgbe_mac_x550em_a:
1103 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
1104 break;
1105 default:
1106 break;
1107 }
1108
1109 return 0;
1110}
1111
1112/**
1113 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
1114 * @hw: pointer to hardware structure
1115 * @speed: pointer to link speed
1116 * @autoneg: boolean auto-negotiation value
1117 */
1118s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
1119 ixgbe_link_speed *speed,
1120 bool *autoneg)
1121{
1122 s32 status = 0;
1123
1124 *autoneg = true;
1125 if (!hw->phy.speeds_supported)
1126 status = ixgbe_get_copper_speeds_supported(hw);
1127
1128 *speed = hw->phy.speeds_supported;
1129 return status;
1130}
1131
1132/**
1133 * ixgbe_check_phy_link_tnx - Determine link and speed status
1134 * @hw: pointer to hardware structure
1135 * @speed: link speed
1136 * @link_up: status of link
1137 *
1138 * Reads the VS1 register to determine if link is up and the current speed for
1139 * the PHY.
1140 **/
1141s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1142 bool *link_up)
1143{
1144 s32 status;
1145 u32 time_out;
1146 u32 max_time_out = 10;
1147 u16 phy_link = 0;
1148 u16 phy_speed = 0;
1149 u16 phy_data = 0;
1150
1151 /* Initialize speed and link to default case */
1152 *link_up = false;
1153 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1154
1155 /*
1156 * Check current speed and link status of the PHY register.
1157 * This is a vendor specific register and may have to
1158 * be changed for other copper PHYs.
1159 */
1160 for (time_out = 0; time_out < max_time_out; time_out++) {
1161 udelay(10);
1162 status = hw->phy.ops.read_reg(hw,
1163 MDIO_STAT1,
1164 MDIO_MMD_VEND1,
1165 &phy_data);
1166 phy_link = phy_data &
1167 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1168 phy_speed = phy_data &
1169 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1170 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1171 *link_up = true;
1172 if (phy_speed ==
1173 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1174 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1175 break;
1176 }
1177 }
1178
1179 return status;
1180}
1181
1182/**
1183 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
1184 * @hw: pointer to hardware structure
1185 *
1186 * Restart autonegotiation and PHY and waits for completion.
1187 * This function always returns success, this is nessary since
1188 * it is called via a function pointer that could call other
1189 * functions that could return an error.
1190 **/
1191s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1192{
1193 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1194 bool autoneg = false;
1195 ixgbe_link_speed speed;
1196
1197 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1198
1199 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1200 /* Set or unset auto-negotiation 10G advertisement */
1201 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
1202 MDIO_MMD_AN,
1203 &autoneg_reg);
1204
1205 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
1206 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1207 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
1208
1209 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
1210 MDIO_MMD_AN,
1211 autoneg_reg);
1212 }
1213
1214 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1215 /* Set or unset auto-negotiation 1G advertisement */
1216 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1217 MDIO_MMD_AN,
1218 &autoneg_reg);
1219
1220 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1221 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1222 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1223
1224 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1225 MDIO_MMD_AN,
1226 autoneg_reg);
1227 }
1228
1229 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1230 /* Set or unset auto-negotiation 100M advertisement */
1231 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
1232 MDIO_MMD_AN,
1233 &autoneg_reg);
1234
1235 autoneg_reg &= ~(ADVERTISE_100FULL |
1236 ADVERTISE_100HALF);
1237 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1238 autoneg_reg |= ADVERTISE_100FULL;
1239
1240 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
1241 MDIO_MMD_AN,
1242 autoneg_reg);
1243 }
1244
1245 /* Blocked by MNG FW so don't reset PHY */
1246 if (ixgbe_check_reset_blocked(hw))
1247 return 0;
1248
1249 /* Restart PHY autonegotiation and wait for completion */
1250 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1251 MDIO_MMD_AN, &autoneg_reg);
1252
1253 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1254
1255 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1256 MDIO_MMD_AN, autoneg_reg);
1257 return 0;
1258}
1259
1260/**
1261 * ixgbe_reset_phy_nl - Performs a PHY reset
1262 * @hw: pointer to hardware structure
1263 **/
1264s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1265{
1266 u16 phy_offset, control, eword, edata, block_crc;
1267 bool end_data = false;
1268 u16 list_offset, data_offset;
1269 u16 phy_data = 0;
1270 s32 ret_val;
1271 u32 i;
1272
1273 /* Blocked by MNG FW so bail */
1274 if (ixgbe_check_reset_blocked(hw))
1275 return 0;
1276
1277 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
1278
1279 /* reset the PHY and poll for completion */
1280 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1281 (phy_data | MDIO_CTRL1_RESET));
1282
1283 for (i = 0; i < 100; i++) {
1284 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1285 &phy_data);
1286 if ((phy_data & MDIO_CTRL1_RESET) == 0)
1287 break;
1288 usleep_range(10000, 20000);
1289 }
1290
1291 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
1292 hw_dbg(hw, "PHY reset did not complete.\n");
1293 return IXGBE_ERR_PHY;
1294 }
1295
1296 /* Get init offsets */
1297 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1298 &data_offset);
1299 if (ret_val)
1300 return ret_val;
1301
1302 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1303 data_offset++;
1304 while (!end_data) {
1305 /*
1306 * Read control word from PHY init contents offset
1307 */
1308 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1309 if (ret_val)
1310 goto err_eeprom;
1311 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1312 IXGBE_CONTROL_SHIFT_NL;
1313 edata = eword & IXGBE_DATA_MASK_NL;
1314 switch (control) {
1315 case IXGBE_DELAY_NL:
1316 data_offset++;
1317 hw_dbg(hw, "DELAY: %d MS\n", edata);
1318 usleep_range(edata * 1000, edata * 2000);
1319 break;
1320 case IXGBE_DATA_NL:
1321 hw_dbg(hw, "DATA:\n");
1322 data_offset++;
1323 ret_val = hw->eeprom.ops.read(hw, data_offset++,
1324 &phy_offset);
1325 if (ret_val)
1326 goto err_eeprom;
1327 for (i = 0; i < edata; i++) {
1328 ret_val = hw->eeprom.ops.read(hw, data_offset,
1329 &eword);
1330 if (ret_val)
1331 goto err_eeprom;
1332 hw->phy.ops.write_reg(hw, phy_offset,
1333 MDIO_MMD_PMAPMD, eword);
1334 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
1335 phy_offset);
1336 data_offset++;
1337 phy_offset++;
1338 }
1339 break;
1340 case IXGBE_CONTROL_NL:
1341 data_offset++;
1342 hw_dbg(hw, "CONTROL:\n");
1343 if (edata == IXGBE_CONTROL_EOL_NL) {
1344 hw_dbg(hw, "EOL\n");
1345 end_data = true;
1346 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1347 hw_dbg(hw, "SOL\n");
1348 } else {
1349 hw_dbg(hw, "Bad control value\n");
1350 return IXGBE_ERR_PHY;
1351 }
1352 break;
1353 default:
1354 hw_dbg(hw, "Bad control type\n");
1355 return IXGBE_ERR_PHY;
1356 }
1357 }
1358
1359 return ret_val;
1360
1361err_eeprom:
1362 hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
1363 return IXGBE_ERR_PHY;
1364}
1365
1366/**
1367 * ixgbe_identify_module_generic - Identifies module type
1368 * @hw: pointer to hardware structure
1369 *
1370 * Determines HW type and calls appropriate function.
1371 **/
1372s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1373{
1374 switch (hw->mac.ops.get_media_type(hw)) {
1375 case ixgbe_media_type_fiber:
1376 return ixgbe_identify_sfp_module_generic(hw);
1377 case ixgbe_media_type_fiber_qsfp:
1378 return ixgbe_identify_qsfp_module_generic(hw);
1379 default:
1380 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1381 return IXGBE_ERR_SFP_NOT_PRESENT;
1382 }
1383
1384 return IXGBE_ERR_SFP_NOT_PRESENT;
1385}
1386
1387/**
1388 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1389 * @hw: pointer to hardware structure
1390 *
1391 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1392 **/
1393s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1394{
1395 struct ixgbe_adapter *adapter = hw->back;
1396 s32 status;
1397 u32 vendor_oui = 0;
1398 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1399 u8 identifier = 0;
1400 u8 comp_codes_1g = 0;
1401 u8 comp_codes_10g = 0;
1402 u8 oui_bytes[3] = {0, 0, 0};
1403 u8 cable_tech = 0;
1404 u8 cable_spec = 0;
1405 u16 enforce_sfp = 0;
1406
1407 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1408 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1409 return IXGBE_ERR_SFP_NOT_PRESENT;
1410 }
1411
1412 /* LAN ID is needed for sfp_type determination */
1413 hw->mac.ops.set_lan_id(hw);
1414
1415 status = hw->phy.ops.read_i2c_eeprom(hw,
1416 IXGBE_SFF_IDENTIFIER,
1417 &identifier);
1418
1419 if (status)
1420 goto err_read_i2c_eeprom;
1421
1422 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1423 hw->phy.type = ixgbe_phy_sfp_unsupported;
1424 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1425 }
1426 status = hw->phy.ops.read_i2c_eeprom(hw,
1427 IXGBE_SFF_1GBE_COMP_CODES,
1428 &comp_codes_1g);
1429
1430 if (status)
1431 goto err_read_i2c_eeprom;
1432
1433 status = hw->phy.ops.read_i2c_eeprom(hw,
1434 IXGBE_SFF_10GBE_COMP_CODES,
1435 &comp_codes_10g);
1436
1437 if (status)
1438 goto err_read_i2c_eeprom;
1439 status = hw->phy.ops.read_i2c_eeprom(hw,
1440 IXGBE_SFF_CABLE_TECHNOLOGY,
1441 &cable_tech);
1442
1443 if (status)
1444 goto err_read_i2c_eeprom;
1445
1446 /* ID Module
1447 * =========
1448 * 0 SFP_DA_CU
1449 * 1 SFP_SR
1450 * 2 SFP_LR
1451 * 3 SFP_DA_CORE0 - 82599-specific
1452 * 4 SFP_DA_CORE1 - 82599-specific
1453 * 5 SFP_SR/LR_CORE0 - 82599-specific
1454 * 6 SFP_SR/LR_CORE1 - 82599-specific
1455 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1456 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1457 * 9 SFP_1g_cu_CORE0 - 82599-specific
1458 * 10 SFP_1g_cu_CORE1 - 82599-specific
1459 * 11 SFP_1g_sx_CORE0 - 82599-specific
1460 * 12 SFP_1g_sx_CORE1 - 82599-specific
1461 */
1462 if (hw->mac.type == ixgbe_mac_82598EB) {
1463 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1464 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1465 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1466 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1467 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1468 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1469 else
1470 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1471 } else {
1472 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1473 if (hw->bus.lan_id == 0)
1474 hw->phy.sfp_type =
1475 ixgbe_sfp_type_da_cu_core0;
1476 else
1477 hw->phy.sfp_type =
1478 ixgbe_sfp_type_da_cu_core1;
1479 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1480 hw->phy.ops.read_i2c_eeprom(
1481 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1482 &cable_spec);
1483 if (cable_spec &
1484 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1485 if (hw->bus.lan_id == 0)
1486 hw->phy.sfp_type =
1487 ixgbe_sfp_type_da_act_lmt_core0;
1488 else
1489 hw->phy.sfp_type =
1490 ixgbe_sfp_type_da_act_lmt_core1;
1491 } else {
1492 hw->phy.sfp_type =
1493 ixgbe_sfp_type_unknown;
1494 }
1495 } else if (comp_codes_10g &
1496 (IXGBE_SFF_10GBASESR_CAPABLE |
1497 IXGBE_SFF_10GBASELR_CAPABLE)) {
1498 if (hw->bus.lan_id == 0)
1499 hw->phy.sfp_type =
1500 ixgbe_sfp_type_srlr_core0;
1501 else
1502 hw->phy.sfp_type =
1503 ixgbe_sfp_type_srlr_core1;
1504 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1505 if (hw->bus.lan_id == 0)
1506 hw->phy.sfp_type =
1507 ixgbe_sfp_type_1g_cu_core0;
1508 else
1509 hw->phy.sfp_type =
1510 ixgbe_sfp_type_1g_cu_core1;
1511 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1512 if (hw->bus.lan_id == 0)
1513 hw->phy.sfp_type =
1514 ixgbe_sfp_type_1g_sx_core0;
1515 else
1516 hw->phy.sfp_type =
1517 ixgbe_sfp_type_1g_sx_core1;
1518 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1519 if (hw->bus.lan_id == 0)
1520 hw->phy.sfp_type =
1521 ixgbe_sfp_type_1g_lx_core0;
1522 else
1523 hw->phy.sfp_type =
1524 ixgbe_sfp_type_1g_lx_core1;
1525 } else {
1526 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1527 }
1528 }
1529
1530 if (hw->phy.sfp_type != stored_sfp_type)
1531 hw->phy.sfp_setup_needed = true;
1532
1533 /* Determine if the SFP+ PHY is dual speed or not. */
1534 hw->phy.multispeed_fiber = false;
1535 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1536 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1537 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1538 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1539 hw->phy.multispeed_fiber = true;
1540
1541 /* Determine PHY vendor */
1542 if (hw->phy.type != ixgbe_phy_nl) {
1543 hw->phy.id = identifier;
1544 status = hw->phy.ops.read_i2c_eeprom(hw,
1545 IXGBE_SFF_VENDOR_OUI_BYTE0,
1546 &oui_bytes[0]);
1547
1548 if (status != 0)
1549 goto err_read_i2c_eeprom;
1550
1551 status = hw->phy.ops.read_i2c_eeprom(hw,
1552 IXGBE_SFF_VENDOR_OUI_BYTE1,
1553 &oui_bytes[1]);
1554
1555 if (status != 0)
1556 goto err_read_i2c_eeprom;
1557
1558 status = hw->phy.ops.read_i2c_eeprom(hw,
1559 IXGBE_SFF_VENDOR_OUI_BYTE2,
1560 &oui_bytes[2]);
1561
1562 if (status != 0)
1563 goto err_read_i2c_eeprom;
1564
1565 vendor_oui =
1566 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1567 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1568 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1569
1570 switch (vendor_oui) {
1571 case IXGBE_SFF_VENDOR_OUI_TYCO:
1572 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1573 hw->phy.type =
1574 ixgbe_phy_sfp_passive_tyco;
1575 break;
1576 case IXGBE_SFF_VENDOR_OUI_FTL:
1577 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1578 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1579 else
1580 hw->phy.type = ixgbe_phy_sfp_ftl;
1581 break;
1582 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1583 hw->phy.type = ixgbe_phy_sfp_avago;
1584 break;
1585 case IXGBE_SFF_VENDOR_OUI_INTEL:
1586 hw->phy.type = ixgbe_phy_sfp_intel;
1587 break;
1588 default:
1589 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1590 hw->phy.type =
1591 ixgbe_phy_sfp_passive_unknown;
1592 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1593 hw->phy.type =
1594 ixgbe_phy_sfp_active_unknown;
1595 else
1596 hw->phy.type = ixgbe_phy_sfp_unknown;
1597 break;
1598 }
1599 }
1600
1601 /* Allow any DA cable vendor */
1602 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1603 IXGBE_SFF_DA_ACTIVE_CABLE))
1604 return 0;
1605
1606 /* Verify supported 1G SFP modules */
1607 if (comp_codes_10g == 0 &&
1608 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1609 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1610 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1611 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1612 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1613 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1614 hw->phy.type = ixgbe_phy_sfp_unsupported;
1615 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1616 }
1617
1618 /* Anything else 82598-based is supported */
1619 if (hw->mac.type == ixgbe_mac_82598EB)
1620 return 0;
1621
1622 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1623 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1624 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1625 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1626 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1627 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1628 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1629 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1630 /* Make sure we're a supported PHY type */
1631 if (hw->phy.type == ixgbe_phy_sfp_intel)
1632 return 0;
1633 if (hw->allow_unsupported_sfp) {
1634 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1635 return 0;
1636 }
1637 hw_dbg(hw, "SFP+ module not supported\n");
1638 hw->phy.type = ixgbe_phy_sfp_unsupported;
1639 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1640 }
1641 return 0;
1642
1643err_read_i2c_eeprom:
1644 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1645 if (hw->phy.type != ixgbe_phy_nl) {
1646 hw->phy.id = 0;
1647 hw->phy.type = ixgbe_phy_unknown;
1648 }
1649 return IXGBE_ERR_SFP_NOT_PRESENT;
1650}
1651
1652/**
1653 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1654 * @hw: pointer to hardware structure
1655 *
1656 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1657 **/
1658static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1659{
1660 struct ixgbe_adapter *adapter = hw->back;
1661 s32 status;
1662 u32 vendor_oui = 0;
1663 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1664 u8 identifier = 0;
1665 u8 comp_codes_1g = 0;
1666 u8 comp_codes_10g = 0;
1667 u8 oui_bytes[3] = {0, 0, 0};
1668 u16 enforce_sfp = 0;
1669 u8 connector = 0;
1670 u8 cable_length = 0;
1671 u8 device_tech = 0;
1672 bool active_cable = false;
1673
1674 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1675 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1676 return IXGBE_ERR_SFP_NOT_PRESENT;
1677 }
1678
1679 /* LAN ID is needed for sfp_type determination */
1680 hw->mac.ops.set_lan_id(hw);
1681
1682 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1683 &identifier);
1684
1685 if (status != 0)
1686 goto err_read_i2c_eeprom;
1687
1688 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1689 hw->phy.type = ixgbe_phy_sfp_unsupported;
1690 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1691 }
1692
1693 hw->phy.id = identifier;
1694
1695 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1696 &comp_codes_10g);
1697
1698 if (status != 0)
1699 goto err_read_i2c_eeprom;
1700
1701 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1702 &comp_codes_1g);
1703
1704 if (status != 0)
1705 goto err_read_i2c_eeprom;
1706
1707 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1708 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1709 if (hw->bus.lan_id == 0)
1710 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1711 else
1712 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1713 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1714 IXGBE_SFF_10GBASELR_CAPABLE)) {
1715 if (hw->bus.lan_id == 0)
1716 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1717 else
1718 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1719 } else {
1720 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1721 active_cable = true;
1722
1723 if (!active_cable) {
1724 /* check for active DA cables that pre-date
1725 * SFF-8436 v3.6
1726 */
1727 hw->phy.ops.read_i2c_eeprom(hw,
1728 IXGBE_SFF_QSFP_CONNECTOR,
1729 &connector);
1730
1731 hw->phy.ops.read_i2c_eeprom(hw,
1732 IXGBE_SFF_QSFP_CABLE_LENGTH,
1733 &cable_length);
1734
1735 hw->phy.ops.read_i2c_eeprom(hw,
1736 IXGBE_SFF_QSFP_DEVICE_TECH,
1737 &device_tech);
1738
1739 if ((connector ==
1740 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1741 (cable_length > 0) &&
1742 ((device_tech >> 4) ==
1743 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1744 active_cable = true;
1745 }
1746
1747 if (active_cable) {
1748 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1749 if (hw->bus.lan_id == 0)
1750 hw->phy.sfp_type =
1751 ixgbe_sfp_type_da_act_lmt_core0;
1752 else
1753 hw->phy.sfp_type =
1754 ixgbe_sfp_type_da_act_lmt_core1;
1755 } else {
1756 /* unsupported module type */
1757 hw->phy.type = ixgbe_phy_sfp_unsupported;
1758 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1759 }
1760 }
1761
1762 if (hw->phy.sfp_type != stored_sfp_type)
1763 hw->phy.sfp_setup_needed = true;
1764
1765 /* Determine if the QSFP+ PHY is dual speed or not. */
1766 hw->phy.multispeed_fiber = false;
1767 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1768 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1769 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1770 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1771 hw->phy.multispeed_fiber = true;
1772
1773 /* Determine PHY vendor for optical modules */
1774 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1775 IXGBE_SFF_10GBASELR_CAPABLE)) {
1776 status = hw->phy.ops.read_i2c_eeprom(hw,
1777 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1778 &oui_bytes[0]);
1779
1780 if (status != 0)
1781 goto err_read_i2c_eeprom;
1782
1783 status = hw->phy.ops.read_i2c_eeprom(hw,
1784 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1785 &oui_bytes[1]);
1786
1787 if (status != 0)
1788 goto err_read_i2c_eeprom;
1789
1790 status = hw->phy.ops.read_i2c_eeprom(hw,
1791 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1792 &oui_bytes[2]);
1793
1794 if (status != 0)
1795 goto err_read_i2c_eeprom;
1796
1797 vendor_oui =
1798 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1799 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1800 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1801
1802 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1803 hw->phy.type = ixgbe_phy_qsfp_intel;
1804 else
1805 hw->phy.type = ixgbe_phy_qsfp_unknown;
1806
1807 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1808 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1809 /* Make sure we're a supported PHY type */
1810 if (hw->phy.type == ixgbe_phy_qsfp_intel)
1811 return 0;
1812 if (hw->allow_unsupported_sfp) {
1813 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1814 return 0;
1815 }
1816 hw_dbg(hw, "QSFP module not supported\n");
1817 hw->phy.type = ixgbe_phy_sfp_unsupported;
1818 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1819 }
1820 return 0;
1821 }
1822 return 0;
1823
1824err_read_i2c_eeprom:
1825 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1826 hw->phy.id = 0;
1827 hw->phy.type = ixgbe_phy_unknown;
1828
1829 return IXGBE_ERR_SFP_NOT_PRESENT;
1830}
1831
1832/**
1833 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1834 * @hw: pointer to hardware structure
1835 * @list_offset: offset to the SFP ID list
1836 * @data_offset: offset to the SFP data block
1837 *
1838 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1839 * so it returns the offsets to the phy init sequence block.
1840 **/
1841s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1842 u16 *list_offset,
1843 u16 *data_offset)
1844{
1845 u16 sfp_id;
1846 u16 sfp_type = hw->phy.sfp_type;
1847
1848 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1849 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1850
1851 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1852 return IXGBE_ERR_SFP_NOT_PRESENT;
1853
1854 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1855 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1856 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1857
1858 /*
1859 * Limiting active cables and 1G Phys must be initialized as
1860 * SR modules
1861 */
1862 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1863 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1864 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1865 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1866 sfp_type = ixgbe_sfp_type_srlr_core0;
1867 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1868 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1869 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1870 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1871 sfp_type = ixgbe_sfp_type_srlr_core1;
1872
1873 /* Read offset to PHY init contents */
1874 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1875 hw_err(hw, "eeprom read at %d failed\n",
1876 IXGBE_PHY_INIT_OFFSET_NL);
1877 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1878 }
1879
1880 if ((!*list_offset) || (*list_offset == 0xFFFF))
1881 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1882
1883 /* Shift offset to first ID word */
1884 (*list_offset)++;
1885
1886 /*
1887 * Find the matching SFP ID in the EEPROM
1888 * and program the init sequence
1889 */
1890 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1891 goto err_phy;
1892
1893 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1894 if (sfp_id == sfp_type) {
1895 (*list_offset)++;
1896 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1897 goto err_phy;
1898 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1899 hw_dbg(hw, "SFP+ module not supported\n");
1900 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1901 } else {
1902 break;
1903 }
1904 } else {
1905 (*list_offset) += 2;
1906 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1907 goto err_phy;
1908 }
1909 }
1910
1911 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1912 hw_dbg(hw, "No matching SFP+ module found\n");
1913 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1914 }
1915
1916 return 0;
1917
1918err_phy:
1919 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
1920 return IXGBE_ERR_PHY;
1921}
1922
1923/**
1924 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1925 * @hw: pointer to hardware structure
1926 * @byte_offset: EEPROM byte offset to read
1927 * @eeprom_data: value read
1928 *
1929 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1930 **/
1931s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1932 u8 *eeprom_data)
1933{
1934 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1935 IXGBE_I2C_EEPROM_DEV_ADDR,
1936 eeprom_data);
1937}
1938
1939/**
1940 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1941 * @hw: pointer to hardware structure
1942 * @byte_offset: byte offset at address 0xA2
1943 * @sff8472_data: value read
1944 *
1945 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1946 **/
1947s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1948 u8 *sff8472_data)
1949{
1950 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1951 IXGBE_I2C_EEPROM_DEV_ADDR2,
1952 sff8472_data);
1953}
1954
1955/**
1956 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1957 * @hw: pointer to hardware structure
1958 * @byte_offset: EEPROM byte offset to write
1959 * @eeprom_data: value to write
1960 *
1961 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1962 **/
1963s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1964 u8 eeprom_data)
1965{
1966 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1967 IXGBE_I2C_EEPROM_DEV_ADDR,
1968 eeprom_data);
1969}
1970
1971/**
1972 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1973 * @hw: pointer to hardware structure
1974 * @offset: eeprom offset to be read
1975 * @addr: I2C address to be read
1976 */
1977static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1978{
1979 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1980 offset == IXGBE_SFF_IDENTIFIER &&
1981 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1982 return true;
1983 return false;
1984}
1985
1986/**
1987 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1988 * @hw: pointer to hardware structure
1989 * @byte_offset: byte offset to read
1990 * @dev_addr: device address
1991 * @data: value read
1992 * @lock: true if to take and release semaphore
1993 *
1994 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1995 * a specified device address.
1996 */
1997static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1998 u8 dev_addr, u8 *data, bool lock)
1999{
2000 s32 status;
2001 u32 max_retry = 10;
2002 u32 retry = 0;
2003 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2004 bool nack = true;
2005
2006 if (hw->mac.type >= ixgbe_mac_X550)
2007 max_retry = 3;
2008 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2009 max_retry = IXGBE_SFP_DETECT_RETRIES;
2010
2011 *data = 0;
2012
2013 do {
2014 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2015 return IXGBE_ERR_SWFW_SYNC;
2016
2017 ixgbe_i2c_start(hw);
2018
2019 /* Device Address and write indication */
2020 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2021 if (status != 0)
2022 goto fail;
2023
2024 status = ixgbe_get_i2c_ack(hw);
2025 if (status != 0)
2026 goto fail;
2027
2028 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2029 if (status != 0)
2030 goto fail;
2031
2032 status = ixgbe_get_i2c_ack(hw);
2033 if (status != 0)
2034 goto fail;
2035
2036 ixgbe_i2c_start(hw);
2037
2038 /* Device Address and read indication */
2039 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2040 if (status != 0)
2041 goto fail;
2042
2043 status = ixgbe_get_i2c_ack(hw);
2044 if (status != 0)
2045 goto fail;
2046
2047 status = ixgbe_clock_in_i2c_byte(hw, data);
2048 if (status != 0)
2049 goto fail;
2050
2051 status = ixgbe_clock_out_i2c_bit(hw, nack);
2052 if (status != 0)
2053 goto fail;
2054
2055 ixgbe_i2c_stop(hw);
2056 if (lock)
2057 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2058 return 0;
2059
2060fail:
2061 ixgbe_i2c_bus_clear(hw);
2062 if (lock) {
2063 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2064 msleep(100);
2065 }
2066 retry++;
2067 if (retry < max_retry)
2068 hw_dbg(hw, "I2C byte read error - Retrying.\n");
2069 else
2070 hw_dbg(hw, "I2C byte read error.\n");
2071
2072 } while (retry < max_retry);
2073
2074 return status;
2075}
2076
2077/**
2078 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2079 * @hw: pointer to hardware structure
2080 * @byte_offset: byte offset to read
2081 * @dev_addr: device address
2082 * @data: value read
2083 *
2084 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2085 * a specified device address.
2086 */
2087s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2088 u8 dev_addr, u8 *data)
2089{
2090 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2091 data, true);
2092}
2093
2094/**
2095 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2096 * @hw: pointer to hardware structure
2097 * @byte_offset: byte offset to read
2098 * @dev_addr: device address
2099 * @data: value read
2100 *
2101 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2102 * a specified device address.
2103 */
2104s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2105 u8 dev_addr, u8 *data)
2106{
2107 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2108 data, false);
2109}
2110
2111/**
2112 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2113 * @hw: pointer to hardware structure
2114 * @byte_offset: byte offset to write
2115 * @dev_addr: device address
2116 * @data: value to write
2117 * @lock: true if to take and release semaphore
2118 *
2119 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2120 * a specified device address.
2121 */
2122static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2123 u8 dev_addr, u8 data, bool lock)
2124{
2125 s32 status;
2126 u32 max_retry = 1;
2127 u32 retry = 0;
2128 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2129
2130 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2131 return IXGBE_ERR_SWFW_SYNC;
2132
2133 do {
2134 ixgbe_i2c_start(hw);
2135
2136 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2137 if (status != 0)
2138 goto fail;
2139
2140 status = ixgbe_get_i2c_ack(hw);
2141 if (status != 0)
2142 goto fail;
2143
2144 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2145 if (status != 0)
2146 goto fail;
2147
2148 status = ixgbe_get_i2c_ack(hw);
2149 if (status != 0)
2150 goto fail;
2151
2152 status = ixgbe_clock_out_i2c_byte(hw, data);
2153 if (status != 0)
2154 goto fail;
2155
2156 status = ixgbe_get_i2c_ack(hw);
2157 if (status != 0)
2158 goto fail;
2159
2160 ixgbe_i2c_stop(hw);
2161 if (lock)
2162 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2163 return 0;
2164
2165fail:
2166 ixgbe_i2c_bus_clear(hw);
2167 retry++;
2168 if (retry < max_retry)
2169 hw_dbg(hw, "I2C byte write error - Retrying.\n");
2170 else
2171 hw_dbg(hw, "I2C byte write error.\n");
2172 } while (retry < max_retry);
2173
2174 if (lock)
2175 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2176
2177 return status;
2178}
2179
2180/**
2181 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2182 * @hw: pointer to hardware structure
2183 * @byte_offset: byte offset to write
2184 * @dev_addr: device address
2185 * @data: value to write
2186 *
2187 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2188 * a specified device address.
2189 */
2190s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2191 u8 dev_addr, u8 data)
2192{
2193 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2194 data, true);
2195}
2196
2197/**
2198 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2199 * @hw: pointer to hardware structure
2200 * @byte_offset: byte offset to write
2201 * @dev_addr: device address
2202 * @data: value to write
2203 *
2204 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2205 * a specified device address.
2206 */
2207s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2208 u8 dev_addr, u8 data)
2209{
2210 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2211 data, false);
2212}
2213
2214/**
2215 * ixgbe_i2c_start - Sets I2C start condition
2216 * @hw: pointer to hardware structure
2217 *
2218 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2219 * Set bit-bang mode on X550 hardware.
2220 **/
2221static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2222{
2223 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2224
2225 i2cctl |= IXGBE_I2C_BB_EN(hw);
2226
2227 /* Start condition must begin with data and clock high */
2228 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2229 ixgbe_raise_i2c_clk(hw, &i2cctl);
2230
2231 /* Setup time for start condition (4.7us) */
2232 udelay(IXGBE_I2C_T_SU_STA);
2233
2234 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2235
2236 /* Hold time for start condition (4us) */
2237 udelay(IXGBE_I2C_T_HD_STA);
2238
2239 ixgbe_lower_i2c_clk(hw, &i2cctl);
2240
2241 /* Minimum low period of clock is 4.7 us */
2242 udelay(IXGBE_I2C_T_LOW);
2243
2244}
2245
2246/**
2247 * ixgbe_i2c_stop - Sets I2C stop condition
2248 * @hw: pointer to hardware structure
2249 *
2250 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2251 * Disables bit-bang mode and negates data output enable on X550
2252 * hardware.
2253 **/
2254static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2255{
2256 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2257 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2258 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2259 u32 bb_en_bit = IXGBE_I2C_BB_EN(hw);
2260
2261 /* Stop condition must begin with data low and clock high */
2262 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2263 ixgbe_raise_i2c_clk(hw, &i2cctl);
2264
2265 /* Setup time for stop condition (4us) */
2266 udelay(IXGBE_I2C_T_SU_STO);
2267
2268 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2269
2270 /* bus free time between stop and start (4.7us)*/
2271 udelay(IXGBE_I2C_T_BUF);
2272
2273 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2274 i2cctl &= ~bb_en_bit;
2275 i2cctl |= data_oe_bit | clk_oe_bit;
2276 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2277 IXGBE_WRITE_FLUSH(hw);
2278 }
2279}
2280
2281/**
2282 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2283 * @hw: pointer to hardware structure
2284 * @data: data byte to clock in
2285 *
2286 * Clocks in one byte data via I2C data/clock
2287 **/
2288static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2289{
2290 s32 i;
2291 bool bit = false;
2292
2293 *data = 0;
2294 for (i = 7; i >= 0; i--) {
2295 ixgbe_clock_in_i2c_bit(hw, &bit);
2296 *data |= bit << i;
2297 }
2298
2299 return 0;
2300}
2301
2302/**
2303 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2304 * @hw: pointer to hardware structure
2305 * @data: data byte clocked out
2306 *
2307 * Clocks out one byte data via I2C data/clock
2308 **/
2309static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2310{
2311 s32 status;
2312 s32 i;
2313 u32 i2cctl;
2314 bool bit = false;
2315
2316 for (i = 7; i >= 0; i--) {
2317 bit = (data >> i) & 0x1;
2318 status = ixgbe_clock_out_i2c_bit(hw, bit);
2319
2320 if (status != 0)
2321 break;
2322 }
2323
2324 /* Release SDA line (set high) */
2325 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2326 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2327 i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw);
2328 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2329 IXGBE_WRITE_FLUSH(hw);
2330
2331 return status;
2332}
2333
2334/**
2335 * ixgbe_get_i2c_ack - Polls for I2C ACK
2336 * @hw: pointer to hardware structure
2337 *
2338 * Clocks in/out one bit via I2C data/clock
2339 **/
2340static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2341{
2342 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2343 s32 status = 0;
2344 u32 i = 0;
2345 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2346 u32 timeout = 10;
2347 bool ack = true;
2348
2349 if (data_oe_bit) {
2350 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2351 i2cctl |= data_oe_bit;
2352 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2353 IXGBE_WRITE_FLUSH(hw);
2354 }
2355 ixgbe_raise_i2c_clk(hw, &i2cctl);
2356
2357 /* Minimum high period of clock is 4us */
2358 udelay(IXGBE_I2C_T_HIGH);
2359
2360 /* Poll for ACK. Note that ACK in I2C spec is
2361 * transition from 1 to 0 */
2362 for (i = 0; i < timeout; i++) {
2363 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2364 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2365
2366 udelay(1);
2367 if (ack == 0)
2368 break;
2369 }
2370
2371 if (ack == 1) {
2372 hw_dbg(hw, "I2C ack was not received.\n");
2373 status = IXGBE_ERR_I2C;
2374 }
2375
2376 ixgbe_lower_i2c_clk(hw, &i2cctl);
2377
2378 /* Minimum low period of clock is 4.7 us */
2379 udelay(IXGBE_I2C_T_LOW);
2380
2381 return status;
2382}
2383
2384/**
2385 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2386 * @hw: pointer to hardware structure
2387 * @data: read data value
2388 *
2389 * Clocks in one bit via I2C data/clock
2390 **/
2391static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2392{
2393 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2394 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2395
2396 if (data_oe_bit) {
2397 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2398 i2cctl |= data_oe_bit;
2399 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2400 IXGBE_WRITE_FLUSH(hw);
2401 }
2402 ixgbe_raise_i2c_clk(hw, &i2cctl);
2403
2404 /* Minimum high period of clock is 4us */
2405 udelay(IXGBE_I2C_T_HIGH);
2406
2407 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2408 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2409
2410 ixgbe_lower_i2c_clk(hw, &i2cctl);
2411
2412 /* Minimum low period of clock is 4.7 us */
2413 udelay(IXGBE_I2C_T_LOW);
2414
2415 return 0;
2416}
2417
2418/**
2419 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2420 * @hw: pointer to hardware structure
2421 * @data: data value to write
2422 *
2423 * Clocks out one bit via I2C data/clock
2424 **/
2425static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2426{
2427 s32 status;
2428 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2429
2430 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2431 if (status == 0) {
2432 ixgbe_raise_i2c_clk(hw, &i2cctl);
2433
2434 /* Minimum high period of clock is 4us */
2435 udelay(IXGBE_I2C_T_HIGH);
2436
2437 ixgbe_lower_i2c_clk(hw, &i2cctl);
2438
2439 /* Minimum low period of clock is 4.7 us.
2440 * This also takes care of the data hold time.
2441 */
2442 udelay(IXGBE_I2C_T_LOW);
2443 } else {
2444 hw_dbg(hw, "I2C data was not set to %X\n", data);
2445 return IXGBE_ERR_I2C;
2446 }
2447
2448 return 0;
2449}
2450/**
2451 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2452 * @hw: pointer to hardware structure
2453 * @i2cctl: Current value of I2CCTL register
2454 *
2455 * Raises the I2C clock line '0'->'1'
2456 * Negates the I2C clock output enable on X550 hardware.
2457 **/
2458static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2459{
2460 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2461 u32 i = 0;
2462 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2463 u32 i2cctl_r = 0;
2464
2465 if (clk_oe_bit) {
2466 *i2cctl |= clk_oe_bit;
2467 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2468 }
2469
2470 for (i = 0; i < timeout; i++) {
2471 *i2cctl |= IXGBE_I2C_CLK_OUT(hw);
2472 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2473 IXGBE_WRITE_FLUSH(hw);
2474 /* SCL rise time (1000ns) */
2475 udelay(IXGBE_I2C_T_RISE);
2476
2477 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2478 if (i2cctl_r & IXGBE_I2C_CLK_IN(hw))
2479 break;
2480 }
2481}
2482
2483/**
2484 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2485 * @hw: pointer to hardware structure
2486 * @i2cctl: Current value of I2CCTL register
2487 *
2488 * Lowers the I2C clock line '1'->'0'
2489 * Asserts the I2C clock output enable on X550 hardware.
2490 **/
2491static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2492{
2493
2494 *i2cctl &= ~IXGBE_I2C_CLK_OUT(hw);
2495 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw);
2496
2497 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2498 IXGBE_WRITE_FLUSH(hw);
2499
2500 /* SCL fall time (300ns) */
2501 udelay(IXGBE_I2C_T_FALL);
2502}
2503
2504/**
2505 * ixgbe_set_i2c_data - Sets the I2C data bit
2506 * @hw: pointer to hardware structure
2507 * @i2cctl: Current value of I2CCTL register
2508 * @data: I2C data value (0 or 1) to set
2509 *
2510 * Sets the I2C data bit
2511 * Asserts the I2C data output enable on X550 hardware.
2512 **/
2513static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2514{
2515 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2516
2517 if (data)
2518 *i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2519 else
2520 *i2cctl &= ~IXGBE_I2C_DATA_OUT(hw);
2521 *i2cctl &= ~data_oe_bit;
2522
2523 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2524 IXGBE_WRITE_FLUSH(hw);
2525
2526 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2527 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2528
2529 if (!data) /* Can't verify data in this case */
2530 return 0;
2531 if (data_oe_bit) {
2532 *i2cctl |= data_oe_bit;
2533 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2534 IXGBE_WRITE_FLUSH(hw);
2535 }
2536
2537 /* Verify data was set correctly */
2538 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2539 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2540 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
2541 return IXGBE_ERR_I2C;
2542 }
2543
2544 return 0;
2545}
2546
2547/**
2548 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2549 * @hw: pointer to hardware structure
2550 * @i2cctl: Current value of I2CCTL register
2551 *
2552 * Returns the I2C data bit value
2553 * Negates the I2C data output enable on X550 hardware.
2554 **/
2555static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2556{
2557 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2558
2559 if (data_oe_bit) {
2560 *i2cctl |= data_oe_bit;
2561 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2562 IXGBE_WRITE_FLUSH(hw);
2563 udelay(IXGBE_I2C_T_FALL);
2564 }
2565
2566 if (*i2cctl & IXGBE_I2C_DATA_IN(hw))
2567 return true;
2568 return false;
2569}
2570
2571/**
2572 * ixgbe_i2c_bus_clear - Clears the I2C bus
2573 * @hw: pointer to hardware structure
2574 *
2575 * Clears the I2C bus by sending nine clock pulses.
2576 * Used when data line is stuck low.
2577 **/
2578static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2579{
2580 u32 i2cctl;
2581 u32 i;
2582
2583 ixgbe_i2c_start(hw);
2584 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2585
2586 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2587
2588 for (i = 0; i < 9; i++) {
2589 ixgbe_raise_i2c_clk(hw, &i2cctl);
2590
2591 /* Min high period of clock is 4us */
2592 udelay(IXGBE_I2C_T_HIGH);
2593
2594 ixgbe_lower_i2c_clk(hw, &i2cctl);
2595
2596 /* Min low period of clock is 4.7us*/
2597 udelay(IXGBE_I2C_T_LOW);
2598 }
2599
2600 ixgbe_i2c_start(hw);
2601
2602 /* Put the i2c bus back to default state */
2603 ixgbe_i2c_stop(hw);
2604}
2605
2606/**
2607 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2608 * @hw: pointer to hardware structure
2609 *
2610 * Checks if the LASI temp alarm status was triggered due to overtemp
2611 **/
2612s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2613{
2614 u16 phy_data = 0;
2615
2616 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2617 return 0;
2618
2619 /* Check that the LASI temp alarm status was triggered */
2620 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2621 MDIO_MMD_PMAPMD, &phy_data);
2622
2623 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2624 return 0;
2625
2626 return IXGBE_ERR_OVERTEMP;
2627}
2628
2629/** ixgbe_set_copper_phy_power - Control power for copper phy
2630 * @hw: pointer to hardware structure
2631 * @on: true for on, false for off
2632 **/
2633s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2634{
2635 u32 status;
2636 u16 reg;
2637
2638 /* Bail if we don't have copper phy */
2639 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2640 return 0;
2641
2642 if (!on && ixgbe_mng_present(hw))
2643 return 0;
2644
2645 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, ®);
2646 if (status)
2647 return status;
2648
2649 if (on) {
2650 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2651 } else {
2652 if (ixgbe_check_reset_blocked(hw))
2653 return 0;
2654 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2655 }
2656
2657 status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg);
2658 return status;
2659}