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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#include <linux/types.h>
5#include <linux/module.h>
6#include <linux/pci.h>
7#include <linux/netdevice.h>
8#include <linux/vmalloc.h>
9#include <linux/string.h>
10#include <linux/in.h>
11#include <linux/interrupt.h>
12#include <linux/ip.h>
13#include <linux/tcp.h>
14#include <linux/sctp.h>
15#include <linux/pkt_sched.h>
16#include <linux/ipv6.h>
17#include <linux/slab.h>
18#include <net/checksum.h>
19#include <net/ip6_checksum.h>
20#include <linux/etherdevice.h>
21#include <linux/ethtool.h>
22#include <linux/if.h>
23#include <linux/if_vlan.h>
24#include <linux/if_macvlan.h>
25#include <linux/if_bridge.h>
26#include <linux/prefetch.h>
27#include <linux/bpf.h>
28#include <linux/bpf_trace.h>
29#include <linux/atomic.h>
30#include <linux/numa.h>
31#include <generated/utsrelease.h>
32#include <scsi/fc/fc_fcoe.h>
33#include <net/udp_tunnel.h>
34#include <net/pkt_cls.h>
35#include <net/tc_act/tc_gact.h>
36#include <net/tc_act/tc_mirred.h>
37#include <net/vxlan.h>
38#include <net/mpls.h>
39#include <net/xdp_sock_drv.h>
40#include <net/xfrm.h>
41
42#include "ixgbe.h"
43#include "ixgbe_common.h"
44#include "ixgbe_dcb_82599.h"
45#include "ixgbe_phy.h"
46#include "ixgbe_sriov.h"
47#include "ixgbe_model.h"
48#include "ixgbe_txrx_common.h"
49
50char ixgbe_driver_name[] = "ixgbe";
51static const char ixgbe_driver_string[] =
52 "Intel(R) 10 Gigabit PCI Express Network Driver";
53#ifdef IXGBE_FCOE
54char ixgbe_default_device_descr[] =
55 "Intel(R) 10 Gigabit Network Connection";
56#else
57static char ixgbe_default_device_descr[] =
58 "Intel(R) 10 Gigabit Network Connection";
59#endif
60static const char ixgbe_copyright[] =
61 "Copyright (c) 1999-2016 Intel Corporation.";
62
63static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
64
65static const struct ixgbe_info *ixgbe_info_tbl[] = {
66 [board_82598] = &ixgbe_82598_info,
67 [board_82599] = &ixgbe_82599_info,
68 [board_X540] = &ixgbe_X540_info,
69 [board_X550] = &ixgbe_X550_info,
70 [board_X550EM_x] = &ixgbe_X550EM_x_info,
71 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info,
72 [board_x550em_a] = &ixgbe_x550em_a_info,
73 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info,
74};
75
76/* ixgbe_pci_tbl - PCI Device ID Table
77 *
78 * Wildcard entries (PCI_ANY_ID) should come last
79 * Last entry must be all 0s
80 *
81 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
82 * Class, Class Mask, private data (not used) }
83 */
84static const struct pci_device_id ixgbe_pci_tbl[] = {
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550},
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x},
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw},
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a },
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a},
129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a },
130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw },
131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw },
132 /* required last entry */
133 {0, }
134};
135MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
136
137#ifdef CONFIG_IXGBE_DCA
138static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
139 void *p);
140static struct notifier_block dca_notifier = {
141 .notifier_call = ixgbe_notify_dca,
142 .next = NULL,
143 .priority = 0
144};
145#endif
146
147#ifdef CONFIG_PCI_IOV
148static unsigned int max_vfs;
149module_param(max_vfs, uint, 0);
150MODULE_PARM_DESC(max_vfs,
151 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
152#endif /* CONFIG_PCI_IOV */
153
154static unsigned int allow_unsupported_sfp;
155module_param(allow_unsupported_sfp, uint, 0);
156MODULE_PARM_DESC(allow_unsupported_sfp,
157 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
158
159#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
160static int debug = -1;
161module_param(debug, int, 0);
162MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
163
164MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
165MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
166MODULE_LICENSE("GPL v2");
167
168static struct workqueue_struct *ixgbe_wq;
169
170static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
171static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *);
172
173static const struct net_device_ops ixgbe_netdev_ops;
174
175static bool netif_is_ixgbe(struct net_device *dev)
176{
177 return dev && (dev->netdev_ops == &ixgbe_netdev_ops);
178}
179
180static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
181 u32 reg, u16 *value)
182{
183 struct pci_dev *parent_dev;
184 struct pci_bus *parent_bus;
185
186 parent_bus = adapter->pdev->bus->parent;
187 if (!parent_bus)
188 return -1;
189
190 parent_dev = parent_bus->self;
191 if (!parent_dev)
192 return -1;
193
194 if (!pci_is_pcie(parent_dev))
195 return -1;
196
197 pcie_capability_read_word(parent_dev, reg, value);
198 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
199 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
200 return -1;
201 return 0;
202}
203
204static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
205{
206 struct ixgbe_hw *hw = &adapter->hw;
207 u16 link_status = 0;
208 int err;
209
210 hw->bus.type = ixgbe_bus_type_pci_express;
211
212 /* Get the negotiated link width and speed from PCI config space of the
213 * parent, as this device is behind a switch
214 */
215 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
216
217 /* assume caller will handle error case */
218 if (err)
219 return err;
220
221 hw->bus.width = ixgbe_convert_bus_width(link_status);
222 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
223
224 return 0;
225}
226
227/**
228 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
229 * @hw: hw specific details
230 *
231 * This function is used by probe to determine whether a device's PCI-Express
232 * bandwidth details should be gathered from the parent bus instead of from the
233 * device. Used to ensure that various locations all have the correct device ID
234 * checks.
235 */
236static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
237{
238 switch (hw->device_id) {
239 case IXGBE_DEV_ID_82599_SFP_SF_QP:
240 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
241 return true;
242 default:
243 return false;
244 }
245}
246
247static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
248 int expected_gts)
249{
250 struct ixgbe_hw *hw = &adapter->hw;
251 struct pci_dev *pdev;
252
253 /* Some devices are not connected over PCIe and thus do not negotiate
254 * speed. These devices do not have valid bus info, and thus any report
255 * we generate may not be correct.
256 */
257 if (hw->bus.type == ixgbe_bus_type_internal)
258 return;
259
260 /* determine whether to use the parent device */
261 if (ixgbe_pcie_from_parent(&adapter->hw))
262 pdev = adapter->pdev->bus->parent->self;
263 else
264 pdev = adapter->pdev;
265
266 pcie_print_link_status(pdev);
267}
268
269static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
270{
271 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
272 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
273 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
274 queue_work(ixgbe_wq, &adapter->service_task);
275}
276
277static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
278{
279 struct ixgbe_adapter *adapter = hw->back;
280
281 if (!hw->hw_addr)
282 return;
283 hw->hw_addr = NULL;
284 e_dev_err("Adapter removed\n");
285 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
286 ixgbe_service_event_schedule(adapter);
287}
288
289static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
290{
291 u8 __iomem *reg_addr;
292 u32 value;
293 int i;
294
295 reg_addr = READ_ONCE(hw->hw_addr);
296 if (ixgbe_removed(reg_addr))
297 return IXGBE_FAILED_READ_REG;
298
299 /* Register read of 0xFFFFFFF can indicate the adapter has been removed,
300 * so perform several status register reads to determine if the adapter
301 * has been removed.
302 */
303 for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) {
304 value = readl(reg_addr + IXGBE_STATUS);
305 if (value != IXGBE_FAILED_READ_REG)
306 break;
307 mdelay(3);
308 }
309
310 if (value == IXGBE_FAILED_READ_REG)
311 ixgbe_remove_adapter(hw);
312 else
313 value = readl(reg_addr + reg);
314 return value;
315}
316
317/**
318 * ixgbe_read_reg - Read from device register
319 * @hw: hw specific details
320 * @reg: offset of register to read
321 *
322 * Returns : value read or IXGBE_FAILED_READ_REG if removed
323 *
324 * This function is used to read device registers. It checks for device
325 * removal by confirming any read that returns all ones by checking the
326 * status register value for all ones. This function avoids reading from
327 * the hardware if a removal was previously detected in which case it
328 * returns IXGBE_FAILED_READ_REG (all ones).
329 */
330u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
331{
332 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr);
333 u32 value;
334
335 if (ixgbe_removed(reg_addr))
336 return IXGBE_FAILED_READ_REG;
337 if (unlikely(hw->phy.nw_mng_if_sel &
338 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) {
339 struct ixgbe_adapter *adapter;
340 int i;
341
342 for (i = 0; i < 200; ++i) {
343 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY);
344 if (likely(!value))
345 goto writes_completed;
346 if (value == IXGBE_FAILED_READ_REG) {
347 ixgbe_remove_adapter(hw);
348 return IXGBE_FAILED_READ_REG;
349 }
350 udelay(5);
351 }
352
353 adapter = hw->back;
354 e_warn(hw, "register writes incomplete %08x\n", value);
355 }
356
357writes_completed:
358 value = readl(reg_addr + reg);
359 if (unlikely(value == IXGBE_FAILED_READ_REG))
360 value = ixgbe_check_remove(hw, reg);
361 return value;
362}
363
364static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
365{
366 u16 value;
367
368 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
369 if (value == IXGBE_FAILED_READ_CFG_WORD) {
370 ixgbe_remove_adapter(hw);
371 return true;
372 }
373 return false;
374}
375
376u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
377{
378 struct ixgbe_adapter *adapter = hw->back;
379 u16 value;
380
381 if (ixgbe_removed(hw->hw_addr))
382 return IXGBE_FAILED_READ_CFG_WORD;
383 pci_read_config_word(adapter->pdev, reg, &value);
384 if (value == IXGBE_FAILED_READ_CFG_WORD &&
385 ixgbe_check_cfg_remove(hw, adapter->pdev))
386 return IXGBE_FAILED_READ_CFG_WORD;
387 return value;
388}
389
390#ifdef CONFIG_PCI_IOV
391static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
392{
393 struct ixgbe_adapter *adapter = hw->back;
394 u32 value;
395
396 if (ixgbe_removed(hw->hw_addr))
397 return IXGBE_FAILED_READ_CFG_DWORD;
398 pci_read_config_dword(adapter->pdev, reg, &value);
399 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
400 ixgbe_check_cfg_remove(hw, adapter->pdev))
401 return IXGBE_FAILED_READ_CFG_DWORD;
402 return value;
403}
404#endif /* CONFIG_PCI_IOV */
405
406void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
407{
408 struct ixgbe_adapter *adapter = hw->back;
409
410 if (ixgbe_removed(hw->hw_addr))
411 return;
412 pci_write_config_word(adapter->pdev, reg, value);
413}
414
415static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
416{
417 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
418
419 /* flush memory to make sure state is correct before next watchdog */
420 smp_mb__before_atomic();
421 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
422}
423
424struct ixgbe_reg_info {
425 u32 ofs;
426 char *name;
427};
428
429static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
430
431 /* General Registers */
432 {IXGBE_CTRL, "CTRL"},
433 {IXGBE_STATUS, "STATUS"},
434 {IXGBE_CTRL_EXT, "CTRL_EXT"},
435
436 /* Interrupt Registers */
437 {IXGBE_EICR, "EICR"},
438
439 /* RX Registers */
440 {IXGBE_SRRCTL(0), "SRRCTL"},
441 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
442 {IXGBE_RDLEN(0), "RDLEN"},
443 {IXGBE_RDH(0), "RDH"},
444 {IXGBE_RDT(0), "RDT"},
445 {IXGBE_RXDCTL(0), "RXDCTL"},
446 {IXGBE_RDBAL(0), "RDBAL"},
447 {IXGBE_RDBAH(0), "RDBAH"},
448
449 /* TX Registers */
450 {IXGBE_TDBAL(0), "TDBAL"},
451 {IXGBE_TDBAH(0), "TDBAH"},
452 {IXGBE_TDLEN(0), "TDLEN"},
453 {IXGBE_TDH(0), "TDH"},
454 {IXGBE_TDT(0), "TDT"},
455 {IXGBE_TXDCTL(0), "TXDCTL"},
456
457 /* List Terminator */
458 { .name = NULL }
459};
460
461
462/*
463 * ixgbe_regdump - register printout routine
464 */
465static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
466{
467 int i;
468 char rname[16];
469 u32 regs[64];
470
471 switch (reginfo->ofs) {
472 case IXGBE_SRRCTL(0):
473 for (i = 0; i < 64; i++)
474 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
475 break;
476 case IXGBE_DCA_RXCTRL(0):
477 for (i = 0; i < 64; i++)
478 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
479 break;
480 case IXGBE_RDLEN(0):
481 for (i = 0; i < 64; i++)
482 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
483 break;
484 case IXGBE_RDH(0):
485 for (i = 0; i < 64; i++)
486 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
487 break;
488 case IXGBE_RDT(0):
489 for (i = 0; i < 64; i++)
490 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
491 break;
492 case IXGBE_RXDCTL(0):
493 for (i = 0; i < 64; i++)
494 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
495 break;
496 case IXGBE_RDBAL(0):
497 for (i = 0; i < 64; i++)
498 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
499 break;
500 case IXGBE_RDBAH(0):
501 for (i = 0; i < 64; i++)
502 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
503 break;
504 case IXGBE_TDBAL(0):
505 for (i = 0; i < 64; i++)
506 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
507 break;
508 case IXGBE_TDBAH(0):
509 for (i = 0; i < 64; i++)
510 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
511 break;
512 case IXGBE_TDLEN(0):
513 for (i = 0; i < 64; i++)
514 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
515 break;
516 case IXGBE_TDH(0):
517 for (i = 0; i < 64; i++)
518 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
519 break;
520 case IXGBE_TDT(0):
521 for (i = 0; i < 64; i++)
522 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
523 break;
524 case IXGBE_TXDCTL(0):
525 for (i = 0; i < 64; i++)
526 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
527 break;
528 default:
529 pr_info("%-15s %08x\n",
530 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs));
531 return;
532 }
533
534 i = 0;
535 while (i < 64) {
536 int j;
537 char buf[9 * 8 + 1];
538 char *p = buf;
539
540 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7);
541 for (j = 0; j < 8; j++)
542 p += sprintf(p, " %08x", regs[i++]);
543 pr_err("%-15s%s\n", rname, buf);
544 }
545
546}
547
548static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n)
549{
550 struct ixgbe_tx_buffer *tx_buffer;
551
552 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean];
553 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
554 n, ring->next_to_use, ring->next_to_clean,
555 (u64)dma_unmap_addr(tx_buffer, dma),
556 dma_unmap_len(tx_buffer, len),
557 tx_buffer->next_to_watch,
558 (u64)tx_buffer->time_stamp);
559}
560
561/*
562 * ixgbe_dump - Print registers, tx-rings and rx-rings
563 */
564static void ixgbe_dump(struct ixgbe_adapter *adapter)
565{
566 struct net_device *netdev = adapter->netdev;
567 struct ixgbe_hw *hw = &adapter->hw;
568 struct ixgbe_reg_info *reginfo;
569 int n = 0;
570 struct ixgbe_ring *ring;
571 struct ixgbe_tx_buffer *tx_buffer;
572 union ixgbe_adv_tx_desc *tx_desc;
573 struct my_u0 { u64 a; u64 b; } *u0;
574 struct ixgbe_ring *rx_ring;
575 union ixgbe_adv_rx_desc *rx_desc;
576 struct ixgbe_rx_buffer *rx_buffer_info;
577 int i = 0;
578
579 if (!netif_msg_hw(adapter))
580 return;
581
582 /* Print netdevice Info */
583 if (netdev) {
584 dev_info(&adapter->pdev->dev, "Net device Info\n");
585 pr_info("Device Name state "
586 "trans_start\n");
587 pr_info("%-15s %016lX %016lX\n",
588 netdev->name,
589 netdev->state,
590 dev_trans_start(netdev));
591 }
592
593 /* Print Registers */
594 dev_info(&adapter->pdev->dev, "Register Dump\n");
595 pr_info(" Register Name Value\n");
596 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
597 reginfo->name; reginfo++) {
598 ixgbe_regdump(hw, reginfo);
599 }
600
601 /* Print TX Ring Summary */
602 if (!netdev || !netif_running(netdev))
603 return;
604
605 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
606 pr_info(" %s %s %s %s\n",
607 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
608 "leng", "ntw", "timestamp");
609 for (n = 0; n < adapter->num_tx_queues; n++) {
610 ring = adapter->tx_ring[n];
611 ixgbe_print_buffer(ring, n);
612 }
613
614 for (n = 0; n < adapter->num_xdp_queues; n++) {
615 ring = adapter->xdp_ring[n];
616 ixgbe_print_buffer(ring, n);
617 }
618
619 /* Print TX Rings */
620 if (!netif_msg_tx_done(adapter))
621 goto rx_ring_summary;
622
623 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
624
625 /* Transmit Descriptor Formats
626 *
627 * 82598 Advanced Transmit Descriptor
628 * +--------------------------------------------------------------+
629 * 0 | Buffer Address [63:0] |
630 * +--------------------------------------------------------------+
631 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
632 * +--------------------------------------------------------------+
633 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
634 *
635 * 82598 Advanced Transmit Descriptor (Write-Back Format)
636 * +--------------------------------------------------------------+
637 * 0 | RSV [63:0] |
638 * +--------------------------------------------------------------+
639 * 8 | RSV | STA | NXTSEQ |
640 * +--------------------------------------------------------------+
641 * 63 36 35 32 31 0
642 *
643 * 82599+ Advanced Transmit Descriptor
644 * +--------------------------------------------------------------+
645 * 0 | Buffer Address [63:0] |
646 * +--------------------------------------------------------------+
647 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
648 * +--------------------------------------------------------------+
649 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
650 *
651 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
652 * +--------------------------------------------------------------+
653 * 0 | RSV [63:0] |
654 * +--------------------------------------------------------------+
655 * 8 | RSV | STA | RSV |
656 * +--------------------------------------------------------------+
657 * 63 36 35 32 31 0
658 */
659
660 for (n = 0; n < adapter->num_tx_queues; n++) {
661 ring = adapter->tx_ring[n];
662 pr_info("------------------------------------\n");
663 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index);
664 pr_info("------------------------------------\n");
665 pr_info("%s%s %s %s %s %s\n",
666 "T [desc] [address 63:0 ] ",
667 "[PlPOIdStDDt Ln] [bi->dma ] ",
668 "leng", "ntw", "timestamp", "bi->skb");
669
670 for (i = 0; ring->desc && (i < ring->count); i++) {
671 tx_desc = IXGBE_TX_DESC(ring, i);
672 tx_buffer = &ring->tx_buffer_info[i];
673 u0 = (struct my_u0 *)tx_desc;
674 if (dma_unmap_len(tx_buffer, len) > 0) {
675 const char *ring_desc;
676
677 if (i == ring->next_to_use &&
678 i == ring->next_to_clean)
679 ring_desc = " NTC/U";
680 else if (i == ring->next_to_use)
681 ring_desc = " NTU";
682 else if (i == ring->next_to_clean)
683 ring_desc = " NTC";
684 else
685 ring_desc = "";
686 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s",
687 i,
688 le64_to_cpu((__force __le64)u0->a),
689 le64_to_cpu((__force __le64)u0->b),
690 (u64)dma_unmap_addr(tx_buffer, dma),
691 dma_unmap_len(tx_buffer, len),
692 tx_buffer->next_to_watch,
693 (u64)tx_buffer->time_stamp,
694 tx_buffer->skb,
695 ring_desc);
696
697 if (netif_msg_pktdata(adapter) &&
698 tx_buffer->skb)
699 print_hex_dump(KERN_INFO, "",
700 DUMP_PREFIX_ADDRESS, 16, 1,
701 tx_buffer->skb->data,
702 dma_unmap_len(tx_buffer, len),
703 true);
704 }
705 }
706 }
707
708 /* Print RX Rings Summary */
709rx_ring_summary:
710 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
711 pr_info("Queue [NTU] [NTC]\n");
712 for (n = 0; n < adapter->num_rx_queues; n++) {
713 rx_ring = adapter->rx_ring[n];
714 pr_info("%5d %5X %5X\n",
715 n, rx_ring->next_to_use, rx_ring->next_to_clean);
716 }
717
718 /* Print RX Rings */
719 if (!netif_msg_rx_status(adapter))
720 return;
721
722 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
723
724 /* Receive Descriptor Formats
725 *
726 * 82598 Advanced Receive Descriptor (Read) Format
727 * 63 1 0
728 * +-----------------------------------------------------+
729 * 0 | Packet Buffer Address [63:1] |A0/NSE|
730 * +----------------------------------------------+------+
731 * 8 | Header Buffer Address [63:1] | DD |
732 * +-----------------------------------------------------+
733 *
734 *
735 * 82598 Advanced Receive Descriptor (Write-Back) Format
736 *
737 * 63 48 47 32 31 30 21 20 16 15 4 3 0
738 * +------------------------------------------------------+
739 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
740 * | Packet | IP | | | | Type | Type |
741 * | Checksum | Ident | | | | | |
742 * +------------------------------------------------------+
743 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
744 * +------------------------------------------------------+
745 * 63 48 47 32 31 20 19 0
746 *
747 * 82599+ Advanced Receive Descriptor (Read) Format
748 * 63 1 0
749 * +-----------------------------------------------------+
750 * 0 | Packet Buffer Address [63:1] |A0/NSE|
751 * +----------------------------------------------+------+
752 * 8 | Header Buffer Address [63:1] | DD |
753 * +-----------------------------------------------------+
754 *
755 *
756 * 82599+ Advanced Receive Descriptor (Write-Back) Format
757 *
758 * 63 48 47 32 31 30 21 20 17 16 4 3 0
759 * +------------------------------------------------------+
760 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
761 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
762 * |/ Flow Dir Flt ID | | | | | |
763 * +------------------------------------------------------+
764 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
765 * +------------------------------------------------------+
766 * 63 48 47 32 31 20 19 0
767 */
768
769 for (n = 0; n < adapter->num_rx_queues; n++) {
770 rx_ring = adapter->rx_ring[n];
771 pr_info("------------------------------------\n");
772 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
773 pr_info("------------------------------------\n");
774 pr_info("%s%s%s\n",
775 "R [desc] [ PktBuf A0] ",
776 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
777 "<-- Adv Rx Read format");
778 pr_info("%s%s%s\n",
779 "RWB[desc] [PcsmIpSHl PtRs] ",
780 "[vl er S cks ln] ---------------- [bi->skb ] ",
781 "<-- Adv Rx Write-Back format");
782
783 for (i = 0; i < rx_ring->count; i++) {
784 const char *ring_desc;
785
786 if (i == rx_ring->next_to_use)
787 ring_desc = " NTU";
788 else if (i == rx_ring->next_to_clean)
789 ring_desc = " NTC";
790 else
791 ring_desc = "";
792
793 rx_buffer_info = &rx_ring->rx_buffer_info[i];
794 rx_desc = IXGBE_RX_DESC(rx_ring, i);
795 u0 = (struct my_u0 *)rx_desc;
796 if (rx_desc->wb.upper.length) {
797 /* Descriptor Done */
798 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n",
799 i,
800 le64_to_cpu((__force __le64)u0->a),
801 le64_to_cpu((__force __le64)u0->b),
802 rx_buffer_info->skb,
803 ring_desc);
804 } else {
805 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n",
806 i,
807 le64_to_cpu((__force __le64)u0->a),
808 le64_to_cpu((__force __le64)u0->b),
809 (u64)rx_buffer_info->dma,
810 rx_buffer_info->skb,
811 ring_desc);
812
813 if (netif_msg_pktdata(adapter) &&
814 rx_buffer_info->dma) {
815 print_hex_dump(KERN_INFO, "",
816 DUMP_PREFIX_ADDRESS, 16, 1,
817 page_address(rx_buffer_info->page) +
818 rx_buffer_info->page_offset,
819 ixgbe_rx_bufsz(rx_ring), true);
820 }
821 }
822 }
823 }
824}
825
826static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
827{
828 u32 ctrl_ext;
829
830 /* Let firmware take over control of h/w */
831 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
832 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
833 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
834}
835
836static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
837{
838 u32 ctrl_ext;
839
840 /* Let firmware know the driver has taken over */
841 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
842 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
843 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
844}
845
846/**
847 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
848 * @adapter: pointer to adapter struct
849 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
850 * @queue: queue to map the corresponding interrupt to
851 * @msix_vector: the vector to map to the corresponding queue
852 *
853 */
854static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
855 u8 queue, u8 msix_vector)
856{
857 u32 ivar, index;
858 struct ixgbe_hw *hw = &adapter->hw;
859 switch (hw->mac.type) {
860 case ixgbe_mac_82598EB:
861 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
862 if (direction == -1)
863 direction = 0;
864 index = (((direction * 64) + queue) >> 2) & 0x1F;
865 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
866 ivar &= ~(0xFF << (8 * (queue & 0x3)));
867 ivar |= (msix_vector << (8 * (queue & 0x3)));
868 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
869 break;
870 case ixgbe_mac_82599EB:
871 case ixgbe_mac_X540:
872 case ixgbe_mac_X550:
873 case ixgbe_mac_X550EM_x:
874 case ixgbe_mac_x550em_a:
875 if (direction == -1) {
876 /* other causes */
877 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
878 index = ((queue & 1) * 8);
879 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
880 ivar &= ~(0xFF << index);
881 ivar |= (msix_vector << index);
882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
883 break;
884 } else {
885 /* tx or rx causes */
886 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
887 index = ((16 * (queue & 1)) + (8 * direction));
888 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
889 ivar &= ~(0xFF << index);
890 ivar |= (msix_vector << index);
891 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
892 break;
893 }
894 default:
895 break;
896 }
897}
898
899void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
900 u64 qmask)
901{
902 u32 mask;
903
904 switch (adapter->hw.mac.type) {
905 case ixgbe_mac_82598EB:
906 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
907 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
908 break;
909 case ixgbe_mac_82599EB:
910 case ixgbe_mac_X540:
911 case ixgbe_mac_X550:
912 case ixgbe_mac_X550EM_x:
913 case ixgbe_mac_x550em_a:
914 mask = (qmask & 0xFFFFFFFF);
915 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
916 mask = (qmask >> 32);
917 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
918 break;
919 default:
920 break;
921 }
922}
923
924static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
925{
926 struct ixgbe_hw *hw = &adapter->hw;
927 struct ixgbe_hw_stats *hwstats = &adapter->stats;
928 int i;
929 u32 data;
930
931 if ((hw->fc.current_mode != ixgbe_fc_full) &&
932 (hw->fc.current_mode != ixgbe_fc_rx_pause))
933 return;
934
935 switch (hw->mac.type) {
936 case ixgbe_mac_82598EB:
937 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
938 break;
939 default:
940 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
941 }
942 hwstats->lxoffrxc += data;
943
944 /* refill credits (no tx hang) if we received xoff */
945 if (!data)
946 return;
947
948 for (i = 0; i < adapter->num_tx_queues; i++)
949 clear_bit(__IXGBE_HANG_CHECK_ARMED,
950 &adapter->tx_ring[i]->state);
951
952 for (i = 0; i < adapter->num_xdp_queues; i++)
953 clear_bit(__IXGBE_HANG_CHECK_ARMED,
954 &adapter->xdp_ring[i]->state);
955}
956
957static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
958{
959 struct ixgbe_hw *hw = &adapter->hw;
960 struct ixgbe_hw_stats *hwstats = &adapter->stats;
961 u32 xoff[8] = {0};
962 u8 tc;
963 int i;
964 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
965
966 if (adapter->ixgbe_ieee_pfc)
967 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
968
969 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
970 ixgbe_update_xoff_rx_lfc(adapter);
971 return;
972 }
973
974 /* update stats for each tc, only valid with PFC enabled */
975 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
976 u32 pxoffrxc;
977
978 switch (hw->mac.type) {
979 case ixgbe_mac_82598EB:
980 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
981 break;
982 default:
983 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
984 }
985 hwstats->pxoffrxc[i] += pxoffrxc;
986 /* Get the TC for given UP */
987 tc = netdev_get_prio_tc_map(adapter->netdev, i);
988 xoff[tc] += pxoffrxc;
989 }
990
991 /* disarm tx queues that have received xoff frames */
992 for (i = 0; i < adapter->num_tx_queues; i++) {
993 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
994
995 tc = tx_ring->dcb_tc;
996 if (xoff[tc])
997 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
998 }
999
1000 for (i = 0; i < adapter->num_xdp_queues; i++) {
1001 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i];
1002
1003 tc = xdp_ring->dcb_tc;
1004 if (xoff[tc])
1005 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state);
1006 }
1007}
1008
1009static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
1010{
1011 return ring->stats.packets;
1012}
1013
1014static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1015{
1016 unsigned int head, tail;
1017
1018 head = ring->next_to_clean;
1019 tail = ring->next_to_use;
1020
1021 return ((head <= tail) ? tail : tail + ring->count) - head;
1022}
1023
1024static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1025{
1026 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1027 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1028 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
1029
1030 clear_check_for_tx_hang(tx_ring);
1031
1032 /*
1033 * Check for a hung queue, but be thorough. This verifies
1034 * that a transmit has been completed since the previous
1035 * check AND there is at least one packet pending. The
1036 * ARMED bit is set to indicate a potential hang. The
1037 * bit is cleared if a pause frame is received to remove
1038 * false hang detection due to PFC or 802.3x frames. By
1039 * requiring this to fail twice we avoid races with
1040 * pfc clearing the ARMED bit and conditions where we
1041 * run the check_tx_hang logic with a transmit completion
1042 * pending but without time to complete it yet.
1043 */
1044 if (tx_done_old == tx_done && tx_pending)
1045 /* make sure it is true for two checks in a row */
1046 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1047 &tx_ring->state);
1048 /* update completed stats and continue */
1049 tx_ring->tx_stats.tx_done_old = tx_done;
1050 /* reset the countdown */
1051 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1052
1053 return false;
1054}
1055
1056/**
1057 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1058 * @adapter: driver private struct
1059 **/
1060static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1061{
1062
1063 /* Do the reset outside of interrupt context */
1064 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1065 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
1066 e_warn(drv, "initiating reset due to tx timeout\n");
1067 ixgbe_service_event_schedule(adapter);
1068 }
1069}
1070
1071/**
1072 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate
1073 * @netdev: network interface device structure
1074 * @queue_index: Tx queue to set
1075 * @maxrate: desired maximum transmit bitrate
1076 **/
1077static int ixgbe_tx_maxrate(struct net_device *netdev,
1078 int queue_index, u32 maxrate)
1079{
1080 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1081 struct ixgbe_hw *hw = &adapter->hw;
1082 u32 bcnrc_val = ixgbe_link_mbps(adapter);
1083
1084 if (!maxrate)
1085 return 0;
1086
1087 /* Calculate the rate factor values to set */
1088 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT;
1089 bcnrc_val /= maxrate;
1090
1091 /* clear everything but the rate factor */
1092 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK |
1093 IXGBE_RTTBCNRC_RF_DEC_MASK;
1094
1095 /* enable the rate scheduler */
1096 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA;
1097
1098 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index);
1099 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
1100
1101 return 0;
1102}
1103
1104/**
1105 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
1106 * @q_vector: structure containing interrupt and ring information
1107 * @tx_ring: tx ring to clean
1108 * @napi_budget: Used to determine if we are in netpoll
1109 **/
1110static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
1111 struct ixgbe_ring *tx_ring, int napi_budget)
1112{
1113 struct ixgbe_adapter *adapter = q_vector->adapter;
1114 struct ixgbe_tx_buffer *tx_buffer;
1115 union ixgbe_adv_tx_desc *tx_desc;
1116 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0;
1117 unsigned int budget = q_vector->tx.work_limit;
1118 unsigned int i = tx_ring->next_to_clean;
1119
1120 if (test_bit(__IXGBE_DOWN, &adapter->state))
1121 return true;
1122
1123 tx_buffer = &tx_ring->tx_buffer_info[i];
1124 tx_desc = IXGBE_TX_DESC(tx_ring, i);
1125 i -= tx_ring->count;
1126
1127 do {
1128 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1129
1130 /* if next_to_watch is not set then there is no work pending */
1131 if (!eop_desc)
1132 break;
1133
1134 /* prevent any other reads prior to eop_desc */
1135 smp_rmb();
1136
1137 /* if DD is not set pending work has not been completed */
1138 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1139 break;
1140
1141 /* clear next_to_watch to prevent false hangs */
1142 tx_buffer->next_to_watch = NULL;
1143
1144 /* update the statistics for this packet */
1145 total_bytes += tx_buffer->bytecount;
1146 total_packets += tx_buffer->gso_segs;
1147 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC)
1148 total_ipsec++;
1149
1150 /* free the skb */
1151 if (ring_is_xdp(tx_ring))
1152 xdp_return_frame(tx_buffer->xdpf);
1153 else
1154 napi_consume_skb(tx_buffer->skb, napi_budget);
1155
1156 /* unmap skb header data */
1157 dma_unmap_single(tx_ring->dev,
1158 dma_unmap_addr(tx_buffer, dma),
1159 dma_unmap_len(tx_buffer, len),
1160 DMA_TO_DEVICE);
1161
1162 /* clear tx_buffer data */
1163 dma_unmap_len_set(tx_buffer, len, 0);
1164
1165 /* unmap remaining buffers */
1166 while (tx_desc != eop_desc) {
1167 tx_buffer++;
1168 tx_desc++;
1169 i++;
1170 if (unlikely(!i)) {
1171 i -= tx_ring->count;
1172 tx_buffer = tx_ring->tx_buffer_info;
1173 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1174 }
1175
1176 /* unmap any remaining paged data */
1177 if (dma_unmap_len(tx_buffer, len)) {
1178 dma_unmap_page(tx_ring->dev,
1179 dma_unmap_addr(tx_buffer, dma),
1180 dma_unmap_len(tx_buffer, len),
1181 DMA_TO_DEVICE);
1182 dma_unmap_len_set(tx_buffer, len, 0);
1183 }
1184 }
1185
1186 /* move us one more past the eop_desc for start of next pkt */
1187 tx_buffer++;
1188 tx_desc++;
1189 i++;
1190 if (unlikely(!i)) {
1191 i -= tx_ring->count;
1192 tx_buffer = tx_ring->tx_buffer_info;
1193 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1194 }
1195
1196 /* issue prefetch for next Tx descriptor */
1197 prefetch(tx_desc);
1198
1199 /* update budget accounting */
1200 budget--;
1201 } while (likely(budget));
1202
1203 i += tx_ring->count;
1204 tx_ring->next_to_clean = i;
1205 u64_stats_update_begin(&tx_ring->syncp);
1206 tx_ring->stats.bytes += total_bytes;
1207 tx_ring->stats.packets += total_packets;
1208 u64_stats_update_end(&tx_ring->syncp);
1209 q_vector->tx.total_bytes += total_bytes;
1210 q_vector->tx.total_packets += total_packets;
1211 adapter->tx_ipsec += total_ipsec;
1212
1213 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1214 /* schedule immediate reset if we believe we hung */
1215 struct ixgbe_hw *hw = &adapter->hw;
1216 e_err(drv, "Detected Tx Unit Hang %s\n"
1217 " Tx Queue <%d>\n"
1218 " TDH, TDT <%x>, <%x>\n"
1219 " next_to_use <%x>\n"
1220 " next_to_clean <%x>\n"
1221 "tx_buffer_info[next_to_clean]\n"
1222 " time_stamp <%lx>\n"
1223 " jiffies <%lx>\n",
1224 ring_is_xdp(tx_ring) ? "(XDP)" : "",
1225 tx_ring->queue_index,
1226 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1227 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1228 tx_ring->next_to_use, i,
1229 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1230
1231 if (!ring_is_xdp(tx_ring))
1232 netif_stop_subqueue(tx_ring->netdev,
1233 tx_ring->queue_index);
1234
1235 e_info(probe,
1236 "tx hang %d detected on queue %d, resetting adapter\n",
1237 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1238
1239 /* schedule immediate reset if we believe we hung */
1240 ixgbe_tx_timeout_reset(adapter);
1241
1242 /* the adapter is about to reset, no point in enabling stuff */
1243 return true;
1244 }
1245
1246 if (ring_is_xdp(tx_ring))
1247 return !!budget;
1248
1249 netdev_tx_completed_queue(txring_txq(tx_ring),
1250 total_packets, total_bytes);
1251
1252#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1253 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1254 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1255 /* Make sure that anybody stopping the queue after this
1256 * sees the new next_to_clean.
1257 */
1258 smp_mb();
1259 if (__netif_subqueue_stopped(tx_ring->netdev,
1260 tx_ring->queue_index)
1261 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1262 netif_wake_subqueue(tx_ring->netdev,
1263 tx_ring->queue_index);
1264 ++tx_ring->tx_stats.restart_queue;
1265 }
1266 }
1267
1268 return !!budget;
1269}
1270
1271#ifdef CONFIG_IXGBE_DCA
1272static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1273 struct ixgbe_ring *tx_ring,
1274 int cpu)
1275{
1276 struct ixgbe_hw *hw = &adapter->hw;
1277 u32 txctrl = 0;
1278 u16 reg_offset;
1279
1280 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1281 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1282
1283 switch (hw->mac.type) {
1284 case ixgbe_mac_82598EB:
1285 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1286 break;
1287 case ixgbe_mac_82599EB:
1288 case ixgbe_mac_X540:
1289 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1290 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1291 break;
1292 default:
1293 /* for unknown hardware do not write register */
1294 return;
1295 }
1296
1297 /*
1298 * We can enable relaxed ordering for reads, but not writes when
1299 * DCA is enabled. This is due to a known issue in some chipsets
1300 * which will cause the DCA tag to be cleared.
1301 */
1302 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1303 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1304 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1305
1306 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1307}
1308
1309static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1310 struct ixgbe_ring *rx_ring,
1311 int cpu)
1312{
1313 struct ixgbe_hw *hw = &adapter->hw;
1314 u32 rxctrl = 0;
1315 u8 reg_idx = rx_ring->reg_idx;
1316
1317 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1318 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1319
1320 switch (hw->mac.type) {
1321 case ixgbe_mac_82599EB:
1322 case ixgbe_mac_X540:
1323 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1324 break;
1325 default:
1326 break;
1327 }
1328
1329 /*
1330 * We can enable relaxed ordering for reads, but not writes when
1331 * DCA is enabled. This is due to a known issue in some chipsets
1332 * which will cause the DCA tag to be cleared.
1333 */
1334 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1335 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
1336 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1337
1338 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1339}
1340
1341static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1342{
1343 struct ixgbe_adapter *adapter = q_vector->adapter;
1344 struct ixgbe_ring *ring;
1345 int cpu = get_cpu();
1346
1347 if (q_vector->cpu == cpu)
1348 goto out_no_update;
1349
1350 ixgbe_for_each_ring(ring, q_vector->tx)
1351 ixgbe_update_tx_dca(adapter, ring, cpu);
1352
1353 ixgbe_for_each_ring(ring, q_vector->rx)
1354 ixgbe_update_rx_dca(adapter, ring, cpu);
1355
1356 q_vector->cpu = cpu;
1357out_no_update:
1358 put_cpu();
1359}
1360
1361static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1362{
1363 int i;
1364
1365 /* always use CB2 mode, difference is masked in the CB driver */
1366 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1367 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1368 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1369 else
1370 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1371 IXGBE_DCA_CTRL_DCA_DISABLE);
1372
1373 for (i = 0; i < adapter->num_q_vectors; i++) {
1374 adapter->q_vector[i]->cpu = -1;
1375 ixgbe_update_dca(adapter->q_vector[i]);
1376 }
1377}
1378
1379static int __ixgbe_notify_dca(struct device *dev, void *data)
1380{
1381 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1382 unsigned long event = *(unsigned long *)data;
1383
1384 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1385 return 0;
1386
1387 switch (event) {
1388 case DCA_PROVIDER_ADD:
1389 /* if we're already enabled, don't do it again */
1390 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1391 break;
1392 if (dca_add_requester(dev) == 0) {
1393 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1394 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1395 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1396 break;
1397 }
1398 fallthrough; /* DCA is disabled. */
1399 case DCA_PROVIDER_REMOVE:
1400 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1401 dca_remove_requester(dev);
1402 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1403 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1404 IXGBE_DCA_CTRL_DCA_DISABLE);
1405 }
1406 break;
1407 }
1408
1409 return 0;
1410}
1411
1412#endif /* CONFIG_IXGBE_DCA */
1413
1414#define IXGBE_RSS_L4_TYPES_MASK \
1415 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1416 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1417 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1418 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1419
1420static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1421 union ixgbe_adv_rx_desc *rx_desc,
1422 struct sk_buff *skb)
1423{
1424 u16 rss_type;
1425
1426 if (!(ring->netdev->features & NETIF_F_RXHASH))
1427 return;
1428
1429 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1430 IXGBE_RXDADV_RSSTYPE_MASK;
1431
1432 if (!rss_type)
1433 return;
1434
1435 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1436 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1437 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
1438}
1439
1440#ifdef IXGBE_FCOE
1441/**
1442 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1443 * @ring: structure containing ring specific data
1444 * @rx_desc: advanced rx descriptor
1445 *
1446 * Returns : true if it is FCoE pkt
1447 */
1448static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1449 union ixgbe_adv_rx_desc *rx_desc)
1450{
1451 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1452
1453 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1454 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1455 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1456 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1457}
1458
1459#endif /* IXGBE_FCOE */
1460/**
1461 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1462 * @ring: structure containing ring specific data
1463 * @rx_desc: current Rx descriptor being processed
1464 * @skb: skb currently being received and modified
1465 **/
1466static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1467 union ixgbe_adv_rx_desc *rx_desc,
1468 struct sk_buff *skb)
1469{
1470 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1471 bool encap_pkt = false;
1472
1473 skb_checksum_none_assert(skb);
1474
1475 /* Rx csum disabled */
1476 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1477 return;
1478
1479 /* check for VXLAN and Geneve packets */
1480 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) {
1481 encap_pkt = true;
1482 skb->encapsulation = 1;
1483 }
1484
1485 /* if IP and error */
1486 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1487 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1488 ring->rx_stats.csum_err++;
1489 return;
1490 }
1491
1492 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1493 return;
1494
1495 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1496 /*
1497 * 82599 errata, UDP frames with a 0 checksum can be marked as
1498 * checksum errors.
1499 */
1500 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1501 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1502 return;
1503
1504 ring->rx_stats.csum_err++;
1505 return;
1506 }
1507
1508 /* It must be a TCP or UDP packet with a valid checksum */
1509 skb->ip_summed = CHECKSUM_UNNECESSARY;
1510 if (encap_pkt) {
1511 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1512 return;
1513
1514 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1515 skb->ip_summed = CHECKSUM_NONE;
1516 return;
1517 }
1518 /* If we checked the outer header let the stack know */
1519 skb->csum_level = 1;
1520 }
1521}
1522
1523static inline unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring)
1524{
1525 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0;
1526}
1527
1528static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1529 struct ixgbe_rx_buffer *bi)
1530{
1531 struct page *page = bi->page;
1532 dma_addr_t dma;
1533
1534 /* since we are recycling buffers we should seldom need to alloc */
1535 if (likely(page))
1536 return true;
1537
1538 /* alloc new page for storage */
1539 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1540 if (unlikely(!page)) {
1541 rx_ring->rx_stats.alloc_rx_page_failed++;
1542 return false;
1543 }
1544
1545 /* map page for use */
1546 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1547 ixgbe_rx_pg_size(rx_ring),
1548 DMA_FROM_DEVICE,
1549 IXGBE_RX_DMA_ATTR);
1550
1551 /*
1552 * if mapping failed free memory back to system since
1553 * there isn't much point in holding memory we can't use
1554 */
1555 if (dma_mapping_error(rx_ring->dev, dma)) {
1556 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1557
1558 rx_ring->rx_stats.alloc_rx_page_failed++;
1559 return false;
1560 }
1561
1562 bi->dma = dma;
1563 bi->page = page;
1564 bi->page_offset = ixgbe_rx_offset(rx_ring);
1565 page_ref_add(page, USHRT_MAX - 1);
1566 bi->pagecnt_bias = USHRT_MAX;
1567 rx_ring->rx_stats.alloc_rx_page++;
1568
1569 return true;
1570}
1571
1572/**
1573 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1574 * @rx_ring: ring to place buffers on
1575 * @cleaned_count: number of buffers to replace
1576 **/
1577void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1578{
1579 union ixgbe_adv_rx_desc *rx_desc;
1580 struct ixgbe_rx_buffer *bi;
1581 u16 i = rx_ring->next_to_use;
1582 u16 bufsz;
1583
1584 /* nothing to do */
1585 if (!cleaned_count)
1586 return;
1587
1588 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1589 bi = &rx_ring->rx_buffer_info[i];
1590 i -= rx_ring->count;
1591
1592 bufsz = ixgbe_rx_bufsz(rx_ring);
1593
1594 do {
1595 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1596 break;
1597
1598 /* sync the buffer for use by the device */
1599 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
1600 bi->page_offset, bufsz,
1601 DMA_FROM_DEVICE);
1602
1603 /*
1604 * Refresh the desc even if buffer_addrs didn't change
1605 * because each write-back erases this info.
1606 */
1607 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1608
1609 rx_desc++;
1610 bi++;
1611 i++;
1612 if (unlikely(!i)) {
1613 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1614 bi = rx_ring->rx_buffer_info;
1615 i -= rx_ring->count;
1616 }
1617
1618 /* clear the length for the next_to_use descriptor */
1619 rx_desc->wb.upper.length = 0;
1620
1621 cleaned_count--;
1622 } while (cleaned_count);
1623
1624 i += rx_ring->count;
1625
1626 if (rx_ring->next_to_use != i) {
1627 rx_ring->next_to_use = i;
1628
1629 /* update next to alloc since we have filled the ring */
1630 rx_ring->next_to_alloc = i;
1631
1632 /* Force memory writes to complete before letting h/w
1633 * know there are new descriptors to fetch. (Only
1634 * applicable for weak-ordered memory model archs,
1635 * such as IA-64).
1636 */
1637 wmb();
1638 writel(i, rx_ring->tail);
1639 }
1640}
1641
1642static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1643 struct sk_buff *skb)
1644{
1645 u16 hdr_len = skb_headlen(skb);
1646
1647 /* set gso_size to avoid messing up TCP MSS */
1648 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1649 IXGBE_CB(skb)->append_cnt);
1650 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1651}
1652
1653static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1654 struct sk_buff *skb)
1655{
1656 /* if append_cnt is 0 then frame is not RSC */
1657 if (!IXGBE_CB(skb)->append_cnt)
1658 return;
1659
1660 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1661 rx_ring->rx_stats.rsc_flush++;
1662
1663 ixgbe_set_rsc_gso_size(rx_ring, skb);
1664
1665 /* gso_size is computed using append_cnt so always clear it last */
1666 IXGBE_CB(skb)->append_cnt = 0;
1667}
1668
1669/**
1670 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1671 * @rx_ring: rx descriptor ring packet is being transacted on
1672 * @rx_desc: pointer to the EOP Rx descriptor
1673 * @skb: pointer to current skb being populated
1674 *
1675 * This function checks the ring, descriptor, and packet information in
1676 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1677 * other fields within the skb.
1678 **/
1679void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1680 union ixgbe_adv_rx_desc *rx_desc,
1681 struct sk_buff *skb)
1682{
1683 struct net_device *dev = rx_ring->netdev;
1684 u32 flags = rx_ring->q_vector->adapter->flags;
1685
1686 ixgbe_update_rsc_stats(rx_ring, skb);
1687
1688 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1689
1690 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1691
1692 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED))
1693 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
1694
1695 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1696 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1697 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1698 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1699 }
1700
1701 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP))
1702 ixgbe_ipsec_rx(rx_ring, rx_desc, skb);
1703
1704 /* record Rx queue, or update MACVLAN statistics */
1705 if (netif_is_ixgbe(dev))
1706 skb_record_rx_queue(skb, rx_ring->queue_index);
1707 else
1708 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true,
1709 false);
1710
1711 skb->protocol = eth_type_trans(skb, dev);
1712}
1713
1714void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1715 struct sk_buff *skb)
1716{
1717 napi_gro_receive(&q_vector->napi, skb);
1718}
1719
1720/**
1721 * ixgbe_is_non_eop - process handling of non-EOP buffers
1722 * @rx_ring: Rx ring being processed
1723 * @rx_desc: Rx descriptor for current buffer
1724 * @skb: Current socket buffer containing buffer in progress
1725 *
1726 * This function updates next to clean. If the buffer is an EOP buffer
1727 * this function exits returning false, otherwise it will place the
1728 * sk_buff in the next buffer to be chained and return true indicating
1729 * that this is in fact a non-EOP buffer.
1730 **/
1731static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1732 union ixgbe_adv_rx_desc *rx_desc,
1733 struct sk_buff *skb)
1734{
1735 u32 ntc = rx_ring->next_to_clean + 1;
1736
1737 /* fetch, update, and store next to clean */
1738 ntc = (ntc < rx_ring->count) ? ntc : 0;
1739 rx_ring->next_to_clean = ntc;
1740
1741 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1742
1743 /* update RSC append count if present */
1744 if (ring_is_rsc_enabled(rx_ring)) {
1745 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1746 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1747
1748 if (unlikely(rsc_enabled)) {
1749 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1750
1751 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1752 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1753
1754 /* update ntc based on RSC value */
1755 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1756 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1757 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1758 }
1759 }
1760
1761 /* if we are the last buffer then there is nothing else to do */
1762 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1763 return false;
1764
1765 /* place skb in next buffer to be received */
1766 rx_ring->rx_buffer_info[ntc].skb = skb;
1767 rx_ring->rx_stats.non_eop_descs++;
1768
1769 return true;
1770}
1771
1772/**
1773 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1774 * @rx_ring: rx descriptor ring packet is being transacted on
1775 * @skb: pointer to current skb being adjusted
1776 *
1777 * This function is an ixgbe specific version of __pskb_pull_tail. The
1778 * main difference between this version and the original function is that
1779 * this function can make several assumptions about the state of things
1780 * that allow for significant optimizations versus the standard function.
1781 * As a result we can do things like drop a frag and maintain an accurate
1782 * truesize for the skb.
1783 */
1784static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1785 struct sk_buff *skb)
1786{
1787 skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
1788 unsigned char *va;
1789 unsigned int pull_len;
1790
1791 /*
1792 * it is valid to use page_address instead of kmap since we are
1793 * working with pages allocated out of the lomem pool per
1794 * alloc_page(GFP_ATOMIC)
1795 */
1796 va = skb_frag_address(frag);
1797
1798 /*
1799 * we need the header to contain the greater of either ETH_HLEN or
1800 * 60 bytes if the skb->len is less than 60 for skb_pad.
1801 */
1802 pull_len = eth_get_headlen(skb->dev, va, IXGBE_RX_HDR_SIZE);
1803
1804 /* align pull length to size of long to optimize memcpy performance */
1805 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1806
1807 /* update all of the pointers */
1808 skb_frag_size_sub(frag, pull_len);
1809 skb_frag_off_add(frag, pull_len);
1810 skb->data_len -= pull_len;
1811 skb->tail += pull_len;
1812}
1813
1814/**
1815 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1816 * @rx_ring: rx descriptor ring packet is being transacted on
1817 * @skb: pointer to current skb being updated
1818 *
1819 * This function provides a basic DMA sync up for the first fragment of an
1820 * skb. The reason for doing this is that the first fragment cannot be
1821 * unmapped until we have reached the end of packet descriptor for a buffer
1822 * chain.
1823 */
1824static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1825 struct sk_buff *skb)
1826{
1827 if (ring_uses_build_skb(rx_ring)) {
1828 unsigned long offset = (unsigned long)(skb->data) & ~PAGE_MASK;
1829
1830 dma_sync_single_range_for_cpu(rx_ring->dev,
1831 IXGBE_CB(skb)->dma,
1832 offset,
1833 skb_headlen(skb),
1834 DMA_FROM_DEVICE);
1835 } else {
1836 skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
1837
1838 dma_sync_single_range_for_cpu(rx_ring->dev,
1839 IXGBE_CB(skb)->dma,
1840 skb_frag_off(frag),
1841 skb_frag_size(frag),
1842 DMA_FROM_DEVICE);
1843 }
1844
1845 /* If the page was released, just unmap it. */
1846 if (unlikely(IXGBE_CB(skb)->page_released)) {
1847 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma,
1848 ixgbe_rx_pg_size(rx_ring),
1849 DMA_FROM_DEVICE,
1850 IXGBE_RX_DMA_ATTR);
1851 }
1852}
1853
1854/**
1855 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1856 * @rx_ring: rx descriptor ring packet is being transacted on
1857 * @rx_desc: pointer to the EOP Rx descriptor
1858 * @skb: pointer to current skb being fixed
1859 *
1860 * Check if the skb is valid in the XDP case it will be an error pointer.
1861 * Return true in this case to abort processing and advance to next
1862 * descriptor.
1863 *
1864 * Check for corrupted packet headers caused by senders on the local L2
1865 * embedded NIC switch not setting up their Tx Descriptors right. These
1866 * should be very rare.
1867 *
1868 * Also address the case where we are pulling data in on pages only
1869 * and as such no data is present in the skb header.
1870 *
1871 * In addition if skb is not at least 60 bytes we need to pad it so that
1872 * it is large enough to qualify as a valid Ethernet frame.
1873 *
1874 * Returns true if an error was encountered and skb was freed.
1875 **/
1876bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1877 union ixgbe_adv_rx_desc *rx_desc,
1878 struct sk_buff *skb)
1879{
1880 struct net_device *netdev = rx_ring->netdev;
1881
1882 /* XDP packets use error pointer so abort at this point */
1883 if (IS_ERR(skb))
1884 return true;
1885
1886 /* Verify netdev is present, and that packet does not have any
1887 * errors that would be unacceptable to the netdev.
1888 */
1889 if (!netdev ||
1890 (unlikely(ixgbe_test_staterr(rx_desc,
1891 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1892 !(netdev->features & NETIF_F_RXALL)))) {
1893 dev_kfree_skb_any(skb);
1894 return true;
1895 }
1896
1897 /* place header in linear portion of buffer */
1898 if (!skb_headlen(skb))
1899 ixgbe_pull_tail(rx_ring, skb);
1900
1901#ifdef IXGBE_FCOE
1902 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1903 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1904 return false;
1905
1906#endif
1907 /* if eth_skb_pad returns an error the skb was freed */
1908 if (eth_skb_pad(skb))
1909 return true;
1910
1911 return false;
1912}
1913
1914/**
1915 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1916 * @rx_ring: rx descriptor ring to store buffers on
1917 * @old_buff: donor buffer to have page reused
1918 *
1919 * Synchronizes page for reuse by the adapter
1920 **/
1921static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1922 struct ixgbe_rx_buffer *old_buff)
1923{
1924 struct ixgbe_rx_buffer *new_buff;
1925 u16 nta = rx_ring->next_to_alloc;
1926
1927 new_buff = &rx_ring->rx_buffer_info[nta];
1928
1929 /* update, and store next to alloc */
1930 nta++;
1931 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1932
1933 /* Transfer page from old buffer to new buffer.
1934 * Move each member individually to avoid possible store
1935 * forwarding stalls and unnecessary copy of skb.
1936 */
1937 new_buff->dma = old_buff->dma;
1938 new_buff->page = old_buff->page;
1939 new_buff->page_offset = old_buff->page_offset;
1940 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
1941}
1942
1943static inline bool ixgbe_page_is_reserved(struct page *page)
1944{
1945 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
1946}
1947
1948static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer)
1949{
1950 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1951 struct page *page = rx_buffer->page;
1952
1953 /* avoid re-using remote pages */
1954 if (unlikely(ixgbe_page_is_reserved(page)))
1955 return false;
1956
1957#if (PAGE_SIZE < 8192)
1958 /* if we are only owner of page we can reuse it */
1959 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1))
1960 return false;
1961#else
1962 /* The last offset is a bit aggressive in that we assume the
1963 * worst case of FCoE being enabled and using a 3K buffer.
1964 * However this should have minimal impact as the 1K extra is
1965 * still less than one buffer in size.
1966 */
1967#define IXGBE_LAST_OFFSET \
1968 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K)
1969 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET)
1970 return false;
1971#endif
1972
1973 /* If we have drained the page fragment pool we need to update
1974 * the pagecnt_bias and page count so that we fully restock the
1975 * number of references the driver holds.
1976 */
1977 if (unlikely(pagecnt_bias == 1)) {
1978 page_ref_add(page, USHRT_MAX - 1);
1979 rx_buffer->pagecnt_bias = USHRT_MAX;
1980 }
1981
1982 return true;
1983}
1984
1985/**
1986 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1987 * @rx_ring: rx descriptor ring to transact packets on
1988 * @rx_buffer: buffer containing page to add
1989 * @skb: sk_buff to place the data into
1990 * @size: size of data in rx_buffer
1991 *
1992 * This function will add the data contained in rx_buffer->page to the skb.
1993 * This is done either through a direct copy if the data in the buffer is
1994 * less than the skb header size, otherwise it will just attach the page as
1995 * a frag to the skb.
1996 *
1997 * The function will then update the page offset if necessary and return
1998 * true if the buffer can be reused by the adapter.
1999 **/
2000static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
2001 struct ixgbe_rx_buffer *rx_buffer,
2002 struct sk_buff *skb,
2003 unsigned int size)
2004{
2005#if (PAGE_SIZE < 8192)
2006 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2007#else
2008 unsigned int truesize = ring_uses_build_skb(rx_ring) ?
2009 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) :
2010 SKB_DATA_ALIGN(size);
2011#endif
2012 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
2013 rx_buffer->page_offset, size, truesize);
2014#if (PAGE_SIZE < 8192)
2015 rx_buffer->page_offset ^= truesize;
2016#else
2017 rx_buffer->page_offset += truesize;
2018#endif
2019}
2020
2021static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring,
2022 union ixgbe_adv_rx_desc *rx_desc,
2023 struct sk_buff **skb,
2024 const unsigned int size)
2025{
2026 struct ixgbe_rx_buffer *rx_buffer;
2027
2028 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2029 prefetchw(rx_buffer->page);
2030 *skb = rx_buffer->skb;
2031
2032 /* Delay unmapping of the first packet. It carries the header
2033 * information, HW may still access the header after the writeback.
2034 * Only unmap it when EOP is reached
2035 */
2036 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) {
2037 if (!*skb)
2038 goto skip_sync;
2039 } else {
2040 if (*skb)
2041 ixgbe_dma_sync_frag(rx_ring, *skb);
2042 }
2043
2044 /* we are reusing so sync this buffer for CPU use */
2045 dma_sync_single_range_for_cpu(rx_ring->dev,
2046 rx_buffer->dma,
2047 rx_buffer->page_offset,
2048 size,
2049 DMA_FROM_DEVICE);
2050skip_sync:
2051 rx_buffer->pagecnt_bias--;
2052
2053 return rx_buffer;
2054}
2055
2056static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring,
2057 struct ixgbe_rx_buffer *rx_buffer,
2058 struct sk_buff *skb)
2059{
2060 if (ixgbe_can_reuse_rx_page(rx_buffer)) {
2061 /* hand second half of page back to the ring */
2062 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2063 } else {
2064 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) {
2065 /* the page has been released from the ring */
2066 IXGBE_CB(skb)->page_released = true;
2067 } else {
2068 /* we are not reusing the buffer so unmap it */
2069 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
2070 ixgbe_rx_pg_size(rx_ring),
2071 DMA_FROM_DEVICE,
2072 IXGBE_RX_DMA_ATTR);
2073 }
2074 __page_frag_cache_drain(rx_buffer->page,
2075 rx_buffer->pagecnt_bias);
2076 }
2077
2078 /* clear contents of rx_buffer */
2079 rx_buffer->page = NULL;
2080 rx_buffer->skb = NULL;
2081}
2082
2083static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring,
2084 struct ixgbe_rx_buffer *rx_buffer,
2085 struct xdp_buff *xdp,
2086 union ixgbe_adv_rx_desc *rx_desc)
2087{
2088 unsigned int size = xdp->data_end - xdp->data;
2089#if (PAGE_SIZE < 8192)
2090 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2091#else
2092 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end -
2093 xdp->data_hard_start);
2094#endif
2095 struct sk_buff *skb;
2096
2097 /* prefetch first cache line of first page */
2098 prefetch(xdp->data);
2099#if L1_CACHE_BYTES < 128
2100 prefetch(xdp->data + L1_CACHE_BYTES);
2101#endif
2102 /* Note, we get here by enabling legacy-rx via:
2103 *
2104 * ethtool --set-priv-flags <dev> legacy-rx on
2105 *
2106 * In this mode, we currently get 0 extra XDP headroom as
2107 * opposed to having legacy-rx off, where we process XDP
2108 * packets going to stack via ixgbe_build_skb(). The latter
2109 * provides us currently with 192 bytes of headroom.
2110 *
2111 * For ixgbe_construct_skb() mode it means that the
2112 * xdp->data_meta will always point to xdp->data, since
2113 * the helper cannot expand the head. Should this ever
2114 * change in future for legacy-rx mode on, then lets also
2115 * add xdp->data_meta handling here.
2116 */
2117
2118 /* allocate a skb to store the frags */
2119 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE);
2120 if (unlikely(!skb))
2121 return NULL;
2122
2123 if (size > IXGBE_RX_HDR_SIZE) {
2124 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2125 IXGBE_CB(skb)->dma = rx_buffer->dma;
2126
2127 skb_add_rx_frag(skb, 0, rx_buffer->page,
2128 xdp->data - page_address(rx_buffer->page),
2129 size, truesize);
2130#if (PAGE_SIZE < 8192)
2131 rx_buffer->page_offset ^= truesize;
2132#else
2133 rx_buffer->page_offset += truesize;
2134#endif
2135 } else {
2136 memcpy(__skb_put(skb, size),
2137 xdp->data, ALIGN(size, sizeof(long)));
2138 rx_buffer->pagecnt_bias++;
2139 }
2140
2141 return skb;
2142}
2143
2144static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring,
2145 struct ixgbe_rx_buffer *rx_buffer,
2146 struct xdp_buff *xdp,
2147 union ixgbe_adv_rx_desc *rx_desc)
2148{
2149 unsigned int metasize = xdp->data - xdp->data_meta;
2150#if (PAGE_SIZE < 8192)
2151 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2152#else
2153 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
2154 SKB_DATA_ALIGN(xdp->data_end -
2155 xdp->data_hard_start);
2156#endif
2157 struct sk_buff *skb;
2158
2159 /* Prefetch first cache line of first page. If xdp->data_meta
2160 * is unused, this points extactly as xdp->data, otherwise we
2161 * likely have a consumer accessing first few bytes of meta
2162 * data, and then actual data.
2163 */
2164 prefetch(xdp->data_meta);
2165#if L1_CACHE_BYTES < 128
2166 prefetch(xdp->data_meta + L1_CACHE_BYTES);
2167#endif
2168
2169 /* build an skb to around the page buffer */
2170 skb = build_skb(xdp->data_hard_start, truesize);
2171 if (unlikely(!skb))
2172 return NULL;
2173
2174 /* update pointers within the skb to store the data */
2175 skb_reserve(skb, xdp->data - xdp->data_hard_start);
2176 __skb_put(skb, xdp->data_end - xdp->data);
2177 if (metasize)
2178 skb_metadata_set(skb, metasize);
2179
2180 /* record DMA address if this is the start of a chain of buffers */
2181 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2182 IXGBE_CB(skb)->dma = rx_buffer->dma;
2183
2184 /* update buffer offset */
2185#if (PAGE_SIZE < 8192)
2186 rx_buffer->page_offset ^= truesize;
2187#else
2188 rx_buffer->page_offset += truesize;
2189#endif
2190
2191 return skb;
2192}
2193
2194static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter,
2195 struct ixgbe_ring *rx_ring,
2196 struct xdp_buff *xdp)
2197{
2198 int err, result = IXGBE_XDP_PASS;
2199 struct bpf_prog *xdp_prog;
2200 struct xdp_frame *xdpf;
2201 u32 act;
2202
2203 rcu_read_lock();
2204 xdp_prog = READ_ONCE(rx_ring->xdp_prog);
2205
2206 if (!xdp_prog)
2207 goto xdp_out;
2208
2209 prefetchw(xdp->data_hard_start); /* xdp_frame write */
2210
2211 act = bpf_prog_run_xdp(xdp_prog, xdp);
2212 switch (act) {
2213 case XDP_PASS:
2214 break;
2215 case XDP_TX:
2216 xdpf = xdp_convert_buff_to_frame(xdp);
2217 if (unlikely(!xdpf)) {
2218 result = IXGBE_XDP_CONSUMED;
2219 break;
2220 }
2221 result = ixgbe_xmit_xdp_ring(adapter, xdpf);
2222 break;
2223 case XDP_REDIRECT:
2224 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog);
2225 if (!err)
2226 result = IXGBE_XDP_REDIR;
2227 else
2228 result = IXGBE_XDP_CONSUMED;
2229 break;
2230 default:
2231 bpf_warn_invalid_xdp_action(act);
2232 fallthrough;
2233 case XDP_ABORTED:
2234 trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
2235 fallthrough; /* handle aborts by dropping packet */
2236 case XDP_DROP:
2237 result = IXGBE_XDP_CONSUMED;
2238 break;
2239 }
2240xdp_out:
2241 rcu_read_unlock();
2242 return ERR_PTR(-result);
2243}
2244
2245static unsigned int ixgbe_rx_frame_truesize(struct ixgbe_ring *rx_ring,
2246 unsigned int size)
2247{
2248 unsigned int truesize;
2249
2250#if (PAGE_SIZE < 8192)
2251 truesize = ixgbe_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */
2252#else
2253 truesize = ring_uses_build_skb(rx_ring) ?
2254 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) +
2255 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
2256 SKB_DATA_ALIGN(size);
2257#endif
2258 return truesize;
2259}
2260
2261static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring,
2262 struct ixgbe_rx_buffer *rx_buffer,
2263 unsigned int size)
2264{
2265 unsigned int truesize = ixgbe_rx_frame_truesize(rx_ring, size);
2266#if (PAGE_SIZE < 8192)
2267 rx_buffer->page_offset ^= truesize;
2268#else
2269 rx_buffer->page_offset += truesize;
2270#endif
2271}
2272
2273/**
2274 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2275 * @q_vector: structure containing interrupt and ring information
2276 * @rx_ring: rx descriptor ring to transact packets on
2277 * @budget: Total limit on number of packets to process
2278 *
2279 * This function provides a "bounce buffer" approach to Rx interrupt
2280 * processing. The advantage to this is that on systems that have
2281 * expensive overhead for IOMMU access this provides a means of avoiding
2282 * it by maintaining the mapping of the page to the syste.
2283 *
2284 * Returns amount of work completed
2285 **/
2286static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
2287 struct ixgbe_ring *rx_ring,
2288 const int budget)
2289{
2290 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2291 struct ixgbe_adapter *adapter = q_vector->adapter;
2292#ifdef IXGBE_FCOE
2293 int ddp_bytes;
2294 unsigned int mss = 0;
2295#endif /* IXGBE_FCOE */
2296 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
2297 unsigned int xdp_xmit = 0;
2298 struct xdp_buff xdp;
2299
2300 xdp.rxq = &rx_ring->xdp_rxq;
2301
2302 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */
2303#if (PAGE_SIZE < 8192)
2304 xdp.frame_sz = ixgbe_rx_frame_truesize(rx_ring, 0);
2305#endif
2306
2307 while (likely(total_rx_packets < budget)) {
2308 union ixgbe_adv_rx_desc *rx_desc;
2309 struct ixgbe_rx_buffer *rx_buffer;
2310 struct sk_buff *skb;
2311 unsigned int size;
2312
2313 /* return some buffers to hardware, one at a time is too slow */
2314 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2315 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2316 cleaned_count = 0;
2317 }
2318
2319 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2320 size = le16_to_cpu(rx_desc->wb.upper.length);
2321 if (!size)
2322 break;
2323
2324 /* This memory barrier is needed to keep us from reading
2325 * any other fields out of the rx_desc until we know the
2326 * descriptor has been written back
2327 */
2328 dma_rmb();
2329
2330 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size);
2331
2332 /* retrieve a buffer from the ring */
2333 if (!skb) {
2334 xdp.data = page_address(rx_buffer->page) +
2335 rx_buffer->page_offset;
2336 xdp.data_meta = xdp.data;
2337 xdp.data_hard_start = xdp.data -
2338 ixgbe_rx_offset(rx_ring);
2339 xdp.data_end = xdp.data + size;
2340#if (PAGE_SIZE > 4096)
2341 /* At larger PAGE_SIZE, frame_sz depend on len size */
2342 xdp.frame_sz = ixgbe_rx_frame_truesize(rx_ring, size);
2343#endif
2344 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp);
2345 }
2346
2347 if (IS_ERR(skb)) {
2348 unsigned int xdp_res = -PTR_ERR(skb);
2349
2350 if (xdp_res & (IXGBE_XDP_TX | IXGBE_XDP_REDIR)) {
2351 xdp_xmit |= xdp_res;
2352 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size);
2353 } else {
2354 rx_buffer->pagecnt_bias++;
2355 }
2356 total_rx_packets++;
2357 total_rx_bytes += size;
2358 } else if (skb) {
2359 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size);
2360 } else if (ring_uses_build_skb(rx_ring)) {
2361 skb = ixgbe_build_skb(rx_ring, rx_buffer,
2362 &xdp, rx_desc);
2363 } else {
2364 skb = ixgbe_construct_skb(rx_ring, rx_buffer,
2365 &xdp, rx_desc);
2366 }
2367
2368 /* exit if we failed to retrieve a buffer */
2369 if (!skb) {
2370 rx_ring->rx_stats.alloc_rx_buff_failed++;
2371 rx_buffer->pagecnt_bias++;
2372 break;
2373 }
2374
2375 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb);
2376 cleaned_count++;
2377
2378 /* place incomplete frames back on ring for completion */
2379 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2380 continue;
2381
2382 /* verify the packet layout is correct */
2383 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2384 continue;
2385
2386 /* probably a little skewed due to removing CRC */
2387 total_rx_bytes += skb->len;
2388
2389 /* populate checksum, timestamp, VLAN, and protocol */
2390 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2391
2392#ifdef IXGBE_FCOE
2393 /* if ddp, not passing to ULD unless for FCP_RSP or error */
2394 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2395 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2396 /* include DDPed FCoE data */
2397 if (ddp_bytes > 0) {
2398 if (!mss) {
2399 mss = rx_ring->netdev->mtu -
2400 sizeof(struct fcoe_hdr) -
2401 sizeof(struct fc_frame_header) -
2402 sizeof(struct fcoe_crc_eof);
2403 if (mss > 512)
2404 mss &= ~511;
2405 }
2406 total_rx_bytes += ddp_bytes;
2407 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2408 mss);
2409 }
2410 if (!ddp_bytes) {
2411 dev_kfree_skb_any(skb);
2412 continue;
2413 }
2414 }
2415
2416#endif /* IXGBE_FCOE */
2417 ixgbe_rx_skb(q_vector, skb);
2418
2419 /* update budget accounting */
2420 total_rx_packets++;
2421 }
2422
2423 if (xdp_xmit & IXGBE_XDP_REDIR)
2424 xdp_do_flush_map();
2425
2426 if (xdp_xmit & IXGBE_XDP_TX) {
2427 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()];
2428
2429 /* Force memory writes to complete before letting h/w
2430 * know there are new descriptors to fetch.
2431 */
2432 wmb();
2433 writel(ring->next_to_use, ring->tail);
2434 }
2435
2436 u64_stats_update_begin(&rx_ring->syncp);
2437 rx_ring->stats.packets += total_rx_packets;
2438 rx_ring->stats.bytes += total_rx_bytes;
2439 u64_stats_update_end(&rx_ring->syncp);
2440 q_vector->rx.total_packets += total_rx_packets;
2441 q_vector->rx.total_bytes += total_rx_bytes;
2442
2443 return total_rx_packets;
2444}
2445
2446/**
2447 * ixgbe_configure_msix - Configure MSI-X hardware
2448 * @adapter: board private structure
2449 *
2450 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2451 * interrupts.
2452 **/
2453static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2454{
2455 struct ixgbe_q_vector *q_vector;
2456 int v_idx;
2457 u32 mask;
2458
2459 /* Populate MSIX to EITR Select */
2460 if (adapter->num_vfs > 32) {
2461 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1;
2462 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2463 }
2464
2465 /*
2466 * Populate the IVAR table and set the ITR values to the
2467 * corresponding register.
2468 */
2469 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2470 struct ixgbe_ring *ring;
2471 q_vector = adapter->q_vector[v_idx];
2472
2473 ixgbe_for_each_ring(ring, q_vector->rx)
2474 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2475
2476 ixgbe_for_each_ring(ring, q_vector->tx)
2477 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2478
2479 ixgbe_write_eitr(q_vector);
2480 }
2481
2482 switch (adapter->hw.mac.type) {
2483 case ixgbe_mac_82598EB:
2484 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2485 v_idx);
2486 break;
2487 case ixgbe_mac_82599EB:
2488 case ixgbe_mac_X540:
2489 case ixgbe_mac_X550:
2490 case ixgbe_mac_X550EM_x:
2491 case ixgbe_mac_x550em_a:
2492 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2493 break;
2494 default:
2495 break;
2496 }
2497 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2498
2499 /* set up to autoclear timer, and the vectors */
2500 mask = IXGBE_EIMS_ENABLE_MASK;
2501 mask &= ~(IXGBE_EIMS_OTHER |
2502 IXGBE_EIMS_MAILBOX |
2503 IXGBE_EIMS_LSC);
2504
2505 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2506}
2507
2508/**
2509 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2510 * @q_vector: structure containing interrupt and ring information
2511 * @ring_container: structure containing ring performance data
2512 *
2513 * Stores a new ITR value based on packets and byte
2514 * counts during the last interrupt. The advantage of per interrupt
2515 * computation is faster updates and more accurate ITR for the current
2516 * traffic pattern. Constants in this function were computed
2517 * based on theoretical maximum wire speed and thresholds were set based
2518 * on testing data as well as attempting to minimize response time
2519 * while increasing bulk throughput.
2520 **/
2521static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2522 struct ixgbe_ring_container *ring_container)
2523{
2524 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS |
2525 IXGBE_ITR_ADAPTIVE_LATENCY;
2526 unsigned int avg_wire_size, packets, bytes;
2527 unsigned long next_update = jiffies;
2528
2529 /* If we don't have any rings just leave ourselves set for maximum
2530 * possible latency so we take ourselves out of the equation.
2531 */
2532 if (!ring_container->ring)
2533 return;
2534
2535 /* If we didn't update within up to 1 - 2 jiffies we can assume
2536 * that either packets are coming in so slow there hasn't been
2537 * any work, or that there is so much work that NAPI is dealing
2538 * with interrupt moderation and we don't need to do anything.
2539 */
2540 if (time_after(next_update, ring_container->next_update))
2541 goto clear_counts;
2542
2543 packets = ring_container->total_packets;
2544
2545 /* We have no packets to actually measure against. This means
2546 * either one of the other queues on this vector is active or
2547 * we are a Tx queue doing TSO with too high of an interrupt rate.
2548 *
2549 * When this occurs just tick up our delay by the minimum value
2550 * and hope that this extra delay will prevent us from being called
2551 * without any work on our queue.
2552 */
2553 if (!packets) {
2554 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC;
2555 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS)
2556 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS;
2557 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY;
2558 goto clear_counts;
2559 }
2560
2561 bytes = ring_container->total_bytes;
2562
2563 /* If packets are less than 4 or bytes are less than 9000 assume
2564 * insufficient data to use bulk rate limiting approach. We are
2565 * likely latency driven.
2566 */
2567 if (packets < 4 && bytes < 9000) {
2568 itr = IXGBE_ITR_ADAPTIVE_LATENCY;
2569 goto adjust_by_size;
2570 }
2571
2572 /* Between 4 and 48 we can assume that our current interrupt delay
2573 * is only slightly too low. As such we should increase it by a small
2574 * fixed amount.
2575 */
2576 if (packets < 48) {
2577 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC;
2578 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS)
2579 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS;
2580 goto clear_counts;
2581 }
2582
2583 /* Between 48 and 96 is our "goldilocks" zone where we are working
2584 * out "just right". Just report that our current ITR is good for us.
2585 */
2586 if (packets < 96) {
2587 itr = q_vector->itr >> 2;
2588 goto clear_counts;
2589 }
2590
2591 /* If packet count is 96 or greater we are likely looking at a slight
2592 * overrun of the delay we want. Try halving our delay to see if that
2593 * will cut the number of packets in half per interrupt.
2594 */
2595 if (packets < 256) {
2596 itr = q_vector->itr >> 3;
2597 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS)
2598 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS;
2599 goto clear_counts;
2600 }
2601
2602 /* The paths below assume we are dealing with a bulk ITR since number
2603 * of packets is 256 or greater. We are just going to have to compute
2604 * a value and try to bring the count under control, though for smaller
2605 * packet sizes there isn't much we can do as NAPI polling will likely
2606 * be kicking in sooner rather than later.
2607 */
2608 itr = IXGBE_ITR_ADAPTIVE_BULK;
2609
2610adjust_by_size:
2611 /* If packet counts are 256 or greater we can assume we have a gross
2612 * overestimation of what the rate should be. Instead of trying to fine
2613 * tune it just use the formula below to try and dial in an exact value
2614 * give the current packet size of the frame.
2615 */
2616 avg_wire_size = bytes / packets;
2617
2618 /* The following is a crude approximation of:
2619 * wmem_default / (size + overhead) = desired_pkts_per_int
2620 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate
2621 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
2622 *
2623 * Assuming wmem_default is 212992 and overhead is 640 bytes per
2624 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
2625 * formula down to
2626 *
2627 * (170 * (size + 24)) / (size + 640) = ITR
2628 *
2629 * We first do some math on the packet size and then finally bitshift
2630 * by 8 after rounding up. We also have to account for PCIe link speed
2631 * difference as ITR scales based on this.
2632 */
2633 if (avg_wire_size <= 60) {
2634 /* Start at 50k ints/sec */
2635 avg_wire_size = 5120;
2636 } else if (avg_wire_size <= 316) {
2637 /* 50K ints/sec to 16K ints/sec */
2638 avg_wire_size *= 40;
2639 avg_wire_size += 2720;
2640 } else if (avg_wire_size <= 1084) {
2641 /* 16K ints/sec to 9.2K ints/sec */
2642 avg_wire_size *= 15;
2643 avg_wire_size += 11452;
2644 } else if (avg_wire_size < 1968) {
2645 /* 9.2K ints/sec to 8K ints/sec */
2646 avg_wire_size *= 5;
2647 avg_wire_size += 22420;
2648 } else {
2649 /* plateau at a limit of 8K ints/sec */
2650 avg_wire_size = 32256;
2651 }
2652
2653 /* If we are in low latency mode half our delay which doubles the rate
2654 * to somewhere between 100K to 16K ints/sec
2655 */
2656 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY)
2657 avg_wire_size >>= 1;
2658
2659 /* Resultant value is 256 times larger than it needs to be. This
2660 * gives us room to adjust the value as needed to either increase
2661 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc.
2662 *
2663 * Use addition as we have already recorded the new latency flag
2664 * for the ITR value.
2665 */
2666 switch (q_vector->adapter->link_speed) {
2667 case IXGBE_LINK_SPEED_10GB_FULL:
2668 case IXGBE_LINK_SPEED_100_FULL:
2669 default:
2670 itr += DIV_ROUND_UP(avg_wire_size,
2671 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) *
2672 IXGBE_ITR_ADAPTIVE_MIN_INC;
2673 break;
2674 case IXGBE_LINK_SPEED_2_5GB_FULL:
2675 case IXGBE_LINK_SPEED_1GB_FULL:
2676 case IXGBE_LINK_SPEED_10_FULL:
2677 if (avg_wire_size > 8064)
2678 avg_wire_size = 8064;
2679 itr += DIV_ROUND_UP(avg_wire_size,
2680 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) *
2681 IXGBE_ITR_ADAPTIVE_MIN_INC;
2682 break;
2683 }
2684
2685clear_counts:
2686 /* write back value */
2687 ring_container->itr = itr;
2688
2689 /* next update should occur within next jiffy */
2690 ring_container->next_update = next_update + 1;
2691
2692 ring_container->total_bytes = 0;
2693 ring_container->total_packets = 0;
2694}
2695
2696/**
2697 * ixgbe_write_eitr - write EITR register in hardware specific way
2698 * @q_vector: structure containing interrupt and ring information
2699 *
2700 * This function is made to be called by ethtool and by the driver
2701 * when it needs to update EITR registers at runtime. Hardware
2702 * specific quirks/differences are taken care of here.
2703 */
2704void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2705{
2706 struct ixgbe_adapter *adapter = q_vector->adapter;
2707 struct ixgbe_hw *hw = &adapter->hw;
2708 int v_idx = q_vector->v_idx;
2709 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2710
2711 switch (adapter->hw.mac.type) {
2712 case ixgbe_mac_82598EB:
2713 /* must write high and low 16 bits to reset counter */
2714 itr_reg |= (itr_reg << 16);
2715 break;
2716 case ixgbe_mac_82599EB:
2717 case ixgbe_mac_X540:
2718 case ixgbe_mac_X550:
2719 case ixgbe_mac_X550EM_x:
2720 case ixgbe_mac_x550em_a:
2721 /*
2722 * set the WDIS bit to not clear the timer bits and cause an
2723 * immediate assertion of the interrupt
2724 */
2725 itr_reg |= IXGBE_EITR_CNT_WDIS;
2726 break;
2727 default:
2728 break;
2729 }
2730 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2731}
2732
2733static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2734{
2735 u32 new_itr;
2736
2737 ixgbe_update_itr(q_vector, &q_vector->tx);
2738 ixgbe_update_itr(q_vector, &q_vector->rx);
2739
2740 /* use the smallest value of new ITR delay calculations */
2741 new_itr = min(q_vector->rx.itr, q_vector->tx.itr);
2742
2743 /* Clear latency flag if set, shift into correct position */
2744 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY;
2745 new_itr <<= 2;
2746
2747 if (new_itr != q_vector->itr) {
2748 /* save the algorithm value here */
2749 q_vector->itr = new_itr;
2750
2751 ixgbe_write_eitr(q_vector);
2752 }
2753}
2754
2755/**
2756 * ixgbe_check_overtemp_subtask - check for over temperature
2757 * @adapter: pointer to adapter
2758 **/
2759static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2760{
2761 struct ixgbe_hw *hw = &adapter->hw;
2762 u32 eicr = adapter->interrupt_event;
2763 s32 rc;
2764
2765 if (test_bit(__IXGBE_DOWN, &adapter->state))
2766 return;
2767
2768 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2769 return;
2770
2771 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2772
2773 switch (hw->device_id) {
2774 case IXGBE_DEV_ID_82599_T3_LOM:
2775 /*
2776 * Since the warning interrupt is for both ports
2777 * we don't have to check if:
2778 * - This interrupt wasn't for our port.
2779 * - We may have missed the interrupt so always have to
2780 * check if we got a LSC
2781 */
2782 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
2783 !(eicr & IXGBE_EICR_LSC))
2784 return;
2785
2786 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2787 u32 speed;
2788 bool link_up = false;
2789
2790 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2791
2792 if (link_up)
2793 return;
2794 }
2795
2796 /* Check if this is not due to overtemp */
2797 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2798 return;
2799
2800 break;
2801 case IXGBE_DEV_ID_X550EM_A_1G_T:
2802 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2803 rc = hw->phy.ops.check_overtemp(hw);
2804 if (rc != IXGBE_ERR_OVERTEMP)
2805 return;
2806 break;
2807 default:
2808 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2809 return;
2810 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
2811 return;
2812 break;
2813 }
2814 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2815
2816 adapter->interrupt_event = 0;
2817}
2818
2819static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2820{
2821 struct ixgbe_hw *hw = &adapter->hw;
2822
2823 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2824 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2825 e_crit(probe, "Fan has stopped, replace the adapter\n");
2826 /* write to clear the interrupt */
2827 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2828 }
2829}
2830
2831static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2832{
2833 struct ixgbe_hw *hw = &adapter->hw;
2834
2835 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2836 return;
2837
2838 switch (adapter->hw.mac.type) {
2839 case ixgbe_mac_82599EB:
2840 /*
2841 * Need to check link state so complete overtemp check
2842 * on service task
2843 */
2844 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2845 (eicr & IXGBE_EICR_LSC)) &&
2846 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2847 adapter->interrupt_event = eicr;
2848 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2849 ixgbe_service_event_schedule(adapter);
2850 return;
2851 }
2852 return;
2853 case ixgbe_mac_x550em_a:
2854 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) {
2855 adapter->interrupt_event = eicr;
2856 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2857 ixgbe_service_event_schedule(adapter);
2858 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
2859 IXGBE_EICR_GPI_SDP0_X550EM_a);
2860 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR,
2861 IXGBE_EICR_GPI_SDP0_X550EM_a);
2862 }
2863 return;
2864 case ixgbe_mac_X550:
2865 case ixgbe_mac_X540:
2866 if (!(eicr & IXGBE_EICR_TS))
2867 return;
2868 break;
2869 default:
2870 return;
2871 }
2872
2873 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2874}
2875
2876static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2877{
2878 switch (hw->mac.type) {
2879 case ixgbe_mac_82598EB:
2880 if (hw->phy.type == ixgbe_phy_nl)
2881 return true;
2882 return false;
2883 case ixgbe_mac_82599EB:
2884 case ixgbe_mac_X550EM_x:
2885 case ixgbe_mac_x550em_a:
2886 switch (hw->mac.ops.get_media_type(hw)) {
2887 case ixgbe_media_type_fiber:
2888 case ixgbe_media_type_fiber_qsfp:
2889 return true;
2890 default:
2891 return false;
2892 }
2893 default:
2894 return false;
2895 }
2896}
2897
2898static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2899{
2900 struct ixgbe_hw *hw = &adapter->hw;
2901 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
2902
2903 if (!ixgbe_is_sfp(hw))
2904 return;
2905
2906 /* Later MAC's use different SDP */
2907 if (hw->mac.type >= ixgbe_mac_X540)
2908 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2909
2910 if (eicr & eicr_mask) {
2911 /* Clear the interrupt */
2912 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
2913 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2914 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2915 adapter->sfp_poll_time = 0;
2916 ixgbe_service_event_schedule(adapter);
2917 }
2918 }
2919
2920 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2921 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2922 /* Clear the interrupt */
2923 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2924 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2925 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2926 ixgbe_service_event_schedule(adapter);
2927 }
2928 }
2929}
2930
2931static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2932{
2933 struct ixgbe_hw *hw = &adapter->hw;
2934
2935 adapter->lsc_int++;
2936 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2937 adapter->link_check_timeout = jiffies;
2938 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2939 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2940 IXGBE_WRITE_FLUSH(hw);
2941 ixgbe_service_event_schedule(adapter);
2942 }
2943}
2944
2945static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2946 u64 qmask)
2947{
2948 u32 mask;
2949 struct ixgbe_hw *hw = &adapter->hw;
2950
2951 switch (hw->mac.type) {
2952 case ixgbe_mac_82598EB:
2953 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2954 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2955 break;
2956 case ixgbe_mac_82599EB:
2957 case ixgbe_mac_X540:
2958 case ixgbe_mac_X550:
2959 case ixgbe_mac_X550EM_x:
2960 case ixgbe_mac_x550em_a:
2961 mask = (qmask & 0xFFFFFFFF);
2962 if (mask)
2963 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2964 mask = (qmask >> 32);
2965 if (mask)
2966 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2967 break;
2968 default:
2969 break;
2970 }
2971 /* skip the flush */
2972}
2973
2974/**
2975 * ixgbe_irq_enable - Enable default interrupt generation settings
2976 * @adapter: board private structure
2977 * @queues: enable irqs for queues
2978 * @flush: flush register write
2979 **/
2980static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2981 bool flush)
2982{
2983 struct ixgbe_hw *hw = &adapter->hw;
2984 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2985
2986 /* don't reenable LSC while waiting for link */
2987 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2988 mask &= ~IXGBE_EIMS_LSC;
2989
2990 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2991 switch (adapter->hw.mac.type) {
2992 case ixgbe_mac_82599EB:
2993 mask |= IXGBE_EIMS_GPI_SDP0(hw);
2994 break;
2995 case ixgbe_mac_X540:
2996 case ixgbe_mac_X550:
2997 case ixgbe_mac_X550EM_x:
2998 case ixgbe_mac_x550em_a:
2999 mask |= IXGBE_EIMS_TS;
3000 break;
3001 default:
3002 break;
3003 }
3004 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3005 mask |= IXGBE_EIMS_GPI_SDP1(hw);
3006 switch (adapter->hw.mac.type) {
3007 case ixgbe_mac_82599EB:
3008 mask |= IXGBE_EIMS_GPI_SDP1(hw);
3009 mask |= IXGBE_EIMS_GPI_SDP2(hw);
3010 fallthrough;
3011 case ixgbe_mac_X540:
3012 case ixgbe_mac_X550:
3013 case ixgbe_mac_X550EM_x:
3014 case ixgbe_mac_x550em_a:
3015 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP ||
3016 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP ||
3017 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N)
3018 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
3019 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
3020 mask |= IXGBE_EICR_GPI_SDP0_X540;
3021 mask |= IXGBE_EIMS_ECC;
3022 mask |= IXGBE_EIMS_MAILBOX;
3023 break;
3024 default:
3025 break;
3026 }
3027
3028 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
3029 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
3030 mask |= IXGBE_EIMS_FLOW_DIR;
3031
3032 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
3033 if (queues)
3034 ixgbe_irq_enable_queues(adapter, ~0);
3035 if (flush)
3036 IXGBE_WRITE_FLUSH(&adapter->hw);
3037}
3038
3039static irqreturn_t ixgbe_msix_other(int irq, void *data)
3040{
3041 struct ixgbe_adapter *adapter = data;
3042 struct ixgbe_hw *hw = &adapter->hw;
3043 u32 eicr;
3044
3045 /*
3046 * Workaround for Silicon errata. Use clear-by-write instead
3047 * of clear-by-read. Reading with EICS will return the
3048 * interrupt causes without clearing, which later be done
3049 * with the write to EICR.
3050 */
3051 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
3052
3053 /* The lower 16bits of the EICR register are for the queue interrupts
3054 * which should be masked here in order to not accidentally clear them if
3055 * the bits are high when ixgbe_msix_other is called. There is a race
3056 * condition otherwise which results in possible performance loss
3057 * especially if the ixgbe_msix_other interrupt is triggering
3058 * consistently (as it would when PPS is turned on for the X540 device)
3059 */
3060 eicr &= 0xFFFF0000;
3061
3062 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
3063
3064 if (eicr & IXGBE_EICR_LSC)
3065 ixgbe_check_lsc(adapter);
3066
3067 if (eicr & IXGBE_EICR_MAILBOX)
3068 ixgbe_msg_task(adapter);
3069
3070 switch (hw->mac.type) {
3071 case ixgbe_mac_82599EB:
3072 case ixgbe_mac_X540:
3073 case ixgbe_mac_X550:
3074 case ixgbe_mac_X550EM_x:
3075 case ixgbe_mac_x550em_a:
3076 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
3077 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
3078 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
3079 ixgbe_service_event_schedule(adapter);
3080 IXGBE_WRITE_REG(hw, IXGBE_EICR,
3081 IXGBE_EICR_GPI_SDP0_X540);
3082 }
3083 if (eicr & IXGBE_EICR_ECC) {
3084 e_info(link, "Received ECC Err, initiating reset\n");
3085 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
3086 ixgbe_service_event_schedule(adapter);
3087 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
3088 }
3089 /* Handle Flow Director Full threshold interrupt */
3090 if (eicr & IXGBE_EICR_FLOW_DIR) {
3091 int reinit_count = 0;
3092 int i;
3093 for (i = 0; i < adapter->num_tx_queues; i++) {
3094 struct ixgbe_ring *ring = adapter->tx_ring[i];
3095 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
3096 &ring->state))
3097 reinit_count++;
3098 }
3099 if (reinit_count) {
3100 /* no more flow director interrupts until after init */
3101 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
3102 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
3103 ixgbe_service_event_schedule(adapter);
3104 }
3105 }
3106 ixgbe_check_sfp_event(adapter, eicr);
3107 ixgbe_check_overtemp_event(adapter, eicr);
3108 break;
3109 default:
3110 break;
3111 }
3112
3113 ixgbe_check_fan_failure(adapter, eicr);
3114
3115 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
3116 ixgbe_ptp_check_pps_event(adapter);
3117
3118 /* re-enable the original interrupt state, no lsc, no queues */
3119 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3120 ixgbe_irq_enable(adapter, false, false);
3121
3122 return IRQ_HANDLED;
3123}
3124
3125static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
3126{
3127 struct ixgbe_q_vector *q_vector = data;
3128
3129 /* EIAM disabled interrupts (on this vector) for us */
3130
3131 if (q_vector->rx.ring || q_vector->tx.ring)
3132 napi_schedule_irqoff(&q_vector->napi);
3133
3134 return IRQ_HANDLED;
3135}
3136
3137/**
3138 * ixgbe_poll - NAPI Rx polling callback
3139 * @napi: structure for representing this polling device
3140 * @budget: how many packets driver is allowed to clean
3141 *
3142 * This function is used for legacy and MSI, NAPI mode
3143 **/
3144int ixgbe_poll(struct napi_struct *napi, int budget)
3145{
3146 struct ixgbe_q_vector *q_vector =
3147 container_of(napi, struct ixgbe_q_vector, napi);
3148 struct ixgbe_adapter *adapter = q_vector->adapter;
3149 struct ixgbe_ring *ring;
3150 int per_ring_budget, work_done = 0;
3151 bool clean_complete = true;
3152
3153#ifdef CONFIG_IXGBE_DCA
3154 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3155 ixgbe_update_dca(q_vector);
3156#endif
3157
3158 ixgbe_for_each_ring(ring, q_vector->tx) {
3159 bool wd = ring->xsk_umem ?
3160 ixgbe_clean_xdp_tx_irq(q_vector, ring, budget) :
3161 ixgbe_clean_tx_irq(q_vector, ring, budget);
3162
3163 if (!wd)
3164 clean_complete = false;
3165 }
3166
3167 /* Exit if we are called by netpoll */
3168 if (budget <= 0)
3169 return budget;
3170
3171 /* attempt to distribute budget to each queue fairly, but don't allow
3172 * the budget to go below 1 because we'll exit polling */
3173 if (q_vector->rx.count > 1)
3174 per_ring_budget = max(budget/q_vector->rx.count, 1);
3175 else
3176 per_ring_budget = budget;
3177
3178 ixgbe_for_each_ring(ring, q_vector->rx) {
3179 int cleaned = ring->xsk_umem ?
3180 ixgbe_clean_rx_irq_zc(q_vector, ring,
3181 per_ring_budget) :
3182 ixgbe_clean_rx_irq(q_vector, ring,
3183 per_ring_budget);
3184
3185 work_done += cleaned;
3186 if (cleaned >= per_ring_budget)
3187 clean_complete = false;
3188 }
3189
3190 /* If all work not completed, return budget and keep polling */
3191 if (!clean_complete)
3192 return budget;
3193
3194 /* all work done, exit the polling mode */
3195 if (likely(napi_complete_done(napi, work_done))) {
3196 if (adapter->rx_itr_setting & 1)
3197 ixgbe_set_itr(q_vector);
3198 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3199 ixgbe_irq_enable_queues(adapter,
3200 BIT_ULL(q_vector->v_idx));
3201 }
3202
3203 return min(work_done, budget - 1);
3204}
3205
3206/**
3207 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
3208 * @adapter: board private structure
3209 *
3210 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
3211 * interrupts from the kernel.
3212 **/
3213static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
3214{
3215 struct net_device *netdev = adapter->netdev;
3216 unsigned int ri = 0, ti = 0;
3217 int vector, err;
3218
3219 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3220 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3221 struct msix_entry *entry = &adapter->msix_entries[vector];
3222
3223 if (q_vector->tx.ring && q_vector->rx.ring) {
3224 snprintf(q_vector->name, sizeof(q_vector->name),
3225 "%s-TxRx-%u", netdev->name, ri++);
3226 ti++;
3227 } else if (q_vector->rx.ring) {
3228 snprintf(q_vector->name, sizeof(q_vector->name),
3229 "%s-rx-%u", netdev->name, ri++);
3230 } else if (q_vector->tx.ring) {
3231 snprintf(q_vector->name, sizeof(q_vector->name),
3232 "%s-tx-%u", netdev->name, ti++);
3233 } else {
3234 /* skip this unused q_vector */
3235 continue;
3236 }
3237 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
3238 q_vector->name, q_vector);
3239 if (err) {
3240 e_err(probe, "request_irq failed for MSIX interrupt "
3241 "Error: %d\n", err);
3242 goto free_queue_irqs;
3243 }
3244 /* If Flow Director is enabled, set interrupt affinity */
3245 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3246 /* assign the mask for this irq */
3247 irq_set_affinity_hint(entry->vector,
3248 &q_vector->affinity_mask);
3249 }
3250 }
3251
3252 err = request_irq(adapter->msix_entries[vector].vector,
3253 ixgbe_msix_other, 0, netdev->name, adapter);
3254 if (err) {
3255 e_err(probe, "request_irq for msix_other failed: %d\n", err);
3256 goto free_queue_irqs;
3257 }
3258
3259 return 0;
3260
3261free_queue_irqs:
3262 while (vector) {
3263 vector--;
3264 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
3265 NULL);
3266 free_irq(adapter->msix_entries[vector].vector,
3267 adapter->q_vector[vector]);
3268 }
3269 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3270 pci_disable_msix(adapter->pdev);
3271 kfree(adapter->msix_entries);
3272 adapter->msix_entries = NULL;
3273 return err;
3274}
3275
3276/**
3277 * ixgbe_intr - legacy mode Interrupt Handler
3278 * @irq: interrupt number
3279 * @data: pointer to a network interface device structure
3280 **/
3281static irqreturn_t ixgbe_intr(int irq, void *data)
3282{
3283 struct ixgbe_adapter *adapter = data;
3284 struct ixgbe_hw *hw = &adapter->hw;
3285 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3286 u32 eicr;
3287
3288 /*
3289 * Workaround for silicon errata #26 on 82598. Mask the interrupt
3290 * before the read of EICR.
3291 */
3292 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
3293
3294 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
3295 * therefore no explicit interrupt disable is necessary */
3296 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3297 if (!eicr) {
3298 /*
3299 * shared interrupt alert!
3300 * make sure interrupts are enabled because the read will
3301 * have disabled interrupts due to EIAM
3302 * finish the workaround of silicon errata on 82598. Unmask
3303 * the interrupt that we masked before the EICR read.
3304 */
3305 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3306 ixgbe_irq_enable(adapter, true, true);
3307 return IRQ_NONE; /* Not our interrupt */
3308 }
3309
3310 if (eicr & IXGBE_EICR_LSC)
3311 ixgbe_check_lsc(adapter);
3312
3313 switch (hw->mac.type) {
3314 case ixgbe_mac_82599EB:
3315 ixgbe_check_sfp_event(adapter, eicr);
3316 fallthrough;
3317 case ixgbe_mac_X540:
3318 case ixgbe_mac_X550:
3319 case ixgbe_mac_X550EM_x:
3320 case ixgbe_mac_x550em_a:
3321 if (eicr & IXGBE_EICR_ECC) {
3322 e_info(link, "Received ECC Err, initiating reset\n");
3323 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
3324 ixgbe_service_event_schedule(adapter);
3325 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
3326 }
3327 ixgbe_check_overtemp_event(adapter, eicr);
3328 break;
3329 default:
3330 break;
3331 }
3332
3333 ixgbe_check_fan_failure(adapter, eicr);
3334 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
3335 ixgbe_ptp_check_pps_event(adapter);
3336
3337 /* would disable interrupts here but EIAM disabled it */
3338 napi_schedule_irqoff(&q_vector->napi);
3339
3340 /*
3341 * re-enable link(maybe) and non-queue interrupts, no flush.
3342 * ixgbe_poll will re-enable the queue interrupts
3343 */
3344 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3345 ixgbe_irq_enable(adapter, false, false);
3346
3347 return IRQ_HANDLED;
3348}
3349
3350/**
3351 * ixgbe_request_irq - initialize interrupts
3352 * @adapter: board private structure
3353 *
3354 * Attempts to configure interrupts using the best available
3355 * capabilities of the hardware and kernel.
3356 **/
3357static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
3358{
3359 struct net_device *netdev = adapter->netdev;
3360 int err;
3361
3362 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3363 err = ixgbe_request_msix_irqs(adapter);
3364 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
3365 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
3366 netdev->name, adapter);
3367 else
3368 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
3369 netdev->name, adapter);
3370
3371 if (err)
3372 e_err(probe, "request_irq failed, Error %d\n", err);
3373
3374 return err;
3375}
3376
3377static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
3378{
3379 int vector;
3380
3381 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3382 free_irq(adapter->pdev->irq, adapter);
3383 return;
3384 }
3385
3386 if (!adapter->msix_entries)
3387 return;
3388
3389 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3390 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3391 struct msix_entry *entry = &adapter->msix_entries[vector];
3392
3393 /* free only the irqs that were actually requested */
3394 if (!q_vector->rx.ring && !q_vector->tx.ring)
3395 continue;
3396
3397 /* clear the affinity_mask in the IRQ descriptor */
3398 irq_set_affinity_hint(entry->vector, NULL);
3399
3400 free_irq(entry->vector, q_vector);
3401 }
3402
3403 free_irq(adapter->msix_entries[vector].vector, adapter);
3404}
3405
3406/**
3407 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3408 * @adapter: board private structure
3409 **/
3410static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3411{
3412 switch (adapter->hw.mac.type) {
3413 case ixgbe_mac_82598EB:
3414 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
3415 break;
3416 case ixgbe_mac_82599EB:
3417 case ixgbe_mac_X540:
3418 case ixgbe_mac_X550:
3419 case ixgbe_mac_X550EM_x:
3420 case ixgbe_mac_x550em_a:
3421 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3422 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
3423 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
3424 break;
3425 default:
3426 break;
3427 }
3428 IXGBE_WRITE_FLUSH(&adapter->hw);
3429 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3430 int vector;
3431
3432 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3433 synchronize_irq(adapter->msix_entries[vector].vector);
3434
3435 synchronize_irq(adapter->msix_entries[vector++].vector);
3436 } else {
3437 synchronize_irq(adapter->pdev->irq);
3438 }
3439}
3440
3441/**
3442 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3443 * @adapter: board private structure
3444 *
3445 **/
3446static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3447{
3448 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3449
3450 ixgbe_write_eitr(q_vector);
3451
3452 ixgbe_set_ivar(adapter, 0, 0, 0);
3453 ixgbe_set_ivar(adapter, 1, 0, 0);
3454
3455 e_info(hw, "Legacy interrupt IVAR setup done\n");
3456}
3457
3458/**
3459 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3460 * @adapter: board private structure
3461 * @ring: structure containing ring specific data
3462 *
3463 * Configure the Tx descriptor ring after a reset.
3464 **/
3465void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3466 struct ixgbe_ring *ring)
3467{
3468 struct ixgbe_hw *hw = &adapter->hw;
3469 u64 tdba = ring->dma;
3470 int wait_loop = 10;
3471 u32 txdctl = IXGBE_TXDCTL_ENABLE;
3472 u8 reg_idx = ring->reg_idx;
3473
3474 ring->xsk_umem = NULL;
3475 if (ring_is_xdp(ring))
3476 ring->xsk_umem = ixgbe_xsk_umem(adapter, ring);
3477
3478 /* disable queue to avoid issues while updating state */
3479 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
3480 IXGBE_WRITE_FLUSH(hw);
3481
3482 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
3483 (tdba & DMA_BIT_MASK(32)));
3484 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3485 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3486 ring->count * sizeof(union ixgbe_adv_tx_desc));
3487 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3488 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
3489 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
3490
3491 /*
3492 * set WTHRESH to encourage burst writeback, it should not be set
3493 * higher than 1 when:
3494 * - ITR is 0 as it could cause false TX hangs
3495 * - ITR is set to > 100k int/sec and BQL is enabled
3496 *
3497 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3498 * to or less than the number of on chip descriptors, which is
3499 * currently 40.
3500 */
3501 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3502 txdctl |= 1u << 16; /* WTHRESH = 1 */
3503 else
3504 txdctl |= 8u << 16; /* WTHRESH = 8 */
3505
3506 /*
3507 * Setting PTHRESH to 32 both improves performance
3508 * and avoids a TX hang with DFP enabled
3509 */
3510 txdctl |= (1u << 8) | /* HTHRESH = 1 */
3511 32; /* PTHRESH = 32 */
3512
3513 /* reinitialize flowdirector state */
3514 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3515 ring->atr_sample_rate = adapter->atr_sample_rate;
3516 ring->atr_count = 0;
3517 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3518 } else {
3519 ring->atr_sample_rate = 0;
3520 }
3521
3522 /* initialize XPS */
3523 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3524 struct ixgbe_q_vector *q_vector = ring->q_vector;
3525
3526 if (q_vector)
3527 netif_set_xps_queue(ring->netdev,
3528 &q_vector->affinity_mask,
3529 ring->queue_index);
3530 }
3531
3532 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3533
3534 /* reinitialize tx_buffer_info */
3535 memset(ring->tx_buffer_info, 0,
3536 sizeof(struct ixgbe_tx_buffer) * ring->count);
3537
3538 /* enable queue */
3539 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3540
3541 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3542 if (hw->mac.type == ixgbe_mac_82598EB &&
3543 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3544 return;
3545
3546 /* poll to verify queue is enabled */
3547 do {
3548 usleep_range(1000, 2000);
3549 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3550 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3551 if (!wait_loop)
3552 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx);
3553}
3554
3555static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3556{
3557 struct ixgbe_hw *hw = &adapter->hw;
3558 u32 rttdcs, mtqc;
3559 u8 tcs = adapter->hw_tcs;
3560
3561 if (hw->mac.type == ixgbe_mac_82598EB)
3562 return;
3563
3564 /* disable the arbiter while setting MTQC */
3565 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3566 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3567 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3568
3569 /* set transmit pool layout */
3570 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3571 mtqc = IXGBE_MTQC_VT_ENA;
3572 if (tcs > 4)
3573 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3574 else if (tcs > 1)
3575 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3576 else if (adapter->ring_feature[RING_F_VMDQ].mask ==
3577 IXGBE_82599_VMDQ_4Q_MASK)
3578 mtqc |= IXGBE_MTQC_32VF;
3579 else
3580 mtqc |= IXGBE_MTQC_64VF;
3581 } else {
3582 if (tcs > 4) {
3583 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3584 } else if (tcs > 1) {
3585 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3586 } else {
3587 u8 max_txq = adapter->num_tx_queues +
3588 adapter->num_xdp_queues;
3589 if (max_txq > 63)
3590 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3591 else
3592 mtqc = IXGBE_MTQC_64Q_1PB;
3593 }
3594 }
3595
3596 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3597
3598 /* Enable Security TX Buffer IFG for multiple pb */
3599 if (tcs) {
3600 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3601 sectx |= IXGBE_SECTX_DCB;
3602 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3603 }
3604
3605 /* re-enable the arbiter */
3606 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3607 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3608}
3609
3610/**
3611 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3612 * @adapter: board private structure
3613 *
3614 * Configure the Tx unit of the MAC after a reset.
3615 **/
3616static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3617{
3618 struct ixgbe_hw *hw = &adapter->hw;
3619 u32 dmatxctl;
3620 u32 i;
3621
3622 ixgbe_setup_mtqc(adapter);
3623
3624 if (hw->mac.type != ixgbe_mac_82598EB) {
3625 /* DMATXCTL.EN must be before Tx queues are enabled */
3626 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3627 dmatxctl |= IXGBE_DMATXCTL_TE;
3628 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3629 }
3630
3631 /* Setup the HW Tx Head and Tail descriptor pointers */
3632 for (i = 0; i < adapter->num_tx_queues; i++)
3633 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3634 for (i = 0; i < adapter->num_xdp_queues; i++)
3635 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]);
3636}
3637
3638static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3639 struct ixgbe_ring *ring)
3640{
3641 struct ixgbe_hw *hw = &adapter->hw;
3642 u8 reg_idx = ring->reg_idx;
3643 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3644
3645 srrctl |= IXGBE_SRRCTL_DROP_EN;
3646
3647 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3648}
3649
3650static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3651 struct ixgbe_ring *ring)
3652{
3653 struct ixgbe_hw *hw = &adapter->hw;
3654 u8 reg_idx = ring->reg_idx;
3655 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3656
3657 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3658
3659 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3660}
3661
3662#ifdef CONFIG_IXGBE_DCB
3663void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3664#else
3665static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3666#endif
3667{
3668 int i;
3669 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3670
3671 if (adapter->ixgbe_ieee_pfc)
3672 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3673
3674 /*
3675 * We should set the drop enable bit if:
3676 * SR-IOV is enabled
3677 * or
3678 * Number of Rx queues > 1 and flow control is disabled
3679 *
3680 * This allows us to avoid head of line blocking for security
3681 * and performance reasons.
3682 */
3683 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3684 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3685 for (i = 0; i < adapter->num_rx_queues; i++)
3686 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3687 } else {
3688 for (i = 0; i < adapter->num_rx_queues; i++)
3689 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3690 }
3691}
3692
3693#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3694
3695static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3696 struct ixgbe_ring *rx_ring)
3697{
3698 struct ixgbe_hw *hw = &adapter->hw;
3699 u32 srrctl;
3700 u8 reg_idx = rx_ring->reg_idx;
3701
3702 if (hw->mac.type == ixgbe_mac_82598EB) {
3703 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3704
3705 /*
3706 * if VMDq is not active we must program one srrctl register
3707 * per RSS queue since we have enabled RDRXCTL.MVMEN
3708 */
3709 reg_idx &= mask;
3710 }
3711
3712 /* configure header buffer length, needed for RSC */
3713 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3714
3715 /* configure the packet buffer length */
3716 if (rx_ring->xsk_umem) {
3717 u32 xsk_buf_len = xsk_umem_get_rx_frame_size(rx_ring->xsk_umem);
3718
3719 /* If the MAC support setting RXDCTL.RLPML, the
3720 * SRRCTL[n].BSIZEPKT is set to PAGE_SIZE and
3721 * RXDCTL.RLPML is set to the actual UMEM buffer
3722 * size. If not, then we are stuck with a 1k buffer
3723 * size resolution. In this case frames larger than
3724 * the UMEM buffer size viewed in a 1k resolution will
3725 * be dropped.
3726 */
3727 if (hw->mac.type != ixgbe_mac_82599EB)
3728 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3729 else
3730 srrctl |= xsk_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3731 } else if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) {
3732 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3733 } else {
3734 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3735 }
3736
3737 /* configure descriptor type */
3738 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3739
3740 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3741}
3742
3743/**
3744 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries
3745 * @adapter: device handle
3746 *
3747 * - 82598/82599/X540: 128
3748 * - X550(non-SRIOV mode): 512
3749 * - X550(SRIOV mode): 64
3750 */
3751u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
3752{
3753 if (adapter->hw.mac.type < ixgbe_mac_X550)
3754 return 128;
3755 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3756 return 64;
3757 else
3758 return 512;
3759}
3760
3761/**
3762 * ixgbe_store_key - Write the RSS key to HW
3763 * @adapter: device handle
3764 *
3765 * Write the RSS key stored in adapter.rss_key to HW.
3766 */
3767void ixgbe_store_key(struct ixgbe_adapter *adapter)
3768{
3769 struct ixgbe_hw *hw = &adapter->hw;
3770 int i;
3771
3772 for (i = 0; i < 10; i++)
3773 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3774}
3775
3776/**
3777 * ixgbe_init_rss_key - Initialize adapter RSS key
3778 * @adapter: device handle
3779 *
3780 * Allocates and initializes the RSS key if it is not allocated.
3781 **/
3782static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter)
3783{
3784 u32 *rss_key;
3785
3786 if (!adapter->rss_key) {
3787 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL);
3788 if (unlikely(!rss_key))
3789 return -ENOMEM;
3790
3791 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE);
3792 adapter->rss_key = rss_key;
3793 }
3794
3795 return 0;
3796}
3797
3798/**
3799 * ixgbe_store_reta - Write the RETA table to HW
3800 * @adapter: device handle
3801 *
3802 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3803 */
3804void ixgbe_store_reta(struct ixgbe_adapter *adapter)
3805{
3806 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3807 struct ixgbe_hw *hw = &adapter->hw;
3808 u32 reta = 0;
3809 u32 indices_multi;
3810 u8 *indir_tbl = adapter->rss_indir_tbl;
3811
3812 /* Fill out the redirection table as follows:
3813 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3814 * indices.
3815 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3816 * - X550: 8 bit wide entries containing 6 bit RSS index
3817 */
3818 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3819 indices_multi = 0x11;
3820 else
3821 indices_multi = 0x1;
3822
3823 /* Write redirection table to HW */
3824 for (i = 0; i < reta_entries; i++) {
3825 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
3826 if ((i & 3) == 3) {
3827 if (i < 128)
3828 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3829 else
3830 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3831 reta);
3832 reta = 0;
3833 }
3834 }
3835}
3836
3837/**
3838 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode)
3839 * @adapter: device handle
3840 *
3841 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3842 */
3843static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
3844{
3845 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3846 struct ixgbe_hw *hw = &adapter->hw;
3847 u32 vfreta = 0;
3848
3849 /* Write redirection table to HW */
3850 for (i = 0; i < reta_entries; i++) {
3851 u16 pool = adapter->num_rx_pools;
3852
3853 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3854 if ((i & 3) != 3)
3855 continue;
3856
3857 while (pool--)
3858 IXGBE_WRITE_REG(hw,
3859 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)),
3860 vfreta);
3861 vfreta = 0;
3862 }
3863}
3864
3865static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3866{
3867 u32 i, j;
3868 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3869 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3870
3871 /* Program table for at least 4 queues w/ SR-IOV so that VFs can
3872 * make full use of any rings they may have. We will use the
3873 * PSRTYPE register to control how many rings we use within the PF.
3874 */
3875 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4))
3876 rss_i = 4;
3877
3878 /* Fill out hash function seeds */
3879 ixgbe_store_key(adapter);
3880
3881 /* Fill out redirection table */
3882 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3883
3884 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3885 if (j == rss_i)
3886 j = 0;
3887
3888 adapter->rss_indir_tbl[i] = j;
3889 }
3890
3891 ixgbe_store_reta(adapter);
3892}
3893
3894static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3895{
3896 struct ixgbe_hw *hw = &adapter->hw;
3897 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3898 int i, j;
3899
3900 /* Fill out hash function seeds */
3901 for (i = 0; i < 10; i++) {
3902 u16 pool = adapter->num_rx_pools;
3903
3904 while (pool--)
3905 IXGBE_WRITE_REG(hw,
3906 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)),
3907 *(adapter->rss_key + i));
3908 }
3909
3910 /* Fill out the redirection table */
3911 for (i = 0, j = 0; i < 64; i++, j++) {
3912 if (j == rss_i)
3913 j = 0;
3914
3915 adapter->rss_indir_tbl[i] = j;
3916 }
3917
3918 ixgbe_store_vfreta(adapter);
3919}
3920
3921static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3922{
3923 struct ixgbe_hw *hw = &adapter->hw;
3924 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
3925 u32 rxcsum;
3926
3927 /* Disable indicating checksum in descriptor, enables RSS hash */
3928 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3929 rxcsum |= IXGBE_RXCSUM_PCSD;
3930 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3931
3932 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3933 if (adapter->ring_feature[RING_F_RSS].mask)
3934 mrqc = IXGBE_MRQC_RSSEN;
3935 } else {
3936 u8 tcs = adapter->hw_tcs;
3937
3938 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3939 if (tcs > 4)
3940 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3941 else if (tcs > 1)
3942 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3943 else if (adapter->ring_feature[RING_F_VMDQ].mask ==
3944 IXGBE_82599_VMDQ_4Q_MASK)
3945 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3946 else
3947 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3948
3949 /* Enable L3/L4 for Tx Switched packets only for X550,
3950 * older devices do not support this feature
3951 */
3952 if (hw->mac.type >= ixgbe_mac_X550)
3953 mrqc |= IXGBE_MRQC_L3L4TXSWEN;
3954 } else {
3955 if (tcs > 4)
3956 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3957 else if (tcs > 1)
3958 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3959 else
3960 mrqc = IXGBE_MRQC_RSSEN;
3961 }
3962 }
3963
3964 /* Perform hash on these packet types */
3965 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3966 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3967 IXGBE_MRQC_RSS_FIELD_IPV6 |
3968 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3969
3970 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3971 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3972 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3973 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3974
3975 if ((hw->mac.type >= ixgbe_mac_X550) &&
3976 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3977 u16 pool = adapter->num_rx_pools;
3978
3979 /* Enable VF RSS mode */
3980 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3981 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3982
3983 /* Setup RSS through the VF registers */
3984 ixgbe_setup_vfreta(adapter);
3985 vfmrqc = IXGBE_MRQC_RSSEN;
3986 vfmrqc |= rss_field;
3987
3988 while (pool--)
3989 IXGBE_WRITE_REG(hw,
3990 IXGBE_PFVFMRQC(VMDQ_P(pool)),
3991 vfmrqc);
3992 } else {
3993 ixgbe_setup_reta(adapter);
3994 mrqc |= rss_field;
3995 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3996 }
3997}
3998
3999/**
4000 * ixgbe_configure_rscctl - enable RSC for the indicated ring
4001 * @adapter: address of board private structure
4002 * @ring: structure containing ring specific data
4003 **/
4004static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
4005 struct ixgbe_ring *ring)
4006{
4007 struct ixgbe_hw *hw = &adapter->hw;
4008 u32 rscctrl;
4009 u8 reg_idx = ring->reg_idx;
4010
4011 if (!ring_is_rsc_enabled(ring))
4012 return;
4013
4014 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
4015 rscctrl |= IXGBE_RSCCTL_RSCEN;
4016 /*
4017 * we must limit the number of descriptors so that the
4018 * total size of max desc * buf_len is not greater
4019 * than 65536
4020 */
4021 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
4022 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
4023}
4024
4025#define IXGBE_MAX_RX_DESC_POLL 10
4026static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
4027 struct ixgbe_ring *ring)
4028{
4029 struct ixgbe_hw *hw = &adapter->hw;
4030 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
4031 u32 rxdctl;
4032 u8 reg_idx = ring->reg_idx;
4033
4034 if (ixgbe_removed(hw->hw_addr))
4035 return;
4036 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
4037 if (hw->mac.type == ixgbe_mac_82598EB &&
4038 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
4039 return;
4040
4041 do {
4042 usleep_range(1000, 2000);
4043 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
4044 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4045
4046 if (!wait_loop) {
4047 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
4048 "the polling period\n", reg_idx);
4049 }
4050}
4051
4052void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
4053 struct ixgbe_ring *ring)
4054{
4055 struct ixgbe_hw *hw = &adapter->hw;
4056 union ixgbe_adv_rx_desc *rx_desc;
4057 u64 rdba = ring->dma;
4058 u32 rxdctl;
4059 u8 reg_idx = ring->reg_idx;
4060
4061 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq);
4062 ring->xsk_umem = ixgbe_xsk_umem(adapter, ring);
4063 if (ring->xsk_umem) {
4064 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
4065 MEM_TYPE_XSK_BUFF_POOL,
4066 NULL));
4067 xsk_buff_set_rxq_info(ring->xsk_umem, &ring->xdp_rxq);
4068 } else {
4069 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
4070 MEM_TYPE_PAGE_SHARED, NULL));
4071 }
4072
4073 /* disable queue to avoid use of these values while updating state */
4074 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
4075 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
4076
4077 /* write value back with RXDCTL.ENABLE bit cleared */
4078 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
4079 IXGBE_WRITE_FLUSH(hw);
4080
4081 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
4082 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
4083 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
4084 ring->count * sizeof(union ixgbe_adv_rx_desc));
4085 /* Force flushing of IXGBE_RDLEN to prevent MDD */
4086 IXGBE_WRITE_FLUSH(hw);
4087
4088 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
4089 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
4090 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
4091
4092 ixgbe_configure_srrctl(adapter, ring);
4093 ixgbe_configure_rscctl(adapter, ring);
4094
4095 if (hw->mac.type == ixgbe_mac_82598EB) {
4096 /*
4097 * enable cache line friendly hardware writes:
4098 * PTHRESH=32 descriptors (half the internal cache),
4099 * this also removes ugly rx_no_buffer_count increment
4100 * HTHRESH=4 descriptors (to minimize latency on fetch)
4101 * WTHRESH=8 burst writeback up to two cache lines
4102 */
4103 rxdctl &= ~0x3FFFFF;
4104 rxdctl |= 0x080420;
4105#if (PAGE_SIZE < 8192)
4106 /* RXDCTL.RLPML does not work on 82599 */
4107 } else if (hw->mac.type != ixgbe_mac_82599EB) {
4108 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK |
4109 IXGBE_RXDCTL_RLPML_EN);
4110
4111 /* Limit the maximum frame size so we don't overrun the skb.
4112 * This can happen in SRIOV mode when the MTU of the VF is
4113 * higher than the MTU of the PF.
4114 */
4115 if (ring_uses_build_skb(ring) &&
4116 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
4117 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB |
4118 IXGBE_RXDCTL_RLPML_EN;
4119#endif
4120 }
4121
4122 if (ring->xsk_umem && hw->mac.type != ixgbe_mac_82599EB) {
4123 u32 xsk_buf_len = xsk_umem_get_rx_frame_size(ring->xsk_umem);
4124
4125 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK |
4126 IXGBE_RXDCTL_RLPML_EN);
4127 rxdctl |= xsk_buf_len | IXGBE_RXDCTL_RLPML_EN;
4128
4129 ring->rx_buf_len = xsk_buf_len;
4130 }
4131
4132 /* initialize rx_buffer_info */
4133 memset(ring->rx_buffer_info, 0,
4134 sizeof(struct ixgbe_rx_buffer) * ring->count);
4135
4136 /* initialize Rx descriptor 0 */
4137 rx_desc = IXGBE_RX_DESC(ring, 0);
4138 rx_desc->wb.upper.length = 0;
4139
4140 /* enable receive descriptor ring */
4141 rxdctl |= IXGBE_RXDCTL_ENABLE;
4142 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
4143
4144 ixgbe_rx_desc_queue_enable(adapter, ring);
4145 if (ring->xsk_umem)
4146 ixgbe_alloc_rx_buffers_zc(ring, ixgbe_desc_unused(ring));
4147 else
4148 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
4149}
4150
4151static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
4152{
4153 struct ixgbe_hw *hw = &adapter->hw;
4154 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
4155 u16 pool = adapter->num_rx_pools;
4156
4157 /* PSRTYPE must be initialized in non 82598 adapters */
4158 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4159 IXGBE_PSRTYPE_UDPHDR |
4160 IXGBE_PSRTYPE_IPV4HDR |
4161 IXGBE_PSRTYPE_L2HDR |
4162 IXGBE_PSRTYPE_IPV6HDR;
4163
4164 if (hw->mac.type == ixgbe_mac_82598EB)
4165 return;
4166
4167 if (rss_i > 3)
4168 psrtype |= 2u << 29;
4169 else if (rss_i > 1)
4170 psrtype |= 1u << 29;
4171
4172 while (pool--)
4173 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4174}
4175
4176static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
4177{
4178 struct ixgbe_hw *hw = &adapter->hw;
4179 u16 pool = adapter->num_rx_pools;
4180 u32 reg_offset, vf_shift, vmolr;
4181 u32 gcr_ext, vmdctl;
4182 int i;
4183
4184 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
4185 return;
4186
4187 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4188 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
4189 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
4190 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
4191 vmdctl |= IXGBE_VT_CTL_REPLEN;
4192 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
4193
4194 /* accept untagged packets until a vlan tag is
4195 * specifically set for the VMDQ queue/pool
4196 */
4197 vmolr = IXGBE_VMOLR_AUPE;
4198 while (pool--)
4199 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr);
4200
4201 vf_shift = VMDQ_P(0) % 32;
4202 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
4203
4204 /* Enable only the PF's pool for Tx/Rx */
4205 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift));
4206 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
4207 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift));
4208 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
4209 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
4210 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
4211
4212 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
4213 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
4214
4215 /* clear VLAN promisc flag so VFTA will be updated if necessary */
4216 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4217
4218 /*
4219 * Set up VF register offsets for selected VT Mode,
4220 * i.e. 32 or 64 VFs for SR-IOV
4221 */
4222 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4223 case IXGBE_82599_VMDQ_8Q_MASK:
4224 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
4225 break;
4226 case IXGBE_82599_VMDQ_4Q_MASK:
4227 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
4228 break;
4229 default:
4230 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
4231 break;
4232 }
4233
4234 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4235
4236 for (i = 0; i < adapter->num_vfs; i++) {
4237 /* configure spoof checking */
4238 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i,
4239 adapter->vfinfo[i].spoofchk_enabled);
4240
4241 /* Enable/Disable RSS query feature */
4242 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
4243 adapter->vfinfo[i].rss_query_enabled);
4244 }
4245}
4246
4247static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
4248{
4249 struct ixgbe_hw *hw = &adapter->hw;
4250 struct net_device *netdev = adapter->netdev;
4251 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4252 struct ixgbe_ring *rx_ring;
4253 int i;
4254 u32 mhadd, hlreg0;
4255
4256#ifdef IXGBE_FCOE
4257 /* adjust max frame to be able to do baby jumbo for FCoE */
4258 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
4259 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
4260 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4261
4262#endif /* IXGBE_FCOE */
4263
4264 /* adjust max frame to be at least the size of a standard frame */
4265 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4266 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
4267
4268 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
4269 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
4270 mhadd &= ~IXGBE_MHADD_MFS_MASK;
4271 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
4272
4273 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
4274 }
4275
4276 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4277 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
4278 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4279 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4280
4281 /*
4282 * Setup the HW Rx Head and Tail Descriptor Pointers and
4283 * the Base and Length of the Rx Descriptor Ring
4284 */
4285 for (i = 0; i < adapter->num_rx_queues; i++) {
4286 rx_ring = adapter->rx_ring[i];
4287
4288 clear_ring_rsc_enabled(rx_ring);
4289 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4290 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
4291
4292 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
4293 set_ring_rsc_enabled(rx_ring);
4294
4295 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state))
4296 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4297
4298 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY)
4299 continue;
4300
4301 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
4302
4303#if (PAGE_SIZE < 8192)
4304 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
4305 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4306
4307 if (IXGBE_2K_TOO_SMALL_WITH_PADDING ||
4308 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
4309 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4310#endif
4311 }
4312}
4313
4314static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
4315{
4316 struct ixgbe_hw *hw = &adapter->hw;
4317 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4318
4319 switch (hw->mac.type) {
4320 case ixgbe_mac_82598EB:
4321 /*
4322 * For VMDq support of different descriptor types or
4323 * buffer sizes through the use of multiple SRRCTL
4324 * registers, RDRXCTL.MVMEN must be set to 1
4325 *
4326 * also, the manual doesn't mention it clearly but DCA hints
4327 * will only use queue 0's tags unless this bit is set. Side
4328 * effects of setting this bit are only that SRRCTL must be
4329 * fully programmed [0..15]
4330 */
4331 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
4332 break;
4333 case ixgbe_mac_X550:
4334 case ixgbe_mac_X550EM_x:
4335 case ixgbe_mac_x550em_a:
4336 if (adapter->num_vfs)
4337 rdrxctl |= IXGBE_RDRXCTL_PSP;
4338 fallthrough;
4339 case ixgbe_mac_82599EB:
4340 case ixgbe_mac_X540:
4341 /* Disable RSC for ACK packets */
4342 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
4343 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
4344 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4345 /* hardware requires some bits to be set by default */
4346 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
4347 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4348 break;
4349 default:
4350 /* We should do nothing since we don't know this hardware */
4351 return;
4352 }
4353
4354 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4355}
4356
4357/**
4358 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
4359 * @adapter: board private structure
4360 *
4361 * Configure the Rx unit of the MAC after a reset.
4362 **/
4363static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
4364{
4365 struct ixgbe_hw *hw = &adapter->hw;
4366 int i;
4367 u32 rxctrl, rfctl;
4368
4369 /* disable receives while setting up the descriptors */
4370 hw->mac.ops.disable_rx(hw);
4371
4372 ixgbe_setup_psrtype(adapter);
4373 ixgbe_setup_rdrxctl(adapter);
4374
4375 /* RSC Setup */
4376 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4377 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
4378 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
4379 rfctl |= IXGBE_RFCTL_RSC_DIS;
4380
4381 /* disable NFS filtering */
4382 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS);
4383 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4384
4385 /* Program registers for the distribution of queues */
4386 ixgbe_setup_mrqc(adapter);
4387
4388 /* set_rx_buffer_len must be called before ring initialization */
4389 ixgbe_set_rx_buffer_len(adapter);
4390
4391 /*
4392 * Setup the HW Rx Head and Tail Descriptor Pointers and
4393 * the Base and Length of the Rx Descriptor Ring
4394 */
4395 for (i = 0; i < adapter->num_rx_queues; i++)
4396 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
4397
4398 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4399 /* disable drop enable for 82598 parts */
4400 if (hw->mac.type == ixgbe_mac_82598EB)
4401 rxctrl |= IXGBE_RXCTRL_DMBYPS;
4402
4403 /* enable all receives */
4404 rxctrl |= IXGBE_RXCTRL_RXEN;
4405 hw->mac.ops.enable_rx_dma(hw, rxctrl);
4406}
4407
4408static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
4409 __be16 proto, u16 vid)
4410{
4411 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4412 struct ixgbe_hw *hw = &adapter->hw;
4413
4414 /* add VID to filter table */
4415 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4416 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid);
4417
4418 set_bit(vid, adapter->active_vlans);
4419
4420 return 0;
4421}
4422
4423static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan)
4424{
4425 u32 vlvf;
4426 int idx;
4427
4428 /* short cut the special case */
4429 if (vlan == 0)
4430 return 0;
4431
4432 /* Search for the vlan id in the VLVF entries */
4433 for (idx = IXGBE_VLVF_ENTRIES; --idx;) {
4434 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx));
4435 if ((vlvf & VLAN_VID_MASK) == vlan)
4436 break;
4437 }
4438
4439 return idx;
4440}
4441
4442void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid)
4443{
4444 struct ixgbe_hw *hw = &adapter->hw;
4445 u32 bits, word;
4446 int idx;
4447
4448 idx = ixgbe_find_vlvf_entry(hw, vid);
4449 if (!idx)
4450 return;
4451
4452 /* See if any other pools are set for this VLAN filter
4453 * entry other than the PF.
4454 */
4455 word = idx * 2 + (VMDQ_P(0) / 32);
4456 bits = ~BIT(VMDQ_P(0) % 32);
4457 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4458
4459 /* Disable the filter so this falls into the default pool. */
4460 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) {
4461 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4462 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0);
4463 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0);
4464 }
4465}
4466
4467static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
4468 __be16 proto, u16 vid)
4469{
4470 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4471 struct ixgbe_hw *hw = &adapter->hw;
4472
4473 /* remove VID from filter table */
4474 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4475 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true);
4476
4477 clear_bit(vid, adapter->active_vlans);
4478
4479 return 0;
4480}
4481
4482/**
4483 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
4484 * @adapter: driver data
4485 */
4486static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
4487{
4488 struct ixgbe_hw *hw = &adapter->hw;
4489 u32 vlnctrl;
4490 int i, j;
4491
4492 switch (hw->mac.type) {
4493 case ixgbe_mac_82598EB:
4494 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4495 vlnctrl &= ~IXGBE_VLNCTRL_VME;
4496 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4497 break;
4498 case ixgbe_mac_82599EB:
4499 case ixgbe_mac_X540:
4500 case ixgbe_mac_X550:
4501 case ixgbe_mac_X550EM_x:
4502 case ixgbe_mac_x550em_a:
4503 for (i = 0; i < adapter->num_rx_queues; i++) {
4504 struct ixgbe_ring *ring = adapter->rx_ring[i];
4505
4506 if (!netif_is_ixgbe(ring->netdev))
4507 continue;
4508
4509 j = ring->reg_idx;
4510 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4511 vlnctrl &= ~IXGBE_RXDCTL_VME;
4512 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4513 }
4514 break;
4515 default:
4516 break;
4517 }
4518}
4519
4520/**
4521 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
4522 * @adapter: driver data
4523 */
4524static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
4525{
4526 struct ixgbe_hw *hw = &adapter->hw;
4527 u32 vlnctrl;
4528 int i, j;
4529
4530 switch (hw->mac.type) {
4531 case ixgbe_mac_82598EB:
4532 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4533 vlnctrl |= IXGBE_VLNCTRL_VME;
4534 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4535 break;
4536 case ixgbe_mac_82599EB:
4537 case ixgbe_mac_X540:
4538 case ixgbe_mac_X550:
4539 case ixgbe_mac_X550EM_x:
4540 case ixgbe_mac_x550em_a:
4541 for (i = 0; i < adapter->num_rx_queues; i++) {
4542 struct ixgbe_ring *ring = adapter->rx_ring[i];
4543
4544 if (!netif_is_ixgbe(ring->netdev))
4545 continue;
4546
4547 j = ring->reg_idx;
4548 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4549 vlnctrl |= IXGBE_RXDCTL_VME;
4550 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4551 }
4552 break;
4553 default:
4554 break;
4555 }
4556}
4557
4558static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter)
4559{
4560 struct ixgbe_hw *hw = &adapter->hw;
4561 u32 vlnctrl, i;
4562
4563 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4564
4565 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
4566 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */
4567 vlnctrl |= IXGBE_VLNCTRL_VFE;
4568 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4569 } else {
4570 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
4571 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4572 return;
4573 }
4574
4575 /* Nothing to do for 82598 */
4576 if (hw->mac.type == ixgbe_mac_82598EB)
4577 return;
4578
4579 /* We are already in VLAN promisc, nothing to do */
4580 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)
4581 return;
4582
4583 /* Set flag so we don't redo unnecessary work */
4584 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC;
4585
4586 /* Add PF to all active pools */
4587 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4588 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32);
4589 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset);
4590
4591 vlvfb |= BIT(VMDQ_P(0) % 32);
4592 IXGBE_WRITE_REG(hw, reg_offset, vlvfb);
4593 }
4594
4595 /* Set all bits in the VLAN filter table array */
4596 for (i = hw->mac.vft_size; i--;)
4597 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U);
4598}
4599
4600#define VFTA_BLOCK_SIZE 8
4601static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset)
4602{
4603 struct ixgbe_hw *hw = &adapter->hw;
4604 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4605 u32 vid_start = vfta_offset * 32;
4606 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4607 u32 i, vid, word, bits;
4608
4609 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4610 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i));
4611
4612 /* pull VLAN ID from VLVF */
4613 vid = vlvf & VLAN_VID_MASK;
4614
4615 /* only concern outselves with a certain range */
4616 if (vid < vid_start || vid >= vid_end)
4617 continue;
4618
4619 if (vlvf) {
4620 /* record VLAN ID in VFTA */
4621 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
4622
4623 /* if PF is part of this then continue */
4624 if (test_bit(vid, adapter->active_vlans))
4625 continue;
4626 }
4627
4628 /* remove PF from the pool */
4629 word = i * 2 + VMDQ_P(0) / 32;
4630 bits = ~BIT(VMDQ_P(0) % 32);
4631 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4632 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits);
4633 }
4634
4635 /* extract values from active_vlans and write back to VFTA */
4636 for (i = VFTA_BLOCK_SIZE; i--;) {
4637 vid = (vfta_offset + i) * 32;
4638 word = vid / BITS_PER_LONG;
4639 bits = vid % BITS_PER_LONG;
4640
4641 vfta[i] |= adapter->active_vlans[word] >> bits;
4642
4643 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]);
4644 }
4645}
4646
4647static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter)
4648{
4649 struct ixgbe_hw *hw = &adapter->hw;
4650 u32 vlnctrl, i;
4651
4652 /* Set VLAN filtering to enabled */
4653 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4654 vlnctrl |= IXGBE_VLNCTRL_VFE;
4655 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4656
4657 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) ||
4658 hw->mac.type == ixgbe_mac_82598EB)
4659 return;
4660
4661 /* We are not in VLAN promisc, nothing to do */
4662 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4663 return;
4664
4665 /* Set flag so we don't redo unnecessary work */
4666 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4667
4668 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE)
4669 ixgbe_scrub_vfta(adapter, i);
4670}
4671
4672static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
4673{
4674 u16 vid = 1;
4675
4676 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
4677
4678 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
4679 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
4680}
4681
4682/**
4683 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4684 * @netdev: network interface device structure
4685 *
4686 * Writes multicast address list to the MTA hash table.
4687 * Returns: -ENOMEM on failure
4688 * 0 on no addresses written
4689 * X on writing X addresses to MTA
4690 **/
4691static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4692{
4693 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4694 struct ixgbe_hw *hw = &adapter->hw;
4695
4696 if (!netif_running(netdev))
4697 return 0;
4698
4699 if (hw->mac.ops.update_mc_addr_list)
4700 hw->mac.ops.update_mc_addr_list(hw, netdev);
4701 else
4702 return -ENOMEM;
4703
4704#ifdef CONFIG_PCI_IOV
4705 ixgbe_restore_vf_multicasts(adapter);
4706#endif
4707
4708 return netdev_mc_count(netdev);
4709}
4710
4711#ifdef CONFIG_PCI_IOV
4712void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4713{
4714 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4715 struct ixgbe_hw *hw = &adapter->hw;
4716 int i;
4717
4718 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4719 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4720
4721 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4722 hw->mac.ops.set_rar(hw, i,
4723 mac_table->addr,
4724 mac_table->pool,
4725 IXGBE_RAH_AV);
4726 else
4727 hw->mac.ops.clear_rar(hw, i);
4728 }
4729}
4730
4731#endif
4732static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4733{
4734 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4735 struct ixgbe_hw *hw = &adapter->hw;
4736 int i;
4737
4738 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4739 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED))
4740 continue;
4741
4742 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4743
4744 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4745 hw->mac.ops.set_rar(hw, i,
4746 mac_table->addr,
4747 mac_table->pool,
4748 IXGBE_RAH_AV);
4749 else
4750 hw->mac.ops.clear_rar(hw, i);
4751 }
4752}
4753
4754static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4755{
4756 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4757 struct ixgbe_hw *hw = &adapter->hw;
4758 int i;
4759
4760 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4761 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4762 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4763 }
4764
4765 ixgbe_sync_mac_table(adapter);
4766}
4767
4768static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool)
4769{
4770 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4771 struct ixgbe_hw *hw = &adapter->hw;
4772 int i, count = 0;
4773
4774 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4775 /* do not count default RAR as available */
4776 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT)
4777 continue;
4778
4779 /* only count unused and addresses that belong to us */
4780 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) {
4781 if (mac_table->pool != pool)
4782 continue;
4783 }
4784
4785 count++;
4786 }
4787
4788 return count;
4789}
4790
4791/* this function destroys the first RAR entry */
4792static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter)
4793{
4794 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4795 struct ixgbe_hw *hw = &adapter->hw;
4796
4797 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN);
4798 mac_table->pool = VMDQ_P(0);
4799
4800 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE;
4801
4802 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool,
4803 IXGBE_RAH_AV);
4804}
4805
4806int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4807 const u8 *addr, u16 pool)
4808{
4809 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4810 struct ixgbe_hw *hw = &adapter->hw;
4811 int i;
4812
4813 if (is_zero_ether_addr(addr))
4814 return -EINVAL;
4815
4816 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4817 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4818 continue;
4819
4820 ether_addr_copy(mac_table->addr, addr);
4821 mac_table->pool = pool;
4822
4823 mac_table->state |= IXGBE_MAC_STATE_MODIFIED |
4824 IXGBE_MAC_STATE_IN_USE;
4825
4826 ixgbe_sync_mac_table(adapter);
4827
4828 return i;
4829 }
4830
4831 return -ENOMEM;
4832}
4833
4834int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
4835 const u8 *addr, u16 pool)
4836{
4837 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4838 struct ixgbe_hw *hw = &adapter->hw;
4839 int i;
4840
4841 if (is_zero_ether_addr(addr))
4842 return -EINVAL;
4843
4844 /* search table for addr, if found clear IN_USE flag and sync */
4845 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4846 /* we can only delete an entry if it is in use */
4847 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE))
4848 continue;
4849 /* we only care about entries that belong to the given pool */
4850 if (mac_table->pool != pool)
4851 continue;
4852 /* we only care about a specific MAC address */
4853 if (!ether_addr_equal(addr, mac_table->addr))
4854 continue;
4855
4856 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4857 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4858
4859 ixgbe_sync_mac_table(adapter);
4860
4861 return 0;
4862 }
4863
4864 return -ENOMEM;
4865}
4866
4867static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr)
4868{
4869 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4870 int ret;
4871
4872 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0));
4873
4874 return min_t(int, ret, 0);
4875}
4876
4877static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr)
4878{
4879 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4880
4881 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0));
4882
4883 return 0;
4884}
4885
4886/**
4887 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
4888 * @netdev: network interface device structure
4889 *
4890 * The set_rx_method entry point is called whenever the unicast/multicast
4891 * address list or the network interface flags are updated. This routine is
4892 * responsible for configuring the hardware for proper unicast, multicast and
4893 * promiscuous mode.
4894 **/
4895void ixgbe_set_rx_mode(struct net_device *netdev)
4896{
4897 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4898 struct ixgbe_hw *hw = &adapter->hw;
4899 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
4900 netdev_features_t features = netdev->features;
4901 int count;
4902
4903 /* Check for Promiscuous and All Multicast modes */
4904 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4905
4906 /* set all bits that we expect to always be set */
4907 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
4908 fctrl |= IXGBE_FCTRL_BAM;
4909 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4910 fctrl |= IXGBE_FCTRL_PMCF;
4911
4912 /* clear the bits we are changing the status of */
4913 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4914 if (netdev->flags & IFF_PROMISC) {
4915 hw->addr_ctrl.user_set_promisc = true;
4916 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4917 vmolr |= IXGBE_VMOLR_MPE;
4918 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4919 } else {
4920 if (netdev->flags & IFF_ALLMULTI) {
4921 fctrl |= IXGBE_FCTRL_MPE;
4922 vmolr |= IXGBE_VMOLR_MPE;
4923 }
4924 hw->addr_ctrl.user_set_promisc = false;
4925 }
4926
4927 /*
4928 * Write addresses to available RAR registers, if there is not
4929 * sufficient space to store all the addresses then enable
4930 * unicast promiscuous mode
4931 */
4932 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) {
4933 fctrl |= IXGBE_FCTRL_UPE;
4934 vmolr |= IXGBE_VMOLR_ROPE;
4935 }
4936
4937 /* Write addresses to the MTA, if the attempt fails
4938 * then we should just turn on promiscuous mode so
4939 * that we can at least receive multicast traffic
4940 */
4941 count = ixgbe_write_mc_addr_list(netdev);
4942 if (count < 0) {
4943 fctrl |= IXGBE_FCTRL_MPE;
4944 vmolr |= IXGBE_VMOLR_MPE;
4945 } else if (count) {
4946 vmolr |= IXGBE_VMOLR_ROMPE;
4947 }
4948
4949 if (hw->mac.type != ixgbe_mac_82598EB) {
4950 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
4951 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4952 IXGBE_VMOLR_ROPE);
4953 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
4954 }
4955
4956 /* This is useful for sniffing bad packets. */
4957 if (features & NETIF_F_RXALL) {
4958 /* UPE and MPE will be handled by normal PROMISC logic
4959 * in e1000e_set_rx_mode */
4960 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4961 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4962 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4963
4964 fctrl &= ~(IXGBE_FCTRL_DPF);
4965 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4966 }
4967
4968 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4969
4970 if (features & NETIF_F_HW_VLAN_CTAG_RX)
4971 ixgbe_vlan_strip_enable(adapter);
4972 else
4973 ixgbe_vlan_strip_disable(adapter);
4974
4975 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
4976 ixgbe_vlan_promisc_disable(adapter);
4977 else
4978 ixgbe_vlan_promisc_enable(adapter);
4979}
4980
4981static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4982{
4983 int q_idx;
4984
4985 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
4986 napi_enable(&adapter->q_vector[q_idx]->napi);
4987}
4988
4989static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4990{
4991 int q_idx;
4992
4993 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
4994 napi_disable(&adapter->q_vector[q_idx]->napi);
4995}
4996
4997static int ixgbe_udp_tunnel_sync(struct net_device *dev, unsigned int table)
4998{
4999 struct ixgbe_adapter *adapter = netdev_priv(dev);
5000 struct ixgbe_hw *hw = &adapter->hw;
5001 struct udp_tunnel_info ti;
5002
5003 udp_tunnel_nic_get_port(dev, table, 0, &ti);
5004 if (ti.type == UDP_TUNNEL_TYPE_VXLAN)
5005 adapter->vxlan_port = ti.port;
5006 else
5007 adapter->geneve_port = ti.port;
5008
5009 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL,
5010 ntohs(adapter->vxlan_port) |
5011 ntohs(adapter->geneve_port) <<
5012 IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT);
5013 return 0;
5014}
5015
5016static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550 = {
5017 .sync_table = ixgbe_udp_tunnel_sync,
5018 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY,
5019 .tables = {
5020 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
5021 },
5022};
5023
5024static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550em_a = {
5025 .sync_table = ixgbe_udp_tunnel_sync,
5026 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY,
5027 .tables = {
5028 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
5029 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, },
5030 },
5031};
5032
5033#ifdef CONFIG_IXGBE_DCB
5034/**
5035 * ixgbe_configure_dcb - Configure DCB hardware
5036 * @adapter: ixgbe adapter struct
5037 *
5038 * This is called by the driver on open to configure the DCB hardware.
5039 * This is also called by the gennetlink interface when reconfiguring
5040 * the DCB state.
5041 */
5042static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
5043{
5044 struct ixgbe_hw *hw = &adapter->hw;
5045 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
5046
5047 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
5048 if (hw->mac.type == ixgbe_mac_82598EB)
5049 netif_set_gso_max_size(adapter->netdev, 65536);
5050 return;
5051 }
5052
5053 if (hw->mac.type == ixgbe_mac_82598EB)
5054 netif_set_gso_max_size(adapter->netdev, 32768);
5055
5056#ifdef IXGBE_FCOE
5057 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
5058 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
5059#endif
5060
5061 /* reconfigure the hardware */
5062 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
5063 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
5064 DCB_TX_CONFIG);
5065 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
5066 DCB_RX_CONFIG);
5067 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
5068 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
5069 ixgbe_dcb_hw_ets(&adapter->hw,
5070 adapter->ixgbe_ieee_ets,
5071 max_frame);
5072 ixgbe_dcb_hw_pfc_config(&adapter->hw,
5073 adapter->ixgbe_ieee_pfc->pfc_en,
5074 adapter->ixgbe_ieee_ets->prio_tc);
5075 }
5076
5077 /* Enable RSS Hash per TC */
5078 if (hw->mac.type != ixgbe_mac_82598EB) {
5079 u32 msb = 0;
5080 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
5081
5082 while (rss_i) {
5083 msb++;
5084 rss_i >>= 1;
5085 }
5086
5087 /* write msb to all 8 TCs in one write */
5088 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
5089 }
5090}
5091#endif
5092
5093/* Additional bittime to account for IXGBE framing */
5094#define IXGBE_ETH_FRAMING 20
5095
5096/**
5097 * ixgbe_hpbthresh - calculate high water mark for flow control
5098 *
5099 * @adapter: board private structure to calculate for
5100 * @pb: packet buffer to calculate
5101 */
5102static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
5103{
5104 struct ixgbe_hw *hw = &adapter->hw;
5105 struct net_device *dev = adapter->netdev;
5106 int link, tc, kb, marker;
5107 u32 dv_id, rx_pba;
5108
5109 /* Calculate max LAN frame size */
5110 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
5111
5112#ifdef IXGBE_FCOE
5113 /* FCoE traffic class uses FCOE jumbo frames */
5114 if ((dev->features & NETIF_F_FCOE_MTU) &&
5115 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
5116 (pb == ixgbe_fcoe_get_tc(adapter)))
5117 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
5118#endif
5119
5120 /* Calculate delay value for device */
5121 switch (hw->mac.type) {
5122 case ixgbe_mac_X540:
5123 case ixgbe_mac_X550:
5124 case ixgbe_mac_X550EM_x:
5125 case ixgbe_mac_x550em_a:
5126 dv_id = IXGBE_DV_X540(link, tc);
5127 break;
5128 default:
5129 dv_id = IXGBE_DV(link, tc);
5130 break;
5131 }
5132
5133 /* Loopback switch introduces additional latency */
5134 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5135 dv_id += IXGBE_B2BT(tc);
5136
5137 /* Delay value is calculated in bit times convert to KB */
5138 kb = IXGBE_BT2KB(dv_id);
5139 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
5140
5141 marker = rx_pba - kb;
5142
5143 /* It is possible that the packet buffer is not large enough
5144 * to provide required headroom. In this case throw an error
5145 * to user and a do the best we can.
5146 */
5147 if (marker < 0) {
5148 e_warn(drv, "Packet Buffer(%i) can not provide enough"
5149 "headroom to support flow control."
5150 "Decrease MTU or number of traffic classes\n", pb);
5151 marker = tc + 1;
5152 }
5153
5154 return marker;
5155}
5156
5157/**
5158 * ixgbe_lpbthresh - calculate low water mark for for flow control
5159 *
5160 * @adapter: board private structure to calculate for
5161 * @pb: packet buffer to calculate
5162 */
5163static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
5164{
5165 struct ixgbe_hw *hw = &adapter->hw;
5166 struct net_device *dev = adapter->netdev;
5167 int tc;
5168 u32 dv_id;
5169
5170 /* Calculate max LAN frame size */
5171 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5172
5173#ifdef IXGBE_FCOE
5174 /* FCoE traffic class uses FCOE jumbo frames */
5175 if ((dev->features & NETIF_F_FCOE_MTU) &&
5176 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
5177 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
5178 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
5179#endif
5180
5181 /* Calculate delay value for device */
5182 switch (hw->mac.type) {
5183 case ixgbe_mac_X540:
5184 case ixgbe_mac_X550:
5185 case ixgbe_mac_X550EM_x:
5186 case ixgbe_mac_x550em_a:
5187 dv_id = IXGBE_LOW_DV_X540(tc);
5188 break;
5189 default:
5190 dv_id = IXGBE_LOW_DV(tc);
5191 break;
5192 }
5193
5194 /* Delay value is calculated in bit times convert to KB */
5195 return IXGBE_BT2KB(dv_id);
5196}
5197
5198/*
5199 * ixgbe_pbthresh_setup - calculate and setup high low water marks
5200 */
5201static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
5202{
5203 struct ixgbe_hw *hw = &adapter->hw;
5204 int num_tc = adapter->hw_tcs;
5205 int i;
5206
5207 if (!num_tc)
5208 num_tc = 1;
5209
5210 for (i = 0; i < num_tc; i++) {
5211 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
5212 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
5213
5214 /* Low water marks must not be larger than high water marks */
5215 if (hw->fc.low_water[i] > hw->fc.high_water[i])
5216 hw->fc.low_water[i] = 0;
5217 }
5218
5219 for (; i < MAX_TRAFFIC_CLASS; i++)
5220 hw->fc.high_water[i] = 0;
5221}
5222
5223static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
5224{
5225 struct ixgbe_hw *hw = &adapter->hw;
5226 int hdrm;
5227 u8 tc = adapter->hw_tcs;
5228
5229 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5230 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5231 hdrm = 32 << adapter->fdir_pballoc;
5232 else
5233 hdrm = 0;
5234
5235 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
5236 ixgbe_pbthresh_setup(adapter);
5237}
5238
5239static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
5240{
5241 struct ixgbe_hw *hw = &adapter->hw;
5242 struct hlist_node *node2;
5243 struct ixgbe_fdir_filter *filter;
5244 u8 queue;
5245
5246 spin_lock(&adapter->fdir_perfect_lock);
5247
5248 if (!hlist_empty(&adapter->fdir_filter_list))
5249 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
5250
5251 hlist_for_each_entry_safe(filter, node2,
5252 &adapter->fdir_filter_list, fdir_node) {
5253 if (filter->action == IXGBE_FDIR_DROP_QUEUE) {
5254 queue = IXGBE_FDIR_DROP_QUEUE;
5255 } else {
5256 u32 ring = ethtool_get_flow_spec_ring(filter->action);
5257 u8 vf = ethtool_get_flow_spec_ring_vf(filter->action);
5258
5259 if (!vf && (ring >= adapter->num_rx_queues)) {
5260 e_err(drv, "FDIR restore failed without VF, ring: %u\n",
5261 ring);
5262 continue;
5263 } else if (vf &&
5264 ((vf > adapter->num_vfs) ||
5265 ring >= adapter->num_rx_queues_per_pool)) {
5266 e_err(drv, "FDIR restore failed with VF, vf: %hhu, ring: %u\n",
5267 vf, ring);
5268 continue;
5269 }
5270
5271 /* Map the ring onto the absolute queue index */
5272 if (!vf)
5273 queue = adapter->rx_ring[ring]->reg_idx;
5274 else
5275 queue = ((vf - 1) *
5276 adapter->num_rx_queues_per_pool) + ring;
5277 }
5278
5279 ixgbe_fdir_write_perfect_filter_82599(hw,
5280 &filter->filter, filter->sw_idx, queue);
5281 }
5282
5283 spin_unlock(&adapter->fdir_perfect_lock);
5284}
5285
5286/**
5287 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
5288 * @rx_ring: ring to free buffers from
5289 **/
5290static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
5291{
5292 u16 i = rx_ring->next_to_clean;
5293 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
5294
5295 if (rx_ring->xsk_umem) {
5296 ixgbe_xsk_clean_rx_ring(rx_ring);
5297 goto skip_free;
5298 }
5299
5300 /* Free all the Rx ring sk_buffs */
5301 while (i != rx_ring->next_to_alloc) {
5302 if (rx_buffer->skb) {
5303 struct sk_buff *skb = rx_buffer->skb;
5304 if (IXGBE_CB(skb)->page_released)
5305 dma_unmap_page_attrs(rx_ring->dev,
5306 IXGBE_CB(skb)->dma,
5307 ixgbe_rx_pg_size(rx_ring),
5308 DMA_FROM_DEVICE,
5309 IXGBE_RX_DMA_ATTR);
5310 dev_kfree_skb(skb);
5311 }
5312
5313 /* Invalidate cache lines that may have been written to by
5314 * device so that we avoid corrupting memory.
5315 */
5316 dma_sync_single_range_for_cpu(rx_ring->dev,
5317 rx_buffer->dma,
5318 rx_buffer->page_offset,
5319 ixgbe_rx_bufsz(rx_ring),
5320 DMA_FROM_DEVICE);
5321
5322 /* free resources associated with mapping */
5323 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
5324 ixgbe_rx_pg_size(rx_ring),
5325 DMA_FROM_DEVICE,
5326 IXGBE_RX_DMA_ATTR);
5327 __page_frag_cache_drain(rx_buffer->page,
5328 rx_buffer->pagecnt_bias);
5329
5330 i++;
5331 rx_buffer++;
5332 if (i == rx_ring->count) {
5333 i = 0;
5334 rx_buffer = rx_ring->rx_buffer_info;
5335 }
5336 }
5337
5338skip_free:
5339 rx_ring->next_to_alloc = 0;
5340 rx_ring->next_to_clean = 0;
5341 rx_ring->next_to_use = 0;
5342}
5343
5344static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter,
5345 struct ixgbe_fwd_adapter *accel)
5346{
5347 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
5348 int num_tc = netdev_get_num_tc(adapter->netdev);
5349 struct net_device *vdev = accel->netdev;
5350 int i, baseq, err;
5351
5352 baseq = accel->pool * adapter->num_rx_queues_per_pool;
5353 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n",
5354 accel->pool, adapter->num_rx_pools,
5355 baseq, baseq + adapter->num_rx_queues_per_pool);
5356
5357 accel->rx_base_queue = baseq;
5358 accel->tx_base_queue = baseq;
5359
5360 /* record configuration for macvlan interface in vdev */
5361 for (i = 0; i < num_tc; i++)
5362 netdev_bind_sb_channel_queue(adapter->netdev, vdev,
5363 i, rss_i, baseq + (rss_i * i));
5364
5365 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
5366 adapter->rx_ring[baseq + i]->netdev = vdev;
5367
5368 /* Guarantee all rings are updated before we update the
5369 * MAC address filter.
5370 */
5371 wmb();
5372
5373 /* ixgbe_add_mac_filter will return an index if it succeeds, so we
5374 * need to only treat it as an error value if it is negative.
5375 */
5376 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr,
5377 VMDQ_P(accel->pool));
5378 if (err >= 0)
5379 return 0;
5380
5381 /* if we cannot add the MAC rule then disable the offload */
5382 macvlan_release_l2fw_offload(vdev);
5383
5384 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
5385 adapter->rx_ring[baseq + i]->netdev = NULL;
5386
5387 netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n");
5388
5389 /* unbind the queues and drop the subordinate channel config */
5390 netdev_unbind_sb_channel(adapter->netdev, vdev);
5391 netdev_set_sb_channel(vdev, 0);
5392
5393 clear_bit(accel->pool, adapter->fwd_bitmask);
5394 kfree(accel);
5395
5396 return err;
5397}
5398
5399static int ixgbe_macvlan_up(struct net_device *vdev,
5400 struct netdev_nested_priv *priv)
5401{
5402 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data;
5403 struct ixgbe_fwd_adapter *accel;
5404
5405 if (!netif_is_macvlan(vdev))
5406 return 0;
5407
5408 accel = macvlan_accel_priv(vdev);
5409 if (!accel)
5410 return 0;
5411
5412 ixgbe_fwd_ring_up(adapter, accel);
5413
5414 return 0;
5415}
5416
5417static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
5418{
5419 struct netdev_nested_priv priv = {
5420 .data = (void *)adapter,
5421 };
5422
5423 netdev_walk_all_upper_dev_rcu(adapter->netdev,
5424 ixgbe_macvlan_up, &priv);
5425}
5426
5427static void ixgbe_configure(struct ixgbe_adapter *adapter)
5428{
5429 struct ixgbe_hw *hw = &adapter->hw;
5430
5431 ixgbe_configure_pb(adapter);
5432#ifdef CONFIG_IXGBE_DCB
5433 ixgbe_configure_dcb(adapter);
5434#endif
5435 /*
5436 * We must restore virtualization before VLANs or else
5437 * the VLVF registers will not be populated
5438 */
5439 ixgbe_configure_virtualization(adapter);
5440
5441 ixgbe_set_rx_mode(adapter->netdev);
5442 ixgbe_restore_vlan(adapter);
5443 ixgbe_ipsec_restore(adapter);
5444
5445 switch (hw->mac.type) {
5446 case ixgbe_mac_82599EB:
5447 case ixgbe_mac_X540:
5448 hw->mac.ops.disable_rx_buff(hw);
5449 break;
5450 default:
5451 break;
5452 }
5453
5454 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5455 ixgbe_init_fdir_signature_82599(&adapter->hw,
5456 adapter->fdir_pballoc);
5457 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
5458 ixgbe_init_fdir_perfect_82599(&adapter->hw,
5459 adapter->fdir_pballoc);
5460 ixgbe_fdir_filter_restore(adapter);
5461 }
5462
5463 switch (hw->mac.type) {
5464 case ixgbe_mac_82599EB:
5465 case ixgbe_mac_X540:
5466 hw->mac.ops.enable_rx_buff(hw);
5467 break;
5468 default:
5469 break;
5470 }
5471
5472#ifdef CONFIG_IXGBE_DCA
5473 /* configure DCA */
5474 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
5475 ixgbe_setup_dca(adapter);
5476#endif /* CONFIG_IXGBE_DCA */
5477
5478#ifdef IXGBE_FCOE
5479 /* configure FCoE L2 filters, redirection table, and Rx control */
5480 ixgbe_configure_fcoe(adapter);
5481
5482#endif /* IXGBE_FCOE */
5483 ixgbe_configure_tx(adapter);
5484 ixgbe_configure_rx(adapter);
5485 ixgbe_configure_dfwd(adapter);
5486}
5487
5488/**
5489 * ixgbe_sfp_link_config - set up SFP+ link
5490 * @adapter: pointer to private adapter struct
5491 **/
5492static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
5493{
5494 /*
5495 * We are assuming the worst case scenario here, and that
5496 * is that an SFP was inserted/removed after the reset
5497 * but before SFP detection was enabled. As such the best
5498 * solution is to just start searching as soon as we start
5499 */
5500 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5501 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5502
5503 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5504 adapter->sfp_poll_time = 0;
5505}
5506
5507/**
5508 * ixgbe_non_sfp_link_config - set up non-SFP+ link
5509 * @hw: pointer to private hardware struct
5510 *
5511 * Returns 0 on success, negative on failure
5512 **/
5513static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
5514{
5515 u32 speed;
5516 bool autoneg, link_up = false;
5517 int ret = IXGBE_ERR_LINK_SETUP;
5518
5519 if (hw->mac.ops.check_link)
5520 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
5521
5522 if (ret)
5523 return ret;
5524
5525 speed = hw->phy.autoneg_advertised;
5526 if (!speed && hw->mac.ops.get_link_capabilities) {
5527 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
5528 &autoneg);
5529 speed &= ~(IXGBE_LINK_SPEED_5GB_FULL |
5530 IXGBE_LINK_SPEED_2_5GB_FULL);
5531 }
5532
5533 if (ret)
5534 return ret;
5535
5536 if (hw->mac.ops.setup_link)
5537 ret = hw->mac.ops.setup_link(hw, speed, link_up);
5538
5539 return ret;
5540}
5541
5542static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
5543{
5544 struct ixgbe_hw *hw = &adapter->hw;
5545 u32 gpie = 0;
5546
5547 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5548 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5549 IXGBE_GPIE_OCD;
5550 gpie |= IXGBE_GPIE_EIAME;
5551 /*
5552 * use EIAM to auto-mask when MSI-X interrupt is asserted
5553 * this saves a register write for every interrupt
5554 */
5555 switch (hw->mac.type) {
5556 case ixgbe_mac_82598EB:
5557 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5558 break;
5559 case ixgbe_mac_82599EB:
5560 case ixgbe_mac_X540:
5561 case ixgbe_mac_X550:
5562 case ixgbe_mac_X550EM_x:
5563 case ixgbe_mac_x550em_a:
5564 default:
5565 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5566 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5567 break;
5568 }
5569 } else {
5570 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
5571 * specifically only auto mask tx and rx interrupts */
5572 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5573 }
5574
5575 /* XXX: to interrupt immediately for EICS writes, enable this */
5576 /* gpie |= IXGBE_GPIE_EIMEN; */
5577
5578 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
5579 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
5580
5581 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
5582 case IXGBE_82599_VMDQ_8Q_MASK:
5583 gpie |= IXGBE_GPIE_VTMODE_16;
5584 break;
5585 case IXGBE_82599_VMDQ_4Q_MASK:
5586 gpie |= IXGBE_GPIE_VTMODE_32;
5587 break;
5588 default:
5589 gpie |= IXGBE_GPIE_VTMODE_64;
5590 break;
5591 }
5592 }
5593
5594 /* Enable Thermal over heat sensor interrupt */
5595 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
5596 switch (adapter->hw.mac.type) {
5597 case ixgbe_mac_82599EB:
5598 gpie |= IXGBE_SDP0_GPIEN_8259X;
5599 break;
5600 default:
5601 break;
5602 }
5603 }
5604
5605 /* Enable fan failure interrupt */
5606 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
5607 gpie |= IXGBE_SDP1_GPIEN(hw);
5608
5609 switch (hw->mac.type) {
5610 case ixgbe_mac_82599EB:
5611 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
5612 break;
5613 case ixgbe_mac_X550EM_x:
5614 case ixgbe_mac_x550em_a:
5615 gpie |= IXGBE_SDP0_GPIEN_X540;
5616 break;
5617 default:
5618 break;
5619 }
5620
5621 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5622}
5623
5624static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
5625{
5626 struct ixgbe_hw *hw = &adapter->hw;
5627 int err;
5628 u32 ctrl_ext;
5629
5630 ixgbe_get_hw_control(adapter);
5631 ixgbe_setup_gpie(adapter);
5632
5633 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5634 ixgbe_configure_msix(adapter);
5635 else
5636 ixgbe_configure_msi_and_legacy(adapter);
5637
5638 /* enable the optics for 82599 SFP+ fiber */
5639 if (hw->mac.ops.enable_tx_laser)
5640 hw->mac.ops.enable_tx_laser(hw);
5641
5642 if (hw->phy.ops.set_phy_power)
5643 hw->phy.ops.set_phy_power(hw, true);
5644
5645 smp_mb__before_atomic();
5646 clear_bit(__IXGBE_DOWN, &adapter->state);
5647 ixgbe_napi_enable_all(adapter);
5648
5649 if (ixgbe_is_sfp(hw)) {
5650 ixgbe_sfp_link_config(adapter);
5651 } else {
5652 err = ixgbe_non_sfp_link_config(hw);
5653 if (err)
5654 e_err(probe, "link_config FAILED %d\n", err);
5655 }
5656
5657 /* clear any pending interrupts, may auto mask */
5658 IXGBE_READ_REG(hw, IXGBE_EICR);
5659 ixgbe_irq_enable(adapter, true, true);
5660
5661 /*
5662 * If this adapter has a fan, check to see if we had a failure
5663 * before we enabled the interrupt.
5664 */
5665 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5666 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5667 if (esdp & IXGBE_ESDP_SDP1)
5668 e_crit(drv, "Fan has stopped, replace the adapter\n");
5669 }
5670
5671 /* bring the link up in the watchdog, this could race with our first
5672 * link up interrupt but shouldn't be a problem */
5673 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5674 adapter->link_check_timeout = jiffies;
5675 mod_timer(&adapter->service_timer, jiffies);
5676
5677 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
5678 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5679 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5680 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
5681}
5682
5683void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5684{
5685 WARN_ON(in_interrupt());
5686 /* put off any impending NetWatchDogTimeout */
5687 netif_trans_update(adapter->netdev);
5688
5689 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
5690 usleep_range(1000, 2000);
5691 if (adapter->hw.phy.type == ixgbe_phy_fw)
5692 ixgbe_watchdog_link_is_down(adapter);
5693 ixgbe_down(adapter);
5694 /*
5695 * If SR-IOV enabled then wait a bit before bringing the adapter
5696 * back up to give the VFs time to respond to the reset. The
5697 * two second wait is based upon the watchdog timer cycle in
5698 * the VF driver.
5699 */
5700 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5701 msleep(2000);
5702 ixgbe_up(adapter);
5703 clear_bit(__IXGBE_RESETTING, &adapter->state);
5704}
5705
5706void ixgbe_up(struct ixgbe_adapter *adapter)
5707{
5708 /* hardware has been reset, we need to reload some things */
5709 ixgbe_configure(adapter);
5710
5711 ixgbe_up_complete(adapter);
5712}
5713
5714static unsigned long ixgbe_get_completion_timeout(struct ixgbe_adapter *adapter)
5715{
5716 u16 devctl2;
5717
5718 pcie_capability_read_word(adapter->pdev, PCI_EXP_DEVCTL2, &devctl2);
5719
5720 switch (devctl2 & IXGBE_PCIDEVCTRL2_TIMEO_MASK) {
5721 case IXGBE_PCIDEVCTRL2_17_34s:
5722 case IXGBE_PCIDEVCTRL2_4_8s:
5723 /* For now we cap the upper limit on delay to 2 seconds
5724 * as we end up going up to 34 seconds of delay in worst
5725 * case timeout value.
5726 */
5727 case IXGBE_PCIDEVCTRL2_1_2s:
5728 return 2000000ul; /* 2.0 s */
5729 case IXGBE_PCIDEVCTRL2_260_520ms:
5730 return 520000ul; /* 520 ms */
5731 case IXGBE_PCIDEVCTRL2_65_130ms:
5732 return 130000ul; /* 130 ms */
5733 case IXGBE_PCIDEVCTRL2_16_32ms:
5734 return 32000ul; /* 32 ms */
5735 case IXGBE_PCIDEVCTRL2_1_2ms:
5736 return 2000ul; /* 2 ms */
5737 case IXGBE_PCIDEVCTRL2_50_100us:
5738 return 100ul; /* 100 us */
5739 case IXGBE_PCIDEVCTRL2_16_32ms_def:
5740 return 32000ul; /* 32 ms */
5741 default:
5742 break;
5743 }
5744
5745 /* We shouldn't need to hit this path, but just in case default as
5746 * though completion timeout is not supported and support 32ms.
5747 */
5748 return 32000ul;
5749}
5750
5751void ixgbe_disable_rx(struct ixgbe_adapter *adapter)
5752{
5753 unsigned long wait_delay, delay_interval;
5754 struct ixgbe_hw *hw = &adapter->hw;
5755 int i, wait_loop;
5756 u32 rxdctl;
5757
5758 /* disable receives */
5759 hw->mac.ops.disable_rx(hw);
5760
5761 if (ixgbe_removed(hw->hw_addr))
5762 return;
5763
5764 /* disable all enabled Rx queues */
5765 for (i = 0; i < adapter->num_rx_queues; i++) {
5766 struct ixgbe_ring *ring = adapter->rx_ring[i];
5767 u8 reg_idx = ring->reg_idx;
5768
5769 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
5770 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
5771 rxdctl |= IXGBE_RXDCTL_SWFLSH;
5772
5773 /* write value back with RXDCTL.ENABLE bit cleared */
5774 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
5775 }
5776
5777 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */
5778 if (hw->mac.type == ixgbe_mac_82598EB &&
5779 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
5780 return;
5781
5782 /* Determine our minimum delay interval. We will increase this value
5783 * with each subsequent test. This way if the device returns quickly
5784 * we should spend as little time as possible waiting, however as
5785 * the time increases we will wait for larger periods of time.
5786 *
5787 * The trick here is that we increase the interval using the
5788 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result
5789 * of that wait is that it totals up to 100x whatever interval we
5790 * choose. Since our minimum wait is 100us we can just divide the
5791 * total timeout by 100 to get our minimum delay interval.
5792 */
5793 delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
5794
5795 wait_loop = IXGBE_MAX_RX_DESC_POLL;
5796 wait_delay = delay_interval;
5797
5798 while (wait_loop--) {
5799 usleep_range(wait_delay, wait_delay + 10);
5800 wait_delay += delay_interval * 2;
5801 rxdctl = 0;
5802
5803 /* OR together the reading of all the active RXDCTL registers,
5804 * and then test the result. We need the disable to complete
5805 * before we start freeing the memory and invalidating the
5806 * DMA mappings.
5807 */
5808 for (i = 0; i < adapter->num_rx_queues; i++) {
5809 struct ixgbe_ring *ring = adapter->rx_ring[i];
5810 u8 reg_idx = ring->reg_idx;
5811
5812 rxdctl |= IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
5813 }
5814
5815 if (!(rxdctl & IXGBE_RXDCTL_ENABLE))
5816 return;
5817 }
5818
5819 e_err(drv,
5820 "RXDCTL.ENABLE for one or more queues not cleared within the polling period\n");
5821}
5822
5823void ixgbe_disable_tx(struct ixgbe_adapter *adapter)
5824{
5825 unsigned long wait_delay, delay_interval;
5826 struct ixgbe_hw *hw = &adapter->hw;
5827 int i, wait_loop;
5828 u32 txdctl;
5829
5830 if (ixgbe_removed(hw->hw_addr))
5831 return;
5832
5833 /* disable all enabled Tx queues */
5834 for (i = 0; i < adapter->num_tx_queues; i++) {
5835 struct ixgbe_ring *ring = adapter->tx_ring[i];
5836 u8 reg_idx = ring->reg_idx;
5837
5838 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5839 }
5840
5841 /* disable all enabled XDP Tx queues */
5842 for (i = 0; i < adapter->num_xdp_queues; i++) {
5843 struct ixgbe_ring *ring = adapter->xdp_ring[i];
5844 u8 reg_idx = ring->reg_idx;
5845
5846 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5847 }
5848
5849 /* If the link is not up there shouldn't be much in the way of
5850 * pending transactions. Those that are left will be flushed out
5851 * when the reset logic goes through the flush sequence to clean out
5852 * the pending Tx transactions.
5853 */
5854 if (!(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
5855 goto dma_engine_disable;
5856
5857 /* Determine our minimum delay interval. We will increase this value
5858 * with each subsequent test. This way if the device returns quickly
5859 * we should spend as little time as possible waiting, however as
5860 * the time increases we will wait for larger periods of time.
5861 *
5862 * The trick here is that we increase the interval using the
5863 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result
5864 * of that wait is that it totals up to 100x whatever interval we
5865 * choose. Since our minimum wait is 100us we can just divide the
5866 * total timeout by 100 to get our minimum delay interval.
5867 */
5868 delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
5869
5870 wait_loop = IXGBE_MAX_RX_DESC_POLL;
5871 wait_delay = delay_interval;
5872
5873 while (wait_loop--) {
5874 usleep_range(wait_delay, wait_delay + 10);
5875 wait_delay += delay_interval * 2;
5876 txdctl = 0;
5877
5878 /* OR together the reading of all the active TXDCTL registers,
5879 * and then test the result. We need the disable to complete
5880 * before we start freeing the memory and invalidating the
5881 * DMA mappings.
5882 */
5883 for (i = 0; i < adapter->num_tx_queues; i++) {
5884 struct ixgbe_ring *ring = adapter->tx_ring[i];
5885 u8 reg_idx = ring->reg_idx;
5886
5887 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
5888 }
5889 for (i = 0; i < adapter->num_xdp_queues; i++) {
5890 struct ixgbe_ring *ring = adapter->xdp_ring[i];
5891 u8 reg_idx = ring->reg_idx;
5892
5893 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
5894 }
5895
5896 if (!(txdctl & IXGBE_TXDCTL_ENABLE))
5897 goto dma_engine_disable;
5898 }
5899
5900 e_err(drv,
5901 "TXDCTL.ENABLE for one or more queues not cleared within the polling period\n");
5902
5903dma_engine_disable:
5904 /* Disable the Tx DMA engine on 82599 and later MAC */
5905 switch (hw->mac.type) {
5906 case ixgbe_mac_82599EB:
5907 case ixgbe_mac_X540:
5908 case ixgbe_mac_X550:
5909 case ixgbe_mac_X550EM_x:
5910 case ixgbe_mac_x550em_a:
5911 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
5912 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5913 ~IXGBE_DMATXCTL_TE));
5914 fallthrough;
5915 default:
5916 break;
5917 }
5918}
5919
5920void ixgbe_reset(struct ixgbe_adapter *adapter)
5921{
5922 struct ixgbe_hw *hw = &adapter->hw;
5923 struct net_device *netdev = adapter->netdev;
5924 int err;
5925
5926 if (ixgbe_removed(hw->hw_addr))
5927 return;
5928 /* lock SFP init bit to prevent race conditions with the watchdog */
5929 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5930 usleep_range(1000, 2000);
5931
5932 /* clear all SFP and link config related flags while holding SFP_INIT */
5933 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5934 IXGBE_FLAG2_SFP_NEEDS_RESET);
5935 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5936
5937 err = hw->mac.ops.init_hw(hw);
5938 switch (err) {
5939 case 0:
5940 case IXGBE_ERR_SFP_NOT_PRESENT:
5941 case IXGBE_ERR_SFP_NOT_SUPPORTED:
5942 break;
5943 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
5944 e_dev_err("master disable timed out\n");
5945 break;
5946 case IXGBE_ERR_EEPROM_VERSION:
5947 /* We are running on a pre-production device, log a warning */
5948 e_dev_warn("This device is a pre-production adapter/LOM. "
5949 "Please be aware there may be issues associated with "
5950 "your hardware. If you are experiencing problems "
5951 "please contact your Intel or hardware "
5952 "representative who provided you with this "
5953 "hardware.\n");
5954 break;
5955 default:
5956 e_dev_err("Hardware Error: %d\n", err);
5957 }
5958
5959 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5960
5961 /* flush entries out of MAC table */
5962 ixgbe_flush_sw_mac_table(adapter);
5963 __dev_uc_unsync(netdev, NULL);
5964
5965 /* do not flush user set addresses */
5966 ixgbe_mac_set_default_filter(adapter);
5967
5968 /* update SAN MAC vmdq pool selection */
5969 if (hw->mac.san_mac_rar_index)
5970 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
5971
5972 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
5973 ixgbe_ptp_reset(adapter);
5974
5975 if (hw->phy.ops.set_phy_power) {
5976 if (!netif_running(adapter->netdev) && !adapter->wol)
5977 hw->phy.ops.set_phy_power(hw, false);
5978 else
5979 hw->phy.ops.set_phy_power(hw, true);
5980 }
5981}
5982
5983/**
5984 * ixgbe_clean_tx_ring - Free Tx Buffers
5985 * @tx_ring: ring to be cleaned
5986 **/
5987static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
5988{
5989 u16 i = tx_ring->next_to_clean;
5990 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
5991
5992 if (tx_ring->xsk_umem) {
5993 ixgbe_xsk_clean_tx_ring(tx_ring);
5994 goto out;
5995 }
5996
5997 while (i != tx_ring->next_to_use) {
5998 union ixgbe_adv_tx_desc *eop_desc, *tx_desc;
5999
6000 /* Free all the Tx ring sk_buffs */
6001 if (ring_is_xdp(tx_ring))
6002 xdp_return_frame(tx_buffer->xdpf);
6003 else
6004 dev_kfree_skb_any(tx_buffer->skb);
6005
6006 /* unmap skb header data */
6007 dma_unmap_single(tx_ring->dev,
6008 dma_unmap_addr(tx_buffer, dma),
6009 dma_unmap_len(tx_buffer, len),
6010 DMA_TO_DEVICE);
6011
6012 /* check for eop_desc to determine the end of the packet */
6013 eop_desc = tx_buffer->next_to_watch;
6014 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6015
6016 /* unmap remaining buffers */
6017 while (tx_desc != eop_desc) {
6018 tx_buffer++;
6019 tx_desc++;
6020 i++;
6021 if (unlikely(i == tx_ring->count)) {
6022 i = 0;
6023 tx_buffer = tx_ring->tx_buffer_info;
6024 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6025 }
6026
6027 /* unmap any remaining paged data */
6028 if (dma_unmap_len(tx_buffer, len))
6029 dma_unmap_page(tx_ring->dev,
6030 dma_unmap_addr(tx_buffer, dma),
6031 dma_unmap_len(tx_buffer, len),
6032 DMA_TO_DEVICE);
6033 }
6034
6035 /* move us one more past the eop_desc for start of next pkt */
6036 tx_buffer++;
6037 i++;
6038 if (unlikely(i == tx_ring->count)) {
6039 i = 0;
6040 tx_buffer = tx_ring->tx_buffer_info;
6041 }
6042 }
6043
6044 /* reset BQL for queue */
6045 if (!ring_is_xdp(tx_ring))
6046 netdev_tx_reset_queue(txring_txq(tx_ring));
6047
6048out:
6049 /* reset next_to_use and next_to_clean */
6050 tx_ring->next_to_use = 0;
6051 tx_ring->next_to_clean = 0;
6052}
6053
6054/**
6055 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
6056 * @adapter: board private structure
6057 **/
6058static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
6059{
6060 int i;
6061
6062 for (i = 0; i < adapter->num_rx_queues; i++)
6063 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
6064}
6065
6066/**
6067 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
6068 * @adapter: board private structure
6069 **/
6070static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
6071{
6072 int i;
6073
6074 for (i = 0; i < adapter->num_tx_queues; i++)
6075 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
6076 for (i = 0; i < adapter->num_xdp_queues; i++)
6077 ixgbe_clean_tx_ring(adapter->xdp_ring[i]);
6078}
6079
6080static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
6081{
6082 struct hlist_node *node2;
6083 struct ixgbe_fdir_filter *filter;
6084
6085 spin_lock(&adapter->fdir_perfect_lock);
6086
6087 hlist_for_each_entry_safe(filter, node2,
6088 &adapter->fdir_filter_list, fdir_node) {
6089 hlist_del(&filter->fdir_node);
6090 kfree(filter);
6091 }
6092 adapter->fdir_filter_count = 0;
6093
6094 spin_unlock(&adapter->fdir_perfect_lock);
6095}
6096
6097void ixgbe_down(struct ixgbe_adapter *adapter)
6098{
6099 struct net_device *netdev = adapter->netdev;
6100 struct ixgbe_hw *hw = &adapter->hw;
6101 int i;
6102
6103 /* signal that we are down to the interrupt handler */
6104 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
6105 return; /* do nothing if already down */
6106
6107 /* Shut off incoming Tx traffic */
6108 netif_tx_stop_all_queues(netdev);
6109
6110 /* call carrier off first to avoid false dev_watchdog timeouts */
6111 netif_carrier_off(netdev);
6112 netif_tx_disable(netdev);
6113
6114 /* Disable Rx */
6115 ixgbe_disable_rx(adapter);
6116
6117 /* synchronize_rcu() needed for pending XDP buffers to drain */
6118 if (adapter->xdp_ring[0])
6119 synchronize_rcu();
6120
6121 ixgbe_irq_disable(adapter);
6122
6123 ixgbe_napi_disable_all(adapter);
6124
6125 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
6126 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
6127 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6128
6129 del_timer_sync(&adapter->service_timer);
6130
6131 if (adapter->num_vfs) {
6132 /* Clear EITR Select mapping */
6133 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
6134
6135 /* Mark all the VFs as inactive */
6136 for (i = 0 ; i < adapter->num_vfs; i++)
6137 adapter->vfinfo[i].clear_to_send = false;
6138
6139 /* ping all the active vfs to let them know we are going down */
6140 ixgbe_ping_all_vfs(adapter);
6141
6142 /* Disable all VFTE/VFRE TX/RX */
6143 ixgbe_disable_tx_rx(adapter);
6144 }
6145
6146 /* disable transmits in the hardware now that interrupts are off */
6147 ixgbe_disable_tx(adapter);
6148
6149 if (!pci_channel_offline(adapter->pdev))
6150 ixgbe_reset(adapter);
6151
6152 /* power down the optics for 82599 SFP+ fiber */
6153 if (hw->mac.ops.disable_tx_laser)
6154 hw->mac.ops.disable_tx_laser(hw);
6155
6156 ixgbe_clean_all_tx_rings(adapter);
6157 ixgbe_clean_all_rx_rings(adapter);
6158}
6159
6160/**
6161 * ixgbe_eee_capable - helper function to determine EEE support on X550
6162 * @adapter: board private structure
6163 */
6164static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter)
6165{
6166 struct ixgbe_hw *hw = &adapter->hw;
6167
6168 switch (hw->device_id) {
6169 case IXGBE_DEV_ID_X550EM_A_1G_T:
6170 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
6171 if (!hw->phy.eee_speeds_supported)
6172 break;
6173 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE;
6174 if (!hw->phy.eee_speeds_advertised)
6175 break;
6176 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED;
6177 break;
6178 default:
6179 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE;
6180 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED;
6181 break;
6182 }
6183}
6184
6185/**
6186 * ixgbe_tx_timeout - Respond to a Tx Hang
6187 * @netdev: network interface device structure
6188 **/
6189static void ixgbe_tx_timeout(struct net_device *netdev, unsigned int txqueue)
6190{
6191 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6192
6193 /* Do the reset outside of interrupt context */
6194 ixgbe_tx_timeout_reset(adapter);
6195}
6196
6197#ifdef CONFIG_IXGBE_DCB
6198static void ixgbe_init_dcb(struct ixgbe_adapter *adapter)
6199{
6200 struct ixgbe_hw *hw = &adapter->hw;
6201 struct tc_configuration *tc;
6202 int j;
6203
6204 switch (hw->mac.type) {
6205 case ixgbe_mac_82598EB:
6206 case ixgbe_mac_82599EB:
6207 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
6208 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
6209 break;
6210 case ixgbe_mac_X540:
6211 case ixgbe_mac_X550:
6212 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
6213 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
6214 break;
6215 case ixgbe_mac_X550EM_x:
6216 case ixgbe_mac_x550em_a:
6217 default:
6218 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS;
6219 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS;
6220 break;
6221 }
6222
6223 /* Configure DCB traffic classes */
6224 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
6225 tc = &adapter->dcb_cfg.tc_config[j];
6226 tc->path[DCB_TX_CONFIG].bwg_id = 0;
6227 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
6228 tc->path[DCB_RX_CONFIG].bwg_id = 0;
6229 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
6230 tc->dcb_pfc = pfc_disabled;
6231 }
6232
6233 /* Initialize default user to priority mapping, UPx->TC0 */
6234 tc = &adapter->dcb_cfg.tc_config[0];
6235 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
6236 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
6237
6238 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
6239 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
6240 adapter->dcb_cfg.pfc_mode_enable = false;
6241 adapter->dcb_set_bitmap = 0x00;
6242 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE)
6243 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
6244 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
6245 sizeof(adapter->temp_dcb_cfg));
6246}
6247#endif
6248
6249/**
6250 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
6251 * @adapter: board private structure to initialize
6252 * @ii: pointer to ixgbe_info for device
6253 *
6254 * ixgbe_sw_init initializes the Adapter private data structure.
6255 * Fields are initialized based on PCI device information and
6256 * OS network device settings (MTU size).
6257 **/
6258static int ixgbe_sw_init(struct ixgbe_adapter *adapter,
6259 const struct ixgbe_info *ii)
6260{
6261 struct ixgbe_hw *hw = &adapter->hw;
6262 struct pci_dev *pdev = adapter->pdev;
6263 unsigned int rss, fdir;
6264 u32 fwsm;
6265 int i;
6266
6267 /* PCI config space info */
6268
6269 hw->vendor_id = pdev->vendor;
6270 hw->device_id = pdev->device;
6271 hw->revision_id = pdev->revision;
6272 hw->subsystem_vendor_id = pdev->subsystem_vendor;
6273 hw->subsystem_device_id = pdev->subsystem_device;
6274
6275 /* get_invariants needs the device IDs */
6276 ii->get_invariants(hw);
6277
6278 /* Set common capability flags and settings */
6279 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
6280 adapter->ring_feature[RING_F_RSS].limit = rss;
6281 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
6282 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
6283 adapter->atr_sample_rate = 20;
6284 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
6285 adapter->ring_feature[RING_F_FDIR].limit = fdir;
6286 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
6287 adapter->ring_feature[RING_F_VMDQ].limit = 1;
6288#ifdef CONFIG_IXGBE_DCA
6289 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
6290#endif
6291#ifdef CONFIG_IXGBE_DCB
6292 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE;
6293 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6294#endif
6295#ifdef IXGBE_FCOE
6296 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
6297 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
6298#ifdef CONFIG_IXGBE_DCB
6299 /* Default traffic class to use for FCoE */
6300 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
6301#endif /* CONFIG_IXGBE_DCB */
6302#endif /* IXGBE_FCOE */
6303
6304 /* initialize static ixgbe jump table entries */
6305 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]),
6306 GFP_KERNEL);
6307 if (!adapter->jump_tables[0])
6308 return -ENOMEM;
6309 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields;
6310
6311 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++)
6312 adapter->jump_tables[i] = NULL;
6313
6314 adapter->mac_table = kcalloc(hw->mac.num_rar_entries,
6315 sizeof(struct ixgbe_mac_addr),
6316 GFP_KERNEL);
6317 if (!adapter->mac_table)
6318 return -ENOMEM;
6319
6320 if (ixgbe_init_rss_key(adapter))
6321 return -ENOMEM;
6322
6323 adapter->af_xdp_zc_qps = bitmap_zalloc(MAX_XDP_QUEUES, GFP_KERNEL);
6324 if (!adapter->af_xdp_zc_qps)
6325 return -ENOMEM;
6326
6327 /* Set MAC specific capability flags and exceptions */
6328 switch (hw->mac.type) {
6329 case ixgbe_mac_82598EB:
6330 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
6331
6332 if (hw->device_id == IXGBE_DEV_ID_82598AT)
6333 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
6334
6335 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
6336 adapter->ring_feature[RING_F_FDIR].limit = 0;
6337 adapter->atr_sample_rate = 0;
6338 adapter->fdir_pballoc = 0;
6339#ifdef IXGBE_FCOE
6340 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6341 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
6342#ifdef CONFIG_IXGBE_DCB
6343 adapter->fcoe.up = 0;
6344#endif /* IXGBE_DCB */
6345#endif /* IXGBE_FCOE */
6346 break;
6347 case ixgbe_mac_82599EB:
6348 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
6349 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6350 break;
6351 case ixgbe_mac_X540:
6352 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
6353 if (fwsm & IXGBE_FWSM_TS_ENABLED)
6354 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6355 break;
6356 case ixgbe_mac_x550em_a:
6357 switch (hw->device_id) {
6358 case IXGBE_DEV_ID_X550EM_A_1G_T:
6359 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
6360 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6361 break;
6362 default:
6363 break;
6364 }
6365 fallthrough;
6366 case ixgbe_mac_X550EM_x:
6367#ifdef CONFIG_IXGBE_DCB
6368 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE;
6369#endif
6370#ifdef IXGBE_FCOE
6371 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6372#ifdef CONFIG_IXGBE_DCB
6373 adapter->fcoe.up = 0;
6374#endif /* IXGBE_DCB */
6375#endif /* IXGBE_FCOE */
6376 fallthrough;
6377 case ixgbe_mac_X550:
6378 if (hw->mac.type == ixgbe_mac_X550)
6379 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6380#ifdef CONFIG_IXGBE_DCA
6381 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
6382#endif
6383 break;
6384 default:
6385 break;
6386 }
6387
6388#ifdef IXGBE_FCOE
6389 /* FCoE support exists, always init the FCoE lock */
6390 spin_lock_init(&adapter->fcoe.lock);
6391
6392#endif
6393 /* n-tuple support exists, always init our spinlock */
6394 spin_lock_init(&adapter->fdir_perfect_lock);
6395
6396#ifdef CONFIG_IXGBE_DCB
6397 ixgbe_init_dcb(adapter);
6398#endif
6399 ixgbe_init_ipsec_offload(adapter);
6400
6401 /* default flow control settings */
6402 hw->fc.requested_mode = ixgbe_fc_full;
6403 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
6404 ixgbe_pbthresh_setup(adapter);
6405 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
6406 hw->fc.send_xon = true;
6407 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
6408
6409#ifdef CONFIG_PCI_IOV
6410 if (max_vfs > 0)
6411 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
6412
6413 /* assign number of SR-IOV VFs */
6414 if (hw->mac.type != ixgbe_mac_82598EB) {
6415 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
6416 max_vfs = 0;
6417 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
6418 }
6419 }
6420#endif /* CONFIG_PCI_IOV */
6421
6422 /* enable itr by default in dynamic mode */
6423 adapter->rx_itr_setting = 1;
6424 adapter->tx_itr_setting = 1;
6425
6426 /* set default ring sizes */
6427 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
6428 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
6429
6430 /* set default work limits */
6431 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
6432
6433 /* initialize eeprom parameters */
6434 if (ixgbe_init_eeprom_params_generic(hw)) {
6435 e_dev_err("EEPROM initialization failed\n");
6436 return -EIO;
6437 }
6438
6439 /* PF holds first pool slot */
6440 set_bit(0, adapter->fwd_bitmask);
6441 set_bit(__IXGBE_DOWN, &adapter->state);
6442
6443 return 0;
6444}
6445
6446/**
6447 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
6448 * @tx_ring: tx descriptor ring (for a specific queue) to setup
6449 *
6450 * Return 0 on success, negative on failure
6451 **/
6452int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
6453{
6454 struct device *dev = tx_ring->dev;
6455 int orig_node = dev_to_node(dev);
6456 int ring_node = NUMA_NO_NODE;
6457 int size;
6458
6459 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
6460
6461 if (tx_ring->q_vector)
6462 ring_node = tx_ring->q_vector->numa_node;
6463
6464 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node);
6465 if (!tx_ring->tx_buffer_info)
6466 tx_ring->tx_buffer_info = vmalloc(size);
6467 if (!tx_ring->tx_buffer_info)
6468 goto err;
6469
6470 /* round up to nearest 4K */
6471 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
6472 tx_ring->size = ALIGN(tx_ring->size, 4096);
6473
6474 set_dev_node(dev, ring_node);
6475 tx_ring->desc = dma_alloc_coherent(dev,
6476 tx_ring->size,
6477 &tx_ring->dma,
6478 GFP_KERNEL);
6479 set_dev_node(dev, orig_node);
6480 if (!tx_ring->desc)
6481 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
6482 &tx_ring->dma, GFP_KERNEL);
6483 if (!tx_ring->desc)
6484 goto err;
6485
6486 tx_ring->next_to_use = 0;
6487 tx_ring->next_to_clean = 0;
6488 return 0;
6489
6490err:
6491 vfree(tx_ring->tx_buffer_info);
6492 tx_ring->tx_buffer_info = NULL;
6493 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
6494 return -ENOMEM;
6495}
6496
6497/**
6498 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
6499 * @adapter: board private structure
6500 *
6501 * If this function returns with an error, then it's possible one or
6502 * more of the rings is populated (while the rest are not). It is the
6503 * callers duty to clean those orphaned rings.
6504 *
6505 * Return 0 on success, negative on failure
6506 **/
6507static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
6508{
6509 int i, j = 0, err = 0;
6510
6511 for (i = 0; i < adapter->num_tx_queues; i++) {
6512 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
6513 if (!err)
6514 continue;
6515
6516 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
6517 goto err_setup_tx;
6518 }
6519 for (j = 0; j < adapter->num_xdp_queues; j++) {
6520 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]);
6521 if (!err)
6522 continue;
6523
6524 e_err(probe, "Allocation for Tx Queue %u failed\n", j);
6525 goto err_setup_tx;
6526 }
6527
6528 return 0;
6529err_setup_tx:
6530 /* rewind the index freeing the rings as we go */
6531 while (j--)
6532 ixgbe_free_tx_resources(adapter->xdp_ring[j]);
6533 while (i--)
6534 ixgbe_free_tx_resources(adapter->tx_ring[i]);
6535 return err;
6536}
6537
6538/**
6539 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
6540 * @adapter: pointer to ixgbe_adapter
6541 * @rx_ring: rx descriptor ring (for a specific queue) to setup
6542 *
6543 * Returns 0 on success, negative on failure
6544 **/
6545int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
6546 struct ixgbe_ring *rx_ring)
6547{
6548 struct device *dev = rx_ring->dev;
6549 int orig_node = dev_to_node(dev);
6550 int ring_node = NUMA_NO_NODE;
6551 int size;
6552
6553 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
6554
6555 if (rx_ring->q_vector)
6556 ring_node = rx_ring->q_vector->numa_node;
6557
6558 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node);
6559 if (!rx_ring->rx_buffer_info)
6560 rx_ring->rx_buffer_info = vmalloc(size);
6561 if (!rx_ring->rx_buffer_info)
6562 goto err;
6563
6564 /* Round up to nearest 4K */
6565 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
6566 rx_ring->size = ALIGN(rx_ring->size, 4096);
6567
6568 set_dev_node(dev, ring_node);
6569 rx_ring->desc = dma_alloc_coherent(dev,
6570 rx_ring->size,
6571 &rx_ring->dma,
6572 GFP_KERNEL);
6573 set_dev_node(dev, orig_node);
6574 if (!rx_ring->desc)
6575 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
6576 &rx_ring->dma, GFP_KERNEL);
6577 if (!rx_ring->desc)
6578 goto err;
6579
6580 rx_ring->next_to_clean = 0;
6581 rx_ring->next_to_use = 0;
6582
6583 /* XDP RX-queue info */
6584 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev,
6585 rx_ring->queue_index) < 0)
6586 goto err;
6587
6588 rx_ring->xdp_prog = adapter->xdp_prog;
6589
6590 return 0;
6591err:
6592 vfree(rx_ring->rx_buffer_info);
6593 rx_ring->rx_buffer_info = NULL;
6594 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
6595 return -ENOMEM;
6596}
6597
6598/**
6599 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
6600 * @adapter: board private structure
6601 *
6602 * If this function returns with an error, then it's possible one or
6603 * more of the rings is populated (while the rest are not). It is the
6604 * callers duty to clean those orphaned rings.
6605 *
6606 * Return 0 on success, negative on failure
6607 **/
6608static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
6609{
6610 int i, err = 0;
6611
6612 for (i = 0; i < adapter->num_rx_queues; i++) {
6613 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
6614 if (!err)
6615 continue;
6616
6617 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
6618 goto err_setup_rx;
6619 }
6620
6621#ifdef IXGBE_FCOE
6622 err = ixgbe_setup_fcoe_ddp_resources(adapter);
6623 if (!err)
6624#endif
6625 return 0;
6626err_setup_rx:
6627 /* rewind the index freeing the rings as we go */
6628 while (i--)
6629 ixgbe_free_rx_resources(adapter->rx_ring[i]);
6630 return err;
6631}
6632
6633/**
6634 * ixgbe_free_tx_resources - Free Tx Resources per Queue
6635 * @tx_ring: Tx descriptor ring for a specific queue
6636 *
6637 * Free all transmit software resources
6638 **/
6639void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
6640{
6641 ixgbe_clean_tx_ring(tx_ring);
6642
6643 vfree(tx_ring->tx_buffer_info);
6644 tx_ring->tx_buffer_info = NULL;
6645
6646 /* if not set, then don't free */
6647 if (!tx_ring->desc)
6648 return;
6649
6650 dma_free_coherent(tx_ring->dev, tx_ring->size,
6651 tx_ring->desc, tx_ring->dma);
6652
6653 tx_ring->desc = NULL;
6654}
6655
6656/**
6657 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
6658 * @adapter: board private structure
6659 *
6660 * Free all transmit software resources
6661 **/
6662static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
6663{
6664 int i;
6665
6666 for (i = 0; i < adapter->num_tx_queues; i++)
6667 if (adapter->tx_ring[i]->desc)
6668 ixgbe_free_tx_resources(adapter->tx_ring[i]);
6669 for (i = 0; i < adapter->num_xdp_queues; i++)
6670 if (adapter->xdp_ring[i]->desc)
6671 ixgbe_free_tx_resources(adapter->xdp_ring[i]);
6672}
6673
6674/**
6675 * ixgbe_free_rx_resources - Free Rx Resources
6676 * @rx_ring: ring to clean the resources from
6677 *
6678 * Free all receive software resources
6679 **/
6680void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
6681{
6682 ixgbe_clean_rx_ring(rx_ring);
6683
6684 rx_ring->xdp_prog = NULL;
6685 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
6686 vfree(rx_ring->rx_buffer_info);
6687 rx_ring->rx_buffer_info = NULL;
6688
6689 /* if not set, then don't free */
6690 if (!rx_ring->desc)
6691 return;
6692
6693 dma_free_coherent(rx_ring->dev, rx_ring->size,
6694 rx_ring->desc, rx_ring->dma);
6695
6696 rx_ring->desc = NULL;
6697}
6698
6699/**
6700 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
6701 * @adapter: board private structure
6702 *
6703 * Free all receive software resources
6704 **/
6705static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
6706{
6707 int i;
6708
6709#ifdef IXGBE_FCOE
6710 ixgbe_free_fcoe_ddp_resources(adapter);
6711
6712#endif
6713 for (i = 0; i < adapter->num_rx_queues; i++)
6714 if (adapter->rx_ring[i]->desc)
6715 ixgbe_free_rx_resources(adapter->rx_ring[i]);
6716}
6717
6718/**
6719 * ixgbe_change_mtu - Change the Maximum Transfer Unit
6720 * @netdev: network interface device structure
6721 * @new_mtu: new value for maximum frame size
6722 *
6723 * Returns 0 on success, negative on failure
6724 **/
6725static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
6726{
6727 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6728
6729 if (adapter->xdp_prog) {
6730 int new_frame_size = new_mtu + ETH_HLEN + ETH_FCS_LEN +
6731 VLAN_HLEN;
6732 int i;
6733
6734 for (i = 0; i < adapter->num_rx_queues; i++) {
6735 struct ixgbe_ring *ring = adapter->rx_ring[i];
6736
6737 if (new_frame_size > ixgbe_rx_bufsz(ring)) {
6738 e_warn(probe, "Requested MTU size is not supported with XDP\n");
6739 return -EINVAL;
6740 }
6741 }
6742 }
6743
6744 /*
6745 * For 82599EB we cannot allow legacy VFs to enable their receive
6746 * paths when MTU greater than 1500 is configured. So display a
6747 * warning that legacy VFs will be disabled.
6748 */
6749 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
6750 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
6751 (new_mtu > ETH_DATA_LEN))
6752 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
6753
6754 netdev_dbg(netdev, "changing MTU from %d to %d\n",
6755 netdev->mtu, new_mtu);
6756
6757 /* must set new MTU before calling down or up */
6758 netdev->mtu = new_mtu;
6759
6760 if (netif_running(netdev))
6761 ixgbe_reinit_locked(adapter);
6762
6763 return 0;
6764}
6765
6766/**
6767 * ixgbe_open - Called when a network interface is made active
6768 * @netdev: network interface device structure
6769 *
6770 * Returns 0 on success, negative value on failure
6771 *
6772 * The open entry point is called when a network interface is made
6773 * active by the system (IFF_UP). At this point all resources needed
6774 * for transmit and receive operations are allocated, the interrupt
6775 * handler is registered with the OS, the watchdog timer is started,
6776 * and the stack is notified that the interface is ready.
6777 **/
6778int ixgbe_open(struct net_device *netdev)
6779{
6780 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6781 struct ixgbe_hw *hw = &adapter->hw;
6782 int err, queues;
6783
6784 /* disallow open during test */
6785 if (test_bit(__IXGBE_TESTING, &adapter->state))
6786 return -EBUSY;
6787
6788 netif_carrier_off(netdev);
6789
6790 /* allocate transmit descriptors */
6791 err = ixgbe_setup_all_tx_resources(adapter);
6792 if (err)
6793 goto err_setup_tx;
6794
6795 /* allocate receive descriptors */
6796 err = ixgbe_setup_all_rx_resources(adapter);
6797 if (err)
6798 goto err_setup_rx;
6799
6800 ixgbe_configure(adapter);
6801
6802 err = ixgbe_request_irq(adapter);
6803 if (err)
6804 goto err_req_irq;
6805
6806 /* Notify the stack of the actual queue counts. */
6807 queues = adapter->num_tx_queues;
6808 err = netif_set_real_num_tx_queues(netdev, queues);
6809 if (err)
6810 goto err_set_queues;
6811
6812 queues = adapter->num_rx_queues;
6813 err = netif_set_real_num_rx_queues(netdev, queues);
6814 if (err)
6815 goto err_set_queues;
6816
6817 ixgbe_ptp_init(adapter);
6818
6819 ixgbe_up_complete(adapter);
6820
6821 udp_tunnel_nic_reset_ntf(netdev);
6822
6823 return 0;
6824
6825err_set_queues:
6826 ixgbe_free_irq(adapter);
6827err_req_irq:
6828 ixgbe_free_all_rx_resources(adapter);
6829 if (hw->phy.ops.set_phy_power && !adapter->wol)
6830 hw->phy.ops.set_phy_power(&adapter->hw, false);
6831err_setup_rx:
6832 ixgbe_free_all_tx_resources(adapter);
6833err_setup_tx:
6834 ixgbe_reset(adapter);
6835
6836 return err;
6837}
6838
6839static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
6840{
6841 ixgbe_ptp_suspend(adapter);
6842
6843 if (adapter->hw.phy.ops.enter_lplu) {
6844 adapter->hw.phy.reset_disable = true;
6845 ixgbe_down(adapter);
6846 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
6847 adapter->hw.phy.reset_disable = false;
6848 } else {
6849 ixgbe_down(adapter);
6850 }
6851
6852 ixgbe_free_irq(adapter);
6853
6854 ixgbe_free_all_tx_resources(adapter);
6855 ixgbe_free_all_rx_resources(adapter);
6856}
6857
6858/**
6859 * ixgbe_close - Disables a network interface
6860 * @netdev: network interface device structure
6861 *
6862 * Returns 0, this is not allowed to fail
6863 *
6864 * The close entry point is called when an interface is de-activated
6865 * by the OS. The hardware is still under the drivers control, but
6866 * needs to be disabled. A global MAC reset is issued to stop the
6867 * hardware, and all transmit and receive resources are freed.
6868 **/
6869int ixgbe_close(struct net_device *netdev)
6870{
6871 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6872
6873 ixgbe_ptp_stop(adapter);
6874
6875 if (netif_device_present(netdev))
6876 ixgbe_close_suspend(adapter);
6877
6878 ixgbe_fdir_filter_exit(adapter);
6879
6880 ixgbe_release_hw_control(adapter);
6881
6882 return 0;
6883}
6884
6885static int __maybe_unused ixgbe_resume(struct device *dev_d)
6886{
6887 struct pci_dev *pdev = to_pci_dev(dev_d);
6888 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6889 struct net_device *netdev = adapter->netdev;
6890 u32 err;
6891
6892 adapter->hw.hw_addr = adapter->io_addr;
6893
6894 smp_mb__before_atomic();
6895 clear_bit(__IXGBE_DISABLED, &adapter->state);
6896 pci_set_master(pdev);
6897
6898 device_wakeup_disable(dev_d);
6899
6900 ixgbe_reset(adapter);
6901
6902 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6903
6904 rtnl_lock();
6905 err = ixgbe_init_interrupt_scheme(adapter);
6906 if (!err && netif_running(netdev))
6907 err = ixgbe_open(netdev);
6908
6909
6910 if (!err)
6911 netif_device_attach(netdev);
6912 rtnl_unlock();
6913
6914 return err;
6915}
6916
6917static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
6918{
6919 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6920 struct net_device *netdev = adapter->netdev;
6921 struct ixgbe_hw *hw = &adapter->hw;
6922 u32 ctrl;
6923 u32 wufc = adapter->wol;
6924
6925 rtnl_lock();
6926 netif_device_detach(netdev);
6927
6928 if (netif_running(netdev))
6929 ixgbe_close_suspend(adapter);
6930
6931 ixgbe_clear_interrupt_scheme(adapter);
6932 rtnl_unlock();
6933
6934 if (hw->mac.ops.stop_link_on_d3)
6935 hw->mac.ops.stop_link_on_d3(hw);
6936
6937 if (wufc) {
6938 u32 fctrl;
6939
6940 ixgbe_set_rx_mode(netdev);
6941
6942 /* enable the optics for 82599 SFP+ fiber as we can WoL */
6943 if (hw->mac.ops.enable_tx_laser)
6944 hw->mac.ops.enable_tx_laser(hw);
6945
6946 /* enable the reception of multicast packets */
6947 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6948 fctrl |= IXGBE_FCTRL_MPE;
6949 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
6950
6951 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
6952 ctrl |= IXGBE_CTRL_GIO_DIS;
6953 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
6954
6955 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
6956 } else {
6957 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
6958 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
6959 }
6960
6961 switch (hw->mac.type) {
6962 case ixgbe_mac_82598EB:
6963 pci_wake_from_d3(pdev, false);
6964 break;
6965 case ixgbe_mac_82599EB:
6966 case ixgbe_mac_X540:
6967 case ixgbe_mac_X550:
6968 case ixgbe_mac_X550EM_x:
6969 case ixgbe_mac_x550em_a:
6970 pci_wake_from_d3(pdev, !!wufc);
6971 break;
6972 default:
6973 break;
6974 }
6975
6976 *enable_wake = !!wufc;
6977 if (hw->phy.ops.set_phy_power && !*enable_wake)
6978 hw->phy.ops.set_phy_power(hw, false);
6979
6980 ixgbe_release_hw_control(adapter);
6981
6982 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
6983 pci_disable_device(pdev);
6984
6985 return 0;
6986}
6987
6988static int __maybe_unused ixgbe_suspend(struct device *dev_d)
6989{
6990 struct pci_dev *pdev = to_pci_dev(dev_d);
6991 int retval;
6992 bool wake;
6993
6994 retval = __ixgbe_shutdown(pdev, &wake);
6995
6996 device_set_wakeup_enable(dev_d, wake);
6997
6998 return retval;
6999}
7000
7001static void ixgbe_shutdown(struct pci_dev *pdev)
7002{
7003 bool wake;
7004
7005 __ixgbe_shutdown(pdev, &wake);
7006
7007 if (system_state == SYSTEM_POWER_OFF) {
7008 pci_wake_from_d3(pdev, wake);
7009 pci_set_power_state(pdev, PCI_D3hot);
7010 }
7011}
7012
7013/**
7014 * ixgbe_update_stats - Update the board statistics counters.
7015 * @adapter: board private structure
7016 **/
7017void ixgbe_update_stats(struct ixgbe_adapter *adapter)
7018{
7019 struct net_device *netdev = adapter->netdev;
7020 struct ixgbe_hw *hw = &adapter->hw;
7021 struct ixgbe_hw_stats *hwstats = &adapter->stats;
7022 u64 total_mpc = 0;
7023 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
7024 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
7025 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
7026 u64 alloc_rx_page = 0;
7027 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
7028
7029 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7030 test_bit(__IXGBE_RESETTING, &adapter->state))
7031 return;
7032
7033 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
7034 u64 rsc_count = 0;
7035 u64 rsc_flush = 0;
7036 for (i = 0; i < adapter->num_rx_queues; i++) {
7037 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
7038 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
7039 }
7040 adapter->rsc_total_count = rsc_count;
7041 adapter->rsc_total_flush = rsc_flush;
7042 }
7043
7044 for (i = 0; i < adapter->num_rx_queues; i++) {
7045 struct ixgbe_ring *rx_ring = READ_ONCE(adapter->rx_ring[i]);
7046
7047 if (!rx_ring)
7048 continue;
7049 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
7050 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page;
7051 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
7052 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
7053 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
7054 bytes += rx_ring->stats.bytes;
7055 packets += rx_ring->stats.packets;
7056 }
7057 adapter->non_eop_descs = non_eop_descs;
7058 adapter->alloc_rx_page = alloc_rx_page;
7059 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
7060 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
7061 adapter->hw_csum_rx_error = hw_csum_rx_error;
7062 netdev->stats.rx_bytes = bytes;
7063 netdev->stats.rx_packets = packets;
7064
7065 bytes = 0;
7066 packets = 0;
7067 /* gather some stats to the adapter struct that are per queue */
7068 for (i = 0; i < adapter->num_tx_queues; i++) {
7069 struct ixgbe_ring *tx_ring = READ_ONCE(adapter->tx_ring[i]);
7070
7071 if (!tx_ring)
7072 continue;
7073 restart_queue += tx_ring->tx_stats.restart_queue;
7074 tx_busy += tx_ring->tx_stats.tx_busy;
7075 bytes += tx_ring->stats.bytes;
7076 packets += tx_ring->stats.packets;
7077 }
7078 for (i = 0; i < adapter->num_xdp_queues; i++) {
7079 struct ixgbe_ring *xdp_ring = READ_ONCE(adapter->xdp_ring[i]);
7080
7081 if (!xdp_ring)
7082 continue;
7083 restart_queue += xdp_ring->tx_stats.restart_queue;
7084 tx_busy += xdp_ring->tx_stats.tx_busy;
7085 bytes += xdp_ring->stats.bytes;
7086 packets += xdp_ring->stats.packets;
7087 }
7088 adapter->restart_queue = restart_queue;
7089 adapter->tx_busy = tx_busy;
7090 netdev->stats.tx_bytes = bytes;
7091 netdev->stats.tx_packets = packets;
7092
7093 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
7094
7095 /* 8 register reads */
7096 for (i = 0; i < 8; i++) {
7097 /* for packet buffers not used, the register should read 0 */
7098 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
7099 missed_rx += mpc;
7100 hwstats->mpc[i] += mpc;
7101 total_mpc += hwstats->mpc[i];
7102 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
7103 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
7104 switch (hw->mac.type) {
7105 case ixgbe_mac_82598EB:
7106 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
7107 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
7108 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7109 hwstats->pxonrxc[i] +=
7110 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
7111 break;
7112 case ixgbe_mac_82599EB:
7113 case ixgbe_mac_X540:
7114 case ixgbe_mac_X550:
7115 case ixgbe_mac_X550EM_x:
7116 case ixgbe_mac_x550em_a:
7117 hwstats->pxonrxc[i] +=
7118 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
7119 break;
7120 default:
7121 break;
7122 }
7123 }
7124
7125 /*16 register reads */
7126 for (i = 0; i < 16; i++) {
7127 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
7128 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
7129 if ((hw->mac.type == ixgbe_mac_82599EB) ||
7130 (hw->mac.type == ixgbe_mac_X540) ||
7131 (hw->mac.type == ixgbe_mac_X550) ||
7132 (hw->mac.type == ixgbe_mac_X550EM_x) ||
7133 (hw->mac.type == ixgbe_mac_x550em_a)) {
7134 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
7135 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
7136 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
7137 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
7138 }
7139 }
7140
7141 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
7142 /* work around hardware counting issue */
7143 hwstats->gprc -= missed_rx;
7144
7145 ixgbe_update_xoff_received(adapter);
7146
7147 /* 82598 hardware only has a 32 bit counter in the high register */
7148 switch (hw->mac.type) {
7149 case ixgbe_mac_82598EB:
7150 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
7151 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
7152 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
7153 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
7154 break;
7155 case ixgbe_mac_X540:
7156 case ixgbe_mac_X550:
7157 case ixgbe_mac_X550EM_x:
7158 case ixgbe_mac_x550em_a:
7159 /* OS2BMC stats are X540 and later */
7160 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
7161 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
7162 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
7163 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
7164 fallthrough;
7165 case ixgbe_mac_82599EB:
7166 for (i = 0; i < 16; i++)
7167 adapter->hw_rx_no_dma_resources +=
7168 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7169 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
7170 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7171 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
7172 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7173 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
7174 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7175 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7176 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
7177 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
7178#ifdef IXGBE_FCOE
7179 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
7180 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
7181 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
7182 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
7183 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
7184 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7185 /* Add up per cpu counters for total ddp aloc fail */
7186 if (adapter->fcoe.ddp_pool) {
7187 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
7188 struct ixgbe_fcoe_ddp_pool *ddp_pool;
7189 unsigned int cpu;
7190 u64 noddp = 0, noddp_ext_buff = 0;
7191 for_each_possible_cpu(cpu) {
7192 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
7193 noddp += ddp_pool->noddp;
7194 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7195 }
7196 hwstats->fcoe_noddp = noddp;
7197 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7198 }
7199#endif /* IXGBE_FCOE */
7200 break;
7201 default:
7202 break;
7203 }
7204 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7205 hwstats->bprc += bprc;
7206 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
7207 if (hw->mac.type == ixgbe_mac_82598EB)
7208 hwstats->mprc -= bprc;
7209 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
7210 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
7211 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
7212 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
7213 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
7214 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
7215 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
7216 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
7217 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7218 hwstats->lxontxc += lxon;
7219 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7220 hwstats->lxofftxc += lxoff;
7221 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
7222 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
7223 /*
7224 * 82598 errata - tx of flow control packets is included in tx counters
7225 */
7226 xon_off_tot = lxon + lxoff;
7227 hwstats->gptc -= xon_off_tot;
7228 hwstats->mptc -= xon_off_tot;
7229 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
7230 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
7231 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
7232 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
7233 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
7234 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
7235 hwstats->ptc64 -= xon_off_tot;
7236 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
7237 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
7238 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
7239 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
7240 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
7241 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
7242
7243 /* Fill out the OS statistics structure */
7244 netdev->stats.multicast = hwstats->mprc;
7245
7246 /* Rx Errors */
7247 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
7248 netdev->stats.rx_dropped = 0;
7249 netdev->stats.rx_length_errors = hwstats->rlec;
7250 netdev->stats.rx_crc_errors = hwstats->crcerrs;
7251 netdev->stats.rx_missed_errors = total_mpc;
7252}
7253
7254/**
7255 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
7256 * @adapter: pointer to the device adapter structure
7257 **/
7258static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
7259{
7260 struct ixgbe_hw *hw = &adapter->hw;
7261 int i;
7262
7263 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
7264 return;
7265
7266 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
7267
7268 /* if interface is down do nothing */
7269 if (test_bit(__IXGBE_DOWN, &adapter->state))
7270 return;
7271
7272 /* do nothing if we are not using signature filters */
7273 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
7274 return;
7275
7276 adapter->fdir_overflow++;
7277
7278 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
7279 for (i = 0; i < adapter->num_tx_queues; i++)
7280 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
7281 &(adapter->tx_ring[i]->state));
7282 for (i = 0; i < adapter->num_xdp_queues; i++)
7283 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
7284 &adapter->xdp_ring[i]->state);
7285 /* re-enable flow director interrupts */
7286 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
7287 } else {
7288 e_err(probe, "failed to finish FDIR re-initialization, "
7289 "ignored adding FDIR ATR filters\n");
7290 }
7291}
7292
7293/**
7294 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
7295 * @adapter: pointer to the device adapter structure
7296 *
7297 * This function serves two purposes. First it strobes the interrupt lines
7298 * in order to make certain interrupts are occurring. Secondly it sets the
7299 * bits needed to check for TX hangs. As a result we should immediately
7300 * determine if a hang has occurred.
7301 */
7302static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
7303{
7304 struct ixgbe_hw *hw = &adapter->hw;
7305 u64 eics = 0;
7306 int i;
7307
7308 /* If we're down, removing or resetting, just bail */
7309 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7310 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7311 test_bit(__IXGBE_RESETTING, &adapter->state))
7312 return;
7313
7314 /* Force detection of hung controller */
7315 if (netif_carrier_ok(adapter->netdev)) {
7316 for (i = 0; i < adapter->num_tx_queues; i++)
7317 set_check_for_tx_hang(adapter->tx_ring[i]);
7318 for (i = 0; i < adapter->num_xdp_queues; i++)
7319 set_check_for_tx_hang(adapter->xdp_ring[i]);
7320 }
7321
7322 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7323 /*
7324 * for legacy and MSI interrupts don't set any bits
7325 * that are enabled for EIAM, because this operation
7326 * would set *both* EIMS and EICS for any bit in EIAM
7327 */
7328 IXGBE_WRITE_REG(hw, IXGBE_EICS,
7329 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
7330 } else {
7331 /* get one bit for every active tx/rx interrupt vector */
7332 for (i = 0; i < adapter->num_q_vectors; i++) {
7333 struct ixgbe_q_vector *qv = adapter->q_vector[i];
7334 if (qv->rx.ring || qv->tx.ring)
7335 eics |= BIT_ULL(i);
7336 }
7337 }
7338
7339 /* Cause software interrupt to ensure rings are cleaned */
7340 ixgbe_irq_rearm_queues(adapter, eics);
7341}
7342
7343/**
7344 * ixgbe_watchdog_update_link - update the link status
7345 * @adapter: pointer to the device adapter structure
7346 **/
7347static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
7348{
7349 struct ixgbe_hw *hw = &adapter->hw;
7350 u32 link_speed = adapter->link_speed;
7351 bool link_up = adapter->link_up;
7352 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
7353
7354 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
7355 return;
7356
7357 if (hw->mac.ops.check_link) {
7358 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
7359 } else {
7360 /* always assume link is up, if no check link function */
7361 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
7362 link_up = true;
7363 }
7364
7365 if (adapter->ixgbe_ieee_pfc)
7366 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
7367
7368 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
7369 hw->mac.ops.fc_enable(hw);
7370 ixgbe_set_rx_drop_en(adapter);
7371 }
7372
7373 if (link_up ||
7374 time_after(jiffies, (adapter->link_check_timeout +
7375 IXGBE_TRY_LINK_TIMEOUT))) {
7376 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
7377 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
7378 IXGBE_WRITE_FLUSH(hw);
7379 }
7380
7381 adapter->link_up = link_up;
7382 adapter->link_speed = link_speed;
7383}
7384
7385static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
7386{
7387#ifdef CONFIG_IXGBE_DCB
7388 struct net_device *netdev = adapter->netdev;
7389 struct dcb_app app = {
7390 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
7391 .protocol = 0,
7392 };
7393 u8 up = 0;
7394
7395 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
7396 up = dcb_ieee_getapp_mask(netdev, &app);
7397
7398 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
7399#endif
7400}
7401
7402/**
7403 * ixgbe_watchdog_link_is_up - update netif_carrier status and
7404 * print link up message
7405 * @adapter: pointer to the device adapter structure
7406 **/
7407static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
7408{
7409 struct net_device *netdev = adapter->netdev;
7410 struct ixgbe_hw *hw = &adapter->hw;
7411 u32 link_speed = adapter->link_speed;
7412 const char *speed_str;
7413 bool flow_rx, flow_tx;
7414
7415 /* only continue if link was previously down */
7416 if (netif_carrier_ok(netdev))
7417 return;
7418
7419 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7420
7421 switch (hw->mac.type) {
7422 case ixgbe_mac_82598EB: {
7423 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
7424 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
7425 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
7426 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
7427 }
7428 break;
7429 case ixgbe_mac_X540:
7430 case ixgbe_mac_X550:
7431 case ixgbe_mac_X550EM_x:
7432 case ixgbe_mac_x550em_a:
7433 case ixgbe_mac_82599EB: {
7434 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
7435 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
7436 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
7437 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
7438 }
7439 break;
7440 default:
7441 flow_tx = false;
7442 flow_rx = false;
7443 break;
7444 }
7445
7446 adapter->last_rx_ptp_check = jiffies;
7447
7448 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
7449 ixgbe_ptp_start_cyclecounter(adapter);
7450
7451 switch (link_speed) {
7452 case IXGBE_LINK_SPEED_10GB_FULL:
7453 speed_str = "10 Gbps";
7454 break;
7455 case IXGBE_LINK_SPEED_5GB_FULL:
7456 speed_str = "5 Gbps";
7457 break;
7458 case IXGBE_LINK_SPEED_2_5GB_FULL:
7459 speed_str = "2.5 Gbps";
7460 break;
7461 case IXGBE_LINK_SPEED_1GB_FULL:
7462 speed_str = "1 Gbps";
7463 break;
7464 case IXGBE_LINK_SPEED_100_FULL:
7465 speed_str = "100 Mbps";
7466 break;
7467 case IXGBE_LINK_SPEED_10_FULL:
7468 speed_str = "10 Mbps";
7469 break;
7470 default:
7471 speed_str = "unknown speed";
7472 break;
7473 }
7474 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
7475 ((flow_rx && flow_tx) ? "RX/TX" :
7476 (flow_rx ? "RX" :
7477 (flow_tx ? "TX" : "None"))));
7478
7479 netif_carrier_on(netdev);
7480 ixgbe_check_vf_rate_limit(adapter);
7481
7482 /* enable transmits */
7483 netif_tx_wake_all_queues(adapter->netdev);
7484
7485 /* update the default user priority for VFs */
7486 ixgbe_update_default_up(adapter);
7487
7488 /* ping all the active vfs to let them know link has changed */
7489 ixgbe_ping_all_vfs(adapter);
7490}
7491
7492/**
7493 * ixgbe_watchdog_link_is_down - update netif_carrier status and
7494 * print link down message
7495 * @adapter: pointer to the adapter structure
7496 **/
7497static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
7498{
7499 struct net_device *netdev = adapter->netdev;
7500 struct ixgbe_hw *hw = &adapter->hw;
7501
7502 adapter->link_up = false;
7503 adapter->link_speed = 0;
7504
7505 /* only continue if link was up previously */
7506 if (!netif_carrier_ok(netdev))
7507 return;
7508
7509 /* poll for SFP+ cable when link is down */
7510 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
7511 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
7512
7513 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
7514 ixgbe_ptp_start_cyclecounter(adapter);
7515
7516 e_info(drv, "NIC Link is Down\n");
7517 netif_carrier_off(netdev);
7518
7519 /* ping all the active vfs to let them know link has changed */
7520 ixgbe_ping_all_vfs(adapter);
7521}
7522
7523static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
7524{
7525 int i;
7526
7527 for (i = 0; i < adapter->num_tx_queues; i++) {
7528 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
7529
7530 if (tx_ring->next_to_use != tx_ring->next_to_clean)
7531 return true;
7532 }
7533
7534 for (i = 0; i < adapter->num_xdp_queues; i++) {
7535 struct ixgbe_ring *ring = adapter->xdp_ring[i];
7536
7537 if (ring->next_to_use != ring->next_to_clean)
7538 return true;
7539 }
7540
7541 return false;
7542}
7543
7544static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
7545{
7546 struct ixgbe_hw *hw = &adapter->hw;
7547 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
7548 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
7549
7550 int i, j;
7551
7552 if (!adapter->num_vfs)
7553 return false;
7554
7555 /* resetting the PF is only needed for MAC before X550 */
7556 if (hw->mac.type >= ixgbe_mac_X550)
7557 return false;
7558
7559 for (i = 0; i < adapter->num_vfs; i++) {
7560 for (j = 0; j < q_per_pool; j++) {
7561 u32 h, t;
7562
7563 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
7564 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
7565
7566 if (h != t)
7567 return true;
7568 }
7569 }
7570
7571 return false;
7572}
7573
7574/**
7575 * ixgbe_watchdog_flush_tx - flush queues on link down
7576 * @adapter: pointer to the device adapter structure
7577 **/
7578static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
7579{
7580 if (!netif_carrier_ok(adapter->netdev)) {
7581 if (ixgbe_ring_tx_pending(adapter) ||
7582 ixgbe_vf_tx_pending(adapter)) {
7583 /* We've lost link, so the controller stops DMA,
7584 * but we've got queued Tx work that's never going
7585 * to get done, so reset controller to flush Tx.
7586 * (Do the reset outside of interrupt context).
7587 */
7588 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
7589 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
7590 }
7591 }
7592}
7593
7594#ifdef CONFIG_PCI_IOV
7595static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
7596{
7597 struct ixgbe_hw *hw = &adapter->hw;
7598 struct pci_dev *pdev = adapter->pdev;
7599 unsigned int vf;
7600 u32 gpc;
7601
7602 if (!(netif_carrier_ok(adapter->netdev)))
7603 return;
7604
7605 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
7606 if (gpc) /* If incrementing then no need for the check below */
7607 return;
7608 /* Check to see if a bad DMA write target from an errant or
7609 * malicious VF has caused a PCIe error. If so then we can
7610 * issue a VFLR to the offending VF(s) and then resume without
7611 * requesting a full slot reset.
7612 */
7613
7614 if (!pdev)
7615 return;
7616
7617 /* check status reg for all VFs owned by this PF */
7618 for (vf = 0; vf < adapter->num_vfs; ++vf) {
7619 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev;
7620 u16 status_reg;
7621
7622 if (!vfdev)
7623 continue;
7624 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
7625 if (status_reg != IXGBE_FAILED_READ_CFG_WORD &&
7626 status_reg & PCI_STATUS_REC_MASTER_ABORT)
7627 pcie_flr(vfdev);
7628 }
7629}
7630
7631static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
7632{
7633 u32 ssvpc;
7634
7635 /* Do not perform spoof check for 82598 or if not in IOV mode */
7636 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7637 adapter->num_vfs == 0)
7638 return;
7639
7640 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
7641
7642 /*
7643 * ssvpc register is cleared on read, if zero then no
7644 * spoofed packets in the last interval.
7645 */
7646 if (!ssvpc)
7647 return;
7648
7649 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
7650}
7651#else
7652static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
7653{
7654}
7655
7656static void
7657ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
7658{
7659}
7660#endif /* CONFIG_PCI_IOV */
7661
7662
7663/**
7664 * ixgbe_watchdog_subtask - check and bring link up
7665 * @adapter: pointer to the device adapter structure
7666 **/
7667static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
7668{
7669 /* if interface is down, removing or resetting, do nothing */
7670 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7671 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7672 test_bit(__IXGBE_RESETTING, &adapter->state))
7673 return;
7674
7675 ixgbe_watchdog_update_link(adapter);
7676
7677 if (adapter->link_up)
7678 ixgbe_watchdog_link_is_up(adapter);
7679 else
7680 ixgbe_watchdog_link_is_down(adapter);
7681
7682 ixgbe_check_for_bad_vf(adapter);
7683 ixgbe_spoof_check(adapter);
7684 ixgbe_update_stats(adapter);
7685
7686 ixgbe_watchdog_flush_tx(adapter);
7687}
7688
7689/**
7690 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
7691 * @adapter: the ixgbe adapter structure
7692 **/
7693static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
7694{
7695 struct ixgbe_hw *hw = &adapter->hw;
7696 s32 err;
7697
7698 /* not searching for SFP so there is nothing to do here */
7699 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
7700 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7701 return;
7702
7703 if (adapter->sfp_poll_time &&
7704 time_after(adapter->sfp_poll_time, jiffies))
7705 return; /* If not yet time to poll for SFP */
7706
7707 /* someone else is in init, wait until next service event */
7708 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7709 return;
7710
7711 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
7712
7713 err = hw->phy.ops.identify_sfp(hw);
7714 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7715 goto sfp_out;
7716
7717 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
7718 /* If no cable is present, then we need to reset
7719 * the next time we find a good cable. */
7720 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
7721 }
7722
7723 /* exit on error */
7724 if (err)
7725 goto sfp_out;
7726
7727 /* exit if reset not needed */
7728 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7729 goto sfp_out;
7730
7731 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
7732
7733 /*
7734 * A module may be identified correctly, but the EEPROM may not have
7735 * support for that module. setup_sfp() will fail in that case, so
7736 * we should not allow that module to load.
7737 */
7738 if (hw->mac.type == ixgbe_mac_82598EB)
7739 err = hw->phy.ops.reset(hw);
7740 else
7741 err = hw->mac.ops.setup_sfp(hw);
7742
7743 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7744 goto sfp_out;
7745
7746 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
7747 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
7748
7749sfp_out:
7750 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7751
7752 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
7753 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
7754 e_dev_err("failed to initialize because an unsupported "
7755 "SFP+ module type was detected.\n");
7756 e_dev_err("Reload the driver after installing a "
7757 "supported module.\n");
7758 unregister_netdev(adapter->netdev);
7759 }
7760}
7761
7762/**
7763 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
7764 * @adapter: the ixgbe adapter structure
7765 **/
7766static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
7767{
7768 struct ixgbe_hw *hw = &adapter->hw;
7769 u32 cap_speed;
7770 u32 speed;
7771 bool autoneg = false;
7772
7773 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
7774 return;
7775
7776 /* someone else is in init, wait until next service event */
7777 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7778 return;
7779
7780 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
7781
7782 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg);
7783
7784 /* advertise highest capable link speed */
7785 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL))
7786 speed = IXGBE_LINK_SPEED_10GB_FULL;
7787 else
7788 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL |
7789 IXGBE_LINK_SPEED_1GB_FULL);
7790
7791 if (hw->mac.ops.setup_link)
7792 hw->mac.ops.setup_link(hw, speed, true);
7793
7794 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
7795 adapter->link_check_timeout = jiffies;
7796 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7797}
7798
7799/**
7800 * ixgbe_service_timer - Timer Call-back
7801 * @t: pointer to timer_list structure
7802 **/
7803static void ixgbe_service_timer(struct timer_list *t)
7804{
7805 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer);
7806 unsigned long next_event_offset;
7807
7808 /* poll faster when waiting for link */
7809 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
7810 next_event_offset = HZ / 10;
7811 else
7812 next_event_offset = HZ * 2;
7813
7814 /* Reset the timer */
7815 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
7816
7817 ixgbe_service_event_schedule(adapter);
7818}
7819
7820static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
7821{
7822 struct ixgbe_hw *hw = &adapter->hw;
7823 u32 status;
7824
7825 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
7826 return;
7827
7828 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
7829
7830 if (!hw->phy.ops.handle_lasi)
7831 return;
7832
7833 status = hw->phy.ops.handle_lasi(&adapter->hw);
7834 if (status != IXGBE_ERR_OVERTEMP)
7835 return;
7836
7837 e_crit(drv, "%s\n", ixgbe_overheat_msg);
7838}
7839
7840static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
7841{
7842 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state))
7843 return;
7844
7845 rtnl_lock();
7846 /* If we're already down, removing or resetting, just bail */
7847 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7848 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7849 test_bit(__IXGBE_RESETTING, &adapter->state)) {
7850 rtnl_unlock();
7851 return;
7852 }
7853
7854 ixgbe_dump(adapter);
7855 netdev_err(adapter->netdev, "Reset adapter\n");
7856 adapter->tx_timeout_count++;
7857
7858 ixgbe_reinit_locked(adapter);
7859 rtnl_unlock();
7860}
7861
7862/**
7863 * ixgbe_check_fw_error - Check firmware for errors
7864 * @adapter: the adapter private structure
7865 *
7866 * Check firmware errors in register FWSM
7867 */
7868static bool ixgbe_check_fw_error(struct ixgbe_adapter *adapter)
7869{
7870 struct ixgbe_hw *hw = &adapter->hw;
7871 u32 fwsm;
7872
7873 /* read fwsm.ext_err_ind register and log errors */
7874 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
7875
7876 if (fwsm & IXGBE_FWSM_EXT_ERR_IND_MASK ||
7877 !(fwsm & IXGBE_FWSM_FW_VAL_BIT))
7878 e_dev_warn("Warning firmware error detected FWSM: 0x%08X\n",
7879 fwsm);
7880
7881 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
7882 e_dev_err("Firmware recovery mode detected. Limiting functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware recovery mode.\n");
7883 return true;
7884 }
7885
7886 return false;
7887}
7888
7889/**
7890 * ixgbe_service_task - manages and runs subtasks
7891 * @work: pointer to work_struct containing our data
7892 **/
7893static void ixgbe_service_task(struct work_struct *work)
7894{
7895 struct ixgbe_adapter *adapter = container_of(work,
7896 struct ixgbe_adapter,
7897 service_task);
7898 if (ixgbe_removed(adapter->hw.hw_addr)) {
7899 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
7900 rtnl_lock();
7901 ixgbe_down(adapter);
7902 rtnl_unlock();
7903 }
7904 ixgbe_service_event_complete(adapter);
7905 return;
7906 }
7907 if (ixgbe_check_fw_error(adapter)) {
7908 if (!test_bit(__IXGBE_DOWN, &adapter->state))
7909 unregister_netdev(adapter->netdev);
7910 ixgbe_service_event_complete(adapter);
7911 return;
7912 }
7913 ixgbe_reset_subtask(adapter);
7914 ixgbe_phy_interrupt_subtask(adapter);
7915 ixgbe_sfp_detection_subtask(adapter);
7916 ixgbe_sfp_link_config_subtask(adapter);
7917 ixgbe_check_overtemp_subtask(adapter);
7918 ixgbe_watchdog_subtask(adapter);
7919 ixgbe_fdir_reinit_subtask(adapter);
7920 ixgbe_check_hang_subtask(adapter);
7921
7922 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
7923 ixgbe_ptp_overflow_check(adapter);
7924 if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER)
7925 ixgbe_ptp_rx_hang(adapter);
7926 ixgbe_ptp_tx_hang(adapter);
7927 }
7928
7929 ixgbe_service_event_complete(adapter);
7930}
7931
7932static int ixgbe_tso(struct ixgbe_ring *tx_ring,
7933 struct ixgbe_tx_buffer *first,
7934 u8 *hdr_len,
7935 struct ixgbe_ipsec_tx_data *itd)
7936{
7937 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
7938 struct sk_buff *skb = first->skb;
7939 union {
7940 struct iphdr *v4;
7941 struct ipv6hdr *v6;
7942 unsigned char *hdr;
7943 } ip;
7944 union {
7945 struct tcphdr *tcp;
7946 struct udphdr *udp;
7947 unsigned char *hdr;
7948 } l4;
7949 u32 paylen, l4_offset;
7950 u32 fceof_saidx = 0;
7951 int err;
7952
7953 if (skb->ip_summed != CHECKSUM_PARTIAL)
7954 return 0;
7955
7956 if (!skb_is_gso(skb))
7957 return 0;
7958
7959 err = skb_cow_head(skb, 0);
7960 if (err < 0)
7961 return err;
7962
7963 if (eth_p_mpls(first->protocol))
7964 ip.hdr = skb_inner_network_header(skb);
7965 else
7966 ip.hdr = skb_network_header(skb);
7967 l4.hdr = skb_checksum_start(skb);
7968
7969 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
7970 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ?
7971 IXGBE_ADVTXD_TUCMD_L4T_UDP : IXGBE_ADVTXD_TUCMD_L4T_TCP;
7972
7973 /* initialize outer IP header fields */
7974 if (ip.v4->version == 4) {
7975 unsigned char *csum_start = skb_checksum_start(skb);
7976 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
7977 int len = csum_start - trans_start;
7978
7979 /* IP header will have to cancel out any data that
7980 * is not a part of the outer IP header, so set to
7981 * a reverse csum if needed, else init check to 0.
7982 */
7983 ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ?
7984 csum_fold(csum_partial(trans_start,
7985 len, 0)) : 0;
7986 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
7987
7988 ip.v4->tot_len = 0;
7989 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7990 IXGBE_TX_FLAGS_CSUM |
7991 IXGBE_TX_FLAGS_IPV4;
7992 } else {
7993 ip.v6->payload_len = 0;
7994 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7995 IXGBE_TX_FLAGS_CSUM;
7996 }
7997
7998 /* determine offset of inner transport header */
7999 l4_offset = l4.hdr - skb->data;
8000
8001 /* remove payload length from inner checksum */
8002 paylen = skb->len - l4_offset;
8003
8004 if (type_tucmd & IXGBE_ADVTXD_TUCMD_L4T_TCP) {
8005 /* compute length of segmentation header */
8006 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
8007 csum_replace_by_diff(&l4.tcp->check,
8008 (__force __wsum)htonl(paylen));
8009 } else {
8010 /* compute length of segmentation header */
8011 *hdr_len = sizeof(*l4.udp) + l4_offset;
8012 csum_replace_by_diff(&l4.udp->check,
8013 (__force __wsum)htonl(paylen));
8014 }
8015
8016 /* update gso size and bytecount with header size */
8017 first->gso_segs = skb_shinfo(skb)->gso_segs;
8018 first->bytecount += (first->gso_segs - 1) * *hdr_len;
8019
8020 /* mss_l4len_id: use 0 as index for TSO */
8021 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT;
8022 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
8023
8024 fceof_saidx |= itd->sa_idx;
8025 type_tucmd |= itd->flags | itd->trailer_len;
8026
8027 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
8028 vlan_macip_lens = l4.hdr - ip.hdr;
8029 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT;
8030 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
8031
8032 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd,
8033 mss_l4len_idx);
8034
8035 return 1;
8036}
8037
8038static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb)
8039{
8040 unsigned int offset = 0;
8041
8042 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
8043
8044 return offset == skb_checksum_start_offset(skb);
8045}
8046
8047static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
8048 struct ixgbe_tx_buffer *first,
8049 struct ixgbe_ipsec_tx_data *itd)
8050{
8051 struct sk_buff *skb = first->skb;
8052 u32 vlan_macip_lens = 0;
8053 u32 fceof_saidx = 0;
8054 u32 type_tucmd = 0;
8055
8056 if (skb->ip_summed != CHECKSUM_PARTIAL) {
8057csum_failed:
8058 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN |
8059 IXGBE_TX_FLAGS_CC)))
8060 return;
8061 goto no_csum;
8062 }
8063
8064 switch (skb->csum_offset) {
8065 case offsetof(struct tcphdr, check):
8066 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
8067 fallthrough;
8068 case offsetof(struct udphdr, check):
8069 break;
8070 case offsetof(struct sctphdr, checksum):
8071 /* validate that this is actually an SCTP request */
8072 if (((first->protocol == htons(ETH_P_IP)) &&
8073 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
8074 ((first->protocol == htons(ETH_P_IPV6)) &&
8075 ixgbe_ipv6_csum_is_sctp(skb))) {
8076 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP;
8077 break;
8078 }
8079 fallthrough;
8080 default:
8081 skb_checksum_help(skb);
8082 goto csum_failed;
8083 }
8084
8085 /* update TX checksum flag */
8086 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
8087 vlan_macip_lens = skb_checksum_start_offset(skb) -
8088 skb_network_offset(skb);
8089no_csum:
8090 /* vlan_macip_lens: MACLEN, VLAN tag */
8091 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
8092 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
8093
8094 fceof_saidx |= itd->sa_idx;
8095 type_tucmd |= itd->flags | itd->trailer_len;
8096
8097 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0);
8098}
8099
8100#define IXGBE_SET_FLAG(_input, _flag, _result) \
8101 ((_flag <= _result) ? \
8102 ((u32)(_input & _flag) * (_result / _flag)) : \
8103 ((u32)(_input & _flag) / (_flag / _result)))
8104
8105static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
8106{
8107 /* set type for advanced descriptor with frame checksum insertion */
8108 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
8109 IXGBE_ADVTXD_DCMD_DEXT |
8110 IXGBE_ADVTXD_DCMD_IFCS;
8111
8112 /* set HW vlan bit if vlan is present */
8113 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
8114 IXGBE_ADVTXD_DCMD_VLE);
8115
8116 /* set segmentation enable bits for TSO/FSO */
8117 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
8118 IXGBE_ADVTXD_DCMD_TSE);
8119
8120 /* set timestamp bit if present */
8121 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
8122 IXGBE_ADVTXD_MAC_TSTAMP);
8123
8124 /* insert frame checksum */
8125 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
8126
8127 return cmd_type;
8128}
8129
8130static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
8131 u32 tx_flags, unsigned int paylen)
8132{
8133 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
8134
8135 /* enable L4 checksum for TSO and TX checksum offload */
8136 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8137 IXGBE_TX_FLAGS_CSUM,
8138 IXGBE_ADVTXD_POPTS_TXSM);
8139
8140 /* enable IPv4 checksum for TSO */
8141 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8142 IXGBE_TX_FLAGS_IPV4,
8143 IXGBE_ADVTXD_POPTS_IXSM);
8144
8145 /* enable IPsec */
8146 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8147 IXGBE_TX_FLAGS_IPSEC,
8148 IXGBE_ADVTXD_POPTS_IPSEC);
8149
8150 /*
8151 * Check Context must be set if Tx switch is enabled, which it
8152 * always is for case where virtual functions are running
8153 */
8154 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8155 IXGBE_TX_FLAGS_CC,
8156 IXGBE_ADVTXD_CC);
8157
8158 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
8159}
8160
8161static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
8162{
8163 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
8164
8165 /* Herbert's original patch had:
8166 * smp_mb__after_netif_stop_queue();
8167 * but since that doesn't exist yet, just open code it.
8168 */
8169 smp_mb();
8170
8171 /* We need to check again in a case another CPU has just
8172 * made room available.
8173 */
8174 if (likely(ixgbe_desc_unused(tx_ring) < size))
8175 return -EBUSY;
8176
8177 /* A reprieve! - use start_queue because it doesn't call schedule */
8178 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
8179 ++tx_ring->tx_stats.restart_queue;
8180 return 0;
8181}
8182
8183static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
8184{
8185 if (likely(ixgbe_desc_unused(tx_ring) >= size))
8186 return 0;
8187
8188 return __ixgbe_maybe_stop_tx(tx_ring, size);
8189}
8190
8191static int ixgbe_tx_map(struct ixgbe_ring *tx_ring,
8192 struct ixgbe_tx_buffer *first,
8193 const u8 hdr_len)
8194{
8195 struct sk_buff *skb = first->skb;
8196 struct ixgbe_tx_buffer *tx_buffer;
8197 union ixgbe_adv_tx_desc *tx_desc;
8198 skb_frag_t *frag;
8199 dma_addr_t dma;
8200 unsigned int data_len, size;
8201 u32 tx_flags = first->tx_flags;
8202 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
8203 u16 i = tx_ring->next_to_use;
8204
8205 tx_desc = IXGBE_TX_DESC(tx_ring, i);
8206
8207 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
8208
8209 size = skb_headlen(skb);
8210 data_len = skb->data_len;
8211
8212#ifdef IXGBE_FCOE
8213 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
8214 if (data_len < sizeof(struct fcoe_crc_eof)) {
8215 size -= sizeof(struct fcoe_crc_eof) - data_len;
8216 data_len = 0;
8217 } else {
8218 data_len -= sizeof(struct fcoe_crc_eof);
8219 }
8220 }
8221
8222#endif
8223 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8224
8225 tx_buffer = first;
8226
8227 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
8228 if (dma_mapping_error(tx_ring->dev, dma))
8229 goto dma_error;
8230
8231 /* record length, and DMA address */
8232 dma_unmap_len_set(tx_buffer, len, size);
8233 dma_unmap_addr_set(tx_buffer, dma, dma);
8234
8235 tx_desc->read.buffer_addr = cpu_to_le64(dma);
8236
8237 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
8238 tx_desc->read.cmd_type_len =
8239 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
8240
8241 i++;
8242 tx_desc++;
8243 if (i == tx_ring->count) {
8244 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
8245 i = 0;
8246 }
8247 tx_desc->read.olinfo_status = 0;
8248
8249 dma += IXGBE_MAX_DATA_PER_TXD;
8250 size -= IXGBE_MAX_DATA_PER_TXD;
8251
8252 tx_desc->read.buffer_addr = cpu_to_le64(dma);
8253 }
8254
8255 if (likely(!data_len))
8256 break;
8257
8258 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
8259
8260 i++;
8261 tx_desc++;
8262 if (i == tx_ring->count) {
8263 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
8264 i = 0;
8265 }
8266 tx_desc->read.olinfo_status = 0;
8267
8268#ifdef IXGBE_FCOE
8269 size = min_t(unsigned int, data_len, skb_frag_size(frag));
8270#else
8271 size = skb_frag_size(frag);
8272#endif
8273 data_len -= size;
8274
8275 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
8276 DMA_TO_DEVICE);
8277
8278 tx_buffer = &tx_ring->tx_buffer_info[i];
8279 }
8280
8281 /* write last descriptor with RS and EOP bits */
8282 cmd_type |= size | IXGBE_TXD_CMD;
8283 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8284
8285 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
8286
8287 /* set the timestamp */
8288 first->time_stamp = jiffies;
8289
8290 skb_tx_timestamp(skb);
8291
8292 /*
8293 * Force memory writes to complete before letting h/w know there
8294 * are new descriptors to fetch. (Only applicable for weak-ordered
8295 * memory model archs, such as IA-64).
8296 *
8297 * We also need this memory barrier to make certain all of the
8298 * status bits have been updated before next_to_watch is written.
8299 */
8300 wmb();
8301
8302 /* set next_to_watch value indicating a packet is present */
8303 first->next_to_watch = tx_desc;
8304
8305 i++;
8306 if (i == tx_ring->count)
8307 i = 0;
8308
8309 tx_ring->next_to_use = i;
8310
8311 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
8312
8313 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
8314 writel(i, tx_ring->tail);
8315 }
8316
8317 return 0;
8318dma_error:
8319 dev_err(tx_ring->dev, "TX DMA map failed\n");
8320
8321 /* clear dma mappings for failed tx_buffer_info map */
8322 for (;;) {
8323 tx_buffer = &tx_ring->tx_buffer_info[i];
8324 if (dma_unmap_len(tx_buffer, len))
8325 dma_unmap_page(tx_ring->dev,
8326 dma_unmap_addr(tx_buffer, dma),
8327 dma_unmap_len(tx_buffer, len),
8328 DMA_TO_DEVICE);
8329 dma_unmap_len_set(tx_buffer, len, 0);
8330 if (tx_buffer == first)
8331 break;
8332 if (i == 0)
8333 i += tx_ring->count;
8334 i--;
8335 }
8336
8337 dev_kfree_skb_any(first->skb);
8338 first->skb = NULL;
8339
8340 tx_ring->next_to_use = i;
8341
8342 return -1;
8343}
8344
8345static void ixgbe_atr(struct ixgbe_ring *ring,
8346 struct ixgbe_tx_buffer *first)
8347{
8348 struct ixgbe_q_vector *q_vector = ring->q_vector;
8349 union ixgbe_atr_hash_dword input = { .dword = 0 };
8350 union ixgbe_atr_hash_dword common = { .dword = 0 };
8351 union {
8352 unsigned char *network;
8353 struct iphdr *ipv4;
8354 struct ipv6hdr *ipv6;
8355 } hdr;
8356 struct tcphdr *th;
8357 unsigned int hlen;
8358 struct sk_buff *skb;
8359 __be16 vlan_id;
8360 int l4_proto;
8361
8362 /* if ring doesn't have a interrupt vector, cannot perform ATR */
8363 if (!q_vector)
8364 return;
8365
8366 /* do nothing if sampling is disabled */
8367 if (!ring->atr_sample_rate)
8368 return;
8369
8370 ring->atr_count++;
8371
8372 /* currently only IPv4/IPv6 with TCP is supported */
8373 if ((first->protocol != htons(ETH_P_IP)) &&
8374 (first->protocol != htons(ETH_P_IPV6)))
8375 return;
8376
8377 /* snag network header to get L4 type and address */
8378 skb = first->skb;
8379 hdr.network = skb_network_header(skb);
8380 if (unlikely(hdr.network <= skb->data))
8381 return;
8382 if (skb->encapsulation &&
8383 first->protocol == htons(ETH_P_IP) &&
8384 hdr.ipv4->protocol == IPPROTO_UDP) {
8385 struct ixgbe_adapter *adapter = q_vector->adapter;
8386
8387 if (unlikely(skb_tail_pointer(skb) < hdr.network +
8388 VXLAN_HEADROOM))
8389 return;
8390
8391 /* verify the port is recognized as VXLAN */
8392 if (adapter->vxlan_port &&
8393 udp_hdr(skb)->dest == adapter->vxlan_port)
8394 hdr.network = skb_inner_network_header(skb);
8395
8396 if (adapter->geneve_port &&
8397 udp_hdr(skb)->dest == adapter->geneve_port)
8398 hdr.network = skb_inner_network_header(skb);
8399 }
8400
8401 /* Make sure we have at least [minimum IPv4 header + TCP]
8402 * or [IPv6 header] bytes
8403 */
8404 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40))
8405 return;
8406
8407 /* Currently only IPv4/IPv6 with TCP is supported */
8408 switch (hdr.ipv4->version) {
8409 case IPVERSION:
8410 /* access ihl as u8 to avoid unaligned access on ia64 */
8411 hlen = (hdr.network[0] & 0x0F) << 2;
8412 l4_proto = hdr.ipv4->protocol;
8413 break;
8414 case 6:
8415 hlen = hdr.network - skb->data;
8416 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL);
8417 hlen -= hdr.network - skb->data;
8418 break;
8419 default:
8420 return;
8421 }
8422
8423 if (l4_proto != IPPROTO_TCP)
8424 return;
8425
8426 if (unlikely(skb_tail_pointer(skb) < hdr.network +
8427 hlen + sizeof(struct tcphdr)))
8428 return;
8429
8430 th = (struct tcphdr *)(hdr.network + hlen);
8431
8432 /* skip this packet since the socket is closing */
8433 if (th->fin)
8434 return;
8435
8436 /* sample on all syn packets or once every atr sample count */
8437 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
8438 return;
8439
8440 /* reset sample count */
8441 ring->atr_count = 0;
8442
8443 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
8444
8445 /*
8446 * src and dst are inverted, think how the receiver sees them
8447 *
8448 * The input is broken into two sections, a non-compressed section
8449 * containing vm_pool, vlan_id, and flow_type. The rest of the data
8450 * is XORed together and stored in the compressed dword.
8451 */
8452 input.formatted.vlan_id = vlan_id;
8453
8454 /*
8455 * since src port and flex bytes occupy the same word XOR them together
8456 * and write the value to source port portion of compressed dword
8457 */
8458 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
8459 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
8460 else
8461 common.port.src ^= th->dest ^ first->protocol;
8462 common.port.dst ^= th->source;
8463
8464 switch (hdr.ipv4->version) {
8465 case IPVERSION:
8466 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
8467 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
8468 break;
8469 case 6:
8470 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
8471 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
8472 hdr.ipv6->saddr.s6_addr32[1] ^
8473 hdr.ipv6->saddr.s6_addr32[2] ^
8474 hdr.ipv6->saddr.s6_addr32[3] ^
8475 hdr.ipv6->daddr.s6_addr32[0] ^
8476 hdr.ipv6->daddr.s6_addr32[1] ^
8477 hdr.ipv6->daddr.s6_addr32[2] ^
8478 hdr.ipv6->daddr.s6_addr32[3];
8479 break;
8480 default:
8481 break;
8482 }
8483
8484 if (hdr.network != skb_network_header(skb))
8485 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
8486
8487 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
8488 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
8489 input, common, ring->queue_index);
8490}
8491
8492#ifdef IXGBE_FCOE
8493static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
8494 struct net_device *sb_dev)
8495{
8496 struct ixgbe_adapter *adapter;
8497 struct ixgbe_ring_feature *f;
8498 int txq;
8499
8500 if (sb_dev) {
8501 u8 tc = netdev_get_prio_tc_map(dev, skb->priority);
8502 struct net_device *vdev = sb_dev;
8503
8504 txq = vdev->tc_to_txq[tc].offset;
8505 txq += reciprocal_scale(skb_get_hash(skb),
8506 vdev->tc_to_txq[tc].count);
8507
8508 return txq;
8509 }
8510
8511 /*
8512 * only execute the code below if protocol is FCoE
8513 * or FIP and we have FCoE enabled on the adapter
8514 */
8515 switch (vlan_get_protocol(skb)) {
8516 case htons(ETH_P_FCOE):
8517 case htons(ETH_P_FIP):
8518 adapter = netdev_priv(dev);
8519
8520 if (!sb_dev && (adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
8521 break;
8522 fallthrough;
8523 default:
8524 return netdev_pick_tx(dev, skb, sb_dev);
8525 }
8526
8527 f = &adapter->ring_feature[RING_F_FCOE];
8528
8529 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
8530 smp_processor_id();
8531
8532 while (txq >= f->indices)
8533 txq -= f->indices;
8534
8535 return txq + f->offset;
8536}
8537
8538#endif
8539int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter,
8540 struct xdp_frame *xdpf)
8541{
8542 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()];
8543 struct ixgbe_tx_buffer *tx_buffer;
8544 union ixgbe_adv_tx_desc *tx_desc;
8545 u32 len, cmd_type;
8546 dma_addr_t dma;
8547 u16 i;
8548
8549 len = xdpf->len;
8550
8551 if (unlikely(!ixgbe_desc_unused(ring)))
8552 return IXGBE_XDP_CONSUMED;
8553
8554 dma = dma_map_single(ring->dev, xdpf->data, len, DMA_TO_DEVICE);
8555 if (dma_mapping_error(ring->dev, dma))
8556 return IXGBE_XDP_CONSUMED;
8557
8558 /* record the location of the first descriptor for this packet */
8559 tx_buffer = &ring->tx_buffer_info[ring->next_to_use];
8560 tx_buffer->bytecount = len;
8561 tx_buffer->gso_segs = 1;
8562 tx_buffer->protocol = 0;
8563
8564 i = ring->next_to_use;
8565 tx_desc = IXGBE_TX_DESC(ring, i);
8566
8567 dma_unmap_len_set(tx_buffer, len, len);
8568 dma_unmap_addr_set(tx_buffer, dma, dma);
8569 tx_buffer->xdpf = xdpf;
8570
8571 tx_desc->read.buffer_addr = cpu_to_le64(dma);
8572
8573 /* put descriptor type bits */
8574 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
8575 IXGBE_ADVTXD_DCMD_DEXT |
8576 IXGBE_ADVTXD_DCMD_IFCS;
8577 cmd_type |= len | IXGBE_TXD_CMD;
8578 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8579 tx_desc->read.olinfo_status =
8580 cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT);
8581
8582 /* Avoid any potential race with xdp_xmit and cleanup */
8583 smp_wmb();
8584
8585 /* set next_to_watch value indicating a packet is present */
8586 i++;
8587 if (i == ring->count)
8588 i = 0;
8589
8590 tx_buffer->next_to_watch = tx_desc;
8591 ring->next_to_use = i;
8592
8593 return IXGBE_XDP_TX;
8594}
8595
8596netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
8597 struct ixgbe_adapter *adapter,
8598 struct ixgbe_ring *tx_ring)
8599{
8600 struct ixgbe_tx_buffer *first;
8601 int tso;
8602 u32 tx_flags = 0;
8603 unsigned short f;
8604 u16 count = TXD_USE_COUNT(skb_headlen(skb));
8605 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 };
8606 __be16 protocol = skb->protocol;
8607 u8 hdr_len = 0;
8608
8609 /*
8610 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
8611 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
8612 * + 2 desc gap to keep tail from touching head,
8613 * + 1 desc for context descriptor,
8614 * otherwise try next time
8615 */
8616 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
8617 count += TXD_USE_COUNT(skb_frag_size(
8618 &skb_shinfo(skb)->frags[f]));
8619
8620 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
8621 tx_ring->tx_stats.tx_busy++;
8622 return NETDEV_TX_BUSY;
8623 }
8624
8625 /* record the location of the first descriptor for this packet */
8626 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
8627 first->skb = skb;
8628 first->bytecount = skb->len;
8629 first->gso_segs = 1;
8630
8631 /* if we have a HW VLAN tag being added default to the HW one */
8632 if (skb_vlan_tag_present(skb)) {
8633 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
8634 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
8635 /* else if it is a SW VLAN check the next protocol and store the tag */
8636 } else if (protocol == htons(ETH_P_8021Q)) {
8637 struct vlan_hdr *vhdr, _vhdr;
8638 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
8639 if (!vhdr)
8640 goto out_drop;
8641
8642 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
8643 IXGBE_TX_FLAGS_VLAN_SHIFT;
8644 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
8645 }
8646 protocol = vlan_get_protocol(skb);
8647
8648 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
8649 adapter->ptp_clock) {
8650 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON &&
8651 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
8652 &adapter->state)) {
8653 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
8654 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
8655
8656 /* schedule check for Tx timestamp */
8657 adapter->ptp_tx_skb = skb_get(skb);
8658 adapter->ptp_tx_start = jiffies;
8659 schedule_work(&adapter->ptp_tx_work);
8660 } else {
8661 adapter->tx_hwtstamp_skipped++;
8662 }
8663 }
8664
8665#ifdef CONFIG_PCI_IOV
8666 /*
8667 * Use the l2switch_enable flag - would be false if the DMA
8668 * Tx switch had been disabled.
8669 */
8670 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
8671 tx_flags |= IXGBE_TX_FLAGS_CC;
8672
8673#endif
8674 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
8675 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8676 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
8677 (skb->priority != TC_PRIO_CONTROL))) {
8678 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
8679 tx_flags |= (skb->priority & 0x7) <<
8680 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
8681 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
8682 struct vlan_ethhdr *vhdr;
8683
8684 if (skb_cow_head(skb, 0))
8685 goto out_drop;
8686 vhdr = (struct vlan_ethhdr *)skb->data;
8687 vhdr->h_vlan_TCI = htons(tx_flags >>
8688 IXGBE_TX_FLAGS_VLAN_SHIFT);
8689 } else {
8690 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
8691 }
8692 }
8693
8694 /* record initial flags and protocol */
8695 first->tx_flags = tx_flags;
8696 first->protocol = protocol;
8697
8698#ifdef IXGBE_FCOE
8699 /* setup tx offload for FCoE */
8700 if ((protocol == htons(ETH_P_FCOE)) &&
8701 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
8702 tso = ixgbe_fso(tx_ring, first, &hdr_len);
8703 if (tso < 0)
8704 goto out_drop;
8705
8706 goto xmit_fcoe;
8707 }
8708
8709#endif /* IXGBE_FCOE */
8710
8711#ifdef CONFIG_IXGBE_IPSEC
8712 if (xfrm_offload(skb) &&
8713 !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx))
8714 goto out_drop;
8715#endif
8716 tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx);
8717 if (tso < 0)
8718 goto out_drop;
8719 else if (!tso)
8720 ixgbe_tx_csum(tx_ring, first, &ipsec_tx);
8721
8722 /* add the ATR filter if ATR is on */
8723 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
8724 ixgbe_atr(tx_ring, first);
8725
8726#ifdef IXGBE_FCOE
8727xmit_fcoe:
8728#endif /* IXGBE_FCOE */
8729 if (ixgbe_tx_map(tx_ring, first, hdr_len))
8730 goto cleanup_tx_timestamp;
8731
8732 return NETDEV_TX_OK;
8733
8734out_drop:
8735 dev_kfree_skb_any(first->skb);
8736 first->skb = NULL;
8737cleanup_tx_timestamp:
8738 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) {
8739 dev_kfree_skb_any(adapter->ptp_tx_skb);
8740 adapter->ptp_tx_skb = NULL;
8741 cancel_work_sync(&adapter->ptp_tx_work);
8742 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
8743 }
8744
8745 return NETDEV_TX_OK;
8746}
8747
8748static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
8749 struct net_device *netdev,
8750 struct ixgbe_ring *ring)
8751{
8752 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8753 struct ixgbe_ring *tx_ring;
8754
8755 /*
8756 * The minimum packet size for olinfo paylen is 17 so pad the skb
8757 * in order to meet this minimum size requirement.
8758 */
8759 if (skb_put_padto(skb, 17))
8760 return NETDEV_TX_OK;
8761
8762 tx_ring = ring ? ring : adapter->tx_ring[skb_get_queue_mapping(skb)];
8763 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &tx_ring->state)))
8764 return NETDEV_TX_BUSY;
8765
8766 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
8767}
8768
8769static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
8770 struct net_device *netdev)
8771{
8772 return __ixgbe_xmit_frame(skb, netdev, NULL);
8773}
8774
8775/**
8776 * ixgbe_set_mac - Change the Ethernet Address of the NIC
8777 * @netdev: network interface device structure
8778 * @p: pointer to an address structure
8779 *
8780 * Returns 0 on success, negative on failure
8781 **/
8782static int ixgbe_set_mac(struct net_device *netdev, void *p)
8783{
8784 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8785 struct ixgbe_hw *hw = &adapter->hw;
8786 struct sockaddr *addr = p;
8787
8788 if (!is_valid_ether_addr(addr->sa_data))
8789 return -EADDRNOTAVAIL;
8790
8791 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
8792 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
8793
8794 ixgbe_mac_set_default_filter(adapter);
8795
8796 return 0;
8797}
8798
8799static int
8800ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
8801{
8802 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8803 struct ixgbe_hw *hw = &adapter->hw;
8804 u16 value;
8805 int rc;
8806
8807 if (adapter->mii_bus) {
8808 int regnum = addr;
8809
8810 if (devad != MDIO_DEVAD_NONE)
8811 regnum |= (devad << 16) | MII_ADDR_C45;
8812
8813 return mdiobus_read(adapter->mii_bus, prtad, regnum);
8814 }
8815
8816 if (prtad != hw->phy.mdio.prtad)
8817 return -EINVAL;
8818 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
8819 if (!rc)
8820 rc = value;
8821 return rc;
8822}
8823
8824static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
8825 u16 addr, u16 value)
8826{
8827 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8828 struct ixgbe_hw *hw = &adapter->hw;
8829
8830 if (adapter->mii_bus) {
8831 int regnum = addr;
8832
8833 if (devad != MDIO_DEVAD_NONE)
8834 regnum |= (devad << 16) | MII_ADDR_C45;
8835
8836 return mdiobus_write(adapter->mii_bus, prtad, regnum, value);
8837 }
8838
8839 if (prtad != hw->phy.mdio.prtad)
8840 return -EINVAL;
8841 return hw->phy.ops.write_reg(hw, addr, devad, value);
8842}
8843
8844static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
8845{
8846 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8847
8848 switch (cmd) {
8849 case SIOCSHWTSTAMP:
8850 return ixgbe_ptp_set_ts_config(adapter, req);
8851 case SIOCGHWTSTAMP:
8852 return ixgbe_ptp_get_ts_config(adapter, req);
8853 case SIOCGMIIPHY:
8854 if (!adapter->hw.phy.ops.read_reg)
8855 return -EOPNOTSUPP;
8856 fallthrough;
8857 default:
8858 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
8859 }
8860}
8861
8862/**
8863 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
8864 * netdev->dev_addrs
8865 * @dev: network interface device structure
8866 *
8867 * Returns non-zero on failure
8868 **/
8869static int ixgbe_add_sanmac_netdev(struct net_device *dev)
8870{
8871 int err = 0;
8872 struct ixgbe_adapter *adapter = netdev_priv(dev);
8873 struct ixgbe_hw *hw = &adapter->hw;
8874
8875 if (is_valid_ether_addr(hw->mac.san_addr)) {
8876 rtnl_lock();
8877 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
8878 rtnl_unlock();
8879
8880 /* update SAN MAC vmdq pool selection */
8881 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
8882 }
8883 return err;
8884}
8885
8886/**
8887 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
8888 * netdev->dev_addrs
8889 * @dev: network interface device structure
8890 *
8891 * Returns non-zero on failure
8892 **/
8893static int ixgbe_del_sanmac_netdev(struct net_device *dev)
8894{
8895 int err = 0;
8896 struct ixgbe_adapter *adapter = netdev_priv(dev);
8897 struct ixgbe_mac_info *mac = &adapter->hw.mac;
8898
8899 if (is_valid_ether_addr(mac->san_addr)) {
8900 rtnl_lock();
8901 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
8902 rtnl_unlock();
8903 }
8904 return err;
8905}
8906
8907static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats,
8908 struct ixgbe_ring *ring)
8909{
8910 u64 bytes, packets;
8911 unsigned int start;
8912
8913 if (ring) {
8914 do {
8915 start = u64_stats_fetch_begin_irq(&ring->syncp);
8916 packets = ring->stats.packets;
8917 bytes = ring->stats.bytes;
8918 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
8919 stats->tx_packets += packets;
8920 stats->tx_bytes += bytes;
8921 }
8922}
8923
8924static void ixgbe_get_stats64(struct net_device *netdev,
8925 struct rtnl_link_stats64 *stats)
8926{
8927 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8928 int i;
8929
8930 rcu_read_lock();
8931 for (i = 0; i < adapter->num_rx_queues; i++) {
8932 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]);
8933 u64 bytes, packets;
8934 unsigned int start;
8935
8936 if (ring) {
8937 do {
8938 start = u64_stats_fetch_begin_irq(&ring->syncp);
8939 packets = ring->stats.packets;
8940 bytes = ring->stats.bytes;
8941 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
8942 stats->rx_packets += packets;
8943 stats->rx_bytes += bytes;
8944 }
8945 }
8946
8947 for (i = 0; i < adapter->num_tx_queues; i++) {
8948 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]);
8949
8950 ixgbe_get_ring_stats64(stats, ring);
8951 }
8952 for (i = 0; i < adapter->num_xdp_queues; i++) {
8953 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]);
8954
8955 ixgbe_get_ring_stats64(stats, ring);
8956 }
8957 rcu_read_unlock();
8958
8959 /* following stats updated by ixgbe_watchdog_task() */
8960 stats->multicast = netdev->stats.multicast;
8961 stats->rx_errors = netdev->stats.rx_errors;
8962 stats->rx_length_errors = netdev->stats.rx_length_errors;
8963 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
8964 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
8965}
8966
8967#ifdef CONFIG_IXGBE_DCB
8968/**
8969 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
8970 * @adapter: pointer to ixgbe_adapter
8971 * @tc: number of traffic classes currently enabled
8972 *
8973 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
8974 * 802.1Q priority maps to a packet buffer that exists.
8975 */
8976static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
8977{
8978 struct ixgbe_hw *hw = &adapter->hw;
8979 u32 reg, rsave;
8980 int i;
8981
8982 /* 82598 have a static priority to TC mapping that can not
8983 * be changed so no validation is needed.
8984 */
8985 if (hw->mac.type == ixgbe_mac_82598EB)
8986 return;
8987
8988 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
8989 rsave = reg;
8990
8991 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
8992 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
8993
8994 /* If up2tc is out of bounds default to zero */
8995 if (up2tc > tc)
8996 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
8997 }
8998
8999 if (reg != rsave)
9000 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
9001
9002 return;
9003}
9004
9005/**
9006 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
9007 * @adapter: Pointer to adapter struct
9008 *
9009 * Populate the netdev user priority to tc map
9010 */
9011static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
9012{
9013 struct net_device *dev = adapter->netdev;
9014 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
9015 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
9016 u8 prio;
9017
9018 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
9019 u8 tc = 0;
9020
9021 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
9022 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
9023 else if (ets)
9024 tc = ets->prio_tc[prio];
9025
9026 netdev_set_prio_tc_map(dev, prio, tc);
9027 }
9028}
9029
9030#endif /* CONFIG_IXGBE_DCB */
9031static int ixgbe_reassign_macvlan_pool(struct net_device *vdev,
9032 struct netdev_nested_priv *priv)
9033{
9034 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data;
9035 struct ixgbe_fwd_adapter *accel;
9036 int pool;
9037
9038 /* we only care about macvlans... */
9039 if (!netif_is_macvlan(vdev))
9040 return 0;
9041
9042 /* that have hardware offload enabled... */
9043 accel = macvlan_accel_priv(vdev);
9044 if (!accel)
9045 return 0;
9046
9047 /* If we can relocate to a different bit do so */
9048 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools);
9049 if (pool < adapter->num_rx_pools) {
9050 set_bit(pool, adapter->fwd_bitmask);
9051 accel->pool = pool;
9052 return 0;
9053 }
9054
9055 /* if we cannot find a free pool then disable the offload */
9056 netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n");
9057 macvlan_release_l2fw_offload(vdev);
9058
9059 /* unbind the queues and drop the subordinate channel config */
9060 netdev_unbind_sb_channel(adapter->netdev, vdev);
9061 netdev_set_sb_channel(vdev, 0);
9062
9063 kfree(accel);
9064
9065 return 0;
9066}
9067
9068static void ixgbe_defrag_macvlan_pools(struct net_device *dev)
9069{
9070 struct ixgbe_adapter *adapter = netdev_priv(dev);
9071 struct netdev_nested_priv priv = {
9072 .data = (void *)adapter,
9073 };
9074
9075 /* flush any stale bits out of the fwd bitmask */
9076 bitmap_clear(adapter->fwd_bitmask, 1, 63);
9077
9078 /* walk through upper devices reassigning pools */
9079 netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool,
9080 &priv);
9081}
9082
9083/**
9084 * ixgbe_setup_tc - configure net_device for multiple traffic classes
9085 *
9086 * @dev: net device to configure
9087 * @tc: number of traffic classes to enable
9088 */
9089int ixgbe_setup_tc(struct net_device *dev, u8 tc)
9090{
9091 struct ixgbe_adapter *adapter = netdev_priv(dev);
9092 struct ixgbe_hw *hw = &adapter->hw;
9093
9094 /* Hardware supports up to 8 traffic classes */
9095 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
9096 return -EINVAL;
9097
9098 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
9099 return -EINVAL;
9100
9101 /* Hardware has to reinitialize queues and interrupts to
9102 * match packet buffer alignment. Unfortunately, the
9103 * hardware is not flexible enough to do this dynamically.
9104 */
9105 if (netif_running(dev))
9106 ixgbe_close(dev);
9107 else
9108 ixgbe_reset(adapter);
9109
9110 ixgbe_clear_interrupt_scheme(adapter);
9111
9112#ifdef CONFIG_IXGBE_DCB
9113 if (tc) {
9114 if (adapter->xdp_prog) {
9115 e_warn(probe, "DCB is not supported with XDP\n");
9116
9117 ixgbe_init_interrupt_scheme(adapter);
9118 if (netif_running(dev))
9119 ixgbe_open(dev);
9120 return -EINVAL;
9121 }
9122
9123 netdev_set_num_tc(dev, tc);
9124 ixgbe_set_prio_tc_map(adapter);
9125
9126 adapter->hw_tcs = tc;
9127 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
9128
9129 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
9130 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
9131 adapter->hw.fc.requested_mode = ixgbe_fc_none;
9132 }
9133 } else {
9134 netdev_reset_tc(dev);
9135
9136 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
9137 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
9138
9139 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
9140 adapter->hw_tcs = tc;
9141
9142 adapter->temp_dcb_cfg.pfc_mode_enable = false;
9143 adapter->dcb_cfg.pfc_mode_enable = false;
9144 }
9145
9146 ixgbe_validate_rtr(adapter, tc);
9147
9148#endif /* CONFIG_IXGBE_DCB */
9149 ixgbe_init_interrupt_scheme(adapter);
9150
9151 ixgbe_defrag_macvlan_pools(dev);
9152
9153 if (netif_running(dev))
9154 return ixgbe_open(dev);
9155
9156 return 0;
9157}
9158
9159static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter,
9160 struct tc_cls_u32_offload *cls)
9161{
9162 u32 hdl = cls->knode.handle;
9163 u32 uhtid = TC_U32_USERHTID(cls->knode.handle);
9164 u32 loc = cls->knode.handle & 0xfffff;
9165 int err = 0, i, j;
9166 struct ixgbe_jump_table *jump = NULL;
9167
9168 if (loc > IXGBE_MAX_HW_ENTRIES)
9169 return -EINVAL;
9170
9171 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE))
9172 return -EINVAL;
9173
9174 /* Clear this filter in the link data it is associated with */
9175 if (uhtid != 0x800) {
9176 jump = adapter->jump_tables[uhtid];
9177 if (!jump)
9178 return -EINVAL;
9179 if (!test_bit(loc - 1, jump->child_loc_map))
9180 return -EINVAL;
9181 clear_bit(loc - 1, jump->child_loc_map);
9182 }
9183
9184 /* Check if the filter being deleted is a link */
9185 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) {
9186 jump = adapter->jump_tables[i];
9187 if (jump && jump->link_hdl == hdl) {
9188 /* Delete filters in the hardware in the child hash
9189 * table associated with this link
9190 */
9191 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) {
9192 if (!test_bit(j, jump->child_loc_map))
9193 continue;
9194 spin_lock(&adapter->fdir_perfect_lock);
9195 err = ixgbe_update_ethtool_fdir_entry(adapter,
9196 NULL,
9197 j + 1);
9198 spin_unlock(&adapter->fdir_perfect_lock);
9199 clear_bit(j, jump->child_loc_map);
9200 }
9201 /* Remove resources for this link */
9202 kfree(jump->input);
9203 kfree(jump->mask);
9204 kfree(jump);
9205 adapter->jump_tables[i] = NULL;
9206 return err;
9207 }
9208 }
9209
9210 spin_lock(&adapter->fdir_perfect_lock);
9211 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc);
9212 spin_unlock(&adapter->fdir_perfect_lock);
9213 return err;
9214}
9215
9216static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter,
9217 struct tc_cls_u32_offload *cls)
9218{
9219 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
9220
9221 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
9222 return -EINVAL;
9223
9224 /* This ixgbe devices do not support hash tables at the moment
9225 * so abort when given hash tables.
9226 */
9227 if (cls->hnode.divisor > 0)
9228 return -EINVAL;
9229
9230 set_bit(uhtid - 1, &adapter->tables);
9231 return 0;
9232}
9233
9234static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter,
9235 struct tc_cls_u32_offload *cls)
9236{
9237 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
9238
9239 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
9240 return -EINVAL;
9241
9242 clear_bit(uhtid - 1, &adapter->tables);
9243 return 0;
9244}
9245
9246#ifdef CONFIG_NET_CLS_ACT
9247struct upper_walk_data {
9248 struct ixgbe_adapter *adapter;
9249 u64 action;
9250 int ifindex;
9251 u8 queue;
9252};
9253
9254static int get_macvlan_queue(struct net_device *upper,
9255 struct netdev_nested_priv *priv)
9256{
9257 if (netif_is_macvlan(upper)) {
9258 struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper);
9259 struct ixgbe_adapter *adapter;
9260 struct upper_walk_data *data;
9261 int ifindex;
9262
9263 data = (struct upper_walk_data *)priv->data;
9264 ifindex = data->ifindex;
9265 adapter = data->adapter;
9266 if (vadapter && upper->ifindex == ifindex) {
9267 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx;
9268 data->action = data->queue;
9269 return 1;
9270 }
9271 }
9272
9273 return 0;
9274}
9275
9276static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex,
9277 u8 *queue, u64 *action)
9278{
9279 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
9280 unsigned int num_vfs = adapter->num_vfs, vf;
9281 struct netdev_nested_priv priv;
9282 struct upper_walk_data data;
9283 struct net_device *upper;
9284
9285 /* redirect to a SRIOV VF */
9286 for (vf = 0; vf < num_vfs; ++vf) {
9287 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev);
9288 if (upper->ifindex == ifindex) {
9289 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask);
9290 *action = vf + 1;
9291 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
9292 return 0;
9293 }
9294 }
9295
9296 /* redirect to a offloaded macvlan netdev */
9297 data.adapter = adapter;
9298 data.ifindex = ifindex;
9299 data.action = 0;
9300 data.queue = 0;
9301 priv.data = (void *)&data;
9302 if (netdev_walk_all_upper_dev_rcu(adapter->netdev,
9303 get_macvlan_queue, &priv)) {
9304 *action = data.action;
9305 *queue = data.queue;
9306
9307 return 0;
9308 }
9309
9310 return -EINVAL;
9311}
9312
9313static int parse_tc_actions(struct ixgbe_adapter *adapter,
9314 struct tcf_exts *exts, u64 *action, u8 *queue)
9315{
9316 const struct tc_action *a;
9317 int i;
9318
9319 if (!tcf_exts_has_actions(exts))
9320 return -EINVAL;
9321
9322 tcf_exts_for_each_action(i, a, exts) {
9323 /* Drop action */
9324 if (is_tcf_gact_shot(a)) {
9325 *action = IXGBE_FDIR_DROP_QUEUE;
9326 *queue = IXGBE_FDIR_DROP_QUEUE;
9327 return 0;
9328 }
9329
9330 /* Redirect to a VF or a offloaded macvlan */
9331 if (is_tcf_mirred_egress_redirect(a)) {
9332 struct net_device *dev = tcf_mirred_dev(a);
9333
9334 if (!dev)
9335 return -EINVAL;
9336 return handle_redirect_action(adapter, dev->ifindex,
9337 queue, action);
9338 }
9339
9340 return -EINVAL;
9341 }
9342
9343 return -EINVAL;
9344}
9345#else
9346static int parse_tc_actions(struct ixgbe_adapter *adapter,
9347 struct tcf_exts *exts, u64 *action, u8 *queue)
9348{
9349 return -EINVAL;
9350}
9351#endif /* CONFIG_NET_CLS_ACT */
9352
9353static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input,
9354 union ixgbe_atr_input *mask,
9355 struct tc_cls_u32_offload *cls,
9356 struct ixgbe_mat_field *field_ptr,
9357 struct ixgbe_nexthdr *nexthdr)
9358{
9359 int i, j, off;
9360 __be32 val, m;
9361 bool found_entry = false, found_jump_field = false;
9362
9363 for (i = 0; i < cls->knode.sel->nkeys; i++) {
9364 off = cls->knode.sel->keys[i].off;
9365 val = cls->knode.sel->keys[i].val;
9366 m = cls->knode.sel->keys[i].mask;
9367
9368 for (j = 0; field_ptr[j].val; j++) {
9369 if (field_ptr[j].off == off) {
9370 field_ptr[j].val(input, mask, (__force u32)val,
9371 (__force u32)m);
9372 input->filter.formatted.flow_type |=
9373 field_ptr[j].type;
9374 found_entry = true;
9375 break;
9376 }
9377 }
9378 if (nexthdr) {
9379 if (nexthdr->off == cls->knode.sel->keys[i].off &&
9380 nexthdr->val ==
9381 (__force u32)cls->knode.sel->keys[i].val &&
9382 nexthdr->mask ==
9383 (__force u32)cls->knode.sel->keys[i].mask)
9384 found_jump_field = true;
9385 else
9386 continue;
9387 }
9388 }
9389
9390 if (nexthdr && !found_jump_field)
9391 return -EINVAL;
9392
9393 if (!found_entry)
9394 return 0;
9395
9396 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
9397 IXGBE_ATR_L4TYPE_MASK;
9398
9399 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
9400 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
9401
9402 return 0;
9403}
9404
9405static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter,
9406 struct tc_cls_u32_offload *cls)
9407{
9408 __be16 protocol = cls->common.protocol;
9409 u32 loc = cls->knode.handle & 0xfffff;
9410 struct ixgbe_hw *hw = &adapter->hw;
9411 struct ixgbe_mat_field *field_ptr;
9412 struct ixgbe_fdir_filter *input = NULL;
9413 union ixgbe_atr_input *mask = NULL;
9414 struct ixgbe_jump_table *jump = NULL;
9415 int i, err = -EINVAL;
9416 u8 queue;
9417 u32 uhtid, link_uhtid;
9418
9419 uhtid = TC_U32_USERHTID(cls->knode.handle);
9420 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle);
9421
9422 /* At the moment cls_u32 jumps to network layer and skips past
9423 * L2 headers. The canonical method to match L2 frames is to use
9424 * negative values. However this is error prone at best but really
9425 * just broken because there is no way to "know" what sort of hdr
9426 * is in front of the network layer. Fix cls_u32 to support L2
9427 * headers when needed.
9428 */
9429 if (protocol != htons(ETH_P_IP))
9430 return err;
9431
9432 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) {
9433 e_err(drv, "Location out of range\n");
9434 return err;
9435 }
9436
9437 /* cls u32 is a graph starting at root node 0x800. The driver tracks
9438 * links and also the fields used to advance the parser across each
9439 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map
9440 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h
9441 * To add support for new nodes update ixgbe_model.h parse structures
9442 * this function _should_ be generic try not to hardcode values here.
9443 */
9444 if (uhtid == 0x800) {
9445 field_ptr = (adapter->jump_tables[0])->mat;
9446 } else {
9447 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
9448 return err;
9449 if (!adapter->jump_tables[uhtid])
9450 return err;
9451 field_ptr = (adapter->jump_tables[uhtid])->mat;
9452 }
9453
9454 if (!field_ptr)
9455 return err;
9456
9457 /* At this point we know the field_ptr is valid and need to either
9458 * build cls_u32 link or attach filter. Because adding a link to
9459 * a handle that does not exist is invalid and the same for adding
9460 * rules to handles that don't exist.
9461 */
9462
9463 if (link_uhtid) {
9464 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps;
9465
9466 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE)
9467 return err;
9468
9469 if (!test_bit(link_uhtid - 1, &adapter->tables))
9470 return err;
9471
9472 /* Multiple filters as links to the same hash table are not
9473 * supported. To add a new filter with the same next header
9474 * but different match/jump conditions, create a new hash table
9475 * and link to it.
9476 */
9477 if (adapter->jump_tables[link_uhtid] &&
9478 (adapter->jump_tables[link_uhtid])->link_hdl) {
9479 e_err(drv, "Link filter exists for link: %x\n",
9480 link_uhtid);
9481 return err;
9482 }
9483
9484 for (i = 0; nexthdr[i].jump; i++) {
9485 if (nexthdr[i].o != cls->knode.sel->offoff ||
9486 nexthdr[i].s != cls->knode.sel->offshift ||
9487 nexthdr[i].m !=
9488 (__force u32)cls->knode.sel->offmask)
9489 return err;
9490
9491 jump = kzalloc(sizeof(*jump), GFP_KERNEL);
9492 if (!jump)
9493 return -ENOMEM;
9494 input = kzalloc(sizeof(*input), GFP_KERNEL);
9495 if (!input) {
9496 err = -ENOMEM;
9497 goto free_jump;
9498 }
9499 mask = kzalloc(sizeof(*mask), GFP_KERNEL);
9500 if (!mask) {
9501 err = -ENOMEM;
9502 goto free_input;
9503 }
9504 jump->input = input;
9505 jump->mask = mask;
9506 jump->link_hdl = cls->knode.handle;
9507
9508 err = ixgbe_clsu32_build_input(input, mask, cls,
9509 field_ptr, &nexthdr[i]);
9510 if (!err) {
9511 jump->mat = nexthdr[i].jump;
9512 adapter->jump_tables[link_uhtid] = jump;
9513 break;
9514 } else {
9515 kfree(mask);
9516 kfree(input);
9517 kfree(jump);
9518 }
9519 }
9520 return 0;
9521 }
9522
9523 input = kzalloc(sizeof(*input), GFP_KERNEL);
9524 if (!input)
9525 return -ENOMEM;
9526 mask = kzalloc(sizeof(*mask), GFP_KERNEL);
9527 if (!mask) {
9528 err = -ENOMEM;
9529 goto free_input;
9530 }
9531
9532 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) {
9533 if ((adapter->jump_tables[uhtid])->input)
9534 memcpy(input, (adapter->jump_tables[uhtid])->input,
9535 sizeof(*input));
9536 if ((adapter->jump_tables[uhtid])->mask)
9537 memcpy(mask, (adapter->jump_tables[uhtid])->mask,
9538 sizeof(*mask));
9539
9540 /* Lookup in all child hash tables if this location is already
9541 * filled with a filter
9542 */
9543 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) {
9544 struct ixgbe_jump_table *link = adapter->jump_tables[i];
9545
9546 if (link && (test_bit(loc - 1, link->child_loc_map))) {
9547 e_err(drv, "Filter exists in location: %x\n",
9548 loc);
9549 err = -EINVAL;
9550 goto err_out;
9551 }
9552 }
9553 }
9554 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL);
9555 if (err)
9556 goto err_out;
9557
9558 err = parse_tc_actions(adapter, cls->knode.exts, &input->action,
9559 &queue);
9560 if (err < 0)
9561 goto err_out;
9562
9563 input->sw_idx = loc;
9564
9565 spin_lock(&adapter->fdir_perfect_lock);
9566
9567 if (hlist_empty(&adapter->fdir_filter_list)) {
9568 memcpy(&adapter->fdir_mask, mask, sizeof(*mask));
9569 err = ixgbe_fdir_set_input_mask_82599(hw, mask);
9570 if (err)
9571 goto err_out_w_lock;
9572 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) {
9573 err = -EINVAL;
9574 goto err_out_w_lock;
9575 }
9576
9577 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask);
9578 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter,
9579 input->sw_idx, queue);
9580 if (!err)
9581 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
9582 spin_unlock(&adapter->fdir_perfect_lock);
9583
9584 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid]))
9585 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map);
9586
9587 kfree(mask);
9588 return err;
9589err_out_w_lock:
9590 spin_unlock(&adapter->fdir_perfect_lock);
9591err_out:
9592 kfree(mask);
9593free_input:
9594 kfree(input);
9595free_jump:
9596 kfree(jump);
9597 return err;
9598}
9599
9600static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter,
9601 struct tc_cls_u32_offload *cls_u32)
9602{
9603 switch (cls_u32->command) {
9604 case TC_CLSU32_NEW_KNODE:
9605 case TC_CLSU32_REPLACE_KNODE:
9606 return ixgbe_configure_clsu32(adapter, cls_u32);
9607 case TC_CLSU32_DELETE_KNODE:
9608 return ixgbe_delete_clsu32(adapter, cls_u32);
9609 case TC_CLSU32_NEW_HNODE:
9610 case TC_CLSU32_REPLACE_HNODE:
9611 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32);
9612 case TC_CLSU32_DELETE_HNODE:
9613 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32);
9614 default:
9615 return -EOPNOTSUPP;
9616 }
9617}
9618
9619static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
9620 void *cb_priv)
9621{
9622 struct ixgbe_adapter *adapter = cb_priv;
9623
9624 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data))
9625 return -EOPNOTSUPP;
9626
9627 switch (type) {
9628 case TC_SETUP_CLSU32:
9629 return ixgbe_setup_tc_cls_u32(adapter, type_data);
9630 default:
9631 return -EOPNOTSUPP;
9632 }
9633}
9634
9635static int ixgbe_setup_tc_mqprio(struct net_device *dev,
9636 struct tc_mqprio_qopt *mqprio)
9637{
9638 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
9639 return ixgbe_setup_tc(dev, mqprio->num_tc);
9640}
9641
9642static LIST_HEAD(ixgbe_block_cb_list);
9643
9644static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type,
9645 void *type_data)
9646{
9647 struct ixgbe_adapter *adapter = netdev_priv(dev);
9648
9649 switch (type) {
9650 case TC_SETUP_BLOCK:
9651 return flow_block_cb_setup_simple(type_data,
9652 &ixgbe_block_cb_list,
9653 ixgbe_setup_tc_block_cb,
9654 adapter, adapter, true);
9655 case TC_SETUP_QDISC_MQPRIO:
9656 return ixgbe_setup_tc_mqprio(dev, type_data);
9657 default:
9658 return -EOPNOTSUPP;
9659 }
9660}
9661
9662#ifdef CONFIG_PCI_IOV
9663void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
9664{
9665 struct net_device *netdev = adapter->netdev;
9666
9667 rtnl_lock();
9668 ixgbe_setup_tc(netdev, adapter->hw_tcs);
9669 rtnl_unlock();
9670}
9671
9672#endif
9673void ixgbe_do_reset(struct net_device *netdev)
9674{
9675 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9676
9677 if (netif_running(netdev))
9678 ixgbe_reinit_locked(adapter);
9679 else
9680 ixgbe_reset(adapter);
9681}
9682
9683static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
9684 netdev_features_t features)
9685{
9686 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9687
9688 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
9689 if (!(features & NETIF_F_RXCSUM))
9690 features &= ~NETIF_F_LRO;
9691
9692 /* Turn off LRO if not RSC capable */
9693 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
9694 features &= ~NETIF_F_LRO;
9695
9696 if (adapter->xdp_prog && (features & NETIF_F_LRO)) {
9697 e_dev_err("LRO is not supported with XDP\n");
9698 features &= ~NETIF_F_LRO;
9699 }
9700
9701 return features;
9702}
9703
9704static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter)
9705{
9706 int rss = min_t(int, ixgbe_max_rss_indices(adapter),
9707 num_online_cpus());
9708
9709 /* go back to full RSS if we're not running SR-IOV */
9710 if (!adapter->ring_feature[RING_F_VMDQ].offset)
9711 adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED |
9712 IXGBE_FLAG_SRIOV_ENABLED);
9713
9714 adapter->ring_feature[RING_F_RSS].limit = rss;
9715 adapter->ring_feature[RING_F_VMDQ].limit = 1;
9716
9717 ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs);
9718}
9719
9720static int ixgbe_set_features(struct net_device *netdev,
9721 netdev_features_t features)
9722{
9723 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9724 netdev_features_t changed = netdev->features ^ features;
9725 bool need_reset = false;
9726
9727 /* Make sure RSC matches LRO, reset if change */
9728 if (!(features & NETIF_F_LRO)) {
9729 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
9730 need_reset = true;
9731 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
9732 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
9733 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
9734 if (adapter->rx_itr_setting == 1 ||
9735 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
9736 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
9737 need_reset = true;
9738 } else if ((changed ^ features) & NETIF_F_LRO) {
9739 e_info(probe, "rx-usecs set too low, "
9740 "disabling RSC\n");
9741 }
9742 }
9743
9744 /*
9745 * Check if Flow Director n-tuple support or hw_tc support was
9746 * enabled or disabled. If the state changed, we need to reset.
9747 */
9748 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) {
9749 /* turn off ATR, enable perfect filters and reset */
9750 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
9751 need_reset = true;
9752
9753 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
9754 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
9755 } else {
9756 /* turn off perfect filters, enable ATR and reset */
9757 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
9758 need_reset = true;
9759
9760 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
9761
9762 /* We cannot enable ATR if SR-IOV is enabled */
9763 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED ||
9764 /* We cannot enable ATR if we have 2 or more tcs */
9765 (adapter->hw_tcs > 1) ||
9766 /* We cannot enable ATR if RSS is disabled */
9767 (adapter->ring_feature[RING_F_RSS].limit <= 1) ||
9768 /* A sample rate of 0 indicates ATR disabled */
9769 (!adapter->atr_sample_rate))
9770 ; /* do nothing not supported */
9771 else /* otherwise supported and set the flag */
9772 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
9773 }
9774
9775 if (changed & NETIF_F_RXALL)
9776 need_reset = true;
9777
9778 netdev->features = features;
9779
9780 if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1)
9781 ixgbe_reset_l2fw_offload(adapter);
9782 else if (need_reset)
9783 ixgbe_do_reset(netdev);
9784 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX |
9785 NETIF_F_HW_VLAN_CTAG_FILTER))
9786 ixgbe_set_rx_mode(netdev);
9787
9788 return 1;
9789}
9790
9791static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
9792 struct net_device *dev,
9793 const unsigned char *addr, u16 vid,
9794 u16 flags,
9795 struct netlink_ext_ack *extack)
9796{
9797 /* guarantee we can provide a unique filter for the unicast address */
9798 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
9799 struct ixgbe_adapter *adapter = netdev_priv(dev);
9800 u16 pool = VMDQ_P(0);
9801
9802 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool))
9803 return -ENOMEM;
9804 }
9805
9806 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
9807}
9808
9809/**
9810 * ixgbe_configure_bridge_mode - set various bridge modes
9811 * @adapter: the private structure
9812 * @mode: requested bridge mode
9813 *
9814 * Configure some settings require for various bridge modes.
9815 **/
9816static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
9817 __u16 mode)
9818{
9819 struct ixgbe_hw *hw = &adapter->hw;
9820 unsigned int p, num_pools;
9821 u32 vmdctl;
9822
9823 switch (mode) {
9824 case BRIDGE_MODE_VEPA:
9825 /* disable Tx loopback, rely on switch hairpin mode */
9826 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
9827
9828 /* must enable Rx switching replication to allow multicast
9829 * packet reception on all VFs, and to enable source address
9830 * pruning.
9831 */
9832 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
9833 vmdctl |= IXGBE_VT_CTL_REPLEN;
9834 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
9835
9836 /* enable Rx source address pruning. Note, this requires
9837 * replication to be enabled or else it does nothing.
9838 */
9839 num_pools = adapter->num_vfs + adapter->num_rx_pools;
9840 for (p = 0; p < num_pools; p++) {
9841 if (hw->mac.ops.set_source_address_pruning)
9842 hw->mac.ops.set_source_address_pruning(hw,
9843 true,
9844 p);
9845 }
9846 break;
9847 case BRIDGE_MODE_VEB:
9848 /* enable Tx loopback for internal VF/PF communication */
9849 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
9850 IXGBE_PFDTXGSWC_VT_LBEN);
9851
9852 /* disable Rx switching replication unless we have SR-IOV
9853 * virtual functions
9854 */
9855 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
9856 if (!adapter->num_vfs)
9857 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
9858 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
9859
9860 /* disable Rx source address pruning, since we don't expect to
9861 * be receiving external loopback of our transmitted frames.
9862 */
9863 num_pools = adapter->num_vfs + adapter->num_rx_pools;
9864 for (p = 0; p < num_pools; p++) {
9865 if (hw->mac.ops.set_source_address_pruning)
9866 hw->mac.ops.set_source_address_pruning(hw,
9867 false,
9868 p);
9869 }
9870 break;
9871 default:
9872 return -EINVAL;
9873 }
9874
9875 adapter->bridge_mode = mode;
9876
9877 e_info(drv, "enabling bridge mode: %s\n",
9878 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
9879
9880 return 0;
9881}
9882
9883static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
9884 struct nlmsghdr *nlh, u16 flags,
9885 struct netlink_ext_ack *extack)
9886{
9887 struct ixgbe_adapter *adapter = netdev_priv(dev);
9888 struct nlattr *attr, *br_spec;
9889 int rem;
9890
9891 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
9892 return -EOPNOTSUPP;
9893
9894 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
9895 if (!br_spec)
9896 return -EINVAL;
9897
9898 nla_for_each_nested(attr, br_spec, rem) {
9899 int status;
9900 __u16 mode;
9901
9902 if (nla_type(attr) != IFLA_BRIDGE_MODE)
9903 continue;
9904
9905 if (nla_len(attr) < sizeof(mode))
9906 return -EINVAL;
9907
9908 mode = nla_get_u16(attr);
9909 status = ixgbe_configure_bridge_mode(adapter, mode);
9910 if (status)
9911 return status;
9912
9913 break;
9914 }
9915
9916 return 0;
9917}
9918
9919static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
9920 struct net_device *dev,
9921 u32 filter_mask, int nlflags)
9922{
9923 struct ixgbe_adapter *adapter = netdev_priv(dev);
9924
9925 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
9926 return 0;
9927
9928 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
9929 adapter->bridge_mode, 0, 0, nlflags,
9930 filter_mask, NULL);
9931}
9932
9933static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
9934{
9935 struct ixgbe_adapter *adapter = netdev_priv(pdev);
9936 struct ixgbe_fwd_adapter *accel;
9937 int tcs = adapter->hw_tcs ? : 1;
9938 int pool, err;
9939
9940 if (adapter->xdp_prog) {
9941 e_warn(probe, "L2FW offload is not supported with XDP\n");
9942 return ERR_PTR(-EINVAL);
9943 }
9944
9945 /* The hardware supported by ixgbe only filters on the destination MAC
9946 * address. In order to avoid issues we only support offloading modes
9947 * where the hardware can actually provide the functionality.
9948 */
9949 if (!macvlan_supports_dest_filter(vdev))
9950 return ERR_PTR(-EMEDIUMTYPE);
9951
9952 /* We need to lock down the macvlan to be a single queue device so that
9953 * we can reuse the tc_to_txq field in the macvlan netdev to represent
9954 * the queue mapping to our netdev.
9955 */
9956 if (netif_is_multiqueue(vdev))
9957 return ERR_PTR(-ERANGE);
9958
9959 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools);
9960 if (pool == adapter->num_rx_pools) {
9961 u16 used_pools = adapter->num_vfs + adapter->num_rx_pools;
9962 u16 reserved_pools;
9963
9964 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
9965 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) ||
9966 adapter->num_rx_pools > IXGBE_MAX_MACVLANS)
9967 return ERR_PTR(-EBUSY);
9968
9969 /* Hardware has a limited number of available pools. Each VF,
9970 * and the PF require a pool. Check to ensure we don't
9971 * attempt to use more then the available number of pools.
9972 */
9973 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
9974 return ERR_PTR(-EBUSY);
9975
9976 /* Enable VMDq flag so device will be set in VM mode */
9977 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED |
9978 IXGBE_FLAG_SRIOV_ENABLED;
9979
9980 /* Try to reserve as many queues per pool as possible,
9981 * we start with the configurations that support 4 queues
9982 * per pools, followed by 2, and then by just 1 per pool.
9983 */
9984 if (used_pools < 32 && adapter->num_rx_pools < 16)
9985 reserved_pools = min_t(u16,
9986 32 - used_pools,
9987 16 - adapter->num_rx_pools);
9988 else if (adapter->num_rx_pools < 32)
9989 reserved_pools = min_t(u16,
9990 64 - used_pools,
9991 32 - adapter->num_rx_pools);
9992 else
9993 reserved_pools = 64 - used_pools;
9994
9995
9996 if (!reserved_pools)
9997 return ERR_PTR(-EBUSY);
9998
9999 adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools;
10000
10001 /* Force reinit of ring allocation with VMDQ enabled */
10002 err = ixgbe_setup_tc(pdev, adapter->hw_tcs);
10003 if (err)
10004 return ERR_PTR(err);
10005
10006 if (pool >= adapter->num_rx_pools)
10007 return ERR_PTR(-ENOMEM);
10008 }
10009
10010 accel = kzalloc(sizeof(*accel), GFP_KERNEL);
10011 if (!accel)
10012 return ERR_PTR(-ENOMEM);
10013
10014 set_bit(pool, adapter->fwd_bitmask);
10015 netdev_set_sb_channel(vdev, pool);
10016 accel->pool = pool;
10017 accel->netdev = vdev;
10018
10019 if (!netif_running(pdev))
10020 return accel;
10021
10022 err = ixgbe_fwd_ring_up(adapter, accel);
10023 if (err)
10024 return ERR_PTR(err);
10025
10026 return accel;
10027}
10028
10029static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
10030{
10031 struct ixgbe_fwd_adapter *accel = priv;
10032 struct ixgbe_adapter *adapter = netdev_priv(pdev);
10033 unsigned int rxbase = accel->rx_base_queue;
10034 unsigned int i;
10035
10036 /* delete unicast filter associated with offloaded interface */
10037 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr,
10038 VMDQ_P(accel->pool));
10039
10040 /* Allow remaining Rx packets to get flushed out of the
10041 * Rx FIFO before we drop the netdev for the ring.
10042 */
10043 usleep_range(10000, 20000);
10044
10045 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
10046 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i];
10047 struct ixgbe_q_vector *qv = ring->q_vector;
10048
10049 /* Make sure we aren't processing any packets and clear
10050 * netdev to shut down the ring.
10051 */
10052 if (netif_running(adapter->netdev))
10053 napi_synchronize(&qv->napi);
10054 ring->netdev = NULL;
10055 }
10056
10057 /* unbind the queues and drop the subordinate channel config */
10058 netdev_unbind_sb_channel(pdev, accel->netdev);
10059 netdev_set_sb_channel(accel->netdev, 0);
10060
10061 clear_bit(accel->pool, adapter->fwd_bitmask);
10062 kfree(accel);
10063}
10064
10065#define IXGBE_MAX_MAC_HDR_LEN 127
10066#define IXGBE_MAX_NETWORK_HDR_LEN 511
10067
10068static netdev_features_t
10069ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
10070 netdev_features_t features)
10071{
10072 unsigned int network_hdr_len, mac_hdr_len;
10073
10074 /* Make certain the headers can be described by a context descriptor */
10075 mac_hdr_len = skb_network_header(skb) - skb->data;
10076 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN))
10077 return features & ~(NETIF_F_HW_CSUM |
10078 NETIF_F_SCTP_CRC |
10079 NETIF_F_GSO_UDP_L4 |
10080 NETIF_F_HW_VLAN_CTAG_TX |
10081 NETIF_F_TSO |
10082 NETIF_F_TSO6);
10083
10084 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
10085 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN))
10086 return features & ~(NETIF_F_HW_CSUM |
10087 NETIF_F_SCTP_CRC |
10088 NETIF_F_GSO_UDP_L4 |
10089 NETIF_F_TSO |
10090 NETIF_F_TSO6);
10091
10092 /* We can only support IPV4 TSO in tunnels if we can mangle the
10093 * inner IP ID field, so strip TSO if MANGLEID is not supported.
10094 * IPsec offoad sets skb->encapsulation but still can handle
10095 * the TSO, so it's the exception.
10096 */
10097 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) {
10098#ifdef CONFIG_IXGBE_IPSEC
10099 if (!secpath_exists(skb))
10100#endif
10101 features &= ~NETIF_F_TSO;
10102 }
10103
10104 return features;
10105}
10106
10107static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog)
10108{
10109 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
10110 struct ixgbe_adapter *adapter = netdev_priv(dev);
10111 struct bpf_prog *old_prog;
10112 bool need_reset;
10113
10114 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
10115 return -EINVAL;
10116
10117 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
10118 return -EINVAL;
10119
10120 /* verify ixgbe ring attributes are sufficient for XDP */
10121 for (i = 0; i < adapter->num_rx_queues; i++) {
10122 struct ixgbe_ring *ring = adapter->rx_ring[i];
10123
10124 if (ring_is_rsc_enabled(ring))
10125 return -EINVAL;
10126
10127 if (frame_size > ixgbe_rx_bufsz(ring))
10128 return -EINVAL;
10129 }
10130
10131 if (nr_cpu_ids > MAX_XDP_QUEUES)
10132 return -ENOMEM;
10133
10134 old_prog = xchg(&adapter->xdp_prog, prog);
10135 need_reset = (!!prog != !!old_prog);
10136
10137 /* If transitioning XDP modes reconfigure rings */
10138 if (need_reset) {
10139 int err;
10140
10141 if (!prog)
10142 /* Wait until ndo_xsk_wakeup completes. */
10143 synchronize_rcu();
10144 err = ixgbe_setup_tc(dev, adapter->hw_tcs);
10145
10146 if (err) {
10147 rcu_assign_pointer(adapter->xdp_prog, old_prog);
10148 return -EINVAL;
10149 }
10150 } else {
10151 for (i = 0; i < adapter->num_rx_queues; i++)
10152 (void)xchg(&adapter->rx_ring[i]->xdp_prog,
10153 adapter->xdp_prog);
10154 }
10155
10156 if (old_prog)
10157 bpf_prog_put(old_prog);
10158
10159 /* Kick start the NAPI context if there is an AF_XDP socket open
10160 * on that queue id. This so that receiving will start.
10161 */
10162 if (need_reset && prog)
10163 for (i = 0; i < adapter->num_rx_queues; i++)
10164 if (adapter->xdp_ring[i]->xsk_umem)
10165 (void)ixgbe_xsk_wakeup(adapter->netdev, i,
10166 XDP_WAKEUP_RX);
10167
10168 return 0;
10169}
10170
10171static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp)
10172{
10173 struct ixgbe_adapter *adapter = netdev_priv(dev);
10174
10175 switch (xdp->command) {
10176 case XDP_SETUP_PROG:
10177 return ixgbe_xdp_setup(dev, xdp->prog);
10178 case XDP_SETUP_XSK_UMEM:
10179 return ixgbe_xsk_umem_setup(adapter, xdp->xsk.umem,
10180 xdp->xsk.queue_id);
10181
10182 default:
10183 return -EINVAL;
10184 }
10185}
10186
10187void ixgbe_xdp_ring_update_tail(struct ixgbe_ring *ring)
10188{
10189 /* Force memory writes to complete before letting h/w know there
10190 * are new descriptors to fetch.
10191 */
10192 wmb();
10193 writel(ring->next_to_use, ring->tail);
10194}
10195
10196static int ixgbe_xdp_xmit(struct net_device *dev, int n,
10197 struct xdp_frame **frames, u32 flags)
10198{
10199 struct ixgbe_adapter *adapter = netdev_priv(dev);
10200 struct ixgbe_ring *ring;
10201 int drops = 0;
10202 int i;
10203
10204 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state)))
10205 return -ENETDOWN;
10206
10207 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
10208 return -EINVAL;
10209
10210 /* During program transitions its possible adapter->xdp_prog is assigned
10211 * but ring has not been configured yet. In this case simply abort xmit.
10212 */
10213 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL;
10214 if (unlikely(!ring))
10215 return -ENXIO;
10216
10217 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &ring->state)))
10218 return -ENXIO;
10219
10220 for (i = 0; i < n; i++) {
10221 struct xdp_frame *xdpf = frames[i];
10222 int err;
10223
10224 err = ixgbe_xmit_xdp_ring(adapter, xdpf);
10225 if (err != IXGBE_XDP_TX) {
10226 xdp_return_frame_rx_napi(xdpf);
10227 drops++;
10228 }
10229 }
10230
10231 if (unlikely(flags & XDP_XMIT_FLUSH))
10232 ixgbe_xdp_ring_update_tail(ring);
10233
10234 return n - drops;
10235}
10236
10237static const struct net_device_ops ixgbe_netdev_ops = {
10238 .ndo_open = ixgbe_open,
10239 .ndo_stop = ixgbe_close,
10240 .ndo_start_xmit = ixgbe_xmit_frame,
10241 .ndo_set_rx_mode = ixgbe_set_rx_mode,
10242 .ndo_validate_addr = eth_validate_addr,
10243 .ndo_set_mac_address = ixgbe_set_mac,
10244 .ndo_change_mtu = ixgbe_change_mtu,
10245 .ndo_tx_timeout = ixgbe_tx_timeout,
10246 .ndo_set_tx_maxrate = ixgbe_tx_maxrate,
10247 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
10248 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
10249 .ndo_do_ioctl = ixgbe_ioctl,
10250 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
10251 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
10252 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
10253 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
10254 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
10255 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust,
10256 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
10257 .ndo_get_stats64 = ixgbe_get_stats64,
10258 .ndo_setup_tc = __ixgbe_setup_tc,
10259#ifdef IXGBE_FCOE
10260 .ndo_select_queue = ixgbe_select_queue,
10261 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
10262 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
10263 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
10264 .ndo_fcoe_enable = ixgbe_fcoe_enable,
10265 .ndo_fcoe_disable = ixgbe_fcoe_disable,
10266 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
10267 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
10268#endif /* IXGBE_FCOE */
10269 .ndo_set_features = ixgbe_set_features,
10270 .ndo_fix_features = ixgbe_fix_features,
10271 .ndo_fdb_add = ixgbe_ndo_fdb_add,
10272 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
10273 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
10274 .ndo_dfwd_add_station = ixgbe_fwd_add,
10275 .ndo_dfwd_del_station = ixgbe_fwd_del,
10276 .ndo_udp_tunnel_add = udp_tunnel_nic_add_port,
10277 .ndo_udp_tunnel_del = udp_tunnel_nic_del_port,
10278 .ndo_features_check = ixgbe_features_check,
10279 .ndo_bpf = ixgbe_xdp,
10280 .ndo_xdp_xmit = ixgbe_xdp_xmit,
10281 .ndo_xsk_wakeup = ixgbe_xsk_wakeup,
10282};
10283
10284static void ixgbe_disable_txr_hw(struct ixgbe_adapter *adapter,
10285 struct ixgbe_ring *tx_ring)
10286{
10287 unsigned long wait_delay, delay_interval;
10288 struct ixgbe_hw *hw = &adapter->hw;
10289 u8 reg_idx = tx_ring->reg_idx;
10290 int wait_loop;
10291 u32 txdctl;
10292
10293 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
10294
10295 /* delay mechanism from ixgbe_disable_tx */
10296 delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
10297
10298 wait_loop = IXGBE_MAX_RX_DESC_POLL;
10299 wait_delay = delay_interval;
10300
10301 while (wait_loop--) {
10302 usleep_range(wait_delay, wait_delay + 10);
10303 wait_delay += delay_interval * 2;
10304 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
10305
10306 if (!(txdctl & IXGBE_TXDCTL_ENABLE))
10307 return;
10308 }
10309
10310 e_err(drv, "TXDCTL.ENABLE not cleared within the polling period\n");
10311}
10312
10313static void ixgbe_disable_txr(struct ixgbe_adapter *adapter,
10314 struct ixgbe_ring *tx_ring)
10315{
10316 set_bit(__IXGBE_TX_DISABLED, &tx_ring->state);
10317 ixgbe_disable_txr_hw(adapter, tx_ring);
10318}
10319
10320static void ixgbe_disable_rxr_hw(struct ixgbe_adapter *adapter,
10321 struct ixgbe_ring *rx_ring)
10322{
10323 unsigned long wait_delay, delay_interval;
10324 struct ixgbe_hw *hw = &adapter->hw;
10325 u8 reg_idx = rx_ring->reg_idx;
10326 int wait_loop;
10327 u32 rxdctl;
10328
10329 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
10330 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
10331 rxdctl |= IXGBE_RXDCTL_SWFLSH;
10332
10333 /* write value back with RXDCTL.ENABLE bit cleared */
10334 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
10335
10336 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */
10337 if (hw->mac.type == ixgbe_mac_82598EB &&
10338 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
10339 return;
10340
10341 /* delay mechanism from ixgbe_disable_rx */
10342 delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
10343
10344 wait_loop = IXGBE_MAX_RX_DESC_POLL;
10345 wait_delay = delay_interval;
10346
10347 while (wait_loop--) {
10348 usleep_range(wait_delay, wait_delay + 10);
10349 wait_delay += delay_interval * 2;
10350 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
10351
10352 if (!(rxdctl & IXGBE_RXDCTL_ENABLE))
10353 return;
10354 }
10355
10356 e_err(drv, "RXDCTL.ENABLE not cleared within the polling period\n");
10357}
10358
10359static void ixgbe_reset_txr_stats(struct ixgbe_ring *tx_ring)
10360{
10361 memset(&tx_ring->stats, 0, sizeof(tx_ring->stats));
10362 memset(&tx_ring->tx_stats, 0, sizeof(tx_ring->tx_stats));
10363}
10364
10365static void ixgbe_reset_rxr_stats(struct ixgbe_ring *rx_ring)
10366{
10367 memset(&rx_ring->stats, 0, sizeof(rx_ring->stats));
10368 memset(&rx_ring->rx_stats, 0, sizeof(rx_ring->rx_stats));
10369}
10370
10371/**
10372 * ixgbe_txrx_ring_disable - Disable Rx/Tx/XDP Tx rings
10373 * @adapter: adapter structure
10374 * @ring: ring index
10375 *
10376 * This function disables a certain Rx/Tx/XDP Tx ring. The function
10377 * assumes that the netdev is running.
10378 **/
10379void ixgbe_txrx_ring_disable(struct ixgbe_adapter *adapter, int ring)
10380{
10381 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring;
10382
10383 rx_ring = adapter->rx_ring[ring];
10384 tx_ring = adapter->tx_ring[ring];
10385 xdp_ring = adapter->xdp_ring[ring];
10386
10387 ixgbe_disable_txr(adapter, tx_ring);
10388 if (xdp_ring)
10389 ixgbe_disable_txr(adapter, xdp_ring);
10390 ixgbe_disable_rxr_hw(adapter, rx_ring);
10391
10392 if (xdp_ring)
10393 synchronize_rcu();
10394
10395 /* Rx/Tx/XDP Tx share the same napi context. */
10396 napi_disable(&rx_ring->q_vector->napi);
10397
10398 ixgbe_clean_tx_ring(tx_ring);
10399 if (xdp_ring)
10400 ixgbe_clean_tx_ring(xdp_ring);
10401 ixgbe_clean_rx_ring(rx_ring);
10402
10403 ixgbe_reset_txr_stats(tx_ring);
10404 if (xdp_ring)
10405 ixgbe_reset_txr_stats(xdp_ring);
10406 ixgbe_reset_rxr_stats(rx_ring);
10407}
10408
10409/**
10410 * ixgbe_txrx_ring_enable - Enable Rx/Tx/XDP Tx rings
10411 * @adapter: adapter structure
10412 * @ring: ring index
10413 *
10414 * This function enables a certain Rx/Tx/XDP Tx ring. The function
10415 * assumes that the netdev is running.
10416 **/
10417void ixgbe_txrx_ring_enable(struct ixgbe_adapter *adapter, int ring)
10418{
10419 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring;
10420
10421 rx_ring = adapter->rx_ring[ring];
10422 tx_ring = adapter->tx_ring[ring];
10423 xdp_ring = adapter->xdp_ring[ring];
10424
10425 /* Rx/Tx/XDP Tx share the same napi context. */
10426 napi_enable(&rx_ring->q_vector->napi);
10427
10428 ixgbe_configure_tx_ring(adapter, tx_ring);
10429 if (xdp_ring)
10430 ixgbe_configure_tx_ring(adapter, xdp_ring);
10431 ixgbe_configure_rx_ring(adapter, rx_ring);
10432
10433 clear_bit(__IXGBE_TX_DISABLED, &tx_ring->state);
10434 if (xdp_ring)
10435 clear_bit(__IXGBE_TX_DISABLED, &xdp_ring->state);
10436}
10437
10438/**
10439 * ixgbe_enumerate_functions - Get the number of ports this device has
10440 * @adapter: adapter structure
10441 *
10442 * This function enumerates the phsyical functions co-located on a single slot,
10443 * in order to determine how many ports a device has. This is most useful in
10444 * determining the required GT/s of PCIe bandwidth necessary for optimal
10445 * performance.
10446 **/
10447static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
10448{
10449 struct pci_dev *entry, *pdev = adapter->pdev;
10450 int physfns = 0;
10451
10452 /* Some cards can not use the generic count PCIe functions method,
10453 * because they are behind a parent switch, so we hardcode these with
10454 * the correct number of functions.
10455 */
10456 if (ixgbe_pcie_from_parent(&adapter->hw))
10457 physfns = 4;
10458
10459 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
10460 /* don't count virtual functions */
10461 if (entry->is_virtfn)
10462 continue;
10463
10464 /* When the devices on the bus don't all match our device ID,
10465 * we can't reliably determine the correct number of
10466 * functions. This can occur if a function has been direct
10467 * attached to a virtual machine using VT-d, for example. In
10468 * this case, simply return -1 to indicate this.
10469 */
10470 if ((entry->vendor != pdev->vendor) ||
10471 (entry->device != pdev->device))
10472 return -1;
10473
10474 physfns++;
10475 }
10476
10477 return physfns;
10478}
10479
10480/**
10481 * ixgbe_wol_supported - Check whether device supports WoL
10482 * @adapter: the adapter private structure
10483 * @device_id: the device ID
10484 * @subdevice_id: the subsystem device ID
10485 *
10486 * This function is used by probe and ethtool to determine
10487 * which devices have WoL support
10488 *
10489 **/
10490bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
10491 u16 subdevice_id)
10492{
10493 struct ixgbe_hw *hw = &adapter->hw;
10494 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
10495
10496 /* WOL not supported on 82598 */
10497 if (hw->mac.type == ixgbe_mac_82598EB)
10498 return false;
10499
10500 /* check eeprom to see if WOL is enabled for X540 and newer */
10501 if (hw->mac.type >= ixgbe_mac_X540) {
10502 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
10503 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
10504 (hw->bus.func == 0)))
10505 return true;
10506 }
10507
10508 /* WOL is determined based on device IDs for 82599 MACs */
10509 switch (device_id) {
10510 case IXGBE_DEV_ID_82599_SFP:
10511 /* Only these subdevices could supports WOL */
10512 switch (subdevice_id) {
10513 case IXGBE_SUBDEV_ID_82599_560FLR:
10514 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6:
10515 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
10516 case IXGBE_SUBDEV_ID_82599_SFP_2OCP:
10517 /* only support first port */
10518 if (hw->bus.func != 0)
10519 break;
10520 fallthrough;
10521 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
10522 case IXGBE_SUBDEV_ID_82599_SFP:
10523 case IXGBE_SUBDEV_ID_82599_RNDC:
10524 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
10525 case IXGBE_SUBDEV_ID_82599_SFP_1OCP:
10526 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1:
10527 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2:
10528 return true;
10529 }
10530 break;
10531 case IXGBE_DEV_ID_82599EN_SFP:
10532 /* Only these subdevices support WOL */
10533 switch (subdevice_id) {
10534 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
10535 return true;
10536 }
10537 break;
10538 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
10539 /* All except this subdevice support WOL */
10540 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
10541 return true;
10542 break;
10543 case IXGBE_DEV_ID_82599_KX4:
10544 return true;
10545 default:
10546 break;
10547 }
10548
10549 return false;
10550}
10551
10552/**
10553 * ixgbe_set_fw_version - Set FW version
10554 * @adapter: the adapter private structure
10555 *
10556 * This function is used by probe and ethtool to determine the FW version to
10557 * format to display. The FW version is taken from the EEPROM/NVM.
10558 */
10559static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter)
10560{
10561 struct ixgbe_hw *hw = &adapter->hw;
10562 struct ixgbe_nvm_version nvm_ver;
10563
10564 ixgbe_get_oem_prod_version(hw, &nvm_ver);
10565 if (nvm_ver.oem_valid) {
10566 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10567 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor,
10568 nvm_ver.oem_release);
10569 return;
10570 }
10571
10572 ixgbe_get_etk_id(hw, &nvm_ver);
10573 ixgbe_get_orom_version(hw, &nvm_ver);
10574
10575 if (nvm_ver.or_valid) {
10576 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10577 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major,
10578 nvm_ver.or_build, nvm_ver.or_patch);
10579 return;
10580 }
10581
10582 /* Set ETrack ID format */
10583 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10584 "0x%08x", nvm_ver.etk_id);
10585}
10586
10587/**
10588 * ixgbe_probe - Device Initialization Routine
10589 * @pdev: PCI device information struct
10590 * @ent: entry in ixgbe_pci_tbl
10591 *
10592 * Returns 0 on success, negative on failure
10593 *
10594 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
10595 * The OS initialization, configuring of the adapter private structure,
10596 * and a hardware reset occur.
10597 **/
10598static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10599{
10600 struct net_device *netdev;
10601 struct ixgbe_adapter *adapter = NULL;
10602 struct ixgbe_hw *hw;
10603 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
10604 int i, err, pci_using_dac, expected_gts;
10605 unsigned int indices = MAX_TX_QUEUES;
10606 u8 part_str[IXGBE_PBANUM_LENGTH];
10607 bool disable_dev = false;
10608#ifdef IXGBE_FCOE
10609 u16 device_caps;
10610#endif
10611 u32 eec;
10612
10613 /* Catch broken hardware that put the wrong VF device ID in
10614 * the PCIe SR-IOV capability.
10615 */
10616 if (pdev->is_virtfn) {
10617 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
10618 pci_name(pdev), pdev->vendor, pdev->device);
10619 return -EINVAL;
10620 }
10621
10622 err = pci_enable_device_mem(pdev);
10623 if (err)
10624 return err;
10625
10626 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
10627 pci_using_dac = 1;
10628 } else {
10629 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10630 if (err) {
10631 dev_err(&pdev->dev,
10632 "No usable DMA configuration, aborting\n");
10633 goto err_dma;
10634 }
10635 pci_using_dac = 0;
10636 }
10637
10638 err = pci_request_mem_regions(pdev, ixgbe_driver_name);
10639 if (err) {
10640 dev_err(&pdev->dev,
10641 "pci_request_selected_regions failed 0x%x\n", err);
10642 goto err_pci_reg;
10643 }
10644
10645 pci_enable_pcie_error_reporting(pdev);
10646
10647 pci_set_master(pdev);
10648 pci_save_state(pdev);
10649
10650 if (ii->mac == ixgbe_mac_82598EB) {
10651#ifdef CONFIG_IXGBE_DCB
10652 /* 8 TC w/ 4 queues per TC */
10653 indices = 4 * MAX_TRAFFIC_CLASS;
10654#else
10655 indices = IXGBE_MAX_RSS_INDICES;
10656#endif
10657 }
10658
10659 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
10660 if (!netdev) {
10661 err = -ENOMEM;
10662 goto err_alloc_etherdev;
10663 }
10664
10665 SET_NETDEV_DEV(netdev, &pdev->dev);
10666
10667 adapter = netdev_priv(netdev);
10668
10669 adapter->netdev = netdev;
10670 adapter->pdev = pdev;
10671 hw = &adapter->hw;
10672 hw->back = adapter;
10673 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
10674
10675 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
10676 pci_resource_len(pdev, 0));
10677 adapter->io_addr = hw->hw_addr;
10678 if (!hw->hw_addr) {
10679 err = -EIO;
10680 goto err_ioremap;
10681 }
10682
10683 netdev->netdev_ops = &ixgbe_netdev_ops;
10684 ixgbe_set_ethtool_ops(netdev);
10685 netdev->watchdog_timeo = 5 * HZ;
10686 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
10687
10688 /* Setup hw api */
10689 hw->mac.ops = *ii->mac_ops;
10690 hw->mac.type = ii->mac;
10691 hw->mvals = ii->mvals;
10692 if (ii->link_ops)
10693 hw->link.ops = *ii->link_ops;
10694
10695 /* EEPROM */
10696 hw->eeprom.ops = *ii->eeprom_ops;
10697 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
10698 if (ixgbe_removed(hw->hw_addr)) {
10699 err = -EIO;
10700 goto err_ioremap;
10701 }
10702 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
10703 if (!(eec & BIT(8)))
10704 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
10705
10706 /* PHY */
10707 hw->phy.ops = *ii->phy_ops;
10708 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
10709 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
10710 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
10711 hw->phy.mdio.mmds = 0;
10712 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10713 hw->phy.mdio.dev = netdev;
10714 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
10715 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
10716
10717 /* setup the private structure */
10718 err = ixgbe_sw_init(adapter, ii);
10719 if (err)
10720 goto err_sw_init;
10721
10722 switch (adapter->hw.mac.type) {
10723 case ixgbe_mac_X550:
10724 case ixgbe_mac_X550EM_x:
10725 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550;
10726 break;
10727 case ixgbe_mac_x550em_a:
10728 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550em_a;
10729 break;
10730 default:
10731 break;
10732 }
10733
10734 /* Make sure the SWFW semaphore is in a valid state */
10735 if (hw->mac.ops.init_swfw_sync)
10736 hw->mac.ops.init_swfw_sync(hw);
10737
10738 /* Make it possible the adapter to be woken up via WOL */
10739 switch (adapter->hw.mac.type) {
10740 case ixgbe_mac_82599EB:
10741 case ixgbe_mac_X540:
10742 case ixgbe_mac_X550:
10743 case ixgbe_mac_X550EM_x:
10744 case ixgbe_mac_x550em_a:
10745 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
10746 break;
10747 default:
10748 break;
10749 }
10750
10751 /*
10752 * If there is a fan on this device and it has failed log the
10753 * failure.
10754 */
10755 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
10756 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
10757 if (esdp & IXGBE_ESDP_SDP1)
10758 e_crit(probe, "Fan has stopped, replace the adapter\n");
10759 }
10760
10761 if (allow_unsupported_sfp)
10762 hw->allow_unsupported_sfp = allow_unsupported_sfp;
10763
10764 /* reset_hw fills in the perm_addr as well */
10765 hw->phy.reset_if_overtemp = true;
10766 err = hw->mac.ops.reset_hw(hw);
10767 hw->phy.reset_if_overtemp = false;
10768 ixgbe_set_eee_capable(adapter);
10769 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
10770 err = 0;
10771 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
10772 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
10773 e_dev_err("Reload the driver after installing a supported module.\n");
10774 goto err_sw_init;
10775 } else if (err) {
10776 e_dev_err("HW Init failed: %d\n", err);
10777 goto err_sw_init;
10778 }
10779
10780#ifdef CONFIG_PCI_IOV
10781 /* SR-IOV not supported on the 82598 */
10782 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
10783 goto skip_sriov;
10784 /* Mailbox */
10785 ixgbe_init_mbx_params_pf(hw);
10786 hw->mbx.ops = ii->mbx_ops;
10787 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
10788 ixgbe_enable_sriov(adapter, max_vfs);
10789skip_sriov:
10790
10791#endif
10792 netdev->features = NETIF_F_SG |
10793 NETIF_F_TSO |
10794 NETIF_F_TSO6 |
10795 NETIF_F_RXHASH |
10796 NETIF_F_RXCSUM |
10797 NETIF_F_HW_CSUM;
10798
10799#define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
10800 NETIF_F_GSO_GRE_CSUM | \
10801 NETIF_F_GSO_IPXIP4 | \
10802 NETIF_F_GSO_IPXIP6 | \
10803 NETIF_F_GSO_UDP_TUNNEL | \
10804 NETIF_F_GSO_UDP_TUNNEL_CSUM)
10805
10806 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES;
10807 netdev->features |= NETIF_F_GSO_PARTIAL |
10808 IXGBE_GSO_PARTIAL_FEATURES;
10809
10810 if (hw->mac.type >= ixgbe_mac_82599EB)
10811 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4;
10812
10813#ifdef CONFIG_IXGBE_IPSEC
10814#define IXGBE_ESP_FEATURES (NETIF_F_HW_ESP | \
10815 NETIF_F_HW_ESP_TX_CSUM | \
10816 NETIF_F_GSO_ESP)
10817
10818 if (adapter->ipsec)
10819 netdev->features |= IXGBE_ESP_FEATURES;
10820#endif
10821 /* copy netdev features into list of user selectable features */
10822 netdev->hw_features |= netdev->features |
10823 NETIF_F_HW_VLAN_CTAG_FILTER |
10824 NETIF_F_HW_VLAN_CTAG_RX |
10825 NETIF_F_HW_VLAN_CTAG_TX |
10826 NETIF_F_RXALL |
10827 NETIF_F_HW_L2FW_DOFFLOAD;
10828
10829 if (hw->mac.type >= ixgbe_mac_82599EB)
10830 netdev->hw_features |= NETIF_F_NTUPLE |
10831 NETIF_F_HW_TC;
10832
10833 if (pci_using_dac)
10834 netdev->features |= NETIF_F_HIGHDMA;
10835
10836 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
10837 netdev->hw_enc_features |= netdev->vlan_features;
10838 netdev->mpls_features |= NETIF_F_SG |
10839 NETIF_F_TSO |
10840 NETIF_F_TSO6 |
10841 NETIF_F_HW_CSUM;
10842 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES;
10843
10844 /* set this bit last since it cannot be part of vlan_features */
10845 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
10846 NETIF_F_HW_VLAN_CTAG_RX |
10847 NETIF_F_HW_VLAN_CTAG_TX;
10848
10849 netdev->priv_flags |= IFF_UNICAST_FLT;
10850 netdev->priv_flags |= IFF_SUPP_NOFCS;
10851
10852 /* MTU range: 68 - 9710 */
10853 netdev->min_mtu = ETH_MIN_MTU;
10854 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN);
10855
10856#ifdef CONFIG_IXGBE_DCB
10857 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE)
10858 netdev->dcbnl_ops = &ixgbe_dcbnl_ops;
10859#endif
10860
10861#ifdef IXGBE_FCOE
10862 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
10863 unsigned int fcoe_l;
10864
10865 if (hw->mac.ops.get_device_caps) {
10866 hw->mac.ops.get_device_caps(hw, &device_caps);
10867 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
10868 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
10869 }
10870
10871
10872 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
10873 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
10874
10875 netdev->features |= NETIF_F_FSO |
10876 NETIF_F_FCOE_CRC;
10877
10878 netdev->vlan_features |= NETIF_F_FSO |
10879 NETIF_F_FCOE_CRC |
10880 NETIF_F_FCOE_MTU;
10881 }
10882#endif /* IXGBE_FCOE */
10883 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
10884 netdev->hw_features |= NETIF_F_LRO;
10885 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
10886 netdev->features |= NETIF_F_LRO;
10887
10888 if (ixgbe_check_fw_error(adapter)) {
10889 err = -EIO;
10890 goto err_sw_init;
10891 }
10892
10893 /* make sure the EEPROM is good */
10894 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
10895 e_dev_err("The EEPROM Checksum Is Not Valid\n");
10896 err = -EIO;
10897 goto err_sw_init;
10898 }
10899
10900 eth_platform_get_mac_address(&adapter->pdev->dev,
10901 adapter->hw.mac.perm_addr);
10902
10903 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
10904
10905 if (!is_valid_ether_addr(netdev->dev_addr)) {
10906 e_dev_err("invalid MAC address\n");
10907 err = -EIO;
10908 goto err_sw_init;
10909 }
10910
10911 /* Set hw->mac.addr to permanent MAC address */
10912 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr);
10913 ixgbe_mac_set_default_filter(adapter);
10914
10915 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0);
10916
10917 if (ixgbe_removed(hw->hw_addr)) {
10918 err = -EIO;
10919 goto err_sw_init;
10920 }
10921 INIT_WORK(&adapter->service_task, ixgbe_service_task);
10922 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
10923 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
10924
10925 err = ixgbe_init_interrupt_scheme(adapter);
10926 if (err)
10927 goto err_sw_init;
10928
10929 for (i = 0; i < adapter->num_rx_queues; i++)
10930 u64_stats_init(&adapter->rx_ring[i]->syncp);
10931 for (i = 0; i < adapter->num_tx_queues; i++)
10932 u64_stats_init(&adapter->tx_ring[i]->syncp);
10933 for (i = 0; i < adapter->num_xdp_queues; i++)
10934 u64_stats_init(&adapter->xdp_ring[i]->syncp);
10935
10936 /* WOL not supported for all devices */
10937 adapter->wol = 0;
10938 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
10939 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
10940 pdev->subsystem_device);
10941 if (hw->wol_enabled)
10942 adapter->wol = IXGBE_WUFC_MAG;
10943
10944 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
10945
10946 /* save off EEPROM version number */
10947 ixgbe_set_fw_version(adapter);
10948
10949 /* pick up the PCI bus settings for reporting later */
10950 if (ixgbe_pcie_from_parent(hw))
10951 ixgbe_get_parent_bus_info(adapter);
10952 else
10953 hw->mac.ops.get_bus_info(hw);
10954
10955 /* calculate the expected PCIe bandwidth required for optimal
10956 * performance. Note that some older parts will never have enough
10957 * bandwidth due to being older generation PCIe parts. We clamp these
10958 * parts to ensure no warning is displayed if it can't be fixed.
10959 */
10960 switch (hw->mac.type) {
10961 case ixgbe_mac_82598EB:
10962 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
10963 break;
10964 default:
10965 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
10966 break;
10967 }
10968
10969 /* don't check link if we failed to enumerate functions */
10970 if (expected_gts > 0)
10971 ixgbe_check_minimum_link(adapter, expected_gts);
10972
10973 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
10974 if (err)
10975 strlcpy(part_str, "Unknown", sizeof(part_str));
10976 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
10977 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
10978 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
10979 part_str);
10980 else
10981 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
10982 hw->mac.type, hw->phy.type, part_str);
10983
10984 e_dev_info("%pM\n", netdev->dev_addr);
10985
10986 /* reset the hardware with the new settings */
10987 err = hw->mac.ops.start_hw(hw);
10988 if (err == IXGBE_ERR_EEPROM_VERSION) {
10989 /* We are running on a pre-production device, log a warning */
10990 e_dev_warn("This device is a pre-production adapter/LOM. "
10991 "Please be aware there may be issues associated "
10992 "with your hardware. If you are experiencing "
10993 "problems please contact your Intel or hardware "
10994 "representative who provided you with this "
10995 "hardware.\n");
10996 }
10997 strcpy(netdev->name, "eth%d");
10998 pci_set_drvdata(pdev, adapter);
10999 err = register_netdev(netdev);
11000 if (err)
11001 goto err_register;
11002
11003
11004 /* power down the optics for 82599 SFP+ fiber */
11005 if (hw->mac.ops.disable_tx_laser)
11006 hw->mac.ops.disable_tx_laser(hw);
11007
11008 /* carrier off reporting is important to ethtool even BEFORE open */
11009 netif_carrier_off(netdev);
11010
11011#ifdef CONFIG_IXGBE_DCA
11012 if (dca_add_requester(&pdev->dev) == 0) {
11013 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
11014 ixgbe_setup_dca(adapter);
11015 }
11016#endif
11017 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
11018 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
11019 for (i = 0; i < adapter->num_vfs; i++)
11020 ixgbe_vf_configuration(pdev, (i | 0x10000000));
11021 }
11022
11023 /* firmware requires driver version to be 0xFFFFFFFF
11024 * since os does not support feature
11025 */
11026 if (hw->mac.ops.set_fw_drv_ver)
11027 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF,
11028 sizeof(UTS_RELEASE) - 1,
11029 UTS_RELEASE);
11030
11031 /* add san mac addr to netdev */
11032 ixgbe_add_sanmac_netdev(netdev);
11033
11034 e_dev_info("%s\n", ixgbe_default_device_descr);
11035
11036#ifdef CONFIG_IXGBE_HWMON
11037 if (ixgbe_sysfs_init(adapter))
11038 e_err(probe, "failed to allocate sysfs resources\n");
11039#endif /* CONFIG_IXGBE_HWMON */
11040
11041 ixgbe_dbg_adapter_init(adapter);
11042
11043 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
11044 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
11045 hw->mac.ops.setup_link(hw,
11046 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
11047 true);
11048
11049 err = ixgbe_mii_bus_init(hw);
11050 if (err)
11051 goto err_netdev;
11052
11053 return 0;
11054
11055err_netdev:
11056 unregister_netdev(netdev);
11057err_register:
11058 ixgbe_release_hw_control(adapter);
11059 ixgbe_clear_interrupt_scheme(adapter);
11060err_sw_init:
11061 ixgbe_disable_sriov(adapter);
11062 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
11063 iounmap(adapter->io_addr);
11064 kfree(adapter->jump_tables[0]);
11065 kfree(adapter->mac_table);
11066 kfree(adapter->rss_key);
11067 bitmap_free(adapter->af_xdp_zc_qps);
11068err_ioremap:
11069 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
11070 free_netdev(netdev);
11071err_alloc_etherdev:
11072 pci_release_mem_regions(pdev);
11073err_pci_reg:
11074err_dma:
11075 if (!adapter || disable_dev)
11076 pci_disable_device(pdev);
11077 return err;
11078}
11079
11080/**
11081 * ixgbe_remove - Device Removal Routine
11082 * @pdev: PCI device information struct
11083 *
11084 * ixgbe_remove is called by the PCI subsystem to alert the driver
11085 * that it should release a PCI device. The could be caused by a
11086 * Hot-Plug event, or because the driver is going to be removed from
11087 * memory.
11088 **/
11089static void ixgbe_remove(struct pci_dev *pdev)
11090{
11091 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11092 struct net_device *netdev;
11093 bool disable_dev;
11094 int i;
11095
11096 /* if !adapter then we already cleaned up in probe */
11097 if (!adapter)
11098 return;
11099
11100 netdev = adapter->netdev;
11101 ixgbe_dbg_adapter_exit(adapter);
11102
11103 set_bit(__IXGBE_REMOVING, &adapter->state);
11104 cancel_work_sync(&adapter->service_task);
11105
11106 if (adapter->mii_bus)
11107 mdiobus_unregister(adapter->mii_bus);
11108
11109#ifdef CONFIG_IXGBE_DCA
11110 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
11111 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
11112 dca_remove_requester(&pdev->dev);
11113 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
11114 IXGBE_DCA_CTRL_DCA_DISABLE);
11115 }
11116
11117#endif
11118#ifdef CONFIG_IXGBE_HWMON
11119 ixgbe_sysfs_exit(adapter);
11120#endif /* CONFIG_IXGBE_HWMON */
11121
11122 /* remove the added san mac */
11123 ixgbe_del_sanmac_netdev(netdev);
11124
11125#ifdef CONFIG_PCI_IOV
11126 ixgbe_disable_sriov(adapter);
11127#endif
11128 if (netdev->reg_state == NETREG_REGISTERED)
11129 unregister_netdev(netdev);
11130
11131 ixgbe_stop_ipsec_offload(adapter);
11132 ixgbe_clear_interrupt_scheme(adapter);
11133
11134 ixgbe_release_hw_control(adapter);
11135
11136#ifdef CONFIG_DCB
11137 kfree(adapter->ixgbe_ieee_pfc);
11138 kfree(adapter->ixgbe_ieee_ets);
11139
11140#endif
11141 iounmap(adapter->io_addr);
11142 pci_release_mem_regions(pdev);
11143
11144 e_dev_info("complete\n");
11145
11146 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) {
11147 if (adapter->jump_tables[i]) {
11148 kfree(adapter->jump_tables[i]->input);
11149 kfree(adapter->jump_tables[i]->mask);
11150 }
11151 kfree(adapter->jump_tables[i]);
11152 }
11153
11154 kfree(adapter->mac_table);
11155 kfree(adapter->rss_key);
11156 bitmap_free(adapter->af_xdp_zc_qps);
11157 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
11158 free_netdev(netdev);
11159
11160 pci_disable_pcie_error_reporting(pdev);
11161
11162 if (disable_dev)
11163 pci_disable_device(pdev);
11164}
11165
11166/**
11167 * ixgbe_io_error_detected - called when PCI error is detected
11168 * @pdev: Pointer to PCI device
11169 * @state: The current pci connection state
11170 *
11171 * This function is called after a PCI bus error affecting
11172 * this device has been detected.
11173 */
11174static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
11175 pci_channel_state_t state)
11176{
11177 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11178 struct net_device *netdev = adapter->netdev;
11179
11180#ifdef CONFIG_PCI_IOV
11181 struct ixgbe_hw *hw = &adapter->hw;
11182 struct pci_dev *bdev, *vfdev;
11183 u32 dw0, dw1, dw2, dw3;
11184 int vf, pos;
11185 u16 req_id, pf_func;
11186
11187 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
11188 adapter->num_vfs == 0)
11189 goto skip_bad_vf_detection;
11190
11191 bdev = pdev->bus->self;
11192 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
11193 bdev = bdev->bus->self;
11194
11195 if (!bdev)
11196 goto skip_bad_vf_detection;
11197
11198 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
11199 if (!pos)
11200 goto skip_bad_vf_detection;
11201
11202 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
11203 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
11204 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
11205 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
11206 if (ixgbe_removed(hw->hw_addr))
11207 goto skip_bad_vf_detection;
11208
11209 req_id = dw1 >> 16;
11210 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
11211 if (!(req_id & 0x0080))
11212 goto skip_bad_vf_detection;
11213
11214 pf_func = req_id & 0x01;
11215 if ((pf_func & 1) == (pdev->devfn & 1)) {
11216 unsigned int device_id;
11217
11218 vf = (req_id & 0x7F) >> 1;
11219 e_dev_err("VF %d has caused a PCIe error\n", vf);
11220 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
11221 "%8.8x\tdw3: %8.8x\n",
11222 dw0, dw1, dw2, dw3);
11223 switch (adapter->hw.mac.type) {
11224 case ixgbe_mac_82599EB:
11225 device_id = IXGBE_82599_VF_DEVICE_ID;
11226 break;
11227 case ixgbe_mac_X540:
11228 device_id = IXGBE_X540_VF_DEVICE_ID;
11229 break;
11230 case ixgbe_mac_X550:
11231 device_id = IXGBE_DEV_ID_X550_VF;
11232 break;
11233 case ixgbe_mac_X550EM_x:
11234 device_id = IXGBE_DEV_ID_X550EM_X_VF;
11235 break;
11236 case ixgbe_mac_x550em_a:
11237 device_id = IXGBE_DEV_ID_X550EM_A_VF;
11238 break;
11239 default:
11240 device_id = 0;
11241 break;
11242 }
11243
11244 /* Find the pci device of the offending VF */
11245 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
11246 while (vfdev) {
11247 if (vfdev->devfn == (req_id & 0xFF))
11248 break;
11249 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
11250 device_id, vfdev);
11251 }
11252 /*
11253 * There's a slim chance the VF could have been hot plugged,
11254 * so if it is no longer present we don't need to issue the
11255 * VFLR. Just clean up the AER in that case.
11256 */
11257 if (vfdev) {
11258 pcie_flr(vfdev);
11259 /* Free device reference count */
11260 pci_dev_put(vfdev);
11261 }
11262 }
11263
11264 /*
11265 * Even though the error may have occurred on the other port
11266 * we still need to increment the vf error reference count for
11267 * both ports because the I/O resume function will be called
11268 * for both of them.
11269 */
11270 adapter->vferr_refcount++;
11271
11272 return PCI_ERS_RESULT_RECOVERED;
11273
11274skip_bad_vf_detection:
11275#endif /* CONFIG_PCI_IOV */
11276 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
11277 return PCI_ERS_RESULT_DISCONNECT;
11278
11279 if (!netif_device_present(netdev))
11280 return PCI_ERS_RESULT_DISCONNECT;
11281
11282 rtnl_lock();
11283 netif_device_detach(netdev);
11284
11285 if (netif_running(netdev))
11286 ixgbe_close_suspend(adapter);
11287
11288 if (state == pci_channel_io_perm_failure) {
11289 rtnl_unlock();
11290 return PCI_ERS_RESULT_DISCONNECT;
11291 }
11292
11293 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
11294 pci_disable_device(pdev);
11295 rtnl_unlock();
11296
11297 /* Request a slot reset. */
11298 return PCI_ERS_RESULT_NEED_RESET;
11299}
11300
11301/**
11302 * ixgbe_io_slot_reset - called after the pci bus has been reset.
11303 * @pdev: Pointer to PCI device
11304 *
11305 * Restart the card from scratch, as if from a cold-boot.
11306 */
11307static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
11308{
11309 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11310 pci_ers_result_t result;
11311
11312 if (pci_enable_device_mem(pdev)) {
11313 e_err(probe, "Cannot re-enable PCI device after reset.\n");
11314 result = PCI_ERS_RESULT_DISCONNECT;
11315 } else {
11316 smp_mb__before_atomic();
11317 clear_bit(__IXGBE_DISABLED, &adapter->state);
11318 adapter->hw.hw_addr = adapter->io_addr;
11319 pci_set_master(pdev);
11320 pci_restore_state(pdev);
11321 pci_save_state(pdev);
11322
11323 pci_wake_from_d3(pdev, false);
11324
11325 ixgbe_reset(adapter);
11326 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
11327 result = PCI_ERS_RESULT_RECOVERED;
11328 }
11329
11330 return result;
11331}
11332
11333/**
11334 * ixgbe_io_resume - called when traffic can start flowing again.
11335 * @pdev: Pointer to PCI device
11336 *
11337 * This callback is called when the error recovery driver tells us that
11338 * its OK to resume normal operation.
11339 */
11340static void ixgbe_io_resume(struct pci_dev *pdev)
11341{
11342 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11343 struct net_device *netdev = adapter->netdev;
11344
11345#ifdef CONFIG_PCI_IOV
11346 if (adapter->vferr_refcount) {
11347 e_info(drv, "Resuming after VF err\n");
11348 adapter->vferr_refcount--;
11349 return;
11350 }
11351
11352#endif
11353 rtnl_lock();
11354 if (netif_running(netdev))
11355 ixgbe_open(netdev);
11356
11357 netif_device_attach(netdev);
11358 rtnl_unlock();
11359}
11360
11361static const struct pci_error_handlers ixgbe_err_handler = {
11362 .error_detected = ixgbe_io_error_detected,
11363 .slot_reset = ixgbe_io_slot_reset,
11364 .resume = ixgbe_io_resume,
11365};
11366
11367static SIMPLE_DEV_PM_OPS(ixgbe_pm_ops, ixgbe_suspend, ixgbe_resume);
11368
11369static struct pci_driver ixgbe_driver = {
11370 .name = ixgbe_driver_name,
11371 .id_table = ixgbe_pci_tbl,
11372 .probe = ixgbe_probe,
11373 .remove = ixgbe_remove,
11374 .driver.pm = &ixgbe_pm_ops,
11375 .shutdown = ixgbe_shutdown,
11376 .sriov_configure = ixgbe_pci_sriov_configure,
11377 .err_handler = &ixgbe_err_handler
11378};
11379
11380/**
11381 * ixgbe_init_module - Driver Registration Routine
11382 *
11383 * ixgbe_init_module is the first routine called when the driver is
11384 * loaded. All it does is register with the PCI subsystem.
11385 **/
11386static int __init ixgbe_init_module(void)
11387{
11388 int ret;
11389 pr_info("%s\n", ixgbe_driver_string);
11390 pr_info("%s\n", ixgbe_copyright);
11391
11392 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name);
11393 if (!ixgbe_wq) {
11394 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name);
11395 return -ENOMEM;
11396 }
11397
11398 ixgbe_dbg_init();
11399
11400 ret = pci_register_driver(&ixgbe_driver);
11401 if (ret) {
11402 destroy_workqueue(ixgbe_wq);
11403 ixgbe_dbg_exit();
11404 return ret;
11405 }
11406
11407#ifdef CONFIG_IXGBE_DCA
11408 dca_register_notify(&dca_notifier);
11409#endif
11410
11411 return 0;
11412}
11413
11414module_init(ixgbe_init_module);
11415
11416/**
11417 * ixgbe_exit_module - Driver Exit Cleanup Routine
11418 *
11419 * ixgbe_exit_module is called just before the driver is removed
11420 * from memory.
11421 **/
11422static void __exit ixgbe_exit_module(void)
11423{
11424#ifdef CONFIG_IXGBE_DCA
11425 dca_unregister_notify(&dca_notifier);
11426#endif
11427 pci_unregister_driver(&ixgbe_driver);
11428
11429 ixgbe_dbg_exit();
11430 if (ixgbe_wq) {
11431 destroy_workqueue(ixgbe_wq);
11432 ixgbe_wq = NULL;
11433 }
11434}
11435
11436#ifdef CONFIG_IXGBE_DCA
11437static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
11438 void *p)
11439{
11440 int ret_val;
11441
11442 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
11443 __ixgbe_notify_dca);
11444
11445 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
11446}
11447
11448#endif /* CONFIG_IXGBE_DCA */
11449
11450module_exit(ixgbe_exit_module);
11451
11452/* ixgbe_main.c */