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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018, Intel Corporation. */
3
4/* Machine-generated file */
5
6#ifndef _ICE_HW_AUTOGEN_H_
7#define _ICE_HW_AUTOGEN_H_
8
9#define QTX_COMM_DBELL(_DBQM) (0x002C0000 + ((_DBQM) * 4))
10#define QTX_COMM_HEAD(_DBQM) (0x000E0000 + ((_DBQM) * 4))
11#define QTX_COMM_HEAD_HEAD_S 0
12#define QTX_COMM_HEAD_HEAD_M ICE_M(0x1FFF, 0)
13#define PF_FW_ARQBAH 0x00080180
14#define PF_FW_ARQBAL 0x00080080
15#define PF_FW_ARQH 0x00080380
16#define PF_FW_ARQH_ARQH_M ICE_M(0x3FF, 0)
17#define PF_FW_ARQLEN 0x00080280
18#define PF_FW_ARQLEN_ARQLEN_M ICE_M(0x3FF, 0)
19#define PF_FW_ARQLEN_ARQVFE_M BIT(28)
20#define PF_FW_ARQLEN_ARQOVFL_M BIT(29)
21#define PF_FW_ARQLEN_ARQCRIT_M BIT(30)
22#define PF_FW_ARQLEN_ARQENABLE_M BIT(31)
23#define PF_FW_ARQT 0x00080480
24#define PF_FW_ATQBAH 0x00080100
25#define PF_FW_ATQBAL 0x00080000
26#define PF_FW_ATQH 0x00080300
27#define PF_FW_ATQH_ATQH_M ICE_M(0x3FF, 0)
28#define PF_FW_ATQLEN 0x00080200
29#define PF_FW_ATQLEN_ATQLEN_M ICE_M(0x3FF, 0)
30#define PF_FW_ATQLEN_ATQVFE_M BIT(28)
31#define PF_FW_ATQLEN_ATQOVFL_M BIT(29)
32#define PF_FW_ATQLEN_ATQCRIT_M BIT(30)
33#define VF_MBX_ARQLEN(_VF) (0x0022BC00 + ((_VF) * 4))
34#define PF_FW_ATQLEN_ATQENABLE_M BIT(31)
35#define PF_FW_ATQT 0x00080400
36#define PF_MBX_ARQBAH 0x0022E400
37#define PF_MBX_ARQBAL 0x0022E380
38#define PF_MBX_ARQH 0x0022E500
39#define PF_MBX_ARQH_ARQH_M ICE_M(0x3FF, 0)
40#define PF_MBX_ARQLEN 0x0022E480
41#define PF_MBX_ARQLEN_ARQLEN_M ICE_M(0x3FF, 0)
42#define PF_MBX_ARQLEN_ARQCRIT_M BIT(30)
43#define PF_MBX_ARQLEN_ARQENABLE_M BIT(31)
44#define PF_MBX_ARQT 0x0022E580
45#define PF_MBX_ATQBAH 0x0022E180
46#define PF_MBX_ATQBAL 0x0022E100
47#define PF_MBX_ATQH 0x0022E280
48#define PF_MBX_ATQH_ATQH_M ICE_M(0x3FF, 0)
49#define PF_MBX_ATQLEN 0x0022E200
50#define PF_MBX_ATQLEN_ATQLEN_M ICE_M(0x3FF, 0)
51#define PF_MBX_ATQLEN_ATQCRIT_M BIT(30)
52#define PF_MBX_ATQLEN_ATQENABLE_M BIT(31)
53#define PF_MBX_ATQT 0x0022E300
54#define PRTDCB_GENC 0x00083000
55#define PRTDCB_GENC_PFCLDA_S 16
56#define PRTDCB_GENC_PFCLDA_M ICE_M(0xFFFF, 16)
57#define PRTDCB_GENS 0x00083020
58#define PRTDCB_GENS_DCBX_STATUS_S 0
59#define PRTDCB_GENS_DCBX_STATUS_M ICE_M(0x7, 0)
60#define PRTDCB_TUP2TC 0x001D26C0
61#define GL_PREEXT_L2_PMASK0(_i) (0x0020F0FC + ((_i) * 4))
62#define GL_PREEXT_L2_PMASK1(_i) (0x0020F108 + ((_i) * 4))
63#define GLFLXP_RXDID_FLX_WRD_0(_i) (0x0045c800 + ((_i) * 4))
64#define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_S 0
65#define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_M ICE_M(0xFF, 0)
66#define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_S 30
67#define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_M ICE_M(0x3, 30)
68#define GLFLXP_RXDID_FLX_WRD_1(_i) (0x0045c900 + ((_i) * 4))
69#define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_S 0
70#define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_M ICE_M(0xFF, 0)
71#define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_S 30
72#define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_M ICE_M(0x3, 30)
73#define GLFLXP_RXDID_FLX_WRD_2(_i) (0x0045ca00 + ((_i) * 4))
74#define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_S 0
75#define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_M ICE_M(0xFF, 0)
76#define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_S 30
77#define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_M ICE_M(0x3, 30)
78#define GLFLXP_RXDID_FLX_WRD_3(_i) (0x0045cb00 + ((_i) * 4))
79#define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_S 0
80#define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_M ICE_M(0xFF, 0)
81#define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_S 30
82#define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_M ICE_M(0x3, 30)
83#define QRXFLXP_CNTXT(_QRX) (0x00480000 + ((_QRX) * 4))
84#define QRXFLXP_CNTXT_RXDID_IDX_S 0
85#define QRXFLXP_CNTXT_RXDID_IDX_M ICE_M(0x3F, 0)
86#define QRXFLXP_CNTXT_RXDID_PRIO_S 8
87#define QRXFLXP_CNTXT_RXDID_PRIO_M ICE_M(0x7, 8)
88#define QRXFLXP_CNTXT_TS_M BIT(11)
89#define GLGEN_RSTAT 0x000B8188
90#define GLGEN_RSTAT_DEVSTATE_M ICE_M(0x3, 0)
91#define GLGEN_RSTCTL 0x000B8180
92#define GLGEN_RSTCTL_GRSTDEL_S 0
93#define GLGEN_RSTCTL_GRSTDEL_M ICE_M(0x3F, GLGEN_RSTCTL_GRSTDEL_S)
94#define GLGEN_RSTAT_RESET_TYPE_S 2
95#define GLGEN_RSTAT_RESET_TYPE_M ICE_M(0x3, 2)
96#define GLGEN_RTRIG 0x000B8190
97#define GLGEN_RTRIG_CORER_M BIT(0)
98#define GLGEN_RTRIG_GLOBR_M BIT(1)
99#define GLGEN_STAT 0x000B612C
100#define GLGEN_VFLRSTAT(_i) (0x00093A04 + ((_i) * 4))
101#define PFGEN_CTRL 0x00091000
102#define PFGEN_CTRL_PFSWR_M BIT(0)
103#define PFGEN_STATE 0x00088000
104#define PRTGEN_STATUS 0x000B8100
105#define VFGEN_RSTAT(_VF) (0x00074000 + ((_VF) * 4))
106#define VPGEN_VFRSTAT(_VF) (0x00090800 + ((_VF) * 4))
107#define VPGEN_VFRSTAT_VFRD_M BIT(0)
108#define VPGEN_VFRTRIG(_VF) (0x00090000 + ((_VF) * 4))
109#define VPGEN_VFRTRIG_VFSWR_M BIT(0)
110#define PFHMC_ERRORDATA 0x00520500
111#define PFHMC_ERRORINFO 0x00520400
112#define GLINT_CTL 0x0016CC54
113#define GLINT_CTL_DIS_AUTOMASK_M BIT(0)
114#define GLINT_CTL_ITR_GRAN_200_S 16
115#define GLINT_CTL_ITR_GRAN_200_M ICE_M(0xF, 16)
116#define GLINT_CTL_ITR_GRAN_100_S 20
117#define GLINT_CTL_ITR_GRAN_100_M ICE_M(0xF, 20)
118#define GLINT_CTL_ITR_GRAN_50_S 24
119#define GLINT_CTL_ITR_GRAN_50_M ICE_M(0xF, 24)
120#define GLINT_CTL_ITR_GRAN_25_S 28
121#define GLINT_CTL_ITR_GRAN_25_M ICE_M(0xF, 28)
122#define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4))
123#define GLINT_DYN_CTL_INTENA_M BIT(0)
124#define GLINT_DYN_CTL_CLEARPBA_M BIT(1)
125#define GLINT_DYN_CTL_SWINT_TRIG_M BIT(2)
126#define GLINT_DYN_CTL_ITR_INDX_S 3
127#define GLINT_DYN_CTL_ITR_INDX_M ICE_M(0x3, 3)
128#define GLINT_DYN_CTL_INTERVAL_S 5
129#define GLINT_DYN_CTL_INTERVAL_M ICE_M(0xFFF, 5)
130#define GLINT_DYN_CTL_SW_ITR_INDX_M ICE_M(0x3, 25)
131#define GLINT_DYN_CTL_WB_ON_ITR_M BIT(30)
132#define GLINT_DYN_CTL_INTENA_MSK_M BIT(31)
133#define GLINT_ITR(_i, _INT) (0x00154000 + ((_i) * 8192 + (_INT) * 4))
134#define GLINT_RATE(_INT) (0x0015A000 + ((_INT) * 4))
135#define GLINT_RATE_INTRL_ENA_M BIT(6)
136#define GLINT_VECT2FUNC(_INT) (0x00162000 + ((_INT) * 4))
137#define GLINT_VECT2FUNC_VF_NUM_S 0
138#define GLINT_VECT2FUNC_VF_NUM_M ICE_M(0xFF, 0)
139#define GLINT_VECT2FUNC_PF_NUM_S 12
140#define GLINT_VECT2FUNC_PF_NUM_M ICE_M(0x7, 12)
141#define GLINT_VECT2FUNC_IS_PF_S 16
142#define GLINT_VECT2FUNC_IS_PF_M BIT(16)
143#define PFINT_FW_CTL 0x0016C800
144#define PFINT_FW_CTL_MSIX_INDX_M ICE_M(0x7FF, 0)
145#define PFINT_FW_CTL_ITR_INDX_S 11
146#define PFINT_FW_CTL_ITR_INDX_M ICE_M(0x3, 11)
147#define PFINT_FW_CTL_CAUSE_ENA_M BIT(30)
148#define PFINT_MBX_CTL 0x0016B280
149#define PFINT_MBX_CTL_MSIX_INDX_M ICE_M(0x7FF, 0)
150#define PFINT_MBX_CTL_ITR_INDX_S 11
151#define PFINT_MBX_CTL_ITR_INDX_M ICE_M(0x3, 11)
152#define PFINT_MBX_CTL_CAUSE_ENA_M BIT(30)
153#define PFINT_OICR 0x0016CA00
154#define PFINT_OICR_ECC_ERR_M BIT(16)
155#define PFINT_OICR_MAL_DETECT_M BIT(19)
156#define PFINT_OICR_GRST_M BIT(20)
157#define PFINT_OICR_PCI_EXCEPTION_M BIT(21)
158#define PFINT_OICR_HMC_ERR_M BIT(26)
159#define PFINT_OICR_PE_CRITERR_M BIT(28)
160#define PFINT_OICR_VFLR_M BIT(29)
161#define PFINT_OICR_SWINT_M BIT(31)
162#define PFINT_OICR_CTL 0x0016CA80
163#define PFINT_OICR_CTL_MSIX_INDX_M ICE_M(0x7FF, 0)
164#define PFINT_OICR_CTL_ITR_INDX_S 11
165#define PFINT_OICR_CTL_ITR_INDX_M ICE_M(0x3, 11)
166#define PFINT_OICR_CTL_CAUSE_ENA_M BIT(30)
167#define PFINT_OICR_ENA 0x0016C900
168#define QINT_RQCTL(_QRX) (0x00150000 + ((_QRX) * 4))
169#define QINT_RQCTL_MSIX_INDX_S 0
170#define QINT_RQCTL_MSIX_INDX_M ICE_M(0x7FF, 0)
171#define QINT_RQCTL_ITR_INDX_S 11
172#define QINT_RQCTL_ITR_INDX_M ICE_M(0x3, 11)
173#define QINT_RQCTL_CAUSE_ENA_M BIT(30)
174#define QINT_TQCTL(_DBQM) (0x00140000 + ((_DBQM) * 4))
175#define QINT_TQCTL_MSIX_INDX_S 0
176#define QINT_TQCTL_MSIX_INDX_M ICE_M(0x7FF, 0)
177#define QINT_TQCTL_ITR_INDX_S 11
178#define QINT_TQCTL_ITR_INDX_M ICE_M(0x3, 11)
179#define QINT_TQCTL_CAUSE_ENA_M BIT(30)
180#define VPINT_ALLOC(_VF) (0x001D1000 + ((_VF) * 4))
181#define VPINT_ALLOC_FIRST_S 0
182#define VPINT_ALLOC_FIRST_M ICE_M(0x7FF, 0)
183#define VPINT_ALLOC_LAST_S 12
184#define VPINT_ALLOC_LAST_M ICE_M(0x7FF, 12)
185#define VPINT_ALLOC_VALID_M BIT(31)
186#define VPINT_ALLOC_PCI(_VF) (0x0009D000 + ((_VF) * 4))
187#define VPINT_ALLOC_PCI_FIRST_S 0
188#define VPINT_ALLOC_PCI_FIRST_M ICE_M(0x7FF, 0)
189#define VPINT_ALLOC_PCI_LAST_S 12
190#define VPINT_ALLOC_PCI_LAST_M ICE_M(0x7FF, 12)
191#define VPINT_ALLOC_PCI_VALID_M BIT(31)
192#define VPINT_MBX_CTL(_VSI) (0x0016A000 + ((_VSI) * 4))
193#define VPINT_MBX_CTL_CAUSE_ENA_M BIT(30)
194#define GLLAN_RCTL_0 0x002941F8
195#define QRX_CONTEXT(_i, _QRX) (0x00280000 + ((_i) * 8192 + (_QRX) * 4))
196#define QRX_CTRL(_QRX) (0x00120000 + ((_QRX) * 4))
197#define QRX_CTRL_MAX_INDEX 2047
198#define QRX_CTRL_QENA_REQ_S 0
199#define QRX_CTRL_QENA_REQ_M BIT(0)
200#define QRX_CTRL_QENA_STAT_S 2
201#define QRX_CTRL_QENA_STAT_M BIT(2)
202#define QRX_ITR(_QRX) (0x00292000 + ((_QRX) * 4))
203#define QRX_TAIL(_QRX) (0x00290000 + ((_QRX) * 4))
204#define QRX_TAIL_MAX_INDEX 2047
205#define QRX_TAIL_TAIL_S 0
206#define QRX_TAIL_TAIL_M ICE_M(0x1FFF, 0)
207#define VPLAN_RX_QBASE(_VF) (0x00072000 + ((_VF) * 4))
208#define VPLAN_RX_QBASE_VFFIRSTQ_S 0
209#define VPLAN_RX_QBASE_VFFIRSTQ_M ICE_M(0x7FF, 0)
210#define VPLAN_RX_QBASE_VFNUMQ_S 16
211#define VPLAN_RX_QBASE_VFNUMQ_M ICE_M(0xFF, 16)
212#define VPLAN_RXQ_MAPENA(_VF) (0x00073000 + ((_VF) * 4))
213#define VPLAN_RXQ_MAPENA_RX_ENA_M BIT(0)
214#define VPLAN_TX_QBASE(_VF) (0x001D1800 + ((_VF) * 4))
215#define VPLAN_TX_QBASE_VFFIRSTQ_S 0
216#define VPLAN_TX_QBASE_VFFIRSTQ_M ICE_M(0x3FFF, 0)
217#define VPLAN_TX_QBASE_VFNUMQ_S 16
218#define VPLAN_TX_QBASE_VFNUMQ_M ICE_M(0xFF, 16)
219#define VPLAN_TXQ_MAPENA(_VF) (0x00073800 + ((_VF) * 4))
220#define VPLAN_TXQ_MAPENA_TX_ENA_M BIT(0)
221#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E36E0 + ((_i) * 32))
222#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8
223#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M ICE_M(0xFFFF, 0)
224#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3800 + ((_i) * 32))
225#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M ICE_M(0xFFFF, 0)
226#define GL_MDCK_TX_TDPU 0x00049348
227#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)
228#define GL_MDET_RX 0x00294C00
229#define GL_MDET_RX_QNUM_S 0
230#define GL_MDET_RX_QNUM_M ICE_M(0x7FFF, 0)
231#define GL_MDET_RX_VF_NUM_S 15
232#define GL_MDET_RX_VF_NUM_M ICE_M(0xFF, 15)
233#define GL_MDET_RX_PF_NUM_S 23
234#define GL_MDET_RX_PF_NUM_M ICE_M(0x7, 23)
235#define GL_MDET_RX_MAL_TYPE_S 26
236#define GL_MDET_RX_MAL_TYPE_M ICE_M(0x1F, 26)
237#define GL_MDET_RX_VALID_M BIT(31)
238#define GL_MDET_TX_PQM 0x002D2E00
239#define GL_MDET_TX_PQM_PF_NUM_S 0
240#define GL_MDET_TX_PQM_PF_NUM_M ICE_M(0x7, 0)
241#define GL_MDET_TX_PQM_VF_NUM_S 4
242#define GL_MDET_TX_PQM_VF_NUM_M ICE_M(0xFF, 4)
243#define GL_MDET_TX_PQM_QNUM_S 12
244#define GL_MDET_TX_PQM_QNUM_M ICE_M(0x3FFF, 12)
245#define GL_MDET_TX_PQM_MAL_TYPE_S 26
246#define GL_MDET_TX_PQM_MAL_TYPE_M ICE_M(0x1F, 26)
247#define GL_MDET_TX_PQM_VALID_M BIT(31)
248#define GL_MDET_TX_TCLAN 0x000FC068
249#define GL_MDET_TX_TCLAN_QNUM_S 0
250#define GL_MDET_TX_TCLAN_QNUM_M ICE_M(0x7FFF, 0)
251#define GL_MDET_TX_TCLAN_VF_NUM_S 15
252#define GL_MDET_TX_TCLAN_VF_NUM_M ICE_M(0xFF, 15)
253#define GL_MDET_TX_TCLAN_PF_NUM_S 23
254#define GL_MDET_TX_TCLAN_PF_NUM_M ICE_M(0x7, 23)
255#define GL_MDET_TX_TCLAN_MAL_TYPE_S 26
256#define GL_MDET_TX_TCLAN_MAL_TYPE_M ICE_M(0x1F, 26)
257#define GL_MDET_TX_TCLAN_VALID_M BIT(31)
258#define PF_MDET_RX 0x00294280
259#define PF_MDET_RX_VALID_M BIT(0)
260#define PF_MDET_TX_PQM 0x002D2C80
261#define PF_MDET_TX_PQM_VALID_M BIT(0)
262#define PF_MDET_TX_TCLAN 0x000FC000
263#define PF_MDET_TX_TCLAN_VALID_M BIT(0)
264#define VP_MDET_RX(_VF) (0x00294400 + ((_VF) * 4))
265#define VP_MDET_RX_VALID_M BIT(0)
266#define VP_MDET_TX_PQM(_VF) (0x002D2000 + ((_VF) * 4))
267#define VP_MDET_TX_PQM_VALID_M BIT(0)
268#define VP_MDET_TX_TCLAN(_VF) (0x000FB800 + ((_VF) * 4))
269#define VP_MDET_TX_TCLAN_VALID_M BIT(0)
270#define VP_MDET_TX_TDPU(_VF) (0x00040000 + ((_VF) * 4))
271#define VP_MDET_TX_TDPU_VALID_M BIT(0)
272#define GLNVM_FLA 0x000B6108
273#define GLNVM_FLA_LOCKED_M BIT(6)
274#define GLNVM_GENS 0x000B6100
275#define GLNVM_GENS_SR_SIZE_S 5
276#define GLNVM_GENS_SR_SIZE_M ICE_M(0x7, 5)
277#define GLNVM_ULD 0x000B6008
278#define GLNVM_ULD_PCIER_DONE_M BIT(0)
279#define GLNVM_ULD_PCIER_DONE_1_M BIT(1)
280#define GLNVM_ULD_CORER_DONE_M BIT(3)
281#define GLNVM_ULD_GLOBR_DONE_M BIT(4)
282#define GLNVM_ULD_POR_DONE_M BIT(5)
283#define GLNVM_ULD_POR_DONE_1_M BIT(8)
284#define GLNVM_ULD_PCIER_DONE_2_M BIT(9)
285#define GLNVM_ULD_PE_DONE_M BIT(10)
286#define GLPCI_CNF2 0x000BE004
287#define GLPCI_CNF2_CACHELINE_SIZE_M BIT(1)
288#define PF_FUNC_RID 0x0009E880
289#define PF_FUNC_RID_FUNC_NUM_S 0
290#define PF_FUNC_RID_FUNC_NUM_M ICE_M(0x7, 0)
291#define PF_PCI_CIAA 0x0009E580
292#define PF_PCI_CIAA_VF_NUM_S 12
293#define PF_PCI_CIAD 0x0009E500
294#define GL_PWR_MODE_CTL 0x000B820C
295#define GL_PWR_MODE_CTL_CAR_MAX_BW_S 30
296#define GL_PWR_MODE_CTL_CAR_MAX_BW_M ICE_M(0x3, 30)
297#define GLQF_FD_CNT 0x00460018
298#define GLQF_FD_CNT_FD_BCNT_S 16
299#define GLQF_FD_CNT_FD_BCNT_M ICE_M(0x7FFF, 16)
300#define GLQF_FD_SIZE 0x00460010
301#define GLQF_FD_SIZE_FD_GSIZE_S 0
302#define GLQF_FD_SIZE_FD_GSIZE_M ICE_M(0x7FFF, 0)
303#define GLQF_FD_SIZE_FD_BSIZE_S 16
304#define GLQF_FD_SIZE_FD_BSIZE_M ICE_M(0x7FFF, 16)
305#define GLQF_FDINSET(_i, _j) (0x00412000 + ((_i) * 4 + (_j) * 512))
306#define GLQF_FDMASK_SEL(_i) (0x00410400 + ((_i) * 4))
307#define GLQF_FDSWAP(_i, _j) (0x00413000 + ((_i) * 4 + (_j) * 512))
308#define PFQF_FD_ENA 0x0043A000
309#define PFQF_FD_ENA_FD_ENA_M BIT(0)
310#define PFQF_FD_SIZE 0x00460100
311#define GLDCB_RTCTQ_RXQNUM_S 0
312#define GLDCB_RTCTQ_RXQNUM_M ICE_M(0x7FF, 0)
313#define GLPRT_BPRCL(_i) (0x00381380 + ((_i) * 8))
314#define GLPRT_BPTCL(_i) (0x00381240 + ((_i) * 8))
315#define GLPRT_CRCERRS(_i) (0x00380100 + ((_i) * 8))
316#define GLPRT_GORCL(_i) (0x00380000 + ((_i) * 8))
317#define GLPRT_GOTCL(_i) (0x00380B40 + ((_i) * 8))
318#define GLPRT_ILLERRC(_i) (0x003801C0 + ((_i) * 8))
319#define GLPRT_LXOFFRXC(_i) (0x003802C0 + ((_i) * 8))
320#define GLPRT_LXOFFTXC(_i) (0x00381180 + ((_i) * 8))
321#define GLPRT_LXONRXC(_i) (0x00380280 + ((_i) * 8))
322#define GLPRT_LXONTXC(_i) (0x00381140 + ((_i) * 8))
323#define GLPRT_MLFC(_i) (0x00380040 + ((_i) * 8))
324#define GLPRT_MPRCL(_i) (0x00381340 + ((_i) * 8))
325#define GLPRT_MPTCL(_i) (0x00381200 + ((_i) * 8))
326#define GLPRT_MRFC(_i) (0x00380080 + ((_i) * 8))
327#define GLPRT_PRC1023L(_i) (0x00380A00 + ((_i) * 8))
328#define GLPRT_PRC127L(_i) (0x00380940 + ((_i) * 8))
329#define GLPRT_PRC1522L(_i) (0x00380A40 + ((_i) * 8))
330#define GLPRT_PRC255L(_i) (0x00380980 + ((_i) * 8))
331#define GLPRT_PRC511L(_i) (0x003809C0 + ((_i) * 8))
332#define GLPRT_PRC64L(_i) (0x00380900 + ((_i) * 8))
333#define GLPRT_PRC9522L(_i) (0x00380A80 + ((_i) * 8))
334#define GLPRT_PTC1023L(_i) (0x00380C80 + ((_i) * 8))
335#define GLPRT_PTC127L(_i) (0x00380BC0 + ((_i) * 8))
336#define GLPRT_PTC1522L(_i) (0x00380CC0 + ((_i) * 8))
337#define GLPRT_PTC255L(_i) (0x00380C00 + ((_i) * 8))
338#define GLPRT_PTC511L(_i) (0x00380C40 + ((_i) * 8))
339#define GLPRT_PTC64L(_i) (0x00380B80 + ((_i) * 8))
340#define GLPRT_PTC9522L(_i) (0x00380D00 + ((_i) * 8))
341#define GLPRT_PXOFFRXC(_i, _j) (0x00380500 + ((_i) * 8 + (_j) * 64))
342#define GLPRT_PXOFFTXC(_i, _j) (0x00380F40 + ((_i) * 8 + (_j) * 64))
343#define GLPRT_PXONRXC(_i, _j) (0x00380300 + ((_i) * 8 + (_j) * 64))
344#define GLPRT_PXONTXC(_i, _j) (0x00380D40 + ((_i) * 8 + (_j) * 64))
345#define GLPRT_RFC(_i) (0x00380AC0 + ((_i) * 8))
346#define GLPRT_RJC(_i) (0x00380B00 + ((_i) * 8))
347#define GLPRT_RLEC(_i) (0x00380140 + ((_i) * 8))
348#define GLPRT_ROC(_i) (0x00380240 + ((_i) * 8))
349#define GLPRT_RUC(_i) (0x00380200 + ((_i) * 8))
350#define GLPRT_RXON2OFFCNT(_i, _j) (0x00380700 + ((_i) * 8 + (_j) * 64))
351#define GLPRT_TDOLD(_i) (0x00381280 + ((_i) * 8))
352#define GLPRT_UPRCL(_i) (0x00381300 + ((_i) * 8))
353#define GLPRT_UPTCL(_i) (0x003811C0 + ((_i) * 8))
354#define GLSTAT_FD_CNT0L(_i) (0x003A0000 + ((_i) * 8))
355#define GLV_BPRCL(_i) (0x003B6000 + ((_i) * 8))
356#define GLV_BPTCL(_i) (0x0030E000 + ((_i) * 8))
357#define GLV_GORCL(_i) (0x003B0000 + ((_i) * 8))
358#define GLV_GOTCL(_i) (0x00300000 + ((_i) * 8))
359#define GLV_MPRCL(_i) (0x003B4000 + ((_i) * 8))
360#define GLV_MPTCL(_i) (0x0030C000 + ((_i) * 8))
361#define GLV_RDPC(_i) (0x00294C04 + ((_i) * 4))
362#define GLV_TEPC(_VSI) (0x00312000 + ((_VSI) * 4))
363#define GLV_UPRCL(_i) (0x003B2000 + ((_i) * 8))
364#define GLV_UPTCL(_i) (0x0030A000 + ((_i) * 8))
365#define PRTRPB_RDPC 0x000AC260
366#define VSIQF_FD_CNT(_VSI) (0x00464000 + ((_VSI) * 4))
367#define VSIQF_FD_CNT_FD_GCNT_S 0
368#define VSIQF_FD_CNT_FD_GCNT_M ICE_M(0x3FFF, 0)
369#define VSIQF_HKEY_MAX_INDEX 12
370#define VSIQF_HLUT_MAX_INDEX 15
371#define PFPM_APM 0x000B8080
372#define PFPM_APM_APME_M BIT(0)
373#define PFPM_WUFC 0x0009DC00
374#define PFPM_WUFC_MAG_M BIT(1)
375#define PFPM_WUS 0x0009DB80
376#define PFPM_WUS_LNKC_M BIT(0)
377#define PFPM_WUS_MAG_M BIT(1)
378#define PFPM_WUS_MNG_M BIT(3)
379#define PFPM_WUS_FW_RST_WK_M BIT(31)
380#define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4))
381#define VFINT_DYN_CTLN_CLEARPBA_M BIT(1)
382
383#endif /* _ICE_HW_AUTOGEN_H_ */