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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _BGMAC_H
3#define _BGMAC_H
4
5#include <linux/netdevice.h>
6
7#define BGMAC_DEV_CTL 0x000
8#define BGMAC_DC_TSM 0x00000002
9#define BGMAC_DC_CFCO 0x00000004
10#define BGMAC_DC_RLSS 0x00000008
11#define BGMAC_DC_MROR 0x00000010
12#define BGMAC_DC_FCM_MASK 0x00000060
13#define BGMAC_DC_FCM_SHIFT 5
14#define BGMAC_DC_NAE 0x00000080
15#define BGMAC_DC_TF 0x00000100
16#define BGMAC_DC_RDS_MASK 0x00030000
17#define BGMAC_DC_RDS_SHIFT 16
18#define BGMAC_DC_TDS_MASK 0x000c0000
19#define BGMAC_DC_TDS_SHIFT 18
20#define BGMAC_DEV_STATUS 0x004 /* Configuration of the interface */
21#define BGMAC_DS_RBF 0x00000001
22#define BGMAC_DS_RDF 0x00000002
23#define BGMAC_DS_RIF 0x00000004
24#define BGMAC_DS_TBF 0x00000008
25#define BGMAC_DS_TDF 0x00000010
26#define BGMAC_DS_TIF 0x00000020
27#define BGMAC_DS_PO 0x00000040
28#define BGMAC_DS_MM_MASK 0x00000300 /* Mode of the interface */
29#define BGMAC_DS_MM_SHIFT 8
30#define BGMAC_BIST_STATUS 0x00c
31#define BGMAC_INT_STATUS 0x020 /* Interrupt status */
32#define BGMAC_IS_MRO 0x00000001
33#define BGMAC_IS_MTO 0x00000002
34#define BGMAC_IS_TFD 0x00000004
35#define BGMAC_IS_LS 0x00000008
36#define BGMAC_IS_MDIO 0x00000010
37#define BGMAC_IS_MR 0x00000020
38#define BGMAC_IS_MT 0x00000040
39#define BGMAC_IS_TO 0x00000080
40#define BGMAC_IS_DESC_ERR 0x00000400 /* Descriptor error */
41#define BGMAC_IS_DATA_ERR 0x00000800 /* Data error */
42#define BGMAC_IS_DESC_PROT_ERR 0x00001000 /* Descriptor protocol error */
43#define BGMAC_IS_RX_DESC_UNDERF 0x00002000 /* Receive descriptor underflow */
44#define BGMAC_IS_RX_F_OVERF 0x00004000 /* Receive FIFO overflow */
45#define BGMAC_IS_TX_F_UNDERF 0x00008000 /* Transmit FIFO underflow */
46#define BGMAC_IS_RX 0x00010000 /* Interrupt for RX queue 0 */
47#define BGMAC_IS_TX0 0x01000000 /* Interrupt for TX queue 0 */
48#define BGMAC_IS_TX1 0x02000000 /* Interrupt for TX queue 1 */
49#define BGMAC_IS_TX2 0x04000000 /* Interrupt for TX queue 2 */
50#define BGMAC_IS_TX3 0x08000000 /* Interrupt for TX queue 3 */
51#define BGMAC_IS_TX_MASK 0x0f000000
52#define BGMAC_IS_INTMASK 0x0f01fcff
53#define BGMAC_IS_ERRMASK 0x0000fc00
54#define BGMAC_INT_MASK 0x024 /* Interrupt mask */
55#define BGMAC_GP_TIMER 0x028
56#define BGMAC_INT_RECV_LAZY 0x100
57#define BGMAC_IRL_TO_MASK 0x00ffffff
58#define BGMAC_IRL_FC_MASK 0xff000000
59#define BGMAC_IRL_FC_SHIFT 24 /* Shift the number of interrupts triggered per received frame */
60#define BGMAC_FLOW_CTL_THRESH 0x104 /* Flow control thresholds */
61#define BGMAC_WRRTHRESH 0x108
62#define BGMAC_GMAC_IDLE_CNT_THRESH 0x10c
63#define BGMAC_PHY_ACCESS 0x180 /* PHY access address */
64#define BGMAC_PA_DATA_MASK 0x0000ffff
65#define BGMAC_PA_ADDR_MASK 0x001f0000
66#define BGMAC_PA_ADDR_SHIFT 16
67#define BGMAC_PA_REG_MASK 0x1f000000
68#define BGMAC_PA_REG_SHIFT 24
69#define BGMAC_PA_WRITE 0x20000000
70#define BGMAC_PA_START 0x40000000
71#define BGMAC_PHY_CNTL 0x188 /* PHY control address */
72#define BGMAC_PC_EPA_MASK 0x0000001f
73#define BGMAC_PC_MCT_MASK 0x007f0000
74#define BGMAC_PC_MCT_SHIFT 16
75#define BGMAC_PC_MTE 0x00800000
76#define BGMAC_TXQ_CTL 0x18c
77#define BGMAC_TXQ_CTL_DBT_MASK 0x00000fff
78#define BGMAC_TXQ_CTL_DBT_SHIFT 0
79#define BGMAC_RXQ_CTL 0x190
80#define BGMAC_RXQ_CTL_DBT_MASK 0x00000fff
81#define BGMAC_RXQ_CTL_DBT_SHIFT 0
82#define BGMAC_RXQ_CTL_PTE 0x00001000
83#define BGMAC_RXQ_CTL_MDP_MASK 0x3f000000
84#define BGMAC_RXQ_CTL_MDP_SHIFT 24
85#define BGMAC_GPIO_SELECT 0x194
86#define BGMAC_GPIO_OUTPUT_EN 0x198
87
88/* For 0x1e0 see BCMA_CLKCTLST. Below are BGMAC specific bits */
89#define BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ 0x00000100
90#define BGMAC_BCMA_CLKCTLST_MISC_PLL_ST 0x01000000
91
92#define BGMAC_HW_WAR 0x1e4
93#define BGMAC_PWR_CTL 0x1e8
94#define BGMAC_DMA_BASE0 0x200 /* Tx and Rx controller */
95#define BGMAC_DMA_BASE1 0x240 /* Tx controller only */
96#define BGMAC_DMA_BASE2 0x280 /* Tx controller only */
97#define BGMAC_DMA_BASE3 0x2C0 /* Tx controller only */
98#define BGMAC_TX_GOOD_OCTETS 0x300
99#define BGMAC_TX_GOOD_OCTETS_HIGH 0x304
100#define BGMAC_TX_GOOD_PKTS 0x308
101#define BGMAC_TX_OCTETS 0x30c
102#define BGMAC_TX_OCTETS_HIGH 0x310
103#define BGMAC_TX_PKTS 0x314
104#define BGMAC_TX_BROADCAST_PKTS 0x318
105#define BGMAC_TX_MULTICAST_PKTS 0x31c
106#define BGMAC_TX_LEN_64 0x320
107#define BGMAC_TX_LEN_65_TO_127 0x324
108#define BGMAC_TX_LEN_128_TO_255 0x328
109#define BGMAC_TX_LEN_256_TO_511 0x32c
110#define BGMAC_TX_LEN_512_TO_1023 0x330
111#define BGMAC_TX_LEN_1024_TO_1522 0x334
112#define BGMAC_TX_LEN_1523_TO_2047 0x338
113#define BGMAC_TX_LEN_2048_TO_4095 0x33c
114#define BGMAC_TX_LEN_4096_TO_8191 0x340
115#define BGMAC_TX_LEN_8192_TO_MAX 0x344
116#define BGMAC_TX_JABBER_PKTS 0x348 /* Error */
117#define BGMAC_TX_OVERSIZE_PKTS 0x34c /* Error */
118#define BGMAC_TX_FRAGMENT_PKTS 0x350
119#define BGMAC_TX_UNDERRUNS 0x354 /* Error */
120#define BGMAC_TX_TOTAL_COLS 0x358
121#define BGMAC_TX_SINGLE_COLS 0x35c
122#define BGMAC_TX_MULTIPLE_COLS 0x360
123#define BGMAC_TX_EXCESSIVE_COLS 0x364 /* Error */
124#define BGMAC_TX_LATE_COLS 0x368 /* Error */
125#define BGMAC_TX_DEFERED 0x36c
126#define BGMAC_TX_CARRIER_LOST 0x370
127#define BGMAC_TX_PAUSE_PKTS 0x374
128#define BGMAC_TX_UNI_PKTS 0x378
129#define BGMAC_TX_Q0_PKTS 0x37c
130#define BGMAC_TX_Q0_OCTETS 0x380
131#define BGMAC_TX_Q0_OCTETS_HIGH 0x384
132#define BGMAC_TX_Q1_PKTS 0x388
133#define BGMAC_TX_Q1_OCTETS 0x38c
134#define BGMAC_TX_Q1_OCTETS_HIGH 0x390
135#define BGMAC_TX_Q2_PKTS 0x394
136#define BGMAC_TX_Q2_OCTETS 0x398
137#define BGMAC_TX_Q2_OCTETS_HIGH 0x39c
138#define BGMAC_TX_Q3_PKTS 0x3a0
139#define BGMAC_TX_Q3_OCTETS 0x3a4
140#define BGMAC_TX_Q3_OCTETS_HIGH 0x3a8
141#define BGMAC_RX_GOOD_OCTETS 0x3b0
142#define BGMAC_RX_GOOD_OCTETS_HIGH 0x3b4
143#define BGMAC_RX_GOOD_PKTS 0x3b8
144#define BGMAC_RX_OCTETS 0x3bc
145#define BGMAC_RX_OCTETS_HIGH 0x3c0
146#define BGMAC_RX_PKTS 0x3c4
147#define BGMAC_RX_BROADCAST_PKTS 0x3c8
148#define BGMAC_RX_MULTICAST_PKTS 0x3cc
149#define BGMAC_RX_LEN_64 0x3d0
150#define BGMAC_RX_LEN_65_TO_127 0x3d4
151#define BGMAC_RX_LEN_128_TO_255 0x3d8
152#define BGMAC_RX_LEN_256_TO_511 0x3dc
153#define BGMAC_RX_LEN_512_TO_1023 0x3e0
154#define BGMAC_RX_LEN_1024_TO_1522 0x3e4
155#define BGMAC_RX_LEN_1523_TO_2047 0x3e8
156#define BGMAC_RX_LEN_2048_TO_4095 0x3ec
157#define BGMAC_RX_LEN_4096_TO_8191 0x3f0
158#define BGMAC_RX_LEN_8192_TO_MAX 0x3f4
159#define BGMAC_RX_JABBER_PKTS 0x3f8 /* Error */
160#define BGMAC_RX_OVERSIZE_PKTS 0x3fc /* Error */
161#define BGMAC_RX_FRAGMENT_PKTS 0x400
162#define BGMAC_RX_MISSED_PKTS 0x404 /* Error */
163#define BGMAC_RX_CRC_ALIGN_ERRS 0x408 /* Error */
164#define BGMAC_RX_UNDERSIZE 0x40c /* Error */
165#define BGMAC_RX_CRC_ERRS 0x410 /* Error */
166#define BGMAC_RX_ALIGN_ERRS 0x414 /* Error */
167#define BGMAC_RX_SYMBOL_ERRS 0x418 /* Error */
168#define BGMAC_RX_PAUSE_PKTS 0x41c
169#define BGMAC_RX_NONPAUSE_PKTS 0x420
170#define BGMAC_RX_SACHANGES 0x424
171#define BGMAC_RX_UNI_PKTS 0x428
172#define BGMAC_UNIMAC_VERSION 0x800
173#define BGMAC_HDBKP_CTL 0x804
174#define BGMAC_CMDCFG 0x808 /* Configuration */
175#define BGMAC_CMDCFG_TE 0x00000001 /* Set to activate TX */
176#define BGMAC_CMDCFG_RE 0x00000002 /* Set to activate RX */
177#define BGMAC_CMDCFG_ES_MASK 0x0000000c /* Ethernet speed see gmac_speed */
178#define BGMAC_CMDCFG_ES_10 0x00000000
179#define BGMAC_CMDCFG_ES_100 0x00000004
180#define BGMAC_CMDCFG_ES_1000 0x00000008
181#define BGMAC_CMDCFG_ES_2500 0x0000000C
182#define BGMAC_CMDCFG_PROM 0x00000010 /* Set to activate promiscuous mode */
183#define BGMAC_CMDCFG_PAD_EN 0x00000020
184#define BGMAC_CMDCFG_CF 0x00000040
185#define BGMAC_CMDCFG_PF 0x00000080
186#define BGMAC_CMDCFG_RPI 0x00000100 /* Unset to enable 802.3x tx flow control */
187#define BGMAC_CMDCFG_TAI 0x00000200
188#define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */
189#define BGMAC_CMDCFG_HD_SHIFT 10
190#define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for core rev 0-3 */
191#define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, for core rev >= 4 */
192#define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */
193#define BGMAC_CMDCFG_AE 0x00400000
194#define BGMAC_CMDCFG_CFE 0x00800000
195#define BGMAC_CMDCFG_NLC 0x01000000
196#define BGMAC_CMDCFG_RL 0x02000000
197#define BGMAC_CMDCFG_RED 0x04000000
198#define BGMAC_CMDCFG_PE 0x08000000
199#define BGMAC_CMDCFG_TPI 0x10000000
200#define BGMAC_CMDCFG_AT 0x20000000
201#define BGMAC_MACADDR_HIGH 0x80c /* High 4 octets of own mac address */
202#define BGMAC_MACADDR_LOW 0x810 /* Low 2 octets of own mac address */
203#define BGMAC_RXMAX_LENGTH 0x814 /* Max receive frame length with vlan tag */
204#define BGMAC_PAUSEQUANTA 0x818
205#define BGMAC_MAC_MODE 0x844
206#define BGMAC_OUTERTAG 0x848
207#define BGMAC_INNERTAG 0x84c
208#define BGMAC_TXIPG 0x85c
209#define BGMAC_PAUSE_CTL 0xb30
210#define BGMAC_TX_FLUSH 0xb34
211#define BGMAC_RX_STATUS 0xb38
212#define BGMAC_TX_STATUS 0xb3c
213
214/* BCMA GMAC core specific IO Control (BCMA_IOCTL) flags */
215#define BGMAC_BCMA_IOCTL_SW_CLKEN 0x00000004 /* PHY Clock Enable */
216#define BGMAC_BCMA_IOCTL_SW_RESET 0x00000008 /* PHY Reset */
217/* The IOCTL values appear to be different in NS, NSP, and NS2, and do not match
218 * the values directly above
219 */
220#define BGMAC_CLK_EN BIT(0)
221#define BGMAC_RESERVED_0 BIT(1)
222#define BGMAC_SOURCE_SYNC_MODE_EN BIT(2)
223#define BGMAC_DEST_SYNC_MODE_EN BIT(3)
224#define BGMAC_TX_CLK_OUT_INVERT_EN BIT(4)
225#define BGMAC_DIRECT_GMII_MODE BIT(5)
226#define BGMAC_CLK_250_SEL BIT(6)
227#define BGMAC_AWCACHE (0xf << 7)
228#define BGMAC_RESERVED_1 (0x1f << 11)
229#define BGMAC_ARCACHE (0xf << 16)
230#define BGMAC_AWUSER (0x3f << 20)
231#define BGMAC_ARUSER (0x3f << 26)
232#define BGMAC_RESERVED BIT(31)
233
234/* BCMA GMAC core specific IO status (BCMA_IOST) flags */
235#define BGMAC_BCMA_IOST_ATTACHED 0x00000800
236
237#define BGMAC_NUM_MIB_TX_REGS \
238 (((BGMAC_TX_Q3_OCTETS_HIGH - BGMAC_TX_GOOD_OCTETS) / 4) + 1)
239#define BGMAC_NUM_MIB_RX_REGS \
240 (((BGMAC_RX_UNI_PKTS - BGMAC_RX_GOOD_OCTETS) / 4) + 1)
241
242#define BGMAC_DMA_TX_CTL 0x00
243#define BGMAC_DMA_TX_ENABLE 0x00000001
244#define BGMAC_DMA_TX_SUSPEND 0x00000002
245#define BGMAC_DMA_TX_LOOPBACK 0x00000004
246#define BGMAC_DMA_TX_FLUSH 0x00000010
247#define BGMAC_DMA_TX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
248#define BGMAC_DMA_TX_MR_SHIFT 6
249#define BGMAC_DMA_TX_MR_1 0
250#define BGMAC_DMA_TX_MR_2 1
251#define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800
252#define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000
253#define BGMAC_DMA_TX_ADDREXT_SHIFT 16
254#define BGMAC_DMA_TX_BL_MASK 0x001C0000 /* BurstLen bits */
255#define BGMAC_DMA_TX_BL_SHIFT 18
256#define BGMAC_DMA_TX_BL_16 0
257#define BGMAC_DMA_TX_BL_32 1
258#define BGMAC_DMA_TX_BL_64 2
259#define BGMAC_DMA_TX_BL_128 3
260#define BGMAC_DMA_TX_BL_256 4
261#define BGMAC_DMA_TX_BL_512 5
262#define BGMAC_DMA_TX_BL_1024 6
263#define BGMAC_DMA_TX_PC_MASK 0x00E00000 /* Prefetch control */
264#define BGMAC_DMA_TX_PC_SHIFT 21
265#define BGMAC_DMA_TX_PC_0 0
266#define BGMAC_DMA_TX_PC_4 1
267#define BGMAC_DMA_TX_PC_8 2
268#define BGMAC_DMA_TX_PC_16 3
269#define BGMAC_DMA_TX_PT_MASK 0x03000000 /* Prefetch threshold */
270#define BGMAC_DMA_TX_PT_SHIFT 24
271#define BGMAC_DMA_TX_PT_1 0
272#define BGMAC_DMA_TX_PT_2 1
273#define BGMAC_DMA_TX_PT_4 2
274#define BGMAC_DMA_TX_PT_8 3
275#define BGMAC_DMA_TX_INDEX 0x04
276#define BGMAC_DMA_TX_RINGLO 0x08
277#define BGMAC_DMA_TX_RINGHI 0x0C
278#define BGMAC_DMA_TX_STATUS 0x10
279#define BGMAC_DMA_TX_STATDPTR 0x00001FFF
280#define BGMAC_DMA_TX_STAT 0xF0000000
281#define BGMAC_DMA_TX_STAT_DISABLED 0x00000000
282#define BGMAC_DMA_TX_STAT_ACTIVE 0x10000000
283#define BGMAC_DMA_TX_STAT_IDLEWAIT 0x20000000
284#define BGMAC_DMA_TX_STAT_STOPPED 0x30000000
285#define BGMAC_DMA_TX_STAT_SUSP 0x40000000
286#define BGMAC_DMA_TX_ERROR 0x14
287#define BGMAC_DMA_TX_ERRDPTR 0x0001FFFF
288#define BGMAC_DMA_TX_ERR 0xF0000000
289#define BGMAC_DMA_TX_ERR_NOERR 0x00000000
290#define BGMAC_DMA_TX_ERR_PROT 0x10000000
291#define BGMAC_DMA_TX_ERR_UNDERRUN 0x20000000
292#define BGMAC_DMA_TX_ERR_TRANSFER 0x30000000
293#define BGMAC_DMA_TX_ERR_DESCREAD 0x40000000
294#define BGMAC_DMA_TX_ERR_CORE 0x50000000
295#define BGMAC_DMA_RX_CTL 0x20
296#define BGMAC_DMA_RX_ENABLE 0x00000001
297#define BGMAC_DMA_RX_FRAME_OFFSET_MASK 0x000000FE
298#define BGMAC_DMA_RX_FRAME_OFFSET_SHIFT 1
299#define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100
300#define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400
301#define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800
302#define BGMAC_DMA_RX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
303#define BGMAC_DMA_RX_MR_SHIFT 6
304#define BGMAC_DMA_TX_MR_1 0
305#define BGMAC_DMA_TX_MR_2 1
306#define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000
307#define BGMAC_DMA_RX_ADDREXT_SHIFT 16
308#define BGMAC_DMA_RX_BL_MASK 0x001C0000 /* BurstLen bits */
309#define BGMAC_DMA_RX_BL_SHIFT 18
310#define BGMAC_DMA_RX_BL_16 0
311#define BGMAC_DMA_RX_BL_32 1
312#define BGMAC_DMA_RX_BL_64 2
313#define BGMAC_DMA_RX_BL_128 3
314#define BGMAC_DMA_RX_BL_256 4
315#define BGMAC_DMA_RX_BL_512 5
316#define BGMAC_DMA_RX_BL_1024 6
317#define BGMAC_DMA_RX_PC_MASK 0x00E00000 /* Prefetch control */
318#define BGMAC_DMA_RX_PC_SHIFT 21
319#define BGMAC_DMA_RX_PC_0 0
320#define BGMAC_DMA_RX_PC_4 1
321#define BGMAC_DMA_RX_PC_8 2
322#define BGMAC_DMA_RX_PC_16 3
323#define BGMAC_DMA_RX_PT_MASK 0x03000000 /* Prefetch threshold */
324#define BGMAC_DMA_RX_PT_SHIFT 24
325#define BGMAC_DMA_RX_PT_1 0
326#define BGMAC_DMA_RX_PT_2 1
327#define BGMAC_DMA_RX_PT_4 2
328#define BGMAC_DMA_RX_PT_8 3
329#define BGMAC_DMA_RX_INDEX 0x24
330#define BGMAC_DMA_RX_RINGLO 0x28
331#define BGMAC_DMA_RX_RINGHI 0x2C
332#define BGMAC_DMA_RX_STATUS 0x30
333#define BGMAC_DMA_RX_STATDPTR 0x00001FFF
334#define BGMAC_DMA_RX_STAT 0xF0000000
335#define BGMAC_DMA_RX_STAT_DISABLED 0x00000000
336#define BGMAC_DMA_RX_STAT_ACTIVE 0x10000000
337#define BGMAC_DMA_RX_STAT_IDLEWAIT 0x20000000
338#define BGMAC_DMA_RX_STAT_STOPPED 0x30000000
339#define BGMAC_DMA_RX_STAT_SUSP 0x40000000
340#define BGMAC_DMA_RX_ERROR 0x34
341#define BGMAC_DMA_RX_ERRDPTR 0x0001FFFF
342#define BGMAC_DMA_RX_ERR 0xF0000000
343#define BGMAC_DMA_RX_ERR_NOERR 0x00000000
344#define BGMAC_DMA_RX_ERR_PROT 0x10000000
345#define BGMAC_DMA_RX_ERR_UNDERRUN 0x20000000
346#define BGMAC_DMA_RX_ERR_TRANSFER 0x30000000
347#define BGMAC_DMA_RX_ERR_DESCREAD 0x40000000
348#define BGMAC_DMA_RX_ERR_CORE 0x50000000
349
350#define BGMAC_DESC_CTL0_EOT 0x10000000 /* End of ring */
351#define BGMAC_DESC_CTL0_IOC 0x20000000 /* IRQ on complete */
352#define BGMAC_DESC_CTL0_EOF 0x40000000 /* End of frame */
353#define BGMAC_DESC_CTL0_SOF 0x80000000 /* Start of frame */
354#define BGMAC_DESC_CTL1_LEN 0x00003FFF
355
356#define BGMAC_PHY_NOREGS BRCM_PSEUDO_PHY_ADDR
357#define BGMAC_PHY_MASK 0x1F
358
359#define BGMAC_MAX_TX_RINGS 4
360#define BGMAC_MAX_RX_RINGS 1
361
362#define BGMAC_TX_RING_SLOTS 128
363#define BGMAC_RX_RING_SLOTS 512
364
365#define BGMAC_RX_HEADER_LEN 28 /* Last 24 bytes are unused. Well... */
366#define BGMAC_RX_FRAME_OFFSET 30 /* There are 2 unused bytes between header and real data */
367#define BGMAC_RX_BUF_OFFSET (NET_SKB_PAD + NET_IP_ALIGN - \
368 BGMAC_RX_FRAME_OFFSET)
369/* Jumbo frame size with FCS */
370#define BGMAC_RX_MAX_FRAME_SIZE 9724
371#define BGMAC_RX_BUF_SIZE (BGMAC_RX_FRAME_OFFSET + BGMAC_RX_MAX_FRAME_SIZE)
372#define BGMAC_RX_ALLOC_SIZE (SKB_DATA_ALIGN(BGMAC_RX_BUF_SIZE + BGMAC_RX_BUF_OFFSET) + \
373 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
374
375#define BGMAC_BFL_ENETROBO 0x0010 /* has ephy roboswitch spi */
376#define BGMAC_BFL_ENETADM 0x0080 /* has ADMtek switch */
377#define BGMAC_BFL_ENETVLAN 0x0100 /* can do vlan */
378
379#define BGMAC_CHIPCTL_1_IF_TYPE_MASK 0x00000030
380#define BGMAC_CHIPCTL_1_IF_TYPE_RMII 0x00000000
381#define BGMAC_CHIPCTL_1_IF_TYPE_MII 0x00000010
382#define BGMAC_CHIPCTL_1_IF_TYPE_RGMII 0x00000020
383#define BGMAC_CHIPCTL_1_SW_TYPE_MASK 0x000000C0
384#define BGMAC_CHIPCTL_1_SW_TYPE_EPHY 0x00000000
385#define BGMAC_CHIPCTL_1_SW_TYPE_EPHYMII 0x00000040
386#define BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII 0x00000080
387#define BGMAC_CHIPCTL_1_SW_TYPE_RGMII 0x000000C0
388#define BGMAC_CHIPCTL_1_RXC_DLL_BYPASS 0x00010000
389
390#define BGMAC_CHIPCTL_4_IF_TYPE_MASK 0x00003000
391#define BGMAC_CHIPCTL_4_IF_TYPE_RMII 0x00000000
392#define BGMAC_CHIPCTL_4_IF_TYPE_MII 0x00001000
393#define BGMAC_CHIPCTL_4_IF_TYPE_RGMII 0x00002000
394#define BGMAC_CHIPCTL_4_SW_TYPE_MASK 0x0000C000
395#define BGMAC_CHIPCTL_4_SW_TYPE_EPHY 0x00000000
396#define BGMAC_CHIPCTL_4_SW_TYPE_EPHYMII 0x00004000
397#define BGMAC_CHIPCTL_4_SW_TYPE_EPHYRMII 0x00008000
398#define BGMAC_CHIPCTL_4_SW_TYPE_RGMII 0x0000C000
399
400#define BGMAC_CHIPCTL_7_IF_TYPE_MASK 0x000000C0
401#define BGMAC_CHIPCTL_7_IF_TYPE_RMII 0x00000000
402#define BGMAC_CHIPCTL_7_IF_TYPE_MII 0x00000040
403#define BGMAC_CHIPCTL_7_IF_TYPE_RGMII 0x00000080
404
405#define BGMAC_WEIGHT 64
406
407#define ETHER_MAX_LEN (ETH_FRAME_LEN + ETH_FCS_LEN)
408
409/* Feature Flags */
410#define BGMAC_FEAT_TX_MASK_SETUP BIT(0)
411#define BGMAC_FEAT_RX_MASK_SETUP BIT(1)
412#define BGMAC_FEAT_IOST_ATTACHED BIT(2)
413#define BGMAC_FEAT_NO_RESET BIT(3)
414#define BGMAC_FEAT_MISC_PLL_REQ BIT(4)
415#define BGMAC_FEAT_SW_TYPE_PHY BIT(5)
416#define BGMAC_FEAT_SW_TYPE_EPHYRMII BIT(6)
417#define BGMAC_FEAT_SW_TYPE_RGMII BIT(7)
418#define BGMAC_FEAT_CMN_PHY_CTL BIT(8)
419#define BGMAC_FEAT_FLW_CTRL1 BIT(9)
420#define BGMAC_FEAT_FLW_CTRL2 BIT(10)
421#define BGMAC_FEAT_SET_RXQ_CLK BIT(11)
422#define BGMAC_FEAT_CLKCTLST BIT(12)
423#define BGMAC_FEAT_NO_CLR_MIB BIT(13)
424#define BGMAC_FEAT_FORCE_SPEED_2500 BIT(14)
425#define BGMAC_FEAT_CMDCFG_SR_REV4 BIT(15)
426#define BGMAC_FEAT_IRQ_ID_OOB_6 BIT(16)
427#define BGMAC_FEAT_CC4_IF_SW_TYPE BIT(17)
428#define BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII BIT(18)
429#define BGMAC_FEAT_CC7_IF_TYPE_RGMII BIT(19)
430#define BGMAC_FEAT_IDM_MASK BIT(20)
431
432struct bgmac_slot_info {
433 union {
434 struct sk_buff *skb;
435 void *buf;
436 };
437 dma_addr_t dma_addr;
438};
439
440struct bgmac_dma_desc {
441 __le32 ctl0;
442 __le32 ctl1;
443 __le32 addr_low;
444 __le32 addr_high;
445} __packed;
446
447enum bgmac_dma_ring_type {
448 BGMAC_DMA_RING_TX,
449 BGMAC_DMA_RING_RX,
450};
451
452/**
453 * bgmac_dma_ring - contains info about DMA ring (either TX or RX one)
454 * @start: index of the first slot containing data
455 * @end: index of a slot that can *not* be read (yet)
456 *
457 * Be really aware of the specific @end meaning. It's an index of a slot *after*
458 * the one containing data that can be read. If @start equals @end the ring is
459 * empty.
460 */
461struct bgmac_dma_ring {
462 u32 start;
463 u32 end;
464
465 struct bgmac_dma_desc *cpu_base;
466 dma_addr_t dma_base;
467 u32 index_base; /* Used for unaligned rings only, otherwise 0 */
468 u16 mmio_base;
469 bool unaligned;
470
471 struct bgmac_slot_info slots[BGMAC_RX_RING_SLOTS];
472};
473
474struct bgmac_rx_header {
475 __le16 len;
476 __le16 flags;
477 __le16 pad[12];
478};
479
480struct bgmac {
481 union {
482 struct {
483 void __iomem *base;
484 void __iomem *idm_base;
485 void __iomem *nicpm_base;
486 } plat;
487 struct {
488 struct bcma_device *core;
489 /* Reference to CMN core for BCM4706 */
490 struct bcma_device *cmn;
491 } bcma;
492 };
493
494 struct device *dev;
495 struct device *dma_dev;
496 u32 feature_flags;
497
498 struct net_device *net_dev;
499 struct napi_struct napi;
500 struct mii_bus *mii_bus;
501
502 /* DMA */
503 struct bgmac_dma_ring tx_ring[BGMAC_MAX_TX_RINGS];
504 struct bgmac_dma_ring rx_ring[BGMAC_MAX_RX_RINGS];
505
506 /* Stats */
507 bool stats_grabbed;
508 u32 mib_tx_regs[BGMAC_NUM_MIB_TX_REGS];
509 u32 mib_rx_regs[BGMAC_NUM_MIB_RX_REGS];
510
511 /* Int */
512 int irq;
513 u32 int_mask;
514
515 /* Current MAC state */
516 int mac_speed;
517 int mac_duplex;
518
519 u8 phyaddr;
520 bool has_robosw;
521
522 bool loopback;
523
524 u32 (*read)(struct bgmac *bgmac, u16 offset);
525 void (*write)(struct bgmac *bgmac, u16 offset, u32 value);
526 u32 (*idm_read)(struct bgmac *bgmac, u16 offset);
527 void (*idm_write)(struct bgmac *bgmac, u16 offset, u32 value);
528 bool (*clk_enabled)(struct bgmac *bgmac);
529 void (*clk_enable)(struct bgmac *bgmac, u32 flags);
530 void (*cco_ctl_maskset)(struct bgmac *bgmac, u32 offset, u32 mask,
531 u32 set);
532 u32 (*get_bus_clock)(struct bgmac *bgmac);
533 void (*cmn_maskset32)(struct bgmac *bgmac, u16 offset, u32 mask,
534 u32 set);
535 int (*phy_connect)(struct bgmac *bgmac);
536};
537
538struct bgmac *bgmac_alloc(struct device *dev);
539int bgmac_enet_probe(struct bgmac *bgmac);
540void bgmac_enet_remove(struct bgmac *bgmac);
541void bgmac_adjust_link(struct net_device *net_dev);
542int bgmac_phy_connect_direct(struct bgmac *bgmac);
543int bgmac_enet_suspend(struct bgmac *bgmac);
544int bgmac_enet_resume(struct bgmac *bgmac);
545
546struct mii_bus *bcma_mdio_mii_register(struct bgmac *bgmac);
547void bcma_mdio_mii_unregister(struct mii_bus *mii_bus);
548
549static inline u32 bgmac_read(struct bgmac *bgmac, u16 offset)
550{
551 return bgmac->read(bgmac, offset);
552}
553
554static inline void bgmac_write(struct bgmac *bgmac, u16 offset, u32 value)
555{
556 bgmac->write(bgmac, offset, value);
557}
558
559static inline u32 bgmac_idm_read(struct bgmac *bgmac, u16 offset)
560{
561 return bgmac->idm_read(bgmac, offset);
562}
563
564static inline void bgmac_idm_write(struct bgmac *bgmac, u16 offset, u32 value)
565{
566 bgmac->idm_write(bgmac, offset, value);
567}
568
569static inline bool bgmac_clk_enabled(struct bgmac *bgmac)
570{
571 return bgmac->clk_enabled(bgmac);
572}
573
574static inline void bgmac_clk_enable(struct bgmac *bgmac, u32 flags)
575{
576 bgmac->clk_enable(bgmac, flags);
577}
578
579static inline void bgmac_cco_ctl_maskset(struct bgmac *bgmac, u32 offset,
580 u32 mask, u32 set)
581{
582 bgmac->cco_ctl_maskset(bgmac, offset, mask, set);
583}
584
585static inline u32 bgmac_get_bus_clock(struct bgmac *bgmac)
586{
587 return bgmac->get_bus_clock(bgmac);
588}
589
590static inline void bgmac_cmn_maskset32(struct bgmac *bgmac, u16 offset,
591 u32 mask, u32 set)
592{
593 bgmac->cmn_maskset32(bgmac, offset, mask, set);
594}
595
596static inline void bgmac_maskset(struct bgmac *bgmac, u16 offset, u32 mask,
597 u32 set)
598{
599 bgmac_write(bgmac, offset, (bgmac_read(bgmac, offset) & mask) | set);
600}
601
602static inline void bgmac_mask(struct bgmac *bgmac, u16 offset, u32 mask)
603{
604 bgmac_maskset(bgmac, offset, mask, 0);
605}
606
607static inline void bgmac_set(struct bgmac *bgmac, u16 offset, u32 set)
608{
609 bgmac_maskset(bgmac, offset, ~0, set);
610}
611
612static inline int bgmac_phy_connect(struct bgmac *bgmac)
613{
614 return bgmac->phy_connect(bgmac);
615}
616#endif /* _BGMAC_H */