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1// SPDX-License-Identifier: GPL-2.0
2/* Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2019 Oleksij Rempel <o.rempel@pengutronix.de>
5 *
6 * List of authors contributed to this driver before mainlining:
7 * Alexander Couzens <lynxis@fe80.eu>
8 * Christian Lamparter <chunkeey@gmail.com>
9 * Chuanhong Guo <gch981213@gmail.com>
10 * Daniel F. Dickinson <cshored@thecshore.com>
11 * David Bauer <mail@david-bauer.net>
12 * Felix Fietkau <nbd@nbd.name>
13 * Gabor Juhos <juhosg@freemail.hu>
14 * Hauke Mehrtens <hauke@hauke-m.de>
15 * Johann Neuhauser <johann@it-neuhauser.de>
16 * John Crispin <john@phrozen.org>
17 * Jo-Philipp Wich <jo@mein.io>
18 * Koen Vandeputte <koen.vandeputte@ncentric.com>
19 * Lucian Cristian <lucian.cristian@gmail.com>
20 * Matt Merhar <mattmerhar@protonmail.com>
21 * Milan Krstic <milan.krstic@gmail.com>
22 * Petr Štetiar <ynezz@true.cz>
23 * Rosen Penev <rosenp@gmail.com>
24 * Stephen Walker <stephendwalker+github@gmail.com>
25 * Vittorio Gambaletta <openwrt@vittgam.net>
26 * Weijie Gao <hackpascal@gmail.com>
27 * Imre Kaloz <kaloz@openwrt.org>
28 */
29
30#include <linux/if_vlan.h>
31#include <linux/mfd/syscon.h>
32#include <linux/of_mdio.h>
33#include <linux/of_net.h>
34#include <linux/of_platform.h>
35#include <linux/phylink.h>
36#include <linux/regmap.h>
37#include <linux/reset.h>
38#include <linux/clk.h>
39#include <linux/io.h>
40
41/* For our NAPI weight bigger does *NOT* mean better - it means more
42 * D-cache misses and lots more wasted cycles than we'll ever
43 * possibly gain from saving instructions.
44 */
45#define AG71XX_NAPI_WEIGHT 32
46#define AG71XX_OOM_REFILL (1 + HZ / 10)
47
48#define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
49#define AG71XX_INT_TX (AG71XX_INT_TX_PS)
50#define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
51
52#define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
53#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
54
55#define AG71XX_TX_MTU_LEN 1540
56
57#define AG71XX_TX_RING_SPLIT 512
58#define AG71XX_TX_RING_DS_PER_PKT DIV_ROUND_UP(AG71XX_TX_MTU_LEN, \
59 AG71XX_TX_RING_SPLIT)
60#define AG71XX_TX_RING_SIZE_DEFAULT 128
61#define AG71XX_RX_RING_SIZE_DEFAULT 256
62
63#define AG71XX_MDIO_RETRY 1000
64#define AG71XX_MDIO_DELAY 5
65#define AG71XX_MDIO_MAX_CLK 5000000
66
67/* Register offsets */
68#define AG71XX_REG_MAC_CFG1 0x0000
69#define MAC_CFG1_TXE BIT(0) /* Tx Enable */
70#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
71#define MAC_CFG1_RXE BIT(2) /* Rx Enable */
72#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
73#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
74#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
75#define MAC_CFG1_SR BIT(31) /* Soft Reset */
76#define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
77 MAC_CFG1_SRX | MAC_CFG1_STX)
78
79#define AG71XX_REG_MAC_CFG2 0x0004
80#define MAC_CFG2_FDX BIT(0)
81#define MAC_CFG2_PAD_CRC_EN BIT(2)
82#define MAC_CFG2_LEN_CHECK BIT(4)
83#define MAC_CFG2_IF_1000 BIT(9)
84#define MAC_CFG2_IF_10_100 BIT(8)
85
86#define AG71XX_REG_MAC_MFL 0x0010
87
88#define AG71XX_REG_MII_CFG 0x0020
89#define MII_CFG_CLK_DIV_4 0
90#define MII_CFG_CLK_DIV_6 2
91#define MII_CFG_CLK_DIV_8 3
92#define MII_CFG_CLK_DIV_10 4
93#define MII_CFG_CLK_DIV_14 5
94#define MII_CFG_CLK_DIV_20 6
95#define MII_CFG_CLK_DIV_28 7
96#define MII_CFG_CLK_DIV_34 8
97#define MII_CFG_CLK_DIV_42 9
98#define MII_CFG_CLK_DIV_50 10
99#define MII_CFG_CLK_DIV_58 11
100#define MII_CFG_CLK_DIV_66 12
101#define MII_CFG_CLK_DIV_74 13
102#define MII_CFG_CLK_DIV_82 14
103#define MII_CFG_CLK_DIV_98 15
104#define MII_CFG_RESET BIT(31)
105
106#define AG71XX_REG_MII_CMD 0x0024
107#define MII_CMD_READ BIT(0)
108
109#define AG71XX_REG_MII_ADDR 0x0028
110#define MII_ADDR_SHIFT 8
111
112#define AG71XX_REG_MII_CTRL 0x002c
113#define AG71XX_REG_MII_STATUS 0x0030
114#define AG71XX_REG_MII_IND 0x0034
115#define MII_IND_BUSY BIT(0)
116#define MII_IND_INVALID BIT(2)
117
118#define AG71XX_REG_MAC_IFCTL 0x0038
119#define MAC_IFCTL_SPEED BIT(16)
120
121#define AG71XX_REG_MAC_ADDR1 0x0040
122#define AG71XX_REG_MAC_ADDR2 0x0044
123#define AG71XX_REG_FIFO_CFG0 0x0048
124#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
125#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
126#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
127#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
128#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
129#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
130 | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
131#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
132
133#define FIFO_CFG0_ENABLE_SHIFT 8
134
135#define AG71XX_REG_FIFO_CFG1 0x004c
136#define AG71XX_REG_FIFO_CFG2 0x0050
137#define AG71XX_REG_FIFO_CFG3 0x0054
138#define AG71XX_REG_FIFO_CFG4 0x0058
139#define FIFO_CFG4_DE BIT(0) /* Drop Event */
140#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
141#define FIFO_CFG4_FC BIT(2) /* False Carrier */
142#define FIFO_CFG4_CE BIT(3) /* Code Error */
143#define FIFO_CFG4_CR BIT(4) /* CRC error */
144#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
145#define FIFO_CFG4_LO BIT(6) /* Length out of range */
146#define FIFO_CFG4_OK BIT(7) /* Packet is OK */
147#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
148#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
149#define FIFO_CFG4_DR BIT(10) /* Dribble */
150#define FIFO_CFG4_LE BIT(11) /* Long Event */
151#define FIFO_CFG4_CF BIT(12) /* Control Frame */
152#define FIFO_CFG4_PF BIT(13) /* Pause Frame */
153#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
154#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
155#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
156#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
157#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
158 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
159 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
160 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
161 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
162 FIFO_CFG4_VT)
163
164#define AG71XX_REG_FIFO_CFG5 0x005c
165#define FIFO_CFG5_DE BIT(0) /* Drop Event */
166#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
167#define FIFO_CFG5_FC BIT(2) /* False Carrier */
168#define FIFO_CFG5_CE BIT(3) /* Code Error */
169#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
170#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
171#define FIFO_CFG5_OK BIT(6) /* Packet is OK */
172#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
173#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
174#define FIFO_CFG5_DR BIT(9) /* Dribble */
175#define FIFO_CFG5_CF BIT(10) /* Control Frame */
176#define FIFO_CFG5_PF BIT(11) /* Pause Frame */
177#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
178#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
179#define FIFO_CFG5_LE BIT(14) /* Long Event */
180#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
181#define FIFO_CFG5_16 BIT(16) /* unknown */
182#define FIFO_CFG5_17 BIT(17) /* unknown */
183#define FIFO_CFG5_SF BIT(18) /* Short Frame */
184#define FIFO_CFG5_BM BIT(19) /* Byte Mode */
185#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
186 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
187 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
188 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
189 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
190 FIFO_CFG5_17 | FIFO_CFG5_SF)
191
192#define AG71XX_REG_TX_CTRL 0x0180
193#define TX_CTRL_TXE BIT(0) /* Tx Enable */
194
195#define AG71XX_REG_TX_DESC 0x0184
196#define AG71XX_REG_TX_STATUS 0x0188
197#define TX_STATUS_PS BIT(0) /* Packet Sent */
198#define TX_STATUS_UR BIT(1) /* Tx Underrun */
199#define TX_STATUS_BE BIT(3) /* Bus Error */
200
201#define AG71XX_REG_RX_CTRL 0x018c
202#define RX_CTRL_RXE BIT(0) /* Rx Enable */
203
204#define AG71XX_DMA_RETRY 10
205#define AG71XX_DMA_DELAY 1
206
207#define AG71XX_REG_RX_DESC 0x0190
208#define AG71XX_REG_RX_STATUS 0x0194
209#define RX_STATUS_PR BIT(0) /* Packet Received */
210#define RX_STATUS_OF BIT(2) /* Rx Overflow */
211#define RX_STATUS_BE BIT(3) /* Bus Error */
212
213#define AG71XX_REG_INT_ENABLE 0x0198
214#define AG71XX_REG_INT_STATUS 0x019c
215#define AG71XX_INT_TX_PS BIT(0)
216#define AG71XX_INT_TX_UR BIT(1)
217#define AG71XX_INT_TX_BE BIT(3)
218#define AG71XX_INT_RX_PR BIT(4)
219#define AG71XX_INT_RX_OF BIT(6)
220#define AG71XX_INT_RX_BE BIT(7)
221
222#define AG71XX_REG_FIFO_DEPTH 0x01a8
223#define AG71XX_REG_RX_SM 0x01b0
224#define AG71XX_REG_TX_SM 0x01b4
225
226#define ETH_SWITCH_HEADER_LEN 2
227
228#define AG71XX_DEFAULT_MSG_ENABLE \
229 (NETIF_MSG_DRV \
230 | NETIF_MSG_PROBE \
231 | NETIF_MSG_LINK \
232 | NETIF_MSG_TIMER \
233 | NETIF_MSG_IFDOWN \
234 | NETIF_MSG_IFUP \
235 | NETIF_MSG_RX_ERR \
236 | NETIF_MSG_TX_ERR)
237
238#define DESC_EMPTY BIT(31)
239#define DESC_MORE BIT(24)
240#define DESC_PKTLEN_M 0xfff
241struct ag71xx_desc {
242 u32 data;
243 u32 ctrl;
244 u32 next;
245 u32 pad;
246} __aligned(4);
247
248#define AG71XX_DESC_SIZE roundup(sizeof(struct ag71xx_desc), \
249 L1_CACHE_BYTES)
250
251struct ag71xx_buf {
252 union {
253 struct {
254 struct sk_buff *skb;
255 unsigned int len;
256 } tx;
257 struct {
258 dma_addr_t dma_addr;
259 void *rx_buf;
260 } rx;
261 };
262};
263
264struct ag71xx_ring {
265 /* "Hot" fields in the data path. */
266 unsigned int curr;
267 unsigned int dirty;
268
269 /* "Cold" fields - not used in the data path. */
270 struct ag71xx_buf *buf;
271 u16 order;
272 u16 desc_split;
273 dma_addr_t descs_dma;
274 u8 *descs_cpu;
275};
276
277enum ag71xx_type {
278 AR7100,
279 AR7240,
280 AR9130,
281 AR9330,
282 AR9340,
283 QCA9530,
284 QCA9550,
285};
286
287struct ag71xx_dcfg {
288 u32 max_frame_len;
289 const u32 *fifodata;
290 u16 desc_pktlen_mask;
291 bool tx_hang_workaround;
292 enum ag71xx_type type;
293};
294
295struct ag71xx {
296 /* Critical data related to the per-packet data path are clustered
297 * early in this structure to help improve the D-cache footprint.
298 */
299 struct ag71xx_ring rx_ring ____cacheline_aligned;
300 struct ag71xx_ring tx_ring ____cacheline_aligned;
301
302 u16 rx_buf_size;
303 u8 rx_buf_offset;
304
305 struct net_device *ndev;
306 struct platform_device *pdev;
307 struct napi_struct napi;
308 u32 msg_enable;
309 const struct ag71xx_dcfg *dcfg;
310
311 /* From this point onwards we're not looking at per-packet fields. */
312 void __iomem *mac_base;
313
314 struct ag71xx_desc *stop_desc;
315 dma_addr_t stop_desc_dma;
316
317 phy_interface_t phy_if_mode;
318 struct phylink *phylink;
319 struct phylink_config phylink_config;
320
321 struct delayed_work restart_work;
322 struct timer_list oom_timer;
323
324 struct reset_control *mac_reset;
325
326 u32 fifodata[3];
327 int mac_idx;
328
329 struct reset_control *mdio_reset;
330 struct mii_bus *mii_bus;
331 struct clk *clk_mdio;
332 struct clk *clk_eth;
333};
334
335static int ag71xx_desc_empty(struct ag71xx_desc *desc)
336{
337 return (desc->ctrl & DESC_EMPTY) != 0;
338}
339
340static struct ag71xx_desc *ag71xx_ring_desc(struct ag71xx_ring *ring, int idx)
341{
342 return (struct ag71xx_desc *)&ring->descs_cpu[idx * AG71XX_DESC_SIZE];
343}
344
345static int ag71xx_ring_size_order(int size)
346{
347 return fls(size - 1);
348}
349
350static bool ag71xx_is(struct ag71xx *ag, enum ag71xx_type type)
351{
352 return ag->dcfg->type == type;
353}
354
355static void ag71xx_wr(struct ag71xx *ag, unsigned int reg, u32 value)
356{
357 iowrite32(value, ag->mac_base + reg);
358 /* flush write */
359 (void)ioread32(ag->mac_base + reg);
360}
361
362static u32 ag71xx_rr(struct ag71xx *ag, unsigned int reg)
363{
364 return ioread32(ag->mac_base + reg);
365}
366
367static void ag71xx_sb(struct ag71xx *ag, unsigned int reg, u32 mask)
368{
369 void __iomem *r;
370
371 r = ag->mac_base + reg;
372 iowrite32(ioread32(r) | mask, r);
373 /* flush write */
374 (void)ioread32(r);
375}
376
377static void ag71xx_cb(struct ag71xx *ag, unsigned int reg, u32 mask)
378{
379 void __iomem *r;
380
381 r = ag->mac_base + reg;
382 iowrite32(ioread32(r) & ~mask, r);
383 /* flush write */
384 (void)ioread32(r);
385}
386
387static void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
388{
389 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
390}
391
392static void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
393{
394 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
395}
396
397static int ag71xx_mdio_wait_busy(struct ag71xx *ag)
398{
399 struct net_device *ndev = ag->ndev;
400 int i;
401
402 for (i = 0; i < AG71XX_MDIO_RETRY; i++) {
403 u32 busy;
404
405 udelay(AG71XX_MDIO_DELAY);
406
407 busy = ag71xx_rr(ag, AG71XX_REG_MII_IND);
408 if (!busy)
409 return 0;
410
411 udelay(AG71XX_MDIO_DELAY);
412 }
413
414 netif_err(ag, link, ndev, "MDIO operation timed out\n");
415
416 return -ETIMEDOUT;
417}
418
419static int ag71xx_mdio_mii_read(struct mii_bus *bus, int addr, int reg)
420{
421 struct ag71xx *ag = bus->priv;
422 int err, val;
423
424 err = ag71xx_mdio_wait_busy(ag);
425 if (err)
426 return err;
427
428 ag71xx_wr(ag, AG71XX_REG_MII_ADDR,
429 ((addr & 0x1f) << MII_ADDR_SHIFT) | (reg & 0xff));
430 /* enable read mode */
431 ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_READ);
432
433 err = ag71xx_mdio_wait_busy(ag);
434 if (err)
435 return err;
436
437 val = ag71xx_rr(ag, AG71XX_REG_MII_STATUS);
438 /* disable read mode */
439 ag71xx_wr(ag, AG71XX_REG_MII_CMD, 0);
440
441 netif_dbg(ag, link, ag->ndev, "mii_read: addr=%04x, reg=%04x, value=%04x\n",
442 addr, reg, val);
443
444 return val;
445}
446
447static int ag71xx_mdio_mii_write(struct mii_bus *bus, int addr, int reg,
448 u16 val)
449{
450 struct ag71xx *ag = bus->priv;
451
452 netif_dbg(ag, link, ag->ndev, "mii_write: addr=%04x, reg=%04x, value=%04x\n",
453 addr, reg, val);
454
455 ag71xx_wr(ag, AG71XX_REG_MII_ADDR,
456 ((addr & 0x1f) << MII_ADDR_SHIFT) | (reg & 0xff));
457 ag71xx_wr(ag, AG71XX_REG_MII_CTRL, val);
458
459 return ag71xx_mdio_wait_busy(ag);
460}
461
462static const u32 ar71xx_mdio_div_table[] = {
463 4, 4, 6, 8, 10, 14, 20, 28,
464};
465
466static const u32 ar7240_mdio_div_table[] = {
467 2, 2, 4, 6, 8, 12, 18, 26, 32, 40, 48, 56, 62, 70, 78, 96,
468};
469
470static const u32 ar933x_mdio_div_table[] = {
471 4, 4, 6, 8, 10, 14, 20, 28, 34, 42, 50, 58, 66, 74, 82, 98,
472};
473
474static int ag71xx_mdio_get_divider(struct ag71xx *ag, u32 *div)
475{
476 unsigned long ref_clock;
477 const u32 *table;
478 int ndivs, i;
479
480 ref_clock = clk_get_rate(ag->clk_mdio);
481 if (!ref_clock)
482 return -EINVAL;
483
484 if (ag71xx_is(ag, AR9330) || ag71xx_is(ag, AR9340)) {
485 table = ar933x_mdio_div_table;
486 ndivs = ARRAY_SIZE(ar933x_mdio_div_table);
487 } else if (ag71xx_is(ag, AR7240)) {
488 table = ar7240_mdio_div_table;
489 ndivs = ARRAY_SIZE(ar7240_mdio_div_table);
490 } else {
491 table = ar71xx_mdio_div_table;
492 ndivs = ARRAY_SIZE(ar71xx_mdio_div_table);
493 }
494
495 for (i = 0; i < ndivs; i++) {
496 unsigned long t;
497
498 t = ref_clock / table[i];
499 if (t <= AG71XX_MDIO_MAX_CLK) {
500 *div = i;
501 return 0;
502 }
503 }
504
505 return -ENOENT;
506}
507
508static int ag71xx_mdio_reset(struct mii_bus *bus)
509{
510 struct ag71xx *ag = bus->priv;
511 int err;
512 u32 t;
513
514 err = ag71xx_mdio_get_divider(ag, &t);
515 if (err)
516 return err;
517
518 ag71xx_wr(ag, AG71XX_REG_MII_CFG, t | MII_CFG_RESET);
519 usleep_range(100, 200);
520
521 ag71xx_wr(ag, AG71XX_REG_MII_CFG, t);
522 usleep_range(100, 200);
523
524 return 0;
525}
526
527static int ag71xx_mdio_probe(struct ag71xx *ag)
528{
529 struct device *dev = &ag->pdev->dev;
530 struct net_device *ndev = ag->ndev;
531 static struct mii_bus *mii_bus;
532 struct device_node *np, *mnp;
533 int err;
534
535 np = dev->of_node;
536 ag->mii_bus = NULL;
537
538 ag->clk_mdio = devm_clk_get(dev, "mdio");
539 if (IS_ERR(ag->clk_mdio)) {
540 netif_err(ag, probe, ndev, "Failed to get mdio clk.\n");
541 return PTR_ERR(ag->clk_mdio);
542 }
543
544 err = clk_prepare_enable(ag->clk_mdio);
545 if (err) {
546 netif_err(ag, probe, ndev, "Failed to enable mdio clk.\n");
547 return err;
548 }
549
550 mii_bus = devm_mdiobus_alloc(dev);
551 if (!mii_bus) {
552 err = -ENOMEM;
553 goto mdio_err_put_clk;
554 }
555
556 ag->mdio_reset = of_reset_control_get_exclusive(np, "mdio");
557 if (IS_ERR(ag->mdio_reset)) {
558 netif_err(ag, probe, ndev, "Failed to get reset mdio.\n");
559 err = PTR_ERR(ag->mdio_reset);
560 goto mdio_err_put_clk;
561 }
562
563 mii_bus->name = "ag71xx_mdio";
564 mii_bus->read = ag71xx_mdio_mii_read;
565 mii_bus->write = ag71xx_mdio_mii_write;
566 mii_bus->reset = ag71xx_mdio_reset;
567 mii_bus->priv = ag;
568 mii_bus->parent = dev;
569 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s.%d", np->name, ag->mac_idx);
570
571 if (!IS_ERR(ag->mdio_reset)) {
572 reset_control_assert(ag->mdio_reset);
573 msleep(100);
574 reset_control_deassert(ag->mdio_reset);
575 msleep(200);
576 }
577
578 mnp = of_get_child_by_name(np, "mdio");
579 err = of_mdiobus_register(mii_bus, mnp);
580 of_node_put(mnp);
581 if (err)
582 goto mdio_err_put_clk;
583
584 ag->mii_bus = mii_bus;
585
586 return 0;
587
588mdio_err_put_clk:
589 clk_disable_unprepare(ag->clk_mdio);
590 return err;
591}
592
593static void ag71xx_mdio_remove(struct ag71xx *ag)
594{
595 if (ag->mii_bus)
596 mdiobus_unregister(ag->mii_bus);
597 clk_disable_unprepare(ag->clk_mdio);
598}
599
600static void ag71xx_hw_stop(struct ag71xx *ag)
601{
602 /* disable all interrupts and stop the rx/tx engine */
603 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
604 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
605 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
606}
607
608static bool ag71xx_check_dma_stuck(struct ag71xx *ag)
609{
610 unsigned long timestamp;
611 u32 rx_sm, tx_sm, rx_fd;
612
613 timestamp = netdev_get_tx_queue(ag->ndev, 0)->trans_start;
614 if (likely(time_before(jiffies, timestamp + HZ / 10)))
615 return false;
616
617 if (!netif_carrier_ok(ag->ndev))
618 return false;
619
620 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
621 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
622 return true;
623
624 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
625 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
626 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
627 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
628 return true;
629
630 return false;
631}
632
633static int ag71xx_tx_packets(struct ag71xx *ag, bool flush)
634{
635 struct ag71xx_ring *ring = &ag->tx_ring;
636 int sent = 0, bytes_compl = 0, n = 0;
637 struct net_device *ndev = ag->ndev;
638 int ring_mask, ring_size;
639 bool dma_stuck = false;
640
641 ring_mask = BIT(ring->order) - 1;
642 ring_size = BIT(ring->order);
643
644 netif_dbg(ag, tx_queued, ndev, "processing TX ring\n");
645
646 while (ring->dirty + n != ring->curr) {
647 struct ag71xx_desc *desc;
648 struct sk_buff *skb;
649 unsigned int i;
650
651 i = (ring->dirty + n) & ring_mask;
652 desc = ag71xx_ring_desc(ring, i);
653 skb = ring->buf[i].tx.skb;
654
655 if (!flush && !ag71xx_desc_empty(desc)) {
656 if (ag->dcfg->tx_hang_workaround &&
657 ag71xx_check_dma_stuck(ag)) {
658 schedule_delayed_work(&ag->restart_work,
659 HZ / 2);
660 dma_stuck = true;
661 }
662 break;
663 }
664
665 if (flush)
666 desc->ctrl |= DESC_EMPTY;
667
668 n++;
669 if (!skb)
670 continue;
671
672 dev_kfree_skb_any(skb);
673 ring->buf[i].tx.skb = NULL;
674
675 bytes_compl += ring->buf[i].tx.len;
676
677 sent++;
678 ring->dirty += n;
679
680 while (n > 0) {
681 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
682 n--;
683 }
684 }
685
686 netif_dbg(ag, tx_done, ndev, "%d packets sent out\n", sent);
687
688 if (!sent)
689 return 0;
690
691 ag->ndev->stats.tx_bytes += bytes_compl;
692 ag->ndev->stats.tx_packets += sent;
693
694 netdev_completed_queue(ag->ndev, sent, bytes_compl);
695 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
696 netif_wake_queue(ag->ndev);
697
698 if (!dma_stuck)
699 cancel_delayed_work(&ag->restart_work);
700
701 return sent;
702}
703
704static void ag71xx_dma_wait_stop(struct ag71xx *ag)
705{
706 struct net_device *ndev = ag->ndev;
707 int i;
708
709 for (i = 0; i < AG71XX_DMA_RETRY; i++) {
710 u32 rx, tx;
711
712 mdelay(AG71XX_DMA_DELAY);
713
714 rx = ag71xx_rr(ag, AG71XX_REG_RX_CTRL) & RX_CTRL_RXE;
715 tx = ag71xx_rr(ag, AG71XX_REG_TX_CTRL) & TX_CTRL_TXE;
716 if (!rx && !tx)
717 return;
718 }
719
720 netif_err(ag, hw, ndev, "DMA stop operation timed out\n");
721}
722
723static void ag71xx_dma_reset(struct ag71xx *ag)
724{
725 struct net_device *ndev = ag->ndev;
726 u32 val;
727 int i;
728
729 /* stop RX and TX */
730 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
731 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
732
733 /* give the hardware some time to really stop all rx/tx activity
734 * clearing the descriptors too early causes random memory corruption
735 */
736 ag71xx_dma_wait_stop(ag);
737
738 /* clear descriptor addresses */
739 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
740 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
741
742 /* clear pending RX/TX interrupts */
743 for (i = 0; i < 256; i++) {
744 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
745 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
746 }
747
748 /* clear pending errors */
749 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
750 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
751
752 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
753 if (val)
754 netif_err(ag, hw, ndev, "unable to clear DMA Rx status: %08x\n",
755 val);
756
757 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
758
759 /* mask out reserved bits */
760 val &= ~0xff000000;
761
762 if (val)
763 netif_err(ag, hw, ndev, "unable to clear DMA Tx status: %08x\n",
764 val);
765}
766
767static void ag71xx_hw_setup(struct ag71xx *ag)
768{
769 u32 init = MAC_CFG1_INIT;
770
771 /* setup MAC configuration registers */
772 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);
773
774 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
775 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
776
777 /* setup max frame length to zero */
778 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
779
780 /* setup FIFO configuration registers */
781 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
782 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]);
783 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]);
784 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
785 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
786}
787
788static unsigned int ag71xx_max_frame_len(unsigned int mtu)
789{
790 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
791}
792
793static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
794{
795 u32 t;
796
797 t = (((u32)mac[5]) << 24) | (((u32)mac[4]) << 16)
798 | (((u32)mac[3]) << 8) | ((u32)mac[2]);
799
800 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
801
802 t = (((u32)mac[1]) << 24) | (((u32)mac[0]) << 16);
803 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
804}
805
806static void ag71xx_fast_reset(struct ag71xx *ag)
807{
808 struct net_device *dev = ag->ndev;
809 u32 rx_ds;
810 u32 mii_reg;
811
812 ag71xx_hw_stop(ag);
813
814 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
815 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
816
817 ag71xx_tx_packets(ag, true);
818
819 reset_control_assert(ag->mac_reset);
820 usleep_range(10, 20);
821 reset_control_deassert(ag->mac_reset);
822 usleep_range(10, 20);
823
824 ag71xx_dma_reset(ag);
825 ag71xx_hw_setup(ag);
826 ag->tx_ring.curr = 0;
827 ag->tx_ring.dirty = 0;
828 netdev_reset_queue(ag->ndev);
829
830 /* setup max frame length */
831 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
832 ag71xx_max_frame_len(ag->ndev->mtu));
833
834 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
835 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
836 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
837
838 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
839}
840
841static void ag71xx_hw_start(struct ag71xx *ag)
842{
843 /* start RX engine */
844 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
845
846 /* enable interrupts */
847 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
848
849 netif_wake_queue(ag->ndev);
850}
851
852static void ag71xx_mac_config(struct phylink_config *config, unsigned int mode,
853 const struct phylink_link_state *state)
854{
855 struct ag71xx *ag = netdev_priv(to_net_dev(config->dev));
856
857 if (phylink_autoneg_inband(mode))
858 return;
859
860 if (!ag71xx_is(ag, AR7100) && !ag71xx_is(ag, AR9130))
861 ag71xx_fast_reset(ag);
862
863 if (ag->tx_ring.desc_split) {
864 ag->fifodata[2] &= 0xffff;
865 ag->fifodata[2] |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
866 }
867
868 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]);
869}
870
871static void ag71xx_mac_validate(struct phylink_config *config,
872 unsigned long *supported,
873 struct phylink_link_state *state)
874{
875 struct ag71xx *ag = netdev_priv(to_net_dev(config->dev));
876 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
877
878 switch (state->interface) {
879 case PHY_INTERFACE_MODE_NA:
880 break;
881 case PHY_INTERFACE_MODE_MII:
882 if ((ag71xx_is(ag, AR9330) && ag->mac_idx == 0) ||
883 ag71xx_is(ag, AR9340) ||
884 ag71xx_is(ag, QCA9530) ||
885 (ag71xx_is(ag, QCA9550) && ag->mac_idx == 1))
886 break;
887 goto unsupported;
888 case PHY_INTERFACE_MODE_GMII:
889 if ((ag71xx_is(ag, AR9330) && ag->mac_idx == 1) ||
890 (ag71xx_is(ag, AR9340) && ag->mac_idx == 1) ||
891 (ag71xx_is(ag, QCA9530) && ag->mac_idx == 1))
892 break;
893 goto unsupported;
894 case PHY_INTERFACE_MODE_SGMII:
895 if (ag71xx_is(ag, QCA9550) && ag->mac_idx == 0)
896 break;
897 goto unsupported;
898 case PHY_INTERFACE_MODE_RMII:
899 if (ag71xx_is(ag, AR9340) && ag->mac_idx == 0)
900 break;
901 goto unsupported;
902 case PHY_INTERFACE_MODE_RGMII:
903 if ((ag71xx_is(ag, AR9340) && ag->mac_idx == 0) ||
904 (ag71xx_is(ag, QCA9550) && ag->mac_idx == 1))
905 break;
906 goto unsupported;
907 default:
908 goto unsupported;
909 }
910
911 phylink_set(mask, MII);
912
913 phylink_set(mask, Autoneg);
914 phylink_set(mask, 10baseT_Half);
915 phylink_set(mask, 10baseT_Full);
916 phylink_set(mask, 100baseT_Half);
917 phylink_set(mask, 100baseT_Full);
918
919 if (state->interface == PHY_INTERFACE_MODE_NA ||
920 state->interface == PHY_INTERFACE_MODE_SGMII ||
921 state->interface == PHY_INTERFACE_MODE_RGMII ||
922 state->interface == PHY_INTERFACE_MODE_GMII) {
923 phylink_set(mask, 1000baseT_Full);
924 phylink_set(mask, 1000baseX_Full);
925 }
926
927 bitmap_and(supported, supported, mask,
928 __ETHTOOL_LINK_MODE_MASK_NBITS);
929 bitmap_and(state->advertising, state->advertising, mask,
930 __ETHTOOL_LINK_MODE_MASK_NBITS);
931
932 return;
933unsupported:
934 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
935}
936
937static void ag71xx_mac_pcs_get_state(struct phylink_config *config,
938 struct phylink_link_state *state)
939{
940 state->link = 0;
941}
942
943static void ag71xx_mac_an_restart(struct phylink_config *config)
944{
945 /* Not Supported */
946}
947
948static void ag71xx_mac_link_down(struct phylink_config *config,
949 unsigned int mode, phy_interface_t interface)
950{
951 struct ag71xx *ag = netdev_priv(to_net_dev(config->dev));
952
953 ag71xx_hw_stop(ag);
954}
955
956static void ag71xx_mac_link_up(struct phylink_config *config,
957 struct phy_device *phy,
958 unsigned int mode, phy_interface_t interface,
959 int speed, int duplex,
960 bool tx_pause, bool rx_pause)
961{
962 struct ag71xx *ag = netdev_priv(to_net_dev(config->dev));
963 u32 cfg2;
964 u32 ifctl;
965 u32 fifo5;
966
967 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
968 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
969 cfg2 |= duplex ? MAC_CFG2_FDX : 0;
970
971 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
972 ifctl &= ~(MAC_IFCTL_SPEED);
973
974 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
975 fifo5 &= ~FIFO_CFG5_BM;
976
977 switch (speed) {
978 case SPEED_1000:
979 cfg2 |= MAC_CFG2_IF_1000;
980 fifo5 |= FIFO_CFG5_BM;
981 break;
982 case SPEED_100:
983 cfg2 |= MAC_CFG2_IF_10_100;
984 ifctl |= MAC_IFCTL_SPEED;
985 break;
986 case SPEED_10:
987 cfg2 |= MAC_CFG2_IF_10_100;
988 break;
989 default:
990 return;
991 }
992
993 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
994 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
995 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
996
997 ag71xx_hw_start(ag);
998}
999
1000static const struct phylink_mac_ops ag71xx_phylink_mac_ops = {
1001 .validate = ag71xx_mac_validate,
1002 .mac_pcs_get_state = ag71xx_mac_pcs_get_state,
1003 .mac_an_restart = ag71xx_mac_an_restart,
1004 .mac_config = ag71xx_mac_config,
1005 .mac_link_down = ag71xx_mac_link_down,
1006 .mac_link_up = ag71xx_mac_link_up,
1007};
1008
1009static int ag71xx_phylink_setup(struct ag71xx *ag)
1010{
1011 struct phylink *phylink;
1012
1013 ag->phylink_config.dev = &ag->ndev->dev;
1014 ag->phylink_config.type = PHYLINK_NETDEV;
1015
1016 phylink = phylink_create(&ag->phylink_config, ag->pdev->dev.fwnode,
1017 ag->phy_if_mode, &ag71xx_phylink_mac_ops);
1018 if (IS_ERR(phylink))
1019 return PTR_ERR(phylink);
1020
1021 ag->phylink = phylink;
1022 return 0;
1023}
1024
1025static void ag71xx_ring_tx_clean(struct ag71xx *ag)
1026{
1027 struct ag71xx_ring *ring = &ag->tx_ring;
1028 int ring_mask = BIT(ring->order) - 1;
1029 u32 bytes_compl = 0, pkts_compl = 0;
1030 struct net_device *ndev = ag->ndev;
1031
1032 while (ring->curr != ring->dirty) {
1033 struct ag71xx_desc *desc;
1034 u32 i = ring->dirty & ring_mask;
1035
1036 desc = ag71xx_ring_desc(ring, i);
1037 if (!ag71xx_desc_empty(desc)) {
1038 desc->ctrl = 0;
1039 ndev->stats.tx_errors++;
1040 }
1041
1042 if (ring->buf[i].tx.skb) {
1043 bytes_compl += ring->buf[i].tx.len;
1044 pkts_compl++;
1045 dev_kfree_skb_any(ring->buf[i].tx.skb);
1046 }
1047 ring->buf[i].tx.skb = NULL;
1048 ring->dirty++;
1049 }
1050
1051 /* flush descriptors */
1052 wmb();
1053
1054 netdev_completed_queue(ndev, pkts_compl, bytes_compl);
1055}
1056
1057static void ag71xx_ring_tx_init(struct ag71xx *ag)
1058{
1059 struct ag71xx_ring *ring = &ag->tx_ring;
1060 int ring_size = BIT(ring->order);
1061 int ring_mask = ring_size - 1;
1062 int i;
1063
1064 for (i = 0; i < ring_size; i++) {
1065 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1066
1067 desc->next = (u32)(ring->descs_dma +
1068 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
1069
1070 desc->ctrl = DESC_EMPTY;
1071 ring->buf[i].tx.skb = NULL;
1072 }
1073
1074 /* flush descriptors */
1075 wmb();
1076
1077 ring->curr = 0;
1078 ring->dirty = 0;
1079 netdev_reset_queue(ag->ndev);
1080}
1081
1082static void ag71xx_ring_rx_clean(struct ag71xx *ag)
1083{
1084 struct ag71xx_ring *ring = &ag->rx_ring;
1085 int ring_size = BIT(ring->order);
1086 int i;
1087
1088 if (!ring->buf)
1089 return;
1090
1091 for (i = 0; i < ring_size; i++)
1092 if (ring->buf[i].rx.rx_buf) {
1093 dma_unmap_single(&ag->pdev->dev,
1094 ring->buf[i].rx.dma_addr,
1095 ag->rx_buf_size, DMA_FROM_DEVICE);
1096 skb_free_frag(ring->buf[i].rx.rx_buf);
1097 }
1098}
1099
1100static int ag71xx_buffer_size(struct ag71xx *ag)
1101{
1102 return ag->rx_buf_size +
1103 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1104}
1105
1106static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
1107 int offset,
1108 void *(*alloc)(unsigned int size))
1109{
1110 struct ag71xx_ring *ring = &ag->rx_ring;
1111 struct ag71xx_desc *desc;
1112 void *data;
1113
1114 desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
1115
1116 data = alloc(ag71xx_buffer_size(ag));
1117 if (!data)
1118 return false;
1119
1120 buf->rx.rx_buf = data;
1121 buf->rx.dma_addr = dma_map_single(&ag->pdev->dev, data, ag->rx_buf_size,
1122 DMA_FROM_DEVICE);
1123 desc->data = (u32)buf->rx.dma_addr + offset;
1124 return true;
1125}
1126
1127static int ag71xx_ring_rx_init(struct ag71xx *ag)
1128{
1129 struct ag71xx_ring *ring = &ag->rx_ring;
1130 struct net_device *ndev = ag->ndev;
1131 int ring_mask = BIT(ring->order) - 1;
1132 int ring_size = BIT(ring->order);
1133 unsigned int i;
1134 int ret;
1135
1136 ret = 0;
1137 for (i = 0; i < ring_size; i++) {
1138 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1139
1140 desc->next = (u32)(ring->descs_dma +
1141 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
1142
1143 netif_dbg(ag, rx_status, ndev, "RX desc at %p, next is %08x\n",
1144 desc, desc->next);
1145 }
1146
1147 for (i = 0; i < ring_size; i++) {
1148 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1149
1150 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], ag->rx_buf_offset,
1151 netdev_alloc_frag)) {
1152 ret = -ENOMEM;
1153 break;
1154 }
1155
1156 desc->ctrl = DESC_EMPTY;
1157 }
1158
1159 /* flush descriptors */
1160 wmb();
1161
1162 ring->curr = 0;
1163 ring->dirty = 0;
1164
1165 return ret;
1166}
1167
1168static int ag71xx_ring_rx_refill(struct ag71xx *ag)
1169{
1170 struct ag71xx_ring *ring = &ag->rx_ring;
1171 int ring_mask = BIT(ring->order) - 1;
1172 int offset = ag->rx_buf_offset;
1173 unsigned int count;
1174
1175 count = 0;
1176 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
1177 struct ag71xx_desc *desc;
1178 unsigned int i;
1179
1180 i = ring->dirty & ring_mask;
1181 desc = ag71xx_ring_desc(ring, i);
1182
1183 if (!ring->buf[i].rx.rx_buf &&
1184 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
1185 napi_alloc_frag))
1186 break;
1187
1188 desc->ctrl = DESC_EMPTY;
1189 count++;
1190 }
1191
1192 /* flush descriptors */
1193 wmb();
1194
1195 netif_dbg(ag, rx_status, ag->ndev, "%u rx descriptors refilled\n",
1196 count);
1197
1198 return count;
1199}
1200
1201static int ag71xx_rings_init(struct ag71xx *ag)
1202{
1203 struct ag71xx_ring *tx = &ag->tx_ring;
1204 struct ag71xx_ring *rx = &ag->rx_ring;
1205 int ring_size, tx_size;
1206
1207 ring_size = BIT(tx->order) + BIT(rx->order);
1208 tx_size = BIT(tx->order);
1209
1210 tx->buf = kcalloc(ring_size, sizeof(*tx->buf), GFP_KERNEL);
1211 if (!tx->buf)
1212 return -ENOMEM;
1213
1214 tx->descs_cpu = dma_alloc_coherent(&ag->pdev->dev,
1215 ring_size * AG71XX_DESC_SIZE,
1216 &tx->descs_dma, GFP_KERNEL);
1217 if (!tx->descs_cpu) {
1218 kfree(tx->buf);
1219 tx->buf = NULL;
1220 return -ENOMEM;
1221 }
1222
1223 rx->buf = &tx->buf[tx_size];
1224 rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE;
1225 rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE;
1226
1227 ag71xx_ring_tx_init(ag);
1228 return ag71xx_ring_rx_init(ag);
1229}
1230
1231static void ag71xx_rings_free(struct ag71xx *ag)
1232{
1233 struct ag71xx_ring *tx = &ag->tx_ring;
1234 struct ag71xx_ring *rx = &ag->rx_ring;
1235 int ring_size;
1236
1237 ring_size = BIT(tx->order) + BIT(rx->order);
1238
1239 if (tx->descs_cpu)
1240 dma_free_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE,
1241 tx->descs_cpu, tx->descs_dma);
1242
1243 kfree(tx->buf);
1244
1245 tx->descs_cpu = NULL;
1246 rx->descs_cpu = NULL;
1247 tx->buf = NULL;
1248 rx->buf = NULL;
1249}
1250
1251static void ag71xx_rings_cleanup(struct ag71xx *ag)
1252{
1253 ag71xx_ring_rx_clean(ag);
1254 ag71xx_ring_tx_clean(ag);
1255 ag71xx_rings_free(ag);
1256
1257 netdev_reset_queue(ag->ndev);
1258}
1259
1260static void ag71xx_hw_init(struct ag71xx *ag)
1261{
1262 ag71xx_hw_stop(ag);
1263
1264 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
1265 usleep_range(20, 30);
1266
1267 reset_control_assert(ag->mac_reset);
1268 msleep(100);
1269 reset_control_deassert(ag->mac_reset);
1270 msleep(200);
1271
1272 ag71xx_hw_setup(ag);
1273
1274 ag71xx_dma_reset(ag);
1275}
1276
1277static int ag71xx_hw_enable(struct ag71xx *ag)
1278{
1279 int ret;
1280
1281 ret = ag71xx_rings_init(ag);
1282 if (ret)
1283 return ret;
1284
1285 napi_enable(&ag->napi);
1286 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
1287 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
1288 netif_start_queue(ag->ndev);
1289
1290 return 0;
1291}
1292
1293static void ag71xx_hw_disable(struct ag71xx *ag)
1294{
1295 netif_stop_queue(ag->ndev);
1296
1297 ag71xx_hw_stop(ag);
1298 ag71xx_dma_reset(ag);
1299
1300 napi_disable(&ag->napi);
1301 del_timer_sync(&ag->oom_timer);
1302
1303 ag71xx_rings_cleanup(ag);
1304}
1305
1306static int ag71xx_open(struct net_device *ndev)
1307{
1308 struct ag71xx *ag = netdev_priv(ndev);
1309 unsigned int max_frame_len;
1310 int ret;
1311
1312 ret = phylink_of_phy_connect(ag->phylink, ag->pdev->dev.of_node, 0);
1313 if (ret) {
1314 netif_err(ag, link, ndev, "phylink_of_phy_connect filed with err: %i\n",
1315 ret);
1316 goto err;
1317 }
1318
1319 max_frame_len = ag71xx_max_frame_len(ndev->mtu);
1320 ag->rx_buf_size =
1321 SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN);
1322
1323 /* setup max frame length */
1324 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
1325 ag71xx_hw_set_macaddr(ag, ndev->dev_addr);
1326
1327 ret = ag71xx_hw_enable(ag);
1328 if (ret)
1329 goto err;
1330
1331 phylink_start(ag->phylink);
1332
1333 return 0;
1334
1335err:
1336 ag71xx_rings_cleanup(ag);
1337 return ret;
1338}
1339
1340static int ag71xx_stop(struct net_device *ndev)
1341{
1342 struct ag71xx *ag = netdev_priv(ndev);
1343
1344 phylink_stop(ag->phylink);
1345 phylink_disconnect_phy(ag->phylink);
1346 ag71xx_hw_disable(ag);
1347
1348 return 0;
1349}
1350
1351static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
1352{
1353 int i, ring_mask, ndesc, split;
1354 struct ag71xx_desc *desc;
1355
1356 ring_mask = BIT(ring->order) - 1;
1357 ndesc = 0;
1358 split = ring->desc_split;
1359
1360 if (!split)
1361 split = len;
1362
1363 while (len > 0) {
1364 unsigned int cur_len = len;
1365
1366 i = (ring->curr + ndesc) & ring_mask;
1367 desc = ag71xx_ring_desc(ring, i);
1368
1369 if (!ag71xx_desc_empty(desc))
1370 return -1;
1371
1372 if (cur_len > split) {
1373 cur_len = split;
1374
1375 /* TX will hang if DMA transfers <= 4 bytes,
1376 * make sure next segment is more than 4 bytes long.
1377 */
1378 if (len <= split + 4)
1379 cur_len -= 4;
1380 }
1381
1382 desc->data = addr;
1383 addr += cur_len;
1384 len -= cur_len;
1385
1386 if (len > 0)
1387 cur_len |= DESC_MORE;
1388
1389 /* prevent early tx attempt of this descriptor */
1390 if (!ndesc)
1391 cur_len |= DESC_EMPTY;
1392
1393 desc->ctrl = cur_len;
1394 ndesc++;
1395 }
1396
1397 return ndesc;
1398}
1399
1400static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
1401 struct net_device *ndev)
1402{
1403 int i, n, ring_min, ring_mask, ring_size;
1404 struct ag71xx *ag = netdev_priv(ndev);
1405 struct ag71xx_ring *ring;
1406 struct ag71xx_desc *desc;
1407 dma_addr_t dma_addr;
1408
1409 ring = &ag->tx_ring;
1410 ring_mask = BIT(ring->order) - 1;
1411 ring_size = BIT(ring->order);
1412
1413 if (skb->len <= 4) {
1414 netif_dbg(ag, tx_err, ndev, "packet len is too small\n");
1415 goto err_drop;
1416 }
1417
1418 dma_addr = dma_map_single(&ag->pdev->dev, skb->data, skb->len,
1419 DMA_TO_DEVICE);
1420
1421 i = ring->curr & ring_mask;
1422 desc = ag71xx_ring_desc(ring, i);
1423
1424 /* setup descriptor fields */
1425 n = ag71xx_fill_dma_desc(ring, (u32)dma_addr,
1426 skb->len & ag->dcfg->desc_pktlen_mask);
1427 if (n < 0)
1428 goto err_drop_unmap;
1429
1430 i = (ring->curr + n - 1) & ring_mask;
1431 ring->buf[i].tx.len = skb->len;
1432 ring->buf[i].tx.skb = skb;
1433
1434 netdev_sent_queue(ndev, skb->len);
1435
1436 skb_tx_timestamp(skb);
1437
1438 desc->ctrl &= ~DESC_EMPTY;
1439 ring->curr += n;
1440
1441 /* flush descriptor */
1442 wmb();
1443
1444 ring_min = 2;
1445 if (ring->desc_split)
1446 ring_min *= AG71XX_TX_RING_DS_PER_PKT;
1447
1448 if (ring->curr - ring->dirty >= ring_size - ring_min) {
1449 netif_dbg(ag, tx_err, ndev, "tx queue full\n");
1450 netif_stop_queue(ndev);
1451 }
1452
1453 netif_dbg(ag, tx_queued, ndev, "packet injected into TX queue\n");
1454
1455 /* enable TX engine */
1456 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
1457
1458 return NETDEV_TX_OK;
1459
1460err_drop_unmap:
1461 dma_unmap_single(&ag->pdev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
1462
1463err_drop:
1464 ndev->stats.tx_dropped++;
1465
1466 dev_kfree_skb(skb);
1467 return NETDEV_TX_OK;
1468}
1469
1470static void ag71xx_oom_timer_handler(struct timer_list *t)
1471{
1472 struct ag71xx *ag = from_timer(ag, t, oom_timer);
1473
1474 napi_schedule(&ag->napi);
1475}
1476
1477static void ag71xx_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1478{
1479 struct ag71xx *ag = netdev_priv(ndev);
1480
1481 netif_err(ag, tx_err, ndev, "tx timeout\n");
1482
1483 schedule_delayed_work(&ag->restart_work, 1);
1484}
1485
1486static void ag71xx_restart_work_func(struct work_struct *work)
1487{
1488 struct ag71xx *ag = container_of(work, struct ag71xx,
1489 restart_work.work);
1490
1491 rtnl_lock();
1492 ag71xx_hw_disable(ag);
1493 ag71xx_hw_enable(ag);
1494
1495 phylink_stop(ag->phylink);
1496 phylink_start(ag->phylink);
1497
1498 rtnl_unlock();
1499}
1500
1501static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
1502{
1503 struct net_device *ndev = ag->ndev;
1504 int ring_mask, ring_size, done = 0;
1505 unsigned int pktlen_mask, offset;
1506 struct sk_buff *next, *skb;
1507 struct ag71xx_ring *ring;
1508 struct list_head rx_list;
1509
1510 ring = &ag->rx_ring;
1511 pktlen_mask = ag->dcfg->desc_pktlen_mask;
1512 offset = ag->rx_buf_offset;
1513 ring_mask = BIT(ring->order) - 1;
1514 ring_size = BIT(ring->order);
1515
1516 netif_dbg(ag, rx_status, ndev, "rx packets, limit=%d, curr=%u, dirty=%u\n",
1517 limit, ring->curr, ring->dirty);
1518
1519 INIT_LIST_HEAD(&rx_list);
1520
1521 while (done < limit) {
1522 unsigned int i = ring->curr & ring_mask;
1523 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1524 int pktlen;
1525 int err = 0;
1526
1527 if (ag71xx_desc_empty(desc))
1528 break;
1529
1530 if ((ring->dirty + ring_size) == ring->curr) {
1531 WARN_ONCE(1, "RX out of ring");
1532 break;
1533 }
1534
1535 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
1536
1537 pktlen = desc->ctrl & pktlen_mask;
1538 pktlen -= ETH_FCS_LEN;
1539
1540 dma_unmap_single(&ag->pdev->dev, ring->buf[i].rx.dma_addr,
1541 ag->rx_buf_size, DMA_FROM_DEVICE);
1542
1543 ndev->stats.rx_packets++;
1544 ndev->stats.rx_bytes += pktlen;
1545
1546 skb = build_skb(ring->buf[i].rx.rx_buf, ag71xx_buffer_size(ag));
1547 if (!skb) {
1548 skb_free_frag(ring->buf[i].rx.rx_buf);
1549 goto next;
1550 }
1551
1552 skb_reserve(skb, offset);
1553 skb_put(skb, pktlen);
1554
1555 if (err) {
1556 ndev->stats.rx_dropped++;
1557 kfree_skb(skb);
1558 } else {
1559 skb->dev = ndev;
1560 skb->ip_summed = CHECKSUM_NONE;
1561 list_add_tail(&skb->list, &rx_list);
1562 }
1563
1564next:
1565 ring->buf[i].rx.rx_buf = NULL;
1566 done++;
1567
1568 ring->curr++;
1569 }
1570
1571 ag71xx_ring_rx_refill(ag);
1572
1573 list_for_each_entry_safe(skb, next, &rx_list, list)
1574 skb->protocol = eth_type_trans(skb, ndev);
1575 netif_receive_skb_list(&rx_list);
1576
1577 netif_dbg(ag, rx_status, ndev, "rx finish, curr=%u, dirty=%u, done=%d\n",
1578 ring->curr, ring->dirty, done);
1579
1580 return done;
1581}
1582
1583static int ag71xx_poll(struct napi_struct *napi, int limit)
1584{
1585 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1586 struct ag71xx_ring *rx_ring = &ag->rx_ring;
1587 int rx_ring_size = BIT(rx_ring->order);
1588 struct net_device *ndev = ag->ndev;
1589 int tx_done, rx_done;
1590 u32 status;
1591
1592 tx_done = ag71xx_tx_packets(ag, false);
1593
1594 netif_dbg(ag, rx_status, ndev, "processing RX ring\n");
1595 rx_done = ag71xx_rx_packets(ag, limit);
1596
1597 if (!rx_ring->buf[rx_ring->dirty % rx_ring_size].rx.rx_buf)
1598 goto oom;
1599
1600 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1601 if (unlikely(status & RX_STATUS_OF)) {
1602 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1603 ndev->stats.rx_fifo_errors++;
1604
1605 /* restart RX */
1606 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1607 }
1608
1609 if (rx_done < limit) {
1610 if (status & RX_STATUS_PR)
1611 goto more;
1612
1613 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1614 if (status & TX_STATUS_PS)
1615 goto more;
1616
1617 netif_dbg(ag, rx_status, ndev, "disable polling mode, rx=%d, tx=%d,limit=%d\n",
1618 rx_done, tx_done, limit);
1619
1620 napi_complete(napi);
1621
1622 /* enable interrupts */
1623 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1624 return rx_done;
1625 }
1626
1627more:
1628 netif_dbg(ag, rx_status, ndev, "stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1629 rx_done, tx_done, limit);
1630 return limit;
1631
1632oom:
1633 netif_err(ag, rx_err, ndev, "out of memory\n");
1634
1635 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1636 napi_complete(napi);
1637 return 0;
1638}
1639
1640static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1641{
1642 struct net_device *ndev = dev_id;
1643 struct ag71xx *ag;
1644 u32 status;
1645
1646 ag = netdev_priv(ndev);
1647 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1648
1649 if (unlikely(!status))
1650 return IRQ_NONE;
1651
1652 if (unlikely(status & AG71XX_INT_ERR)) {
1653 if (status & AG71XX_INT_TX_BE) {
1654 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1655 netif_err(ag, intr, ndev, "TX BUS error\n");
1656 }
1657 if (status & AG71XX_INT_RX_BE) {
1658 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1659 netif_err(ag, intr, ndev, "RX BUS error\n");
1660 }
1661 }
1662
1663 if (likely(status & AG71XX_INT_POLL)) {
1664 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1665 netif_dbg(ag, intr, ndev, "enable polling mode\n");
1666 napi_schedule(&ag->napi);
1667 }
1668
1669 return IRQ_HANDLED;
1670}
1671
1672static int ag71xx_change_mtu(struct net_device *ndev, int new_mtu)
1673{
1674 struct ag71xx *ag = netdev_priv(ndev);
1675
1676 ndev->mtu = new_mtu;
1677 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
1678 ag71xx_max_frame_len(ndev->mtu));
1679
1680 return 0;
1681}
1682
1683static const struct net_device_ops ag71xx_netdev_ops = {
1684 .ndo_open = ag71xx_open,
1685 .ndo_stop = ag71xx_stop,
1686 .ndo_start_xmit = ag71xx_hard_start_xmit,
1687 .ndo_do_ioctl = phy_do_ioctl,
1688 .ndo_tx_timeout = ag71xx_tx_timeout,
1689 .ndo_change_mtu = ag71xx_change_mtu,
1690 .ndo_set_mac_address = eth_mac_addr,
1691 .ndo_validate_addr = eth_validate_addr,
1692};
1693
1694static const u32 ar71xx_addr_ar7100[] = {
1695 0x19000000, 0x1a000000,
1696};
1697
1698static int ag71xx_probe(struct platform_device *pdev)
1699{
1700 struct device_node *np = pdev->dev.of_node;
1701 const struct ag71xx_dcfg *dcfg;
1702 struct net_device *ndev;
1703 struct resource *res;
1704 const void *mac_addr;
1705 int tx_size, err, i;
1706 struct ag71xx *ag;
1707
1708 if (!np)
1709 return -ENODEV;
1710
1711 ndev = devm_alloc_etherdev(&pdev->dev, sizeof(*ag));
1712 if (!ndev)
1713 return -ENOMEM;
1714
1715 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1716 if (!res)
1717 return -EINVAL;
1718
1719 dcfg = of_device_get_match_data(&pdev->dev);
1720 if (!dcfg)
1721 return -EINVAL;
1722
1723 ag = netdev_priv(ndev);
1724 ag->mac_idx = -1;
1725 for (i = 0; i < ARRAY_SIZE(ar71xx_addr_ar7100); i++) {
1726 if (ar71xx_addr_ar7100[i] == res->start)
1727 ag->mac_idx = i;
1728 }
1729
1730 if (ag->mac_idx < 0) {
1731 netif_err(ag, probe, ndev, "unknown mac idx\n");
1732 return -EINVAL;
1733 }
1734
1735 ag->clk_eth = devm_clk_get(&pdev->dev, "eth");
1736 if (IS_ERR(ag->clk_eth)) {
1737 netif_err(ag, probe, ndev, "Failed to get eth clk.\n");
1738 return PTR_ERR(ag->clk_eth);
1739 }
1740
1741 SET_NETDEV_DEV(ndev, &pdev->dev);
1742
1743 ag->pdev = pdev;
1744 ag->ndev = ndev;
1745 ag->dcfg = dcfg;
1746 ag->msg_enable = netif_msg_init(-1, AG71XX_DEFAULT_MSG_ENABLE);
1747 memcpy(ag->fifodata, dcfg->fifodata, sizeof(ag->fifodata));
1748
1749 ag->mac_reset = devm_reset_control_get(&pdev->dev, "mac");
1750 if (IS_ERR(ag->mac_reset)) {
1751 netif_err(ag, probe, ndev, "missing mac reset\n");
1752 err = PTR_ERR(ag->mac_reset);
1753 goto err_free;
1754 }
1755
1756 ag->mac_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1757 if (!ag->mac_base) {
1758 err = -ENOMEM;
1759 goto err_free;
1760 }
1761
1762 ndev->irq = platform_get_irq(pdev, 0);
1763 err = devm_request_irq(&pdev->dev, ndev->irq, ag71xx_interrupt,
1764 0x0, dev_name(&pdev->dev), ndev);
1765 if (err) {
1766 netif_err(ag, probe, ndev, "unable to request IRQ %d\n",
1767 ndev->irq);
1768 goto err_free;
1769 }
1770
1771 ndev->netdev_ops = &ag71xx_netdev_ops;
1772
1773 INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func);
1774 timer_setup(&ag->oom_timer, ag71xx_oom_timer_handler, 0);
1775
1776 tx_size = AG71XX_TX_RING_SIZE_DEFAULT;
1777 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT);
1778
1779 ndev->min_mtu = 68;
1780 ndev->max_mtu = dcfg->max_frame_len - ag71xx_max_frame_len(0);
1781
1782 ag->rx_buf_offset = NET_SKB_PAD;
1783 if (!ag71xx_is(ag, AR7100) && !ag71xx_is(ag, AR9130))
1784 ag->rx_buf_offset += NET_IP_ALIGN;
1785
1786 if (ag71xx_is(ag, AR7100)) {
1787 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1788 tx_size *= AG71XX_TX_RING_DS_PER_PKT;
1789 }
1790 ag->tx_ring.order = ag71xx_ring_size_order(tx_size);
1791
1792 ag->stop_desc = dmam_alloc_coherent(&pdev->dev,
1793 sizeof(struct ag71xx_desc),
1794 &ag->stop_desc_dma, GFP_KERNEL);
1795 if (!ag->stop_desc) {
1796 err = -ENOMEM;
1797 goto err_free;
1798 }
1799
1800 ag->stop_desc->data = 0;
1801 ag->stop_desc->ctrl = 0;
1802 ag->stop_desc->next = (u32)ag->stop_desc_dma;
1803
1804 mac_addr = of_get_mac_address(np);
1805 if (!IS_ERR(mac_addr))
1806 memcpy(ndev->dev_addr, mac_addr, ETH_ALEN);
1807 if (IS_ERR(mac_addr) || !is_valid_ether_addr(ndev->dev_addr)) {
1808 netif_err(ag, probe, ndev, "invalid MAC address, using random address\n");
1809 eth_random_addr(ndev->dev_addr);
1810 }
1811
1812 err = of_get_phy_mode(np, &ag->phy_if_mode);
1813 if (err) {
1814 netif_err(ag, probe, ndev, "missing phy-mode property in DT\n");
1815 goto err_free;
1816 }
1817
1818 netif_napi_add(ndev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1819
1820 err = clk_prepare_enable(ag->clk_eth);
1821 if (err) {
1822 netif_err(ag, probe, ndev, "Failed to enable eth clk.\n");
1823 goto err_free;
1824 }
1825
1826 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);
1827
1828 ag71xx_hw_init(ag);
1829
1830 err = ag71xx_mdio_probe(ag);
1831 if (err)
1832 goto err_put_clk;
1833
1834 platform_set_drvdata(pdev, ndev);
1835
1836 err = ag71xx_phylink_setup(ag);
1837 if (err) {
1838 netif_err(ag, probe, ndev, "failed to setup phylink (%d)\n", err);
1839 goto err_mdio_remove;
1840 }
1841
1842 err = register_netdev(ndev);
1843 if (err) {
1844 netif_err(ag, probe, ndev, "unable to register net device\n");
1845 platform_set_drvdata(pdev, NULL);
1846 goto err_mdio_remove;
1847 }
1848
1849 netif_info(ag, probe, ndev, "Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1850 (unsigned long)ag->mac_base, ndev->irq,
1851 phy_modes(ag->phy_if_mode));
1852
1853 return 0;
1854
1855err_mdio_remove:
1856 ag71xx_mdio_remove(ag);
1857err_put_clk:
1858 clk_disable_unprepare(ag->clk_eth);
1859err_free:
1860 free_netdev(ndev);
1861 return err;
1862}
1863
1864static int ag71xx_remove(struct platform_device *pdev)
1865{
1866 struct net_device *ndev = platform_get_drvdata(pdev);
1867 struct ag71xx *ag;
1868
1869 if (!ndev)
1870 return 0;
1871
1872 ag = netdev_priv(ndev);
1873 unregister_netdev(ndev);
1874 ag71xx_mdio_remove(ag);
1875 clk_disable_unprepare(ag->clk_eth);
1876 platform_set_drvdata(pdev, NULL);
1877
1878 return 0;
1879}
1880
1881static const u32 ar71xx_fifo_ar7100[] = {
1882 0x0fff0000, 0x00001fff, 0x00780fff,
1883};
1884
1885static const u32 ar71xx_fifo_ar9130[] = {
1886 0x0fff0000, 0x00001fff, 0x008001ff,
1887};
1888
1889static const u32 ar71xx_fifo_ar9330[] = {
1890 0x0010ffff, 0x015500aa, 0x01f00140,
1891};
1892
1893static const struct ag71xx_dcfg ag71xx_dcfg_ar7100 = {
1894 .type = AR7100,
1895 .fifodata = ar71xx_fifo_ar7100,
1896 .max_frame_len = 1540,
1897 .desc_pktlen_mask = SZ_4K - 1,
1898 .tx_hang_workaround = false,
1899};
1900
1901static const struct ag71xx_dcfg ag71xx_dcfg_ar7240 = {
1902 .type = AR7240,
1903 .fifodata = ar71xx_fifo_ar7100,
1904 .max_frame_len = 1540,
1905 .desc_pktlen_mask = SZ_4K - 1,
1906 .tx_hang_workaround = true,
1907};
1908
1909static const struct ag71xx_dcfg ag71xx_dcfg_ar9130 = {
1910 .type = AR9130,
1911 .fifodata = ar71xx_fifo_ar9130,
1912 .max_frame_len = 1540,
1913 .desc_pktlen_mask = SZ_4K - 1,
1914 .tx_hang_workaround = false,
1915};
1916
1917static const struct ag71xx_dcfg ag71xx_dcfg_ar9330 = {
1918 .type = AR9330,
1919 .fifodata = ar71xx_fifo_ar9330,
1920 .max_frame_len = 1540,
1921 .desc_pktlen_mask = SZ_4K - 1,
1922 .tx_hang_workaround = true,
1923};
1924
1925static const struct ag71xx_dcfg ag71xx_dcfg_ar9340 = {
1926 .type = AR9340,
1927 .fifodata = ar71xx_fifo_ar9330,
1928 .max_frame_len = SZ_16K - 1,
1929 .desc_pktlen_mask = SZ_16K - 1,
1930 .tx_hang_workaround = true,
1931};
1932
1933static const struct ag71xx_dcfg ag71xx_dcfg_qca9530 = {
1934 .type = QCA9530,
1935 .fifodata = ar71xx_fifo_ar9330,
1936 .max_frame_len = SZ_16K - 1,
1937 .desc_pktlen_mask = SZ_16K - 1,
1938 .tx_hang_workaround = true,
1939};
1940
1941static const struct ag71xx_dcfg ag71xx_dcfg_qca9550 = {
1942 .type = QCA9550,
1943 .fifodata = ar71xx_fifo_ar9330,
1944 .max_frame_len = 1540,
1945 .desc_pktlen_mask = SZ_16K - 1,
1946 .tx_hang_workaround = true,
1947};
1948
1949static const struct of_device_id ag71xx_match[] = {
1950 { .compatible = "qca,ar7100-eth", .data = &ag71xx_dcfg_ar7100 },
1951 { .compatible = "qca,ar7240-eth", .data = &ag71xx_dcfg_ar7240 },
1952 { .compatible = "qca,ar7241-eth", .data = &ag71xx_dcfg_ar7240 },
1953 { .compatible = "qca,ar7242-eth", .data = &ag71xx_dcfg_ar7240 },
1954 { .compatible = "qca,ar9130-eth", .data = &ag71xx_dcfg_ar9130 },
1955 { .compatible = "qca,ar9330-eth", .data = &ag71xx_dcfg_ar9330 },
1956 { .compatible = "qca,ar9340-eth", .data = &ag71xx_dcfg_ar9340 },
1957 { .compatible = "qca,qca9530-eth", .data = &ag71xx_dcfg_qca9530 },
1958 { .compatible = "qca,qca9550-eth", .data = &ag71xx_dcfg_qca9550 },
1959 { .compatible = "qca,qca9560-eth", .data = &ag71xx_dcfg_qca9550 },
1960 {}
1961};
1962
1963static struct platform_driver ag71xx_driver = {
1964 .probe = ag71xx_probe,
1965 .remove = ag71xx_remove,
1966 .driver = {
1967 .name = "ag71xx",
1968 .of_match_table = ag71xx_match,
1969 }
1970};
1971
1972module_platform_driver(ag71xx_driver);
1973MODULE_LICENSE("GPL v2");