1/* This file is part of the Emulex RoCE Device Driver for
  2 * RoCE (RDMA over Converged Ethernet) adapters.
  3 * Copyright (C) 2012-2015 Emulex. All rights reserved.
  4 * EMULEX and SLI are trademarks of Emulex.
  5 * www.emulex.com
  6 *
  7 * This software is available to you under a choice of one of two licenses.
  8 * You may choose to be licensed under the terms of the GNU General Public
  9 * License (GPL) Version 2, available from the file COPYING in the main
 10 * directory of this source tree, or the BSD license below:
 11 *
 12 * Redistribution and use in source and binary forms, with or without
 13 * modification, are permitted provided that the following conditions
 14 * are met:
 15 *
 16 * - Redistributions of source code must retain the above copyright notice,
 17 *   this list of conditions and the following disclaimer.
 18 *
 19 * - Redistributions in binary form must reproduce the above copyright
 20 *   notice, this list of conditions and the following disclaimer in
 21 *   the documentation and/or other materials provided with the distribution.
 22 *
 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 34 *
 35 * Contact Information:
 36 * linux-drivers@emulex.com
 37 *
 38 * Emulex
 39 * 3333 Susan Street
 40 * Costa Mesa, CA 92626
 41 */
 42
 43#ifndef __OCRDMA_H__
 44#define __OCRDMA_H__
 45
 46#include <linux/mutex.h>
 47#include <linux/list.h>
 48#include <linux/spinlock.h>
 49#include <linux/pci.h>
 50
 51#include <rdma/ib_verbs.h>
 52#include <rdma/ib_user_verbs.h>
 53#include <rdma/ib_addr.h>
 54
 55#include <be_roce.h>
 56#include "ocrdma_sli.h"
 57
 58#define OCRDMA_ROCE_DRV_VERSION "11.0.0.0"
 59
 60#define OCRDMA_ROCE_DRV_DESC "Emulex OneConnect RoCE Driver"
 61#define OCRDMA_NODE_DESC "Emulex OneConnect RoCE HCA"
 62
 63#define OC_NAME_SH	OCRDMA_NODE_DESC "(Skyhawk)"
 64#define OC_NAME_UNKNOWN OCRDMA_NODE_DESC "(Unknown)"
 65
 66#define OC_SKH_DEVICE_PF 0x720
 67#define OC_SKH_DEVICE_VF 0x728
 68#define OCRDMA_MAX_AH 512
 69
 70#define OCRDMA_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME)
 71
 72#define convert_to_64bit(lo, hi) ((u64)hi << 32 | (u64)lo)
 73#define EQ_INTR_PER_SEC_THRSH_HI 150000
 74#define EQ_INTR_PER_SEC_THRSH_LOW 100000
 75#define EQ_AIC_MAX_EQD 20
 76#define EQ_AIC_MIN_EQD 0
 77
 78void ocrdma_eqd_set_task(struct work_struct *work);
 79
 80struct ocrdma_dev_attr {
 81	u8 fw_ver[32];
 82	u32 vendor_id;
 83	u32 device_id;
 84	u16 max_pd;
 85	u16 max_dpp_pds;
 86	u16 max_cq;
 87	u16 max_cqe;
 88	u16 max_qp;
 89	u16 max_wqe;
 90	u16 max_rqe;
 91	u16 max_srq;
 92	u32 max_inline_data;
 93	int max_send_sge;
 94	int max_recv_sge;
 95	int max_srq_sge;
 96	int max_rdma_sge;
 97	int max_mr;
 98	u64 max_mr_size;
 99	u32 max_num_mr_pbl;
100	int max_mw;
101	int max_map_per_fmr;
102	int max_pages_per_frmr;
103	u16 max_ord_per_qp;
104	u16 max_ird_per_qp;
105
106	int device_cap_flags;
107	u8 cq_overflow_detect;
108	u8 srq_supported;
109
110	u32 wqe_size;
111	u32 rqe_size;
112	u32 ird_page_size;
113	u8 local_ca_ack_delay;
114	u8 ird;
115	u8 num_ird_pages;
116	u8 udp_encap;
117};
118
119struct ocrdma_dma_mem {
120	void *va;
121	dma_addr_t pa;
122	u32 size;
123};
124
125struct ocrdma_pbl {
126	void *va;
127	dma_addr_t pa;
128};
129
130struct ocrdma_queue_info {
131	void *va;
132	dma_addr_t dma;
133	u32 size;
134	u16 len;
135	u16 entry_size;		/* Size of an element in the queue */
136	u16 id;			/* qid, where to ring the doorbell. */
137	u16 head, tail;
138	bool created;
139};
140
141struct ocrdma_aic_obj {         /* Adaptive interrupt coalescing (AIC) info */
142	u32 prev_eqd;
143	u64 eq_intr_cnt;
144	u64 prev_eq_intr_cnt;
145};
146
147struct ocrdma_eq {
148	struct ocrdma_queue_info q;
149	u32 vector;
150	int cq_cnt;
151	struct ocrdma_dev *dev;
152	char irq_name[32];
153	struct ocrdma_aic_obj aic_obj;
154};
155
156struct ocrdma_mq {
157	struct ocrdma_queue_info sq;
158	struct ocrdma_queue_info cq;
159	bool rearm_cq;
160};
161
162struct mqe_ctx {
163	struct mutex lock; /* for serializing mailbox commands on MQ */
164	wait_queue_head_t cmd_wait;
165	u32 tag;
166	u16 cqe_status;
167	u16 ext_status;
168	bool cmd_done;
169	bool fw_error_state;
170};
171
172struct ocrdma_hw_mr {
173	u32 lkey;
174	u8 fr_mr;
175	u8 remote_atomic;
176	u8 remote_rd;
177	u8 remote_wr;
178	u8 local_rd;
179	u8 local_wr;
180	u8 mw_bind;
181	u8 rsvd;
182	u64 len;
183	struct ocrdma_pbl *pbl_table;
184	u32 num_pbls;
185	u32 num_pbes;
186	u32 pbl_size;
187	u32 pbe_size;
188	u64 fbo;
189	u64 va;
190};
191
192struct ocrdma_mr {
193	struct ib_mr ibmr;
194	struct ib_umem *umem;
195	struct ocrdma_hw_mr hwmr;
196	u64 *pages;
197	u32 npages;
198};
199
200struct ocrdma_stats {
201	u8 type;
202	struct ocrdma_dev *dev;
203};
204
205struct ocrdma_pd_resource_mgr {
206	u32 pd_norm_start;
207	u16 pd_norm_count;
208	u16 pd_norm_thrsh;
209	u16 max_normal_pd;
210	u32 pd_dpp_start;
211	u16 pd_dpp_count;
212	u16 pd_dpp_thrsh;
213	u16 max_dpp_pd;
214	u16 dpp_page_index;
215	unsigned long *pd_norm_bitmap;
216	unsigned long *pd_dpp_bitmap;
217	bool pd_prealloc_valid;
218};
219
220struct stats_mem {
221	struct ocrdma_mqe mqe;
222	void *va;
223	dma_addr_t pa;
224	u32 size;
225	char *debugfs_mem;
226};
227
228struct phy_info {
229	u16 auto_speeds_supported;
230	u16 fixed_speeds_supported;
231	u16 phy_type;
232	u16 interface_type;
233};
234
235enum ocrdma_flags {
236	OCRDMA_FLAGS_LINK_STATUS_INIT = 0x01
237};
238
239struct ocrdma_dev {
240	struct ib_device ibdev;
241	struct ocrdma_dev_attr attr;
242
243	struct mutex dev_lock; /* provides syncronise access to device data */
244	spinlock_t flush_q_lock ____cacheline_aligned;
245
246	struct ocrdma_cq **cq_tbl;
247	struct ocrdma_qp **qp_tbl;
248
249	struct ocrdma_eq *eq_tbl;
250	int eq_cnt;
251	struct delayed_work eqd_work;
252	u16 base_eqid;
253	u16 max_eq;
254
255	/* provided synchronization to sgid table for
256	 * updating gid entries triggered by notifier.
257	 */
258	spinlock_t sgid_lock;
259
260	int gsi_qp_created;
261	struct ocrdma_cq *gsi_sqcq;
262	struct ocrdma_cq *gsi_rqcq;
263
264	struct {
265		struct ocrdma_av *va;
266		dma_addr_t pa;
267		u32 size;
268		u32 num_ah;
269		/* provide synchronization for av
270		 * entry allocations.
271		 */
272		spinlock_t lock;
273		u32 ahid;
274		struct ocrdma_pbl pbl;
275	} av_tbl;
276
277	void *mbx_cmd;
278	struct ocrdma_mq mq;
279	struct mqe_ctx mqe_ctx;
280
281	struct be_dev_info nic_info;
282	struct phy_info phy;
283	char model_number[32];
284	u32 hba_port_num;
285
286	struct list_head entry;
287	int id;
288	u64 *stag_arr;
289	u8 sl; /* service level */
290	bool pfc_state;
291	atomic_t update_sl;
292	u16 pvid;
293	u32 asic_id;
294	u32 flags;
295
296	ulong last_stats_time;
297	struct mutex stats_lock; /* provide synch for debugfs operations */
298	struct stats_mem stats_mem;
299	struct ocrdma_stats rsrc_stats;
300	struct ocrdma_stats rx_stats;
301	struct ocrdma_stats wqe_stats;
302	struct ocrdma_stats tx_stats;
303	struct ocrdma_stats db_err_stats;
304	struct ocrdma_stats tx_qp_err_stats;
305	struct ocrdma_stats rx_qp_err_stats;
306	struct ocrdma_stats tx_dbg_stats;
307	struct ocrdma_stats rx_dbg_stats;
308	struct ocrdma_stats driver_stats;
309	struct ocrdma_stats reset_stats;
310	struct dentry *dir;
311	atomic_t async_err_stats[OCRDMA_MAX_ASYNC_ERRORS];
312	atomic_t cqe_err_stats[OCRDMA_MAX_CQE_ERR];
313	struct ocrdma_pd_resource_mgr *pd_mgr;
314};
315
316struct ocrdma_cq {
317	struct ib_cq ibcq;
318	struct ocrdma_cqe *va;
319	u32 phase;
320	u32 getp;	/* pointer to pending wrs to
321			 * return to stack, wrap arounds
322			 * at max_hw_cqe
323			 */
324	u32 max_hw_cqe;
325	bool phase_change;
326	spinlock_t cq_lock ____cacheline_aligned; /* provide synchronization
327						   * to cq polling
328						   */
329	/* syncronizes cq completion handler invoked from multiple context */
330	spinlock_t comp_handler_lock ____cacheline_aligned;
331	u16 id;
332	u16 eqn;
333
334	struct ocrdma_ucontext *ucontext;
335	dma_addr_t pa;
336	u32 len;
337	u32 cqe_cnt;
338
339	/* head of all qp's sq and rq for which cqes need to be flushed
340	 * by the software.
341	 */
342	struct list_head sq_head, rq_head;
343};
344
345struct ocrdma_pd {
346	struct ib_pd ibpd;
347	struct ocrdma_ucontext *uctx;
348	u32 id;
349	int num_dpp_qp;
350	u32 dpp_page;
351	bool dpp_enabled;
352};
353
354struct ocrdma_ah {
355	struct ib_ah ibah;
356	struct ocrdma_av *av;
357	u16 sgid_index;
358	u32 id;
359	u8 hdr_type;
360};
361
362struct ocrdma_qp_hwq_info {
363	u8 *va;			/* virtual address */
364	u32 max_sges;
365	u32 head, tail;
366	u32 entry_size;
367	u32 max_cnt;
368	u32 max_wqe_idx;
369	u16 dbid;		/* qid, where to ring the doorbell. */
370	u32 len;
371	dma_addr_t pa;
372};
373
374struct ocrdma_srq {
375	struct ib_srq ibsrq;
376	u8 __iomem *db;
377	struct ocrdma_qp_hwq_info rq;
378	u64 *rqe_wr_id_tbl;
379	u32 *idx_bit_fields;
380	u32 bit_fields_len;
381
382	/* provide synchronization to multiple context(s) posting rqe */
383	spinlock_t q_lock ____cacheline_aligned;
384
385	struct ocrdma_pd *pd;
386	u32 id;
387};
388
389struct ocrdma_qp {
390	struct ib_qp ibqp;
391
392	u8 __iomem *sq_db;
393	struct ocrdma_qp_hwq_info sq;
394	struct {
395		uint64_t wrid;
396		uint16_t dpp_wqe_idx;
397		uint16_t dpp_wqe;
398		uint8_t  signaled;
399		uint8_t  rsvd[3];
400	} *wqe_wr_id_tbl;
401	u32 max_inline_data;
402
403	/* provide synchronization to multiple context(s) posting wqe, rqe */
404	spinlock_t q_lock ____cacheline_aligned;
405	struct ocrdma_cq *sq_cq;
406	/* list maintained per CQ to flush SQ errors */
407	struct list_head sq_entry;
408
409	u8 __iomem *rq_db;
410	struct ocrdma_qp_hwq_info rq;
411	u64 *rqe_wr_id_tbl;
412	struct ocrdma_cq *rq_cq;
413	struct ocrdma_srq *srq;
414	/* list maintained per CQ to flush RQ errors */
415	struct list_head rq_entry;
416
417	enum ocrdma_qp_state state;	/*  QP state */
418	int cap_flags;
419	u32 max_ord, max_ird;
420
421	u32 id;
422	struct ocrdma_pd *pd;
423
424	enum ib_qp_type qp_type;
425
426	int sgid_idx;
427	u32 qkey;
428	bool dpp_enabled;
429	u8 *ird_q_va;
430	bool signaled;
431};
432
433struct ocrdma_ucontext {
434	struct ib_ucontext ibucontext;
435
436	struct list_head mm_head;
437	struct mutex mm_list_lock; /* protects list entries of mm type */
438	struct ocrdma_pd *cntxt_pd;
439	int pd_in_use;
440
441	struct {
442		u32 *va;
443		dma_addr_t pa;
444		u32 len;
445	} ah_tbl;
446};
447
448struct ocrdma_mm {
449	struct {
450		u64 phy_addr;
451		unsigned long len;
452	} key;
453	struct list_head entry;
454};
455
456static inline struct ocrdma_dev *get_ocrdma_dev(struct ib_device *ibdev)
457{
458	return container_of(ibdev, struct ocrdma_dev, ibdev);
459}
460
461static inline struct ocrdma_ucontext *get_ocrdma_ucontext(struct ib_ucontext
462							  *ibucontext)
463{
464	return container_of(ibucontext, struct ocrdma_ucontext, ibucontext);
465}
466
467static inline struct ocrdma_pd *get_ocrdma_pd(struct ib_pd *ibpd)
468{
469	return container_of(ibpd, struct ocrdma_pd, ibpd);
470}
471
472static inline struct ocrdma_cq *get_ocrdma_cq(struct ib_cq *ibcq)
473{
474	return container_of(ibcq, struct ocrdma_cq, ibcq);
475}
476
477static inline struct ocrdma_qp *get_ocrdma_qp(struct ib_qp *ibqp)
478{
479	return container_of(ibqp, struct ocrdma_qp, ibqp);
480}
481
482static inline struct ocrdma_mr *get_ocrdma_mr(struct ib_mr *ibmr)
483{
484	return container_of(ibmr, struct ocrdma_mr, ibmr);
485}
486
487static inline struct ocrdma_ah *get_ocrdma_ah(struct ib_ah *ibah)
488{
489	return container_of(ibah, struct ocrdma_ah, ibah);
490}
491
492static inline struct ocrdma_srq *get_ocrdma_srq(struct ib_srq *ibsrq)
493{
494	return container_of(ibsrq, struct ocrdma_srq, ibsrq);
495}
496
497static inline int is_cqe_valid(struct ocrdma_cq *cq, struct ocrdma_cqe *cqe)
498{
499	int cqe_valid;
500	cqe_valid = le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_VALID;
501	return (cqe_valid == cq->phase);
502}
503
504static inline int is_cqe_for_sq(struct ocrdma_cqe *cqe)
505{
506	return (le32_to_cpu(cqe->flags_status_srcqpn) &
507		OCRDMA_CQE_QTYPE) ? 0 : 1;
508}
509
510static inline int is_cqe_invalidated(struct ocrdma_cqe *cqe)
511{
512	return (le32_to_cpu(cqe->flags_status_srcqpn) &
513		OCRDMA_CQE_INVALIDATE) ? 1 : 0;
514}
515
516static inline int is_cqe_imm(struct ocrdma_cqe *cqe)
517{
518	return (le32_to_cpu(cqe->flags_status_srcqpn) &
519		OCRDMA_CQE_IMM) ? 1 : 0;
520}
521
522static inline int is_cqe_wr_imm(struct ocrdma_cqe *cqe)
523{
524	return (le32_to_cpu(cqe->flags_status_srcqpn) &
525		OCRDMA_CQE_WRITE_IMM) ? 1 : 0;
526}
527
528static inline int ocrdma_resolve_dmac(struct ocrdma_dev *dev,
529		struct rdma_ah_attr *ah_attr, u8 *mac_addr)
530{
531	struct in6_addr in6;
532
533	memcpy(&in6, rdma_ah_read_grh(ah_attr)->dgid.raw, sizeof(in6));
534	if (rdma_is_multicast_addr(&in6))
535		rdma_get_mcast_mac(&in6, mac_addr);
536	else if (rdma_link_local_addr(&in6))
537		rdma_get_ll_mac(&in6, mac_addr);
538	else
539		memcpy(mac_addr, ah_attr->roce.dmac, ETH_ALEN);
540	return 0;
541}
542
543static inline char *hca_name(struct ocrdma_dev *dev)
544{
545	switch (dev->nic_info.pdev->device) {
546	case OC_SKH_DEVICE_PF:
547	case OC_SKH_DEVICE_VF:
548		return OC_NAME_SH;
549	default:
550		return OC_NAME_UNKNOWN;
551	}
552}
553
554static inline int ocrdma_get_eq_table_index(struct ocrdma_dev *dev,
555		int eqid)
556{
557	int indx;
558
559	for (indx = 0; indx < dev->eq_cnt; indx++) {
560		if (dev->eq_tbl[indx].q.id == eqid)
561			return indx;
562	}
563
564	return -EINVAL;
565}
566
567static inline u8 ocrdma_get_asic_type(struct ocrdma_dev *dev)
568{
569	if (dev->nic_info.dev_family == 0xF && !dev->asic_id) {
570		pci_read_config_dword(
571			dev->nic_info.pdev,
572			OCRDMA_SLI_ASIC_ID_OFFSET, &dev->asic_id);
573	}
574
575	return (dev->asic_id & OCRDMA_SLI_ASIC_GEN_NUM_MASK) >>
576				OCRDMA_SLI_ASIC_GEN_NUM_SHIFT;
577}
578
579static inline u8 ocrdma_get_pfc_prio(u8 *pfc, u8 prio)
580{
581	return *(pfc + prio);
582}
583
584static inline u8 ocrdma_get_app_prio(u8 *app_prio, u8 prio)
585{
586	return *(app_prio + prio);
587}
588
589static inline u8 ocrdma_is_enabled_and_synced(u32 state)
590{	/* May also be used to interpret TC-state, QCN-state
591	 * Appl-state and Logical-link-state in future.
592	 */
593	return (state & OCRDMA_STATE_FLAG_ENABLED) &&
594		(state & OCRDMA_STATE_FLAG_SYNC);
595}
596
597static inline u8 ocrdma_get_ae_link_state(u32 ae_state)
598{
599	return ((ae_state & OCRDMA_AE_LSC_LS_MASK) >> OCRDMA_AE_LSC_LS_SHIFT);
600}
601
602static inline bool ocrdma_is_udp_encap_supported(struct ocrdma_dev *dev)
603{
604	return (dev->attr.udp_encap & OCRDMA_L3_TYPE_IPV4) ||
605	       (dev->attr.udp_encap & OCRDMA_L3_TYPE_IPV6);
606}
607
608#endif