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1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#include <linux/mlx4/cq.h>
35#include <linux/mlx4/qp.h>
36#include <linux/slab.h>
37
38#include "mlx4_ib.h"
39#include "user.h"
40
41static void mlx4_ib_cq_comp(struct mlx4_cq *cq)
42{
43 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
44 ibcq->comp_handler(ibcq, ibcq->cq_context);
45}
46
47static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type)
48{
49 struct ib_event event;
50 struct ib_cq *ibcq;
51
52 if (type != MLX4_EVENT_TYPE_CQ_ERROR) {
53 printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
54 "on CQ %06x\n", type, cq->cqn);
55 return;
56 }
57
58 ibcq = &to_mibcq(cq)->ibcq;
59 if (ibcq->event_handler) {
60 event.device = ibcq->device;
61 event.event = IB_EVENT_CQ_ERR;
62 event.element.cq = ibcq;
63 ibcq->event_handler(&event, ibcq->cq_context);
64 }
65}
66
67static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n)
68{
69 return mlx4_buf_offset(&buf->buf, n * sizeof (struct mlx4_cqe));
70}
71
72static void *get_cqe(struct mlx4_ib_cq *cq, int n)
73{
74 return get_cqe_from_buf(&cq->buf, n);
75}
76
77static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n)
78{
79 struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe);
80
81 return (!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
82 !!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe;
83}
84
85static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq)
86{
87 return get_sw_cqe(cq, cq->mcq.cons_index);
88}
89
90int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
91{
92 struct mlx4_ib_cq *mcq = to_mcq(cq);
93 struct mlx4_ib_dev *dev = to_mdev(cq->device);
94
95 return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period);
96}
97
98static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent)
99{
100 int err;
101
102 err = mlx4_buf_alloc(dev->dev, nent * sizeof(struct mlx4_cqe),
103 PAGE_SIZE * 2, &buf->buf);
104
105 if (err)
106 goto out;
107
108 err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift,
109 &buf->mtt);
110 if (err)
111 goto err_buf;
112
113 err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf);
114 if (err)
115 goto err_mtt;
116
117 return 0;
118
119err_mtt:
120 mlx4_mtt_cleanup(dev->dev, &buf->mtt);
121
122err_buf:
123 mlx4_buf_free(dev->dev, nent * sizeof(struct mlx4_cqe),
124 &buf->buf);
125
126out:
127 return err;
128}
129
130static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe)
131{
132 mlx4_buf_free(dev->dev, (cqe + 1) * sizeof(struct mlx4_cqe), &buf->buf);
133}
134
135static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, struct ib_ucontext *context,
136 struct mlx4_ib_cq_buf *buf, struct ib_umem **umem,
137 u64 buf_addr, int cqe)
138{
139 int err;
140
141 *umem = ib_umem_get(context, buf_addr, cqe * sizeof (struct mlx4_cqe),
142 IB_ACCESS_LOCAL_WRITE, 1);
143 if (IS_ERR(*umem))
144 return PTR_ERR(*umem);
145
146 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(*umem),
147 ilog2((*umem)->page_size), &buf->mtt);
148 if (err)
149 goto err_buf;
150
151 err = mlx4_ib_umem_write_mtt(dev, &buf->mtt, *umem);
152 if (err)
153 goto err_mtt;
154
155 return 0;
156
157err_mtt:
158 mlx4_mtt_cleanup(dev->dev, &buf->mtt);
159
160err_buf:
161 ib_umem_release(*umem);
162
163 return err;
164}
165
166struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev, int entries, int vector,
167 struct ib_ucontext *context,
168 struct ib_udata *udata)
169{
170 struct mlx4_ib_dev *dev = to_mdev(ibdev);
171 struct mlx4_ib_cq *cq;
172 struct mlx4_uar *uar;
173 int err;
174
175 if (entries < 1 || entries > dev->dev->caps.max_cqes)
176 return ERR_PTR(-EINVAL);
177
178 cq = kmalloc(sizeof *cq, GFP_KERNEL);
179 if (!cq)
180 return ERR_PTR(-ENOMEM);
181
182 entries = roundup_pow_of_two(entries + 1);
183 cq->ibcq.cqe = entries - 1;
184 mutex_init(&cq->resize_mutex);
185 spin_lock_init(&cq->lock);
186 cq->resize_buf = NULL;
187 cq->resize_umem = NULL;
188
189 if (context) {
190 struct mlx4_ib_create_cq ucmd;
191
192 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
193 err = -EFAULT;
194 goto err_cq;
195 }
196
197 err = mlx4_ib_get_cq_umem(dev, context, &cq->buf, &cq->umem,
198 ucmd.buf_addr, entries);
199 if (err)
200 goto err_cq;
201
202 err = mlx4_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
203 &cq->db);
204 if (err)
205 goto err_mtt;
206
207 uar = &to_mucontext(context)->uar;
208 } else {
209 err = mlx4_db_alloc(dev->dev, &cq->db, 1);
210 if (err)
211 goto err_cq;
212
213 cq->mcq.set_ci_db = cq->db.db;
214 cq->mcq.arm_db = cq->db.db + 1;
215 *cq->mcq.set_ci_db = 0;
216 *cq->mcq.arm_db = 0;
217
218 err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries);
219 if (err)
220 goto err_db;
221
222 uar = &dev->priv_uar;
223 }
224
225 err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar,
226 cq->db.dma, &cq->mcq, vector, 0);
227 if (err)
228 goto err_dbmap;
229
230 cq->mcq.comp = mlx4_ib_cq_comp;
231 cq->mcq.event = mlx4_ib_cq_event;
232
233 if (context)
234 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) {
235 err = -EFAULT;
236 goto err_dbmap;
237 }
238
239 return &cq->ibcq;
240
241err_dbmap:
242 if (context)
243 mlx4_ib_db_unmap_user(to_mucontext(context), &cq->db);
244
245err_mtt:
246 mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt);
247
248 if (context)
249 ib_umem_release(cq->umem);
250 else
251 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
252
253err_db:
254 if (!context)
255 mlx4_db_free(dev->dev, &cq->db);
256
257err_cq:
258 kfree(cq);
259
260 return ERR_PTR(err);
261}
262
263static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
264 int entries)
265{
266 int err;
267
268 if (cq->resize_buf)
269 return -EBUSY;
270
271 cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC);
272 if (!cq->resize_buf)
273 return -ENOMEM;
274
275 err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries);
276 if (err) {
277 kfree(cq->resize_buf);
278 cq->resize_buf = NULL;
279 return err;
280 }
281
282 cq->resize_buf->cqe = entries - 1;
283
284 return 0;
285}
286
287static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
288 int entries, struct ib_udata *udata)
289{
290 struct mlx4_ib_resize_cq ucmd;
291 int err;
292
293 if (cq->resize_umem)
294 return -EBUSY;
295
296 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd))
297 return -EFAULT;
298
299 cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC);
300 if (!cq->resize_buf)
301 return -ENOMEM;
302
303 err = mlx4_ib_get_cq_umem(dev, cq->umem->context, &cq->resize_buf->buf,
304 &cq->resize_umem, ucmd.buf_addr, entries);
305 if (err) {
306 kfree(cq->resize_buf);
307 cq->resize_buf = NULL;
308 return err;
309 }
310
311 cq->resize_buf->cqe = entries - 1;
312
313 return 0;
314}
315
316static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq)
317{
318 u32 i;
319
320 i = cq->mcq.cons_index;
321 while (get_sw_cqe(cq, i & cq->ibcq.cqe))
322 ++i;
323
324 return i - cq->mcq.cons_index;
325}
326
327static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq)
328{
329 struct mlx4_cqe *cqe, *new_cqe;
330 int i;
331
332 i = cq->mcq.cons_index;
333 cqe = get_cqe(cq, i & cq->ibcq.cqe);
334 while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) {
335 new_cqe = get_cqe_from_buf(&cq->resize_buf->buf,
336 (i + 1) & cq->resize_buf->cqe);
337 memcpy(new_cqe, get_cqe(cq, i & cq->ibcq.cqe), sizeof(struct mlx4_cqe));
338 new_cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) |
339 (((i + 1) & (cq->resize_buf->cqe + 1)) ? MLX4_CQE_OWNER_MASK : 0);
340 cqe = get_cqe(cq, ++i & cq->ibcq.cqe);
341 }
342 ++cq->mcq.cons_index;
343}
344
345int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
346{
347 struct mlx4_ib_dev *dev = to_mdev(ibcq->device);
348 struct mlx4_ib_cq *cq = to_mcq(ibcq);
349 struct mlx4_mtt mtt;
350 int outst_cqe;
351 int err;
352
353 mutex_lock(&cq->resize_mutex);
354
355 if (entries < 1 || entries > dev->dev->caps.max_cqes) {
356 err = -EINVAL;
357 goto out;
358 }
359
360 entries = roundup_pow_of_two(entries + 1);
361 if (entries == ibcq->cqe + 1) {
362 err = 0;
363 goto out;
364 }
365
366 if (ibcq->uobject) {
367 err = mlx4_alloc_resize_umem(dev, cq, entries, udata);
368 if (err)
369 goto out;
370 } else {
371 /* Can't be smaller than the number of outstanding CQEs */
372 outst_cqe = mlx4_ib_get_outstanding_cqes(cq);
373 if (entries < outst_cqe + 1) {
374 err = 0;
375 goto out;
376 }
377
378 err = mlx4_alloc_resize_buf(dev, cq, entries);
379 if (err)
380 goto out;
381 }
382
383 mtt = cq->buf.mtt;
384
385 err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt);
386 if (err)
387 goto err_buf;
388
389 mlx4_mtt_cleanup(dev->dev, &mtt);
390 if (ibcq->uobject) {
391 cq->buf = cq->resize_buf->buf;
392 cq->ibcq.cqe = cq->resize_buf->cqe;
393 ib_umem_release(cq->umem);
394 cq->umem = cq->resize_umem;
395
396 kfree(cq->resize_buf);
397 cq->resize_buf = NULL;
398 cq->resize_umem = NULL;
399 } else {
400 struct mlx4_ib_cq_buf tmp_buf;
401 int tmp_cqe = 0;
402
403 spin_lock_irq(&cq->lock);
404 if (cq->resize_buf) {
405 mlx4_ib_cq_resize_copy_cqes(cq);
406 tmp_buf = cq->buf;
407 tmp_cqe = cq->ibcq.cqe;
408 cq->buf = cq->resize_buf->buf;
409 cq->ibcq.cqe = cq->resize_buf->cqe;
410
411 kfree(cq->resize_buf);
412 cq->resize_buf = NULL;
413 }
414 spin_unlock_irq(&cq->lock);
415
416 if (tmp_cqe)
417 mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe);
418 }
419
420 goto out;
421
422err_buf:
423 mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt);
424 if (!ibcq->uobject)
425 mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf,
426 cq->resize_buf->cqe);
427
428 kfree(cq->resize_buf);
429 cq->resize_buf = NULL;
430
431 if (cq->resize_umem) {
432 ib_umem_release(cq->resize_umem);
433 cq->resize_umem = NULL;
434 }
435
436out:
437 mutex_unlock(&cq->resize_mutex);
438 return err;
439}
440
441int mlx4_ib_destroy_cq(struct ib_cq *cq)
442{
443 struct mlx4_ib_dev *dev = to_mdev(cq->device);
444 struct mlx4_ib_cq *mcq = to_mcq(cq);
445
446 mlx4_cq_free(dev->dev, &mcq->mcq);
447 mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt);
448
449 if (cq->uobject) {
450 mlx4_ib_db_unmap_user(to_mucontext(cq->uobject->context), &mcq->db);
451 ib_umem_release(mcq->umem);
452 } else {
453 mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe);
454 mlx4_db_free(dev->dev, &mcq->db);
455 }
456
457 kfree(mcq);
458
459 return 0;
460}
461
462static void dump_cqe(void *cqe)
463{
464 __be32 *buf = cqe;
465
466 printk(KERN_DEBUG "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
467 be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]),
468 be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]),
469 be32_to_cpu(buf[6]), be32_to_cpu(buf[7]));
470}
471
472static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe,
473 struct ib_wc *wc)
474{
475 if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) {
476 printk(KERN_DEBUG "local QP operation err "
477 "(QPN %06x, WQE index %x, vendor syndrome %02x, "
478 "opcode = %02x)\n",
479 be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index),
480 cqe->vendor_err_syndrome,
481 cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
482 dump_cqe(cqe);
483 }
484
485 switch (cqe->syndrome) {
486 case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR:
487 wc->status = IB_WC_LOC_LEN_ERR;
488 break;
489 case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR:
490 wc->status = IB_WC_LOC_QP_OP_ERR;
491 break;
492 case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR:
493 wc->status = IB_WC_LOC_PROT_ERR;
494 break;
495 case MLX4_CQE_SYNDROME_WR_FLUSH_ERR:
496 wc->status = IB_WC_WR_FLUSH_ERR;
497 break;
498 case MLX4_CQE_SYNDROME_MW_BIND_ERR:
499 wc->status = IB_WC_MW_BIND_ERR;
500 break;
501 case MLX4_CQE_SYNDROME_BAD_RESP_ERR:
502 wc->status = IB_WC_BAD_RESP_ERR;
503 break;
504 case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR:
505 wc->status = IB_WC_LOC_ACCESS_ERR;
506 break;
507 case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
508 wc->status = IB_WC_REM_INV_REQ_ERR;
509 break;
510 case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR:
511 wc->status = IB_WC_REM_ACCESS_ERR;
512 break;
513 case MLX4_CQE_SYNDROME_REMOTE_OP_ERR:
514 wc->status = IB_WC_REM_OP_ERR;
515 break;
516 case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
517 wc->status = IB_WC_RETRY_EXC_ERR;
518 break;
519 case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
520 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
521 break;
522 case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR:
523 wc->status = IB_WC_REM_ABORT_ERR;
524 break;
525 default:
526 wc->status = IB_WC_GENERAL_ERR;
527 break;
528 }
529
530 wc->vendor_err = cqe->vendor_err_syndrome;
531}
532
533static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum)
534{
535 return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
536 MLX4_CQE_STATUS_IPV4F |
537 MLX4_CQE_STATUS_IPV4OPT |
538 MLX4_CQE_STATUS_IPV6 |
539 MLX4_CQE_STATUS_IPOK)) ==
540 cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
541 MLX4_CQE_STATUS_IPOK)) &&
542 (status & cpu_to_be16(MLX4_CQE_STATUS_UDP |
543 MLX4_CQE_STATUS_TCP)) &&
544 checksum == cpu_to_be16(0xffff);
545}
546
547static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq,
548 struct mlx4_ib_qp **cur_qp,
549 struct ib_wc *wc)
550{
551 struct mlx4_cqe *cqe;
552 struct mlx4_qp *mqp;
553 struct mlx4_ib_wq *wq;
554 struct mlx4_ib_srq *srq;
555 int is_send;
556 int is_error;
557 u32 g_mlpath_rqpn;
558 u16 wqe_ctr;
559
560repoll:
561 cqe = next_cqe_sw(cq);
562 if (!cqe)
563 return -EAGAIN;
564
565 ++cq->mcq.cons_index;
566
567 /*
568 * Make sure we read CQ entry contents after we've checked the
569 * ownership bit.
570 */
571 rmb();
572
573 is_send = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK;
574 is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
575 MLX4_CQE_OPCODE_ERROR;
576
577 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_OPCODE_NOP &&
578 is_send)) {
579 printk(KERN_WARNING "Completion for NOP opcode detected!\n");
580 return -EINVAL;
581 }
582
583 /* Resize CQ in progress */
584 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) {
585 if (cq->resize_buf) {
586 struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device);
587
588 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
589 cq->buf = cq->resize_buf->buf;
590 cq->ibcq.cqe = cq->resize_buf->cqe;
591
592 kfree(cq->resize_buf);
593 cq->resize_buf = NULL;
594 }
595
596 goto repoll;
597 }
598
599 if (!*cur_qp ||
600 (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) {
601 /*
602 * We do not have to take the QP table lock here,
603 * because CQs will be locked while QPs are removed
604 * from the table.
605 */
606 mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev,
607 be32_to_cpu(cqe->vlan_my_qpn));
608 if (unlikely(!mqp)) {
609 printk(KERN_WARNING "CQ %06x with entry for unknown QPN %06x\n",
610 cq->mcq.cqn, be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK);
611 return -EINVAL;
612 }
613
614 *cur_qp = to_mibqp(mqp);
615 }
616
617 wc->qp = &(*cur_qp)->ibqp;
618
619 if (is_send) {
620 wq = &(*cur_qp)->sq;
621 if (!(*cur_qp)->sq_signal_bits) {
622 wqe_ctr = be16_to_cpu(cqe->wqe_index);
623 wq->tail += (u16) (wqe_ctr - (u16) wq->tail);
624 }
625 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
626 ++wq->tail;
627 } else if ((*cur_qp)->ibqp.srq) {
628 srq = to_msrq((*cur_qp)->ibqp.srq);
629 wqe_ctr = be16_to_cpu(cqe->wqe_index);
630 wc->wr_id = srq->wrid[wqe_ctr];
631 mlx4_ib_free_srq_wqe(srq, wqe_ctr);
632 } else {
633 wq = &(*cur_qp)->rq;
634 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
635 ++wq->tail;
636 }
637
638 if (unlikely(is_error)) {
639 mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc);
640 return 0;
641 }
642
643 wc->status = IB_WC_SUCCESS;
644
645 if (is_send) {
646 wc->wc_flags = 0;
647 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
648 case MLX4_OPCODE_RDMA_WRITE_IMM:
649 wc->wc_flags |= IB_WC_WITH_IMM;
650 case MLX4_OPCODE_RDMA_WRITE:
651 wc->opcode = IB_WC_RDMA_WRITE;
652 break;
653 case MLX4_OPCODE_SEND_IMM:
654 wc->wc_flags |= IB_WC_WITH_IMM;
655 case MLX4_OPCODE_SEND:
656 case MLX4_OPCODE_SEND_INVAL:
657 wc->opcode = IB_WC_SEND;
658 break;
659 case MLX4_OPCODE_RDMA_READ:
660 wc->opcode = IB_WC_RDMA_READ;
661 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
662 break;
663 case MLX4_OPCODE_ATOMIC_CS:
664 wc->opcode = IB_WC_COMP_SWAP;
665 wc->byte_len = 8;
666 break;
667 case MLX4_OPCODE_ATOMIC_FA:
668 wc->opcode = IB_WC_FETCH_ADD;
669 wc->byte_len = 8;
670 break;
671 case MLX4_OPCODE_MASKED_ATOMIC_CS:
672 wc->opcode = IB_WC_MASKED_COMP_SWAP;
673 wc->byte_len = 8;
674 break;
675 case MLX4_OPCODE_MASKED_ATOMIC_FA:
676 wc->opcode = IB_WC_MASKED_FETCH_ADD;
677 wc->byte_len = 8;
678 break;
679 case MLX4_OPCODE_BIND_MW:
680 wc->opcode = IB_WC_BIND_MW;
681 break;
682 case MLX4_OPCODE_LSO:
683 wc->opcode = IB_WC_LSO;
684 break;
685 case MLX4_OPCODE_FMR:
686 wc->opcode = IB_WC_FAST_REG_MR;
687 break;
688 case MLX4_OPCODE_LOCAL_INVAL:
689 wc->opcode = IB_WC_LOCAL_INV;
690 break;
691 }
692 } else {
693 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
694
695 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
696 case MLX4_RECV_OPCODE_RDMA_WRITE_IMM:
697 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
698 wc->wc_flags = IB_WC_WITH_IMM;
699 wc->ex.imm_data = cqe->immed_rss_invalid;
700 break;
701 case MLX4_RECV_OPCODE_SEND_INVAL:
702 wc->opcode = IB_WC_RECV;
703 wc->wc_flags = IB_WC_WITH_INVALIDATE;
704 wc->ex.invalidate_rkey = be32_to_cpu(cqe->immed_rss_invalid);
705 break;
706 case MLX4_RECV_OPCODE_SEND:
707 wc->opcode = IB_WC_RECV;
708 wc->wc_flags = 0;
709 break;
710 case MLX4_RECV_OPCODE_SEND_IMM:
711 wc->opcode = IB_WC_RECV;
712 wc->wc_flags = IB_WC_WITH_IMM;
713 wc->ex.imm_data = cqe->immed_rss_invalid;
714 break;
715 }
716
717 wc->slid = be16_to_cpu(cqe->rlid);
718 wc->sl = be16_to_cpu(cqe->sl_vid) >> 12;
719 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
720 wc->src_qp = g_mlpath_rqpn & 0xffffff;
721 wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;
722 wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0;
723 wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f;
724 wc->csum_ok = mlx4_ib_ipoib_csum_ok(cqe->status, cqe->checksum);
725 }
726
727 return 0;
728}
729
730int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
731{
732 struct mlx4_ib_cq *cq = to_mcq(ibcq);
733 struct mlx4_ib_qp *cur_qp = NULL;
734 unsigned long flags;
735 int npolled;
736 int err = 0;
737
738 spin_lock_irqsave(&cq->lock, flags);
739
740 for (npolled = 0; npolled < num_entries; ++npolled) {
741 err = mlx4_ib_poll_one(cq, &cur_qp, wc + npolled);
742 if (err)
743 break;
744 }
745
746 if (npolled)
747 mlx4_cq_set_ci(&cq->mcq);
748
749 spin_unlock_irqrestore(&cq->lock, flags);
750
751 if (err == 0 || err == -EAGAIN)
752 return npolled;
753 else
754 return err;
755}
756
757int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
758{
759 mlx4_cq_arm(&to_mcq(ibcq)->mcq,
760 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
761 MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT,
762 to_mdev(ibcq->device)->uar_map,
763 MLX4_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->uar_lock));
764
765 return 0;
766}
767
768void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
769{
770 u32 prod_index;
771 int nfreed = 0;
772 struct mlx4_cqe *cqe, *dest;
773 u8 owner_bit;
774
775 /*
776 * First we need to find the current producer index, so we
777 * know where to start cleaning from. It doesn't matter if HW
778 * adds new entries after this loop -- the QP we're worried
779 * about is already in RESET, so the new entries won't come
780 * from our QP and therefore don't need to be checked.
781 */
782 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index)
783 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
784 break;
785
786 /*
787 * Now sweep backwards through the CQ, removing CQ entries
788 * that match our QP by copying older entries on top of them.
789 */
790 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
791 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
792 if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) {
793 if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK))
794 mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index));
795 ++nfreed;
796 } else if (nfreed) {
797 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
798 owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK;
799 memcpy(dest, cqe, sizeof *cqe);
800 dest->owner_sr_opcode = owner_bit |
801 (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
802 }
803 }
804
805 if (nfreed) {
806 cq->mcq.cons_index += nfreed;
807 /*
808 * Make sure update of buffer contents is done before
809 * updating consumer index.
810 */
811 wmb();
812 mlx4_cq_set_ci(&cq->mcq);
813 }
814}
815
816void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
817{
818 spin_lock_irq(&cq->lock);
819 __mlx4_ib_cq_clean(cq, qpn, srq);
820 spin_unlock_irq(&cq->lock);
821}
1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#include <linux/mlx4/cq.h>
35#include <linux/mlx4/qp.h>
36#include <linux/mlx4/srq.h>
37#include <linux/slab.h>
38
39#include "mlx4_ib.h"
40#include <rdma/mlx4-abi.h>
41#include <rdma/uverbs_ioctl.h>
42
43static void mlx4_ib_cq_comp(struct mlx4_cq *cq)
44{
45 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
46 ibcq->comp_handler(ibcq, ibcq->cq_context);
47}
48
49static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type)
50{
51 struct ib_event event;
52 struct ib_cq *ibcq;
53
54 if (type != MLX4_EVENT_TYPE_CQ_ERROR) {
55 pr_warn("Unexpected event type %d "
56 "on CQ %06x\n", type, cq->cqn);
57 return;
58 }
59
60 ibcq = &to_mibcq(cq)->ibcq;
61 if (ibcq->event_handler) {
62 event.device = ibcq->device;
63 event.event = IB_EVENT_CQ_ERR;
64 event.element.cq = ibcq;
65 ibcq->event_handler(&event, ibcq->cq_context);
66 }
67}
68
69static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n)
70{
71 return mlx4_buf_offset(&buf->buf, n * buf->entry_size);
72}
73
74static void *get_cqe(struct mlx4_ib_cq *cq, int n)
75{
76 return get_cqe_from_buf(&cq->buf, n);
77}
78
79static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n)
80{
81 struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe);
82 struct mlx4_cqe *tcqe = ((cq->buf.entry_size == 64) ? (cqe + 1) : cqe);
83
84 return (!!(tcqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
85 !!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe;
86}
87
88static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq)
89{
90 return get_sw_cqe(cq, cq->mcq.cons_index);
91}
92
93int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
94{
95 struct mlx4_ib_cq *mcq = to_mcq(cq);
96 struct mlx4_ib_dev *dev = to_mdev(cq->device);
97
98 return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period);
99}
100
101static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent)
102{
103 int err;
104
105 err = mlx4_buf_alloc(dev->dev, nent * dev->dev->caps.cqe_size,
106 PAGE_SIZE * 2, &buf->buf);
107
108 if (err)
109 goto out;
110
111 buf->entry_size = dev->dev->caps.cqe_size;
112 err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift,
113 &buf->mtt);
114 if (err)
115 goto err_buf;
116
117 err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf);
118 if (err)
119 goto err_mtt;
120
121 return 0;
122
123err_mtt:
124 mlx4_mtt_cleanup(dev->dev, &buf->mtt);
125
126err_buf:
127 mlx4_buf_free(dev->dev, nent * buf->entry_size, &buf->buf);
128
129out:
130 return err;
131}
132
133static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe)
134{
135 mlx4_buf_free(dev->dev, (cqe + 1) * buf->entry_size, &buf->buf);
136}
137
138static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, struct ib_udata *udata,
139 struct mlx4_ib_cq_buf *buf,
140 struct ib_umem **umem, u64 buf_addr, int cqe)
141{
142 int err;
143 int cqe_size = dev->dev->caps.cqe_size;
144 int shift;
145 int n;
146
147 *umem = ib_umem_get(&dev->ib_dev, buf_addr, cqe * cqe_size,
148 IB_ACCESS_LOCAL_WRITE);
149 if (IS_ERR(*umem))
150 return PTR_ERR(*umem);
151
152 n = ib_umem_page_count(*umem);
153 shift = mlx4_ib_umem_calc_optimal_mtt_size(*umem, 0, &n);
154 err = mlx4_mtt_init(dev->dev, n, shift, &buf->mtt);
155
156 if (err)
157 goto err_buf;
158
159 err = mlx4_ib_umem_write_mtt(dev, &buf->mtt, *umem);
160 if (err)
161 goto err_mtt;
162
163 return 0;
164
165err_mtt:
166 mlx4_mtt_cleanup(dev->dev, &buf->mtt);
167
168err_buf:
169 ib_umem_release(*umem);
170
171 return err;
172}
173
174#define CQ_CREATE_FLAGS_SUPPORTED IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION
175int mlx4_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
176 struct ib_udata *udata)
177{
178 struct ib_device *ibdev = ibcq->device;
179 int entries = attr->cqe;
180 int vector = attr->comp_vector;
181 struct mlx4_ib_dev *dev = to_mdev(ibdev);
182 struct mlx4_ib_cq *cq = to_mcq(ibcq);
183 struct mlx4_uar *uar;
184 void *buf_addr;
185 int err;
186 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context(
187 udata, struct mlx4_ib_ucontext, ibucontext);
188
189 if (entries < 1 || entries > dev->dev->caps.max_cqes)
190 return -EINVAL;
191
192 if (attr->flags & ~CQ_CREATE_FLAGS_SUPPORTED)
193 return -EINVAL;
194
195 entries = roundup_pow_of_two(entries + 1);
196 cq->ibcq.cqe = entries - 1;
197 mutex_init(&cq->resize_mutex);
198 spin_lock_init(&cq->lock);
199 cq->resize_buf = NULL;
200 cq->resize_umem = NULL;
201 cq->create_flags = attr->flags;
202 INIT_LIST_HEAD(&cq->send_qp_list);
203 INIT_LIST_HEAD(&cq->recv_qp_list);
204
205 if (udata) {
206 struct mlx4_ib_create_cq ucmd;
207
208 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
209 err = -EFAULT;
210 goto err_cq;
211 }
212
213 buf_addr = (void *)(unsigned long)ucmd.buf_addr;
214 err = mlx4_ib_get_cq_umem(dev, udata, &cq->buf, &cq->umem,
215 ucmd.buf_addr, entries);
216 if (err)
217 goto err_cq;
218
219 err = mlx4_ib_db_map_user(udata, ucmd.db_addr, &cq->db);
220 if (err)
221 goto err_mtt;
222
223 uar = &context->uar;
224 cq->mcq.usage = MLX4_RES_USAGE_USER_VERBS;
225 } else {
226 err = mlx4_db_alloc(dev->dev, &cq->db, 1);
227 if (err)
228 goto err_cq;
229
230 cq->mcq.set_ci_db = cq->db.db;
231 cq->mcq.arm_db = cq->db.db + 1;
232 *cq->mcq.set_ci_db = 0;
233 *cq->mcq.arm_db = 0;
234
235 err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries);
236 if (err)
237 goto err_db;
238
239 buf_addr = &cq->buf.buf;
240
241 uar = &dev->priv_uar;
242 cq->mcq.usage = MLX4_RES_USAGE_DRIVER;
243 }
244
245 if (dev->eq_table)
246 vector = dev->eq_table[vector % ibdev->num_comp_vectors];
247
248 err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar, cq->db.dma,
249 &cq->mcq, vector, 0,
250 !!(cq->create_flags &
251 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION),
252 buf_addr, !!udata);
253 if (err)
254 goto err_dbmap;
255
256 if (udata)
257 cq->mcq.tasklet_ctx.comp = mlx4_ib_cq_comp;
258 else
259 cq->mcq.comp = mlx4_ib_cq_comp;
260 cq->mcq.event = mlx4_ib_cq_event;
261
262 if (udata)
263 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) {
264 err = -EFAULT;
265 goto err_cq_free;
266 }
267
268 return 0;
269
270err_cq_free:
271 mlx4_cq_free(dev->dev, &cq->mcq);
272
273err_dbmap:
274 if (udata)
275 mlx4_ib_db_unmap_user(context, &cq->db);
276
277err_mtt:
278 mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt);
279
280 ib_umem_release(cq->umem);
281 if (!udata)
282 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
283
284err_db:
285 if (!udata)
286 mlx4_db_free(dev->dev, &cq->db);
287err_cq:
288 return err;
289}
290
291static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
292 int entries)
293{
294 int err;
295
296 if (cq->resize_buf)
297 return -EBUSY;
298
299 cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_KERNEL);
300 if (!cq->resize_buf)
301 return -ENOMEM;
302
303 err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries);
304 if (err) {
305 kfree(cq->resize_buf);
306 cq->resize_buf = NULL;
307 return err;
308 }
309
310 cq->resize_buf->cqe = entries - 1;
311
312 return 0;
313}
314
315static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
316 int entries, struct ib_udata *udata)
317{
318 struct mlx4_ib_resize_cq ucmd;
319 int err;
320
321 if (cq->resize_umem)
322 return -EBUSY;
323
324 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd))
325 return -EFAULT;
326
327 cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_KERNEL);
328 if (!cq->resize_buf)
329 return -ENOMEM;
330
331 err = mlx4_ib_get_cq_umem(dev, udata, &cq->resize_buf->buf,
332 &cq->resize_umem, ucmd.buf_addr, entries);
333 if (err) {
334 kfree(cq->resize_buf);
335 cq->resize_buf = NULL;
336 return err;
337 }
338
339 cq->resize_buf->cqe = entries - 1;
340
341 return 0;
342}
343
344static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq)
345{
346 u32 i;
347
348 i = cq->mcq.cons_index;
349 while (get_sw_cqe(cq, i))
350 ++i;
351
352 return i - cq->mcq.cons_index;
353}
354
355static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq)
356{
357 struct mlx4_cqe *cqe, *new_cqe;
358 int i;
359 int cqe_size = cq->buf.entry_size;
360 int cqe_inc = cqe_size == 64 ? 1 : 0;
361
362 i = cq->mcq.cons_index;
363 cqe = get_cqe(cq, i & cq->ibcq.cqe);
364 cqe += cqe_inc;
365
366 while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) {
367 new_cqe = get_cqe_from_buf(&cq->resize_buf->buf,
368 (i + 1) & cq->resize_buf->cqe);
369 memcpy(new_cqe, get_cqe(cq, i & cq->ibcq.cqe), cqe_size);
370 new_cqe += cqe_inc;
371
372 new_cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) |
373 (((i + 1) & (cq->resize_buf->cqe + 1)) ? MLX4_CQE_OWNER_MASK : 0);
374 cqe = get_cqe(cq, ++i & cq->ibcq.cqe);
375 cqe += cqe_inc;
376 }
377 ++cq->mcq.cons_index;
378}
379
380int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
381{
382 struct mlx4_ib_dev *dev = to_mdev(ibcq->device);
383 struct mlx4_ib_cq *cq = to_mcq(ibcq);
384 struct mlx4_mtt mtt;
385 int outst_cqe;
386 int err;
387
388 mutex_lock(&cq->resize_mutex);
389 if (entries < 1 || entries > dev->dev->caps.max_cqes) {
390 err = -EINVAL;
391 goto out;
392 }
393
394 entries = roundup_pow_of_two(entries + 1);
395 if (entries == ibcq->cqe + 1) {
396 err = 0;
397 goto out;
398 }
399
400 if (entries > dev->dev->caps.max_cqes + 1) {
401 err = -EINVAL;
402 goto out;
403 }
404
405 if (ibcq->uobject) {
406 err = mlx4_alloc_resize_umem(dev, cq, entries, udata);
407 if (err)
408 goto out;
409 } else {
410 /* Can't be smaller than the number of outstanding CQEs */
411 outst_cqe = mlx4_ib_get_outstanding_cqes(cq);
412 if (entries < outst_cqe + 1) {
413 err = -EINVAL;
414 goto out;
415 }
416
417 err = mlx4_alloc_resize_buf(dev, cq, entries);
418 if (err)
419 goto out;
420 }
421
422 mtt = cq->buf.mtt;
423
424 err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt);
425 if (err)
426 goto err_buf;
427
428 mlx4_mtt_cleanup(dev->dev, &mtt);
429 if (ibcq->uobject) {
430 cq->buf = cq->resize_buf->buf;
431 cq->ibcq.cqe = cq->resize_buf->cqe;
432 ib_umem_release(cq->umem);
433 cq->umem = cq->resize_umem;
434
435 kfree(cq->resize_buf);
436 cq->resize_buf = NULL;
437 cq->resize_umem = NULL;
438 } else {
439 struct mlx4_ib_cq_buf tmp_buf;
440 int tmp_cqe = 0;
441
442 spin_lock_irq(&cq->lock);
443 if (cq->resize_buf) {
444 mlx4_ib_cq_resize_copy_cqes(cq);
445 tmp_buf = cq->buf;
446 tmp_cqe = cq->ibcq.cqe;
447 cq->buf = cq->resize_buf->buf;
448 cq->ibcq.cqe = cq->resize_buf->cqe;
449
450 kfree(cq->resize_buf);
451 cq->resize_buf = NULL;
452 }
453 spin_unlock_irq(&cq->lock);
454
455 if (tmp_cqe)
456 mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe);
457 }
458
459 goto out;
460
461err_buf:
462 mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt);
463 if (!ibcq->uobject)
464 mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf,
465 cq->resize_buf->cqe);
466
467 kfree(cq->resize_buf);
468 cq->resize_buf = NULL;
469
470 ib_umem_release(cq->resize_umem);
471 cq->resize_umem = NULL;
472out:
473 mutex_unlock(&cq->resize_mutex);
474
475 return err;
476}
477
478void mlx4_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata)
479{
480 struct mlx4_ib_dev *dev = to_mdev(cq->device);
481 struct mlx4_ib_cq *mcq = to_mcq(cq);
482
483 mlx4_cq_free(dev->dev, &mcq->mcq);
484 mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt);
485
486 if (udata) {
487 mlx4_ib_db_unmap_user(
488 rdma_udata_to_drv_context(
489 udata,
490 struct mlx4_ib_ucontext,
491 ibucontext),
492 &mcq->db);
493 } else {
494 mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe);
495 mlx4_db_free(dev->dev, &mcq->db);
496 }
497 ib_umem_release(mcq->umem);
498}
499
500static void dump_cqe(void *cqe)
501{
502 __be32 *buf = cqe;
503
504 pr_debug("CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
505 be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]),
506 be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]),
507 be32_to_cpu(buf[6]), be32_to_cpu(buf[7]));
508}
509
510static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe,
511 struct ib_wc *wc)
512{
513 if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) {
514 pr_debug("local QP operation err "
515 "(QPN %06x, WQE index %x, vendor syndrome %02x, "
516 "opcode = %02x)\n",
517 be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index),
518 cqe->vendor_err_syndrome,
519 cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
520 dump_cqe(cqe);
521 }
522
523 switch (cqe->syndrome) {
524 case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR:
525 wc->status = IB_WC_LOC_LEN_ERR;
526 break;
527 case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR:
528 wc->status = IB_WC_LOC_QP_OP_ERR;
529 break;
530 case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR:
531 wc->status = IB_WC_LOC_PROT_ERR;
532 break;
533 case MLX4_CQE_SYNDROME_WR_FLUSH_ERR:
534 wc->status = IB_WC_WR_FLUSH_ERR;
535 break;
536 case MLX4_CQE_SYNDROME_MW_BIND_ERR:
537 wc->status = IB_WC_MW_BIND_ERR;
538 break;
539 case MLX4_CQE_SYNDROME_BAD_RESP_ERR:
540 wc->status = IB_WC_BAD_RESP_ERR;
541 break;
542 case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR:
543 wc->status = IB_WC_LOC_ACCESS_ERR;
544 break;
545 case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
546 wc->status = IB_WC_REM_INV_REQ_ERR;
547 break;
548 case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR:
549 wc->status = IB_WC_REM_ACCESS_ERR;
550 break;
551 case MLX4_CQE_SYNDROME_REMOTE_OP_ERR:
552 wc->status = IB_WC_REM_OP_ERR;
553 break;
554 case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
555 wc->status = IB_WC_RETRY_EXC_ERR;
556 break;
557 case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
558 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
559 break;
560 case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR:
561 wc->status = IB_WC_REM_ABORT_ERR;
562 break;
563 default:
564 wc->status = IB_WC_GENERAL_ERR;
565 break;
566 }
567
568 wc->vendor_err = cqe->vendor_err_syndrome;
569}
570
571static int mlx4_ib_ipoib_csum_ok(__be16 status, u8 badfcs_enc, __be16 checksum)
572{
573 return ((badfcs_enc & MLX4_CQE_STATUS_L4_CSUM) ||
574 ((status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
575 (status & cpu_to_be16(MLX4_CQE_STATUS_TCP |
576 MLX4_CQE_STATUS_UDP)) &&
577 (checksum == cpu_to_be16(0xffff))));
578}
579
580static void use_tunnel_data(struct mlx4_ib_qp *qp, struct mlx4_ib_cq *cq, struct ib_wc *wc,
581 unsigned tail, struct mlx4_cqe *cqe, int is_eth)
582{
583 struct mlx4_ib_proxy_sqp_hdr *hdr;
584
585 ib_dma_sync_single_for_cpu(qp->ibqp.device,
586 qp->sqp_proxy_rcv[tail].map,
587 sizeof (struct mlx4_ib_proxy_sqp_hdr),
588 DMA_FROM_DEVICE);
589 hdr = (struct mlx4_ib_proxy_sqp_hdr *) (qp->sqp_proxy_rcv[tail].addr);
590 wc->pkey_index = be16_to_cpu(hdr->tun.pkey_index);
591 wc->src_qp = be32_to_cpu(hdr->tun.flags_src_qp) & 0xFFFFFF;
592 wc->wc_flags |= (hdr->tun.g_ml_path & 0x80) ? (IB_WC_GRH) : 0;
593 wc->dlid_path_bits = 0;
594
595 if (is_eth) {
596 wc->slid = 0;
597 wc->vlan_id = be16_to_cpu(hdr->tun.sl_vid);
598 memcpy(&(wc->smac[0]), (char *)&hdr->tun.mac_31_0, 4);
599 memcpy(&(wc->smac[4]), (char *)&hdr->tun.slid_mac_47_32, 2);
600 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
601 } else {
602 wc->slid = be16_to_cpu(hdr->tun.slid_mac_47_32);
603 wc->sl = (u8) (be16_to_cpu(hdr->tun.sl_vid) >> 12);
604 }
605}
606
607static void mlx4_ib_qp_sw_comp(struct mlx4_ib_qp *qp, int num_entries,
608 struct ib_wc *wc, int *npolled, int is_send)
609{
610 struct mlx4_ib_wq *wq;
611 unsigned cur;
612 int i;
613
614 wq = is_send ? &qp->sq : &qp->rq;
615 cur = wq->head - wq->tail;
616
617 if (cur == 0)
618 return;
619
620 for (i = 0; i < cur && *npolled < num_entries; i++) {
621 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
622 wc->status = IB_WC_WR_FLUSH_ERR;
623 wc->vendor_err = MLX4_CQE_SYNDROME_WR_FLUSH_ERR;
624 wq->tail++;
625 (*npolled)++;
626 wc->qp = &qp->ibqp;
627 wc++;
628 }
629}
630
631static void mlx4_ib_poll_sw_comp(struct mlx4_ib_cq *cq, int num_entries,
632 struct ib_wc *wc, int *npolled)
633{
634 struct mlx4_ib_qp *qp;
635
636 *npolled = 0;
637 /* Find uncompleted WQEs belonging to that cq and return
638 * simulated FLUSH_ERR completions
639 */
640 list_for_each_entry(qp, &cq->send_qp_list, cq_send_list) {
641 mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 1);
642 if (*npolled >= num_entries)
643 goto out;
644 }
645
646 list_for_each_entry(qp, &cq->recv_qp_list, cq_recv_list) {
647 mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 0);
648 if (*npolled >= num_entries)
649 goto out;
650 }
651
652out:
653 return;
654}
655
656static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq,
657 struct mlx4_ib_qp **cur_qp,
658 struct ib_wc *wc)
659{
660 struct mlx4_cqe *cqe;
661 struct mlx4_qp *mqp;
662 struct mlx4_ib_wq *wq;
663 struct mlx4_ib_srq *srq;
664 struct mlx4_srq *msrq = NULL;
665 int is_send;
666 int is_error;
667 int is_eth;
668 u32 g_mlpath_rqpn;
669 u16 wqe_ctr;
670 unsigned tail = 0;
671
672repoll:
673 cqe = next_cqe_sw(cq);
674 if (!cqe)
675 return -EAGAIN;
676
677 if (cq->buf.entry_size == 64)
678 cqe++;
679
680 ++cq->mcq.cons_index;
681
682 /*
683 * Make sure we read CQ entry contents after we've checked the
684 * ownership bit.
685 */
686 rmb();
687
688 is_send = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK;
689 is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
690 MLX4_CQE_OPCODE_ERROR;
691
692 /* Resize CQ in progress */
693 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) {
694 if (cq->resize_buf) {
695 struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device);
696
697 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
698 cq->buf = cq->resize_buf->buf;
699 cq->ibcq.cqe = cq->resize_buf->cqe;
700
701 kfree(cq->resize_buf);
702 cq->resize_buf = NULL;
703 }
704
705 goto repoll;
706 }
707
708 if (!*cur_qp ||
709 (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) {
710 /*
711 * We do not have to take the QP table lock here,
712 * because CQs will be locked while QPs are removed
713 * from the table.
714 */
715 mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev,
716 be32_to_cpu(cqe->vlan_my_qpn));
717 *cur_qp = to_mibqp(mqp);
718 }
719
720 wc->qp = &(*cur_qp)->ibqp;
721
722 if (wc->qp->qp_type == IB_QPT_XRC_TGT) {
723 u32 srq_num;
724 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
725 srq_num = g_mlpath_rqpn & 0xffffff;
726 /* SRQ is also in the radix tree */
727 msrq = mlx4_srq_lookup(to_mdev(cq->ibcq.device)->dev,
728 srq_num);
729 }
730
731 if (is_send) {
732 wq = &(*cur_qp)->sq;
733 if (!(*cur_qp)->sq_signal_bits) {
734 wqe_ctr = be16_to_cpu(cqe->wqe_index);
735 wq->tail += (u16) (wqe_ctr - (u16) wq->tail);
736 }
737 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
738 ++wq->tail;
739 } else if ((*cur_qp)->ibqp.srq) {
740 srq = to_msrq((*cur_qp)->ibqp.srq);
741 wqe_ctr = be16_to_cpu(cqe->wqe_index);
742 wc->wr_id = srq->wrid[wqe_ctr];
743 mlx4_ib_free_srq_wqe(srq, wqe_ctr);
744 } else if (msrq) {
745 srq = to_mibsrq(msrq);
746 wqe_ctr = be16_to_cpu(cqe->wqe_index);
747 wc->wr_id = srq->wrid[wqe_ctr];
748 mlx4_ib_free_srq_wqe(srq, wqe_ctr);
749 } else {
750 wq = &(*cur_qp)->rq;
751 tail = wq->tail & (wq->wqe_cnt - 1);
752 wc->wr_id = wq->wrid[tail];
753 ++wq->tail;
754 }
755
756 if (unlikely(is_error)) {
757 mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc);
758 return 0;
759 }
760
761 wc->status = IB_WC_SUCCESS;
762
763 if (is_send) {
764 wc->wc_flags = 0;
765 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
766 case MLX4_OPCODE_RDMA_WRITE_IMM:
767 wc->wc_flags |= IB_WC_WITH_IMM;
768 fallthrough;
769 case MLX4_OPCODE_RDMA_WRITE:
770 wc->opcode = IB_WC_RDMA_WRITE;
771 break;
772 case MLX4_OPCODE_SEND_IMM:
773 wc->wc_flags |= IB_WC_WITH_IMM;
774 fallthrough;
775 case MLX4_OPCODE_SEND:
776 case MLX4_OPCODE_SEND_INVAL:
777 wc->opcode = IB_WC_SEND;
778 break;
779 case MLX4_OPCODE_RDMA_READ:
780 wc->opcode = IB_WC_RDMA_READ;
781 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
782 break;
783 case MLX4_OPCODE_ATOMIC_CS:
784 wc->opcode = IB_WC_COMP_SWAP;
785 wc->byte_len = 8;
786 break;
787 case MLX4_OPCODE_ATOMIC_FA:
788 wc->opcode = IB_WC_FETCH_ADD;
789 wc->byte_len = 8;
790 break;
791 case MLX4_OPCODE_MASKED_ATOMIC_CS:
792 wc->opcode = IB_WC_MASKED_COMP_SWAP;
793 wc->byte_len = 8;
794 break;
795 case MLX4_OPCODE_MASKED_ATOMIC_FA:
796 wc->opcode = IB_WC_MASKED_FETCH_ADD;
797 wc->byte_len = 8;
798 break;
799 case MLX4_OPCODE_LSO:
800 wc->opcode = IB_WC_LSO;
801 break;
802 case MLX4_OPCODE_FMR:
803 wc->opcode = IB_WC_REG_MR;
804 break;
805 case MLX4_OPCODE_LOCAL_INVAL:
806 wc->opcode = IB_WC_LOCAL_INV;
807 break;
808 }
809 } else {
810 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
811
812 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
813 case MLX4_RECV_OPCODE_RDMA_WRITE_IMM:
814 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
815 wc->wc_flags = IB_WC_WITH_IMM;
816 wc->ex.imm_data = cqe->immed_rss_invalid;
817 break;
818 case MLX4_RECV_OPCODE_SEND_INVAL:
819 wc->opcode = IB_WC_RECV;
820 wc->wc_flags = IB_WC_WITH_INVALIDATE;
821 wc->ex.invalidate_rkey = be32_to_cpu(cqe->immed_rss_invalid);
822 break;
823 case MLX4_RECV_OPCODE_SEND:
824 wc->opcode = IB_WC_RECV;
825 wc->wc_flags = 0;
826 break;
827 case MLX4_RECV_OPCODE_SEND_IMM:
828 wc->opcode = IB_WC_RECV;
829 wc->wc_flags = IB_WC_WITH_IMM;
830 wc->ex.imm_data = cqe->immed_rss_invalid;
831 break;
832 }
833
834 is_eth = (rdma_port_get_link_layer(wc->qp->device,
835 (*cur_qp)->port) ==
836 IB_LINK_LAYER_ETHERNET);
837 if (mlx4_is_mfunc(to_mdev(cq->ibcq.device)->dev)) {
838 if ((*cur_qp)->mlx4_ib_qp_type &
839 (MLX4_IB_QPT_PROXY_SMI_OWNER |
840 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
841 use_tunnel_data(*cur_qp, cq, wc, tail, cqe,
842 is_eth);
843 return 0;
844 }
845 }
846
847 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
848 wc->src_qp = g_mlpath_rqpn & 0xffffff;
849 wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;
850 wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0;
851 wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f;
852 wc->wc_flags |= mlx4_ib_ipoib_csum_ok(cqe->status,
853 cqe->badfcs_enc,
854 cqe->checksum) ? IB_WC_IP_CSUM_OK : 0;
855 if (is_eth) {
856 wc->slid = 0;
857 wc->sl = be16_to_cpu(cqe->sl_vid) >> 13;
858 if (be32_to_cpu(cqe->vlan_my_qpn) &
859 MLX4_CQE_CVLAN_PRESENT_MASK) {
860 wc->vlan_id = be16_to_cpu(cqe->sl_vid) &
861 MLX4_CQE_VID_MASK;
862 } else {
863 wc->vlan_id = 0xffff;
864 }
865 memcpy(wc->smac, cqe->smac, ETH_ALEN);
866 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
867 } else {
868 wc->slid = be16_to_cpu(cqe->rlid);
869 wc->sl = be16_to_cpu(cqe->sl_vid) >> 12;
870 wc->vlan_id = 0xffff;
871 }
872 }
873
874 return 0;
875}
876
877int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
878{
879 struct mlx4_ib_cq *cq = to_mcq(ibcq);
880 struct mlx4_ib_qp *cur_qp = NULL;
881 unsigned long flags;
882 int npolled;
883 struct mlx4_ib_dev *mdev = to_mdev(cq->ibcq.device);
884
885 spin_lock_irqsave(&cq->lock, flags);
886 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
887 mlx4_ib_poll_sw_comp(cq, num_entries, wc, &npolled);
888 goto out;
889 }
890
891 for (npolled = 0; npolled < num_entries; ++npolled) {
892 if (mlx4_ib_poll_one(cq, &cur_qp, wc + npolled))
893 break;
894 }
895
896 mlx4_cq_set_ci(&cq->mcq);
897
898out:
899 spin_unlock_irqrestore(&cq->lock, flags);
900
901 return npolled;
902}
903
904int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
905{
906 mlx4_cq_arm(&to_mcq(ibcq)->mcq,
907 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
908 MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT,
909 to_mdev(ibcq->device)->uar_map,
910 MLX4_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->uar_lock));
911
912 return 0;
913}
914
915void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
916{
917 u32 prod_index;
918 int nfreed = 0;
919 struct mlx4_cqe *cqe, *dest;
920 u8 owner_bit;
921 int cqe_inc = cq->buf.entry_size == 64 ? 1 : 0;
922
923 /*
924 * First we need to find the current producer index, so we
925 * know where to start cleaning from. It doesn't matter if HW
926 * adds new entries after this loop -- the QP we're worried
927 * about is already in RESET, so the new entries won't come
928 * from our QP and therefore don't need to be checked.
929 */
930 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index)
931 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
932 break;
933
934 /*
935 * Now sweep backwards through the CQ, removing CQ entries
936 * that match our QP by copying older entries on top of them.
937 */
938 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
939 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
940 cqe += cqe_inc;
941
942 if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) {
943 if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK))
944 mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index));
945 ++nfreed;
946 } else if (nfreed) {
947 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
948 dest += cqe_inc;
949
950 owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK;
951 memcpy(dest, cqe, sizeof *cqe);
952 dest->owner_sr_opcode = owner_bit |
953 (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
954 }
955 }
956
957 if (nfreed) {
958 cq->mcq.cons_index += nfreed;
959 /*
960 * Make sure update of buffer contents is done before
961 * updating consumer index.
962 */
963 wmb();
964 mlx4_cq_set_ci(&cq->mcq);
965 }
966}
967
968void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
969{
970 spin_lock_irq(&cq->lock);
971 __mlx4_ib_cq_clean(cq, qpn, srq);
972 spin_unlock_irq(&cq->lock);
973}