1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * Copyright 2016 Linaro Ltd.
 4 * Copyright 2016 ZTE Corporation.
 5 */
 6
 7#ifndef __ZX_VOU_H__
 8#define __ZX_VOU_H__
 9
10#define VOU_CRTC_MASK		0x3
11
12/* VOU output interfaces */
13enum vou_inf_id {
14	VOU_HDMI	= 0,
15	VOU_RGB_LCD	= 1,
16	VOU_TV_ENC	= 2,
17	VOU_MIPI_DSI	= 3,
18	VOU_LVDS	= 4,
19	VOU_VGA		= 5,
20};
21
22enum vou_inf_hdmi_audio {
23	VOU_HDMI_AUD_SPDIF	= BIT(0),
24	VOU_HDMI_AUD_I2S	= BIT(1),
25	VOU_HDMI_AUD_DSD	= BIT(2),
26	VOU_HDMI_AUD_HBR	= BIT(3),
27	VOU_HDMI_AUD_PARALLEL	= BIT(4),
28};
29
30void vou_inf_hdmi_audio_sel(struct drm_crtc *crtc,
31			    enum vou_inf_hdmi_audio aud);
32void vou_inf_enable(enum vou_inf_id id, struct drm_crtc *crtc);
33void vou_inf_disable(enum vou_inf_id id, struct drm_crtc *crtc);
34
35enum vou_div_id {
36	VOU_DIV_VGA,
37	VOU_DIV_PIC,
38	VOU_DIV_TVENC,
39	VOU_DIV_HDMI_PNX,
40	VOU_DIV_HDMI,
41	VOU_DIV_INF,
42	VOU_DIV_LAYER,
43};
44
45enum vou_div_val {
46	VOU_DIV_1 = 0,
47	VOU_DIV_2 = 1,
48	VOU_DIV_4 = 3,
49	VOU_DIV_8 = 7,
50};
51
52struct vou_div_config {
53	enum vou_div_id id;
54	enum vou_div_val val;
55};
56
57void zx_vou_config_dividers(struct drm_crtc *crtc,
58			    struct vou_div_config *configs, int num);
59
60void zx_vou_layer_enable(struct drm_plane *plane);
61void zx_vou_layer_disable(struct drm_plane *plane,
62			  struct drm_plane_state *old_state);
63
64#endif /* __ZX_VOU_H__ */