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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 Broadcom
4 */
5
6/**
7 * DOC: VC4 CRTC module
8 *
9 * In VC4, the Pixel Valve is what most closely corresponds to the
10 * DRM's concept of a CRTC. The PV generates video timings from the
11 * encoder's clock plus its configuration. It pulls scaled pixels from
12 * the HVS at that timing, and feeds it to the encoder.
13 *
14 * However, the DRM CRTC also collects the configuration of all the
15 * DRM planes attached to it. As a result, the CRTC is also
16 * responsible for writing the display list for the HVS channel that
17 * the CRTC will use.
18 *
19 * The 2835 has 3 different pixel valves. pv0 in the audio power
20 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
21 * image domain can feed either HDMI or the SDTV controller. The
22 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
23 * SDTV, etc.) according to which output type is chosen in the mux.
24 *
25 * For power management, the pixel valve's registers are all clocked
26 * by the AXI clock, while the timings and FIFOs make use of the
27 * output-specific clock. Since the encoders also directly consume
28 * the CPRMAN clocks, and know what timings they need, they are the
29 * ones that set the clock.
30 */
31
32#include <linux/clk.h>
33#include <linux/component.h>
34#include <linux/of_device.h>
35
36#include <drm/drm_atomic.h>
37#include <drm/drm_atomic_helper.h>
38#include <drm/drm_atomic_uapi.h>
39#include <drm/drm_fb_cma_helper.h>
40#include <drm/drm_print.h>
41#include <drm/drm_probe_helper.h>
42#include <drm/drm_vblank.h>
43
44#include "vc4_drv.h"
45#include "vc4_regs.h"
46
47#define HVS_FIFO_LATENCY_PIX 6
48
49#define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
50#define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
51
52static const struct debugfs_reg32 crtc_regs[] = {
53 VC4_REG32(PV_CONTROL),
54 VC4_REG32(PV_V_CONTROL),
55 VC4_REG32(PV_VSYNCD_EVEN),
56 VC4_REG32(PV_HORZA),
57 VC4_REG32(PV_HORZB),
58 VC4_REG32(PV_VERTA),
59 VC4_REG32(PV_VERTB),
60 VC4_REG32(PV_VERTA_EVEN),
61 VC4_REG32(PV_VERTB_EVEN),
62 VC4_REG32(PV_INTEN),
63 VC4_REG32(PV_INTSTAT),
64 VC4_REG32(PV_STAT),
65 VC4_REG32(PV_HACT_ACT),
66};
67
68static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
69 bool in_vblank_irq,
70 int *vpos, int *hpos,
71 ktime_t *stime, ktime_t *etime,
72 const struct drm_display_mode *mode)
73{
74 struct drm_device *dev = crtc->dev;
75 struct vc4_dev *vc4 = to_vc4_dev(dev);
76 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
77 u32 val;
78 int fifo_lines;
79 int vblank_lines;
80 bool ret = false;
81
82 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
83
84 /* Get optional system timestamp before query. */
85 if (stime)
86 *stime = ktime_get();
87
88 /*
89 * Read vertical scanline which is currently composed for our
90 * pixelvalve by the HVS, and also the scaler status.
91 */
92 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
93
94 /* Get optional system timestamp after query. */
95 if (etime)
96 *etime = ktime_get();
97
98 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
99
100 /* Vertical position of hvs composed scanline. */
101 *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
102 *hpos = 0;
103
104 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
105 *vpos /= 2;
106
107 /* Use hpos to correct for field offset in interlaced mode. */
108 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
109 *hpos += mode->crtc_htotal / 2;
110 }
111
112 /* This is the offset we need for translating hvs -> pv scanout pos. */
113 fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
114
115 if (fifo_lines > 0)
116 ret = true;
117
118 /* HVS more than fifo_lines into frame for compositing? */
119 if (*vpos > fifo_lines) {
120 /*
121 * We are in active scanout and can get some meaningful results
122 * from HVS. The actual PV scanout can not trail behind more
123 * than fifo_lines as that is the fifo's capacity. Assume that
124 * in active scanout the HVS and PV work in lockstep wrt. HVS
125 * refilling the fifo and PV consuming from the fifo, ie.
126 * whenever the PV consumes and frees up a scanline in the
127 * fifo, the HVS will immediately refill it, therefore
128 * incrementing vpos. Therefore we choose HVS read position -
129 * fifo size in scanlines as a estimate of the real scanout
130 * position of the PV.
131 */
132 *vpos -= fifo_lines + 1;
133
134 return ret;
135 }
136
137 /*
138 * Less: This happens when we are in vblank and the HVS, after getting
139 * the VSTART restart signal from the PV, just started refilling its
140 * fifo with new lines from the top-most lines of the new framebuffers.
141 * The PV does not scan out in vblank, so does not remove lines from
142 * the fifo, so the fifo will be full quickly and the HVS has to pause.
143 * We can't get meaningful readings wrt. scanline position of the PV
144 * and need to make things up in a approximative but consistent way.
145 */
146 vblank_lines = mode->vtotal - mode->vdisplay;
147
148 if (in_vblank_irq) {
149 /*
150 * Assume the irq handler got called close to first
151 * line of vblank, so PV has about a full vblank
152 * scanlines to go, and as a base timestamp use the
153 * one taken at entry into vblank irq handler, so it
154 * is not affected by random delays due to lock
155 * contention on event_lock or vblank_time lock in
156 * the core.
157 */
158 *vpos = -vblank_lines;
159
160 if (stime)
161 *stime = vc4_crtc->t_vblank;
162 if (etime)
163 *etime = vc4_crtc->t_vblank;
164
165 /*
166 * If the HVS fifo is not yet full then we know for certain
167 * we are at the very beginning of vblank, as the hvs just
168 * started refilling, and the stime and etime timestamps
169 * truly correspond to start of vblank.
170 *
171 * Unfortunately there's no way to report this to upper levels
172 * and make it more useful.
173 */
174 } else {
175 /*
176 * No clue where we are inside vblank. Return a vpos of zero,
177 * which will cause calling code to just return the etime
178 * timestamp uncorrected. At least this is no worse than the
179 * standard fallback.
180 */
181 *vpos = 0;
182 }
183
184 return ret;
185}
186
187void vc4_crtc_destroy(struct drm_crtc *crtc)
188{
189 drm_crtc_cleanup(crtc);
190}
191
192static u32 vc4_get_fifo_full_level(u32 format)
193{
194 static const u32 fifo_len_bytes = 64;
195
196 switch (format) {
197 case PV_CONTROL_FORMAT_DSIV_16:
198 case PV_CONTROL_FORMAT_DSIC_16:
199 return fifo_len_bytes - 2 * HVS_FIFO_LATENCY_PIX;
200 case PV_CONTROL_FORMAT_DSIV_18:
201 return fifo_len_bytes - 14;
202 case PV_CONTROL_FORMAT_24:
203 case PV_CONTROL_FORMAT_DSIV_24:
204 default:
205 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
206 }
207}
208
209/*
210 * Returns the encoder attached to the CRTC.
211 *
212 * VC4 can only scan out to one encoder at a time, while the DRM core
213 * allows drivers to push pixels to more than one encoder from the
214 * same CRTC.
215 */
216static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
217{
218 struct drm_connector *connector;
219 struct drm_connector_list_iter conn_iter;
220
221 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
222 drm_for_each_connector_iter(connector, &conn_iter) {
223 if (connector->state->crtc == crtc) {
224 drm_connector_list_iter_end(&conn_iter);
225 return connector->encoder;
226 }
227 }
228 drm_connector_list_iter_end(&conn_iter);
229
230 return NULL;
231}
232
233static void vc4_crtc_config_pv(struct drm_crtc *crtc)
234{
235 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
236 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
237 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
238 struct drm_crtc_state *state = crtc->state;
239 struct drm_display_mode *mode = &state->adjusted_mode;
240 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
241 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
242 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
243 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
244 u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
245
246 /* Reset the PV fifo. */
247 CRTC_WRITE(PV_CONTROL, 0);
248 CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
249 CRTC_WRITE(PV_CONTROL, 0);
250
251 CRTC_WRITE(PV_HORZA,
252 VC4_SET_FIELD((mode->htotal -
253 mode->hsync_end) * pixel_rep,
254 PV_HORZA_HBP) |
255 VC4_SET_FIELD((mode->hsync_end -
256 mode->hsync_start) * pixel_rep,
257 PV_HORZA_HSYNC));
258 CRTC_WRITE(PV_HORZB,
259 VC4_SET_FIELD((mode->hsync_start -
260 mode->hdisplay) * pixel_rep,
261 PV_HORZB_HFP) |
262 VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
263
264 CRTC_WRITE(PV_VERTA,
265 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
266 PV_VERTA_VBP) |
267 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
268 PV_VERTA_VSYNC));
269 CRTC_WRITE(PV_VERTB,
270 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
271 PV_VERTB_VFP) |
272 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
273
274 if (interlace) {
275 CRTC_WRITE(PV_VERTA_EVEN,
276 VC4_SET_FIELD(mode->crtc_vtotal -
277 mode->crtc_vsync_end - 1,
278 PV_VERTA_VBP) |
279 VC4_SET_FIELD(mode->crtc_vsync_end -
280 mode->crtc_vsync_start,
281 PV_VERTA_VSYNC));
282 CRTC_WRITE(PV_VERTB_EVEN,
283 VC4_SET_FIELD(mode->crtc_vsync_start -
284 mode->crtc_vdisplay,
285 PV_VERTB_VFP) |
286 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
287
288 /* We set up first field even mode for HDMI. VEC's
289 * NTSC mode would want first field odd instead, once
290 * we support it (to do so, set ODD_FIRST and put the
291 * delay in VSYNCD_EVEN instead).
292 */
293 CRTC_WRITE(PV_V_CONTROL,
294 PV_VCONTROL_CONTINUOUS |
295 (is_dsi ? PV_VCONTROL_DSI : 0) |
296 PV_VCONTROL_INTERLACE |
297 VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
298 PV_VCONTROL_ODD_DELAY));
299 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
300 } else {
301 CRTC_WRITE(PV_V_CONTROL,
302 PV_VCONTROL_CONTINUOUS |
303 (is_dsi ? PV_VCONTROL_DSI : 0));
304 }
305
306 if (is_dsi)
307 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
308
309 CRTC_WRITE(PV_CONTROL,
310 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
311 VC4_SET_FIELD(vc4_get_fifo_full_level(format),
312 PV_CONTROL_FIFO_LEVEL) |
313 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
314 PV_CONTROL_CLR_AT_START |
315 PV_CONTROL_TRIGGER_UNDERFLOW |
316 PV_CONTROL_WAIT_HSTART |
317 VC4_SET_FIELD(vc4_encoder->clock_select,
318 PV_CONTROL_CLK_SELECT) |
319 PV_CONTROL_FIFO_CLR |
320 PV_CONTROL_EN);
321}
322
323static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
324{
325 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
326 bool debug_dump_regs = false;
327
328 if (debug_dump_regs) {
329 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
330 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",
331 drm_crtc_index(crtc));
332 drm_print_regset32(&p, &vc4_crtc->regset);
333 }
334
335 vc4_crtc_config_pv(crtc);
336
337 vc4_hvs_mode_set_nofb(crtc);
338
339 if (debug_dump_regs) {
340 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
341 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",
342 drm_crtc_index(crtc));
343 drm_print_regset32(&p, &vc4_crtc->regset);
344 }
345}
346
347static void require_hvs_enabled(struct drm_device *dev)
348{
349 struct vc4_dev *vc4 = to_vc4_dev(dev);
350
351 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
352 SCALER_DISPCTRL_ENABLE);
353}
354
355static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
356 struct drm_crtc_state *old_state)
357{
358 struct drm_device *dev = crtc->dev;
359 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
360 int ret;
361
362 require_hvs_enabled(dev);
363
364 /* Disable vblank irq handling before crtc is disabled. */
365 drm_crtc_vblank_off(crtc);
366
367 CRTC_WRITE(PV_V_CONTROL,
368 CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
369 ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
370 WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
371
372 vc4_hvs_atomic_disable(crtc, old_state);
373
374 /*
375 * Make sure we issue a vblank event after disabling the CRTC if
376 * someone was waiting it.
377 */
378 if (crtc->state->event) {
379 unsigned long flags;
380
381 spin_lock_irqsave(&dev->event_lock, flags);
382 drm_crtc_send_vblank_event(crtc, crtc->state->event);
383 crtc->state->event = NULL;
384 spin_unlock_irqrestore(&dev->event_lock, flags);
385 }
386}
387
388static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
389 struct drm_crtc_state *old_state)
390{
391 struct drm_device *dev = crtc->dev;
392 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
393
394 require_hvs_enabled(dev);
395
396 /* Enable vblank irq handling before crtc is started otherwise
397 * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
398 */
399 drm_crtc_vblank_on(crtc);
400
401 vc4_hvs_atomic_enable(crtc, old_state);
402
403 /* When feeding the transposer block the pixelvalve is unneeded and
404 * should not be enabled.
405 */
406 CRTC_WRITE(PV_V_CONTROL,
407 CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
408}
409
410static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
411 const struct drm_display_mode *mode)
412{
413 /* Do not allow doublescan modes from user space */
414 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
415 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
416 crtc->base.id);
417 return MODE_NO_DBLESCAN;
418 }
419
420 return MODE_OK;
421}
422
423void vc4_crtc_get_margins(struct drm_crtc_state *state,
424 unsigned int *left, unsigned int *right,
425 unsigned int *top, unsigned int *bottom)
426{
427 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
428 struct drm_connector_state *conn_state;
429 struct drm_connector *conn;
430 int i;
431
432 *left = vc4_state->margins.left;
433 *right = vc4_state->margins.right;
434 *top = vc4_state->margins.top;
435 *bottom = vc4_state->margins.bottom;
436
437 /* We have to interate over all new connector states because
438 * vc4_crtc_get_margins() might be called before
439 * vc4_crtc_atomic_check() which means margins info in vc4_crtc_state
440 * might be outdated.
441 */
442 for_each_new_connector_in_state(state->state, conn, conn_state, i) {
443 if (conn_state->crtc != state->crtc)
444 continue;
445
446 *left = conn_state->tv.margins.left;
447 *right = conn_state->tv.margins.right;
448 *top = conn_state->tv.margins.top;
449 *bottom = conn_state->tv.margins.bottom;
450 break;
451 }
452}
453
454static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
455 struct drm_crtc_state *state)
456{
457 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
458 struct drm_connector *conn;
459 struct drm_connector_state *conn_state;
460 int ret, i;
461
462 ret = vc4_hvs_atomic_check(crtc, state);
463 if (ret)
464 return ret;
465
466 for_each_new_connector_in_state(state->state, conn, conn_state, i) {
467 if (conn_state->crtc != crtc)
468 continue;
469
470 vc4_state->margins.left = conn_state->tv.margins.left;
471 vc4_state->margins.right = conn_state->tv.margins.right;
472 vc4_state->margins.top = conn_state->tv.margins.top;
473 vc4_state->margins.bottom = conn_state->tv.margins.bottom;
474 break;
475 }
476
477 return 0;
478}
479
480static int vc4_enable_vblank(struct drm_crtc *crtc)
481{
482 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
483
484 CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
485
486 return 0;
487}
488
489static void vc4_disable_vblank(struct drm_crtc *crtc)
490{
491 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
492
493 CRTC_WRITE(PV_INTEN, 0);
494}
495
496static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
497{
498 struct drm_crtc *crtc = &vc4_crtc->base;
499 struct drm_device *dev = crtc->dev;
500 struct vc4_dev *vc4 = to_vc4_dev(dev);
501 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
502 u32 chan = vc4_crtc->channel;
503 unsigned long flags;
504
505 spin_lock_irqsave(&dev->event_lock, flags);
506 if (vc4_crtc->event &&
507 (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)) ||
508 vc4_state->feed_txp)) {
509 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
510 vc4_crtc->event = NULL;
511 drm_crtc_vblank_put(crtc);
512
513 /* Wait for the page flip to unmask the underrun to ensure that
514 * the display list was updated by the hardware. Before that
515 * happens, the HVS will be using the previous display list with
516 * the CRTC and encoder already reconfigured, leading to
517 * underruns. This can be seen when reconfiguring the CRTC.
518 */
519 vc4_hvs_unmask_underrun(dev, vc4_crtc->channel);
520 }
521 spin_unlock_irqrestore(&dev->event_lock, flags);
522}
523
524void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
525{
526 crtc->t_vblank = ktime_get();
527 drm_crtc_handle_vblank(&crtc->base);
528 vc4_crtc_handle_page_flip(crtc);
529}
530
531static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
532{
533 struct vc4_crtc *vc4_crtc = data;
534 u32 stat = CRTC_READ(PV_INTSTAT);
535 irqreturn_t ret = IRQ_NONE;
536
537 if (stat & PV_INT_VFP_START) {
538 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
539 vc4_crtc_handle_vblank(vc4_crtc);
540 ret = IRQ_HANDLED;
541 }
542
543 return ret;
544}
545
546struct vc4_async_flip_state {
547 struct drm_crtc *crtc;
548 struct drm_framebuffer *fb;
549 struct drm_framebuffer *old_fb;
550 struct drm_pending_vblank_event *event;
551
552 struct vc4_seqno_cb cb;
553};
554
555/* Called when the V3D execution for the BO being flipped to is done, so that
556 * we can actually update the plane's address to point to it.
557 */
558static void
559vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
560{
561 struct vc4_async_flip_state *flip_state =
562 container_of(cb, struct vc4_async_flip_state, cb);
563 struct drm_crtc *crtc = flip_state->crtc;
564 struct drm_device *dev = crtc->dev;
565 struct vc4_dev *vc4 = to_vc4_dev(dev);
566 struct drm_plane *plane = crtc->primary;
567
568 vc4_plane_async_set_fb(plane, flip_state->fb);
569 if (flip_state->event) {
570 unsigned long flags;
571
572 spin_lock_irqsave(&dev->event_lock, flags);
573 drm_crtc_send_vblank_event(crtc, flip_state->event);
574 spin_unlock_irqrestore(&dev->event_lock, flags);
575 }
576
577 drm_crtc_vblank_put(crtc);
578 drm_framebuffer_put(flip_state->fb);
579
580 /* Decrement the BO usecnt in order to keep the inc/dec calls balanced
581 * when the planes are updated through the async update path.
582 * FIXME: we should move to generic async-page-flip when it's
583 * available, so that we can get rid of this hand-made cleanup_fb()
584 * logic.
585 */
586 if (flip_state->old_fb) {
587 struct drm_gem_cma_object *cma_bo;
588 struct vc4_bo *bo;
589
590 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
591 bo = to_vc4_bo(&cma_bo->base);
592 vc4_bo_dec_usecnt(bo);
593 drm_framebuffer_put(flip_state->old_fb);
594 }
595
596 kfree(flip_state);
597
598 up(&vc4->async_modeset);
599}
600
601/* Implements async (non-vblank-synced) page flips.
602 *
603 * The page flip ioctl needs to return immediately, so we grab the
604 * modeset semaphore on the pipe, and queue the address update for
605 * when V3D is done with the BO being flipped to.
606 */
607static int vc4_async_page_flip(struct drm_crtc *crtc,
608 struct drm_framebuffer *fb,
609 struct drm_pending_vblank_event *event,
610 uint32_t flags)
611{
612 struct drm_device *dev = crtc->dev;
613 struct vc4_dev *vc4 = to_vc4_dev(dev);
614 struct drm_plane *plane = crtc->primary;
615 int ret = 0;
616 struct vc4_async_flip_state *flip_state;
617 struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
618 struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
619
620 /* Increment the BO usecnt here, so that we never end up with an
621 * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
622 * plane is later updated through the non-async path.
623 * FIXME: we should move to generic async-page-flip when it's
624 * available, so that we can get rid of this hand-made prepare_fb()
625 * logic.
626 */
627 ret = vc4_bo_inc_usecnt(bo);
628 if (ret)
629 return ret;
630
631 flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
632 if (!flip_state) {
633 vc4_bo_dec_usecnt(bo);
634 return -ENOMEM;
635 }
636
637 drm_framebuffer_get(fb);
638 flip_state->fb = fb;
639 flip_state->crtc = crtc;
640 flip_state->event = event;
641
642 /* Make sure all other async modesetes have landed. */
643 ret = down_interruptible(&vc4->async_modeset);
644 if (ret) {
645 drm_framebuffer_put(fb);
646 vc4_bo_dec_usecnt(bo);
647 kfree(flip_state);
648 return ret;
649 }
650
651 /* Save the current FB before it's replaced by the new one in
652 * drm_atomic_set_fb_for_plane(). We'll need the old FB in
653 * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
654 * it consistent.
655 * FIXME: we should move to generic async-page-flip when it's
656 * available, so that we can get rid of this hand-made cleanup_fb()
657 * logic.
658 */
659 flip_state->old_fb = plane->state->fb;
660 if (flip_state->old_fb)
661 drm_framebuffer_get(flip_state->old_fb);
662
663 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
664
665 /* Immediately update the plane's legacy fb pointer, so that later
666 * modeset prep sees the state that will be present when the semaphore
667 * is released.
668 */
669 drm_atomic_set_fb_for_plane(plane->state, fb);
670
671 vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
672 vc4_async_page_flip_complete);
673
674 /* Driver takes ownership of state on successful async commit. */
675 return 0;
676}
677
678int vc4_page_flip(struct drm_crtc *crtc,
679 struct drm_framebuffer *fb,
680 struct drm_pending_vblank_event *event,
681 uint32_t flags,
682 struct drm_modeset_acquire_ctx *ctx)
683{
684 if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
685 return vc4_async_page_flip(crtc, fb, event, flags);
686 else
687 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
688}
689
690struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
691{
692 struct vc4_crtc_state *vc4_state, *old_vc4_state;
693
694 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
695 if (!vc4_state)
696 return NULL;
697
698 old_vc4_state = to_vc4_crtc_state(crtc->state);
699 vc4_state->feed_txp = old_vc4_state->feed_txp;
700 vc4_state->margins = old_vc4_state->margins;
701
702 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
703 return &vc4_state->base;
704}
705
706void vc4_crtc_destroy_state(struct drm_crtc *crtc,
707 struct drm_crtc_state *state)
708{
709 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
710 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
711
712 if (drm_mm_node_allocated(&vc4_state->mm)) {
713 unsigned long flags;
714
715 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
716 drm_mm_remove_node(&vc4_state->mm);
717 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
718
719 }
720
721 drm_atomic_helper_crtc_destroy_state(crtc, state);
722}
723
724void vc4_crtc_reset(struct drm_crtc *crtc)
725{
726 if (crtc->state)
727 vc4_crtc_destroy_state(crtc, crtc->state);
728 crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL);
729 if (crtc->state)
730 __drm_atomic_helper_crtc_reset(crtc, crtc->state);
731}
732
733static const struct drm_crtc_funcs vc4_crtc_funcs = {
734 .set_config = drm_atomic_helper_set_config,
735 .destroy = vc4_crtc_destroy,
736 .page_flip = vc4_page_flip,
737 .set_property = NULL,
738 .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
739 .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
740 .reset = vc4_crtc_reset,
741 .atomic_duplicate_state = vc4_crtc_duplicate_state,
742 .atomic_destroy_state = vc4_crtc_destroy_state,
743 .gamma_set = drm_atomic_helper_legacy_gamma_set,
744 .enable_vblank = vc4_enable_vblank,
745 .disable_vblank = vc4_disable_vblank,
746 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
747};
748
749static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
750 .mode_set_nofb = vc4_crtc_mode_set_nofb,
751 .mode_valid = vc4_crtc_mode_valid,
752 .atomic_check = vc4_crtc_atomic_check,
753 .atomic_flush = vc4_hvs_atomic_flush,
754 .atomic_enable = vc4_crtc_atomic_enable,
755 .atomic_disable = vc4_crtc_atomic_disable,
756 .get_scanout_position = vc4_crtc_get_scanout_position,
757};
758
759static const struct vc4_pv_data bcm2835_pv0_data = {
760 .base = {
761 .hvs_channel = 0,
762 },
763 .debugfs_name = "crtc0_regs",
764 .encoder_types = {
765 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
766 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
767 },
768};
769
770static const struct vc4_pv_data bcm2835_pv1_data = {
771 .base = {
772 .hvs_channel = 2,
773 },
774 .debugfs_name = "crtc1_regs",
775 .encoder_types = {
776 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
777 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
778 },
779};
780
781static const struct vc4_pv_data bcm2835_pv2_data = {
782 .base = {
783 .hvs_channel = 1,
784 },
785 .debugfs_name = "crtc2_regs",
786 .encoder_types = {
787 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
788 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
789 },
790};
791
792static const struct of_device_id vc4_crtc_dt_match[] = {
793 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
794 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
795 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data },
796 {}
797};
798
799static void vc4_set_crtc_possible_masks(struct drm_device *drm,
800 struct drm_crtc *crtc)
801{
802 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
803 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
804 const enum vc4_encoder_type *encoder_types = pv_data->encoder_types;
805 struct drm_encoder *encoder;
806
807 drm_for_each_encoder(encoder, drm) {
808 struct vc4_encoder *vc4_encoder;
809 int i;
810
811 vc4_encoder = to_vc4_encoder(encoder);
812 for (i = 0; i < ARRAY_SIZE(pv_data->encoder_types); i++) {
813 if (vc4_encoder->type == encoder_types[i]) {
814 vc4_encoder->clock_select = i;
815 encoder->possible_crtcs |= drm_crtc_mask(crtc);
816 break;
817 }
818 }
819 }
820}
821
822static void
823vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
824{
825 struct drm_device *drm = vc4_crtc->base.dev;
826 struct vc4_dev *vc4 = to_vc4_dev(drm);
827 u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
828 /* Top/base are supposed to be 4-pixel aligned, but the
829 * Raspberry Pi firmware fills the low bits (which are
830 * presumably ignored).
831 */
832 u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
833 u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
834
835 vc4_crtc->cob_size = top - base + 4;
836}
837
838int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
839 const struct drm_crtc_funcs *crtc_funcs,
840 const struct drm_crtc_helper_funcs *crtc_helper_funcs)
841{
842 struct drm_crtc *crtc = &vc4_crtc->base;
843 struct drm_plane *primary_plane;
844 unsigned int i;
845
846 /* For now, we create just the primary and the legacy cursor
847 * planes. We should be able to stack more planes on easily,
848 * but to do that we would need to compute the bandwidth
849 * requirement of the plane configuration, and reject ones
850 * that will take too much.
851 */
852 primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
853 if (IS_ERR(primary_plane)) {
854 dev_err(drm->dev, "failed to construct primary plane\n");
855 return PTR_ERR(primary_plane);
856 }
857
858 drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
859 crtc_funcs, NULL);
860 drm_crtc_helper_add(crtc, crtc_helper_funcs);
861 vc4_crtc->channel = vc4_crtc->data->hvs_channel;
862 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
863 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
864
865 /* We support CTM, but only for one CRTC at a time. It's therefore
866 * implemented as private driver state in vc4_kms, not here.
867 */
868 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
869 vc4_crtc_get_cob_allocation(vc4_crtc);
870
871 for (i = 0; i < crtc->gamma_size; i++) {
872 vc4_crtc->lut_r[i] = i;
873 vc4_crtc->lut_g[i] = i;
874 vc4_crtc->lut_b[i] = i;
875 }
876
877 return 0;
878}
879
880static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
881{
882 struct platform_device *pdev = to_platform_device(dev);
883 struct drm_device *drm = dev_get_drvdata(master);
884 const struct vc4_pv_data *pv_data;
885 struct vc4_crtc *vc4_crtc;
886 struct drm_crtc *crtc;
887 struct drm_plane *destroy_plane, *temp;
888 int ret;
889
890 vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
891 if (!vc4_crtc)
892 return -ENOMEM;
893 crtc = &vc4_crtc->base;
894
895 pv_data = of_device_get_match_data(dev);
896 if (!pv_data)
897 return -ENODEV;
898 vc4_crtc->data = &pv_data->base;
899 vc4_crtc->pdev = pdev;
900
901 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
902 if (IS_ERR(vc4_crtc->regs))
903 return PTR_ERR(vc4_crtc->regs);
904
905 vc4_crtc->regset.base = vc4_crtc->regs;
906 vc4_crtc->regset.regs = crtc_regs;
907 vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);
908
909 ret = vc4_crtc_init(drm, vc4_crtc,
910 &vc4_crtc_funcs, &vc4_crtc_helper_funcs);
911 if (ret)
912 return ret;
913 vc4_set_crtc_possible_masks(drm, crtc);
914
915 CRTC_WRITE(PV_INTEN, 0);
916 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
917 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
918 vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
919 if (ret)
920 goto err_destroy_planes;
921
922 platform_set_drvdata(pdev, vc4_crtc);
923
924 vc4_debugfs_add_regset32(drm, pv_data->debugfs_name,
925 &vc4_crtc->regset);
926
927 return 0;
928
929err_destroy_planes:
930 list_for_each_entry_safe(destroy_plane, temp,
931 &drm->mode_config.plane_list, head) {
932 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc))
933 destroy_plane->funcs->destroy(destroy_plane);
934 }
935
936 return ret;
937}
938
939static void vc4_crtc_unbind(struct device *dev, struct device *master,
940 void *data)
941{
942 struct platform_device *pdev = to_platform_device(dev);
943 struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
944
945 vc4_crtc_destroy(&vc4_crtc->base);
946
947 CRTC_WRITE(PV_INTEN, 0);
948
949 platform_set_drvdata(pdev, NULL);
950}
951
952static const struct component_ops vc4_crtc_ops = {
953 .bind = vc4_crtc_bind,
954 .unbind = vc4_crtc_unbind,
955};
956
957static int vc4_crtc_dev_probe(struct platform_device *pdev)
958{
959 return component_add(&pdev->dev, &vc4_crtc_ops);
960}
961
962static int vc4_crtc_dev_remove(struct platform_device *pdev)
963{
964 component_del(&pdev->dev, &vc4_crtc_ops);
965 return 0;
966}
967
968struct platform_driver vc4_crtc_driver = {
969 .probe = vc4_crtc_dev_probe,
970 .remove = vc4_crtc_dev_remove,
971 .driver = {
972 .name = "vc4_crtc",
973 .of_match_table = vc4_crtc_dt_match,
974 },
975};