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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net>
4 */
5
6#include <linux/delay.h>
7#include <linux/of_address.h>
8
9#include "sun8i_dw_hdmi.h"
10
11/*
12 * Address can be actually any value. Here is set to same value as
13 * it is set in BSP driver.
14 */
15#define I2C_ADDR 0x69
16
17static const struct dw_hdmi_mpll_config sun50i_h6_mpll_cfg[] = {
18 {
19 30666000, {
20 { 0x00b3, 0x0000 },
21 { 0x2153, 0x0000 },
22 { 0x40f3, 0x0000 },
23 },
24 }, {
25 36800000, {
26 { 0x00b3, 0x0000 },
27 { 0x2153, 0x0000 },
28 { 0x40a2, 0x0001 },
29 },
30 }, {
31 46000000, {
32 { 0x00b3, 0x0000 },
33 { 0x2142, 0x0001 },
34 { 0x40a2, 0x0001 },
35 },
36 }, {
37 61333000, {
38 { 0x0072, 0x0001 },
39 { 0x2142, 0x0001 },
40 { 0x40a2, 0x0001 },
41 },
42 }, {
43 73600000, {
44 { 0x0072, 0x0001 },
45 { 0x2142, 0x0001 },
46 { 0x4061, 0x0002 },
47 },
48 }, {
49 92000000, {
50 { 0x0072, 0x0001 },
51 { 0x2145, 0x0002 },
52 { 0x4061, 0x0002 },
53 },
54 }, {
55 122666000, {
56 { 0x0051, 0x0002 },
57 { 0x2145, 0x0002 },
58 { 0x4061, 0x0002 },
59 },
60 }, {
61 147200000, {
62 { 0x0051, 0x0002 },
63 { 0x2145, 0x0002 },
64 { 0x4064, 0x0003 },
65 },
66 }, {
67 184000000, {
68 { 0x0051, 0x0002 },
69 { 0x214c, 0x0003 },
70 { 0x4064, 0x0003 },
71 },
72 }, {
73 226666000, {
74 { 0x0040, 0x0003 },
75 { 0x214c, 0x0003 },
76 { 0x4064, 0x0003 },
77 },
78 }, {
79 272000000, {
80 { 0x0040, 0x0003 },
81 { 0x214c, 0x0003 },
82 { 0x5a64, 0x0003 },
83 },
84 }, {
85 340000000, {
86 { 0x0040, 0x0003 },
87 { 0x3b4c, 0x0003 },
88 { 0x5a64, 0x0003 },
89 },
90 }, {
91 594000000, {
92 { 0x1a40, 0x0003 },
93 { 0x3b4c, 0x0003 },
94 { 0x5a64, 0x0003 },
95 },
96 }, {
97 ~0UL, {
98 { 0x0000, 0x0000 },
99 { 0x0000, 0x0000 },
100 { 0x0000, 0x0000 },
101 },
102 }
103};
104
105static const struct dw_hdmi_curr_ctrl sun50i_h6_cur_ctr[] = {
106 /* pixelclk bpp8 bpp10 bpp12 */
107 { 25175000, { 0x0000, 0x0000, 0x0000 }, },
108 { 27000000, { 0x0012, 0x0000, 0x0000 }, },
109 { 59400000, { 0x0008, 0x0008, 0x0008 }, },
110 { 72000000, { 0x0008, 0x0008, 0x001b }, },
111 { 74250000, { 0x0013, 0x0013, 0x0013 }, },
112 { 90000000, { 0x0008, 0x001a, 0x001b }, },
113 { 118800000, { 0x001b, 0x001a, 0x001b }, },
114 { 144000000, { 0x001b, 0x001a, 0x0034 }, },
115 { 180000000, { 0x001b, 0x0033, 0x0034 }, },
116 { 216000000, { 0x0036, 0x0033, 0x0034 }, },
117 { 237600000, { 0x0036, 0x0033, 0x001b }, },
118 { 288000000, { 0x0036, 0x001b, 0x001b }, },
119 { 297000000, { 0x0019, 0x001b, 0x0019 }, },
120 { 330000000, { 0x0036, 0x001b, 0x001b }, },
121 { 594000000, { 0x003f, 0x001b, 0x001b }, },
122 { ~0UL, { 0x0000, 0x0000, 0x0000 }, }
123};
124
125static const struct dw_hdmi_phy_config sun50i_h6_phy_config[] = {
126 /*pixelclk symbol term vlev*/
127 { 74250000, 0x8009, 0x0004, 0x0232},
128 { 148500000, 0x8029, 0x0004, 0x0273},
129 { 594000000, 0x8039, 0x0004, 0x014a},
130 { ~0UL, 0x0000, 0x0000, 0x0000}
131};
132
133static int sun8i_hdmi_phy_config_a83t(struct dw_hdmi *hdmi,
134 struct sun8i_hdmi_phy *phy,
135 unsigned int clk_rate)
136{
137 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
138 SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN,
139 SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN);
140
141 /* power down */
142 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
143 dw_hdmi_phy_gen2_pddq(hdmi, 1);
144
145 dw_hdmi_phy_reset(hdmi);
146
147 dw_hdmi_phy_gen2_pddq(hdmi, 0);
148
149 dw_hdmi_phy_i2c_set_addr(hdmi, I2C_ADDR);
150
151 /*
152 * Values are taken from BSP HDMI driver. Although AW didn't
153 * release any documentation, explanation of this values can
154 * be found in i.MX 6Dual/6Quad Reference Manual.
155 */
156 if (clk_rate <= 27000000) {
157 dw_hdmi_phy_i2c_write(hdmi, 0x01e0, 0x06);
158 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);
159 dw_hdmi_phy_i2c_write(hdmi, 0x08da, 0x10);
160 dw_hdmi_phy_i2c_write(hdmi, 0x0007, 0x19);
161 dw_hdmi_phy_i2c_write(hdmi, 0x0318, 0x0e);
162 dw_hdmi_phy_i2c_write(hdmi, 0x8009, 0x09);
163 } else if (clk_rate <= 74250000) {
164 dw_hdmi_phy_i2c_write(hdmi, 0x0540, 0x06);
165 dw_hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
166 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
167 dw_hdmi_phy_i2c_write(hdmi, 0x0007, 0x19);
168 dw_hdmi_phy_i2c_write(hdmi, 0x02b5, 0x0e);
169 dw_hdmi_phy_i2c_write(hdmi, 0x8009, 0x09);
170 } else if (clk_rate <= 148500000) {
171 dw_hdmi_phy_i2c_write(hdmi, 0x04a0, 0x06);
172 dw_hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
173 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
174 dw_hdmi_phy_i2c_write(hdmi, 0x0002, 0x19);
175 dw_hdmi_phy_i2c_write(hdmi, 0x0021, 0x0e);
176 dw_hdmi_phy_i2c_write(hdmi, 0x8029, 0x09);
177 } else {
178 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x06);
179 dw_hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);
180 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
181 dw_hdmi_phy_i2c_write(hdmi, 0x0002, 0x19);
182 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x0e);
183 dw_hdmi_phy_i2c_write(hdmi, 0x802b, 0x09);
184 }
185
186 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x1e);
187 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);
188 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x17);
189
190 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
191
192 return 0;
193}
194
195static int sun8i_hdmi_phy_config_h3(struct dw_hdmi *hdmi,
196 struct sun8i_hdmi_phy *phy,
197 unsigned int clk_rate)
198{
199 u32 pll_cfg1_init;
200 u32 pll_cfg2_init;
201 u32 ana_cfg1_end;
202 u32 ana_cfg2_init;
203 u32 ana_cfg3_init;
204 u32 b_offset = 0;
205 u32 val;
206
207 /* bandwidth / frequency independent settings */
208
209 pll_cfg1_init = SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN |
210 SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN |
211 SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(7) |
212 SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(1) |
213 SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN |
214 SUN8I_HDMI_PHY_PLL_CFG1_CS |
215 SUN8I_HDMI_PHY_PLL_CFG1_CP_S(2) |
216 SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(63) |
217 SUN8I_HDMI_PHY_PLL_CFG1_BWS;
218
219 pll_cfg2_init = SUN8I_HDMI_PHY_PLL_CFG2_SV_H |
220 SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN |
221 SUN8I_HDMI_PHY_PLL_CFG2_SDIV2;
222
223 ana_cfg1_end = SUN8I_HDMI_PHY_ANA_CFG1_REG_SVBH(1) |
224 SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT |
225 SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT |
226 SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT |
227 SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT |
228 SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL |
229 SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG |
230 SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS |
231 SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN |
232 SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK |
233 SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL |
234 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK |
235 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 |
236 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 |
237 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 |
238 SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2 |
239 SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 |
240 SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 |
241 SUN8I_HDMI_PHY_ANA_CFG1_CKEN |
242 SUN8I_HDMI_PHY_ANA_CFG1_LDOEN |
243 SUN8I_HDMI_PHY_ANA_CFG1_ENVBS |
244 SUN8I_HDMI_PHY_ANA_CFG1_ENBI;
245
246 ana_cfg2_init = SUN8I_HDMI_PHY_ANA_CFG2_M_EN |
247 SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK |
248 SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN |
249 SUN8I_HDMI_PHY_ANA_CFG2_REG_CKSS(1) |
250 SUN8I_HDMI_PHY_ANA_CFG2_REG_CSMPS(1);
251
252 ana_cfg3_init = SUN8I_HDMI_PHY_ANA_CFG3_REG_WIRE(0x3e0) |
253 SUN8I_HDMI_PHY_ANA_CFG3_SDAEN |
254 SUN8I_HDMI_PHY_ANA_CFG3_SCLEN;
255
256 /* bandwidth / frequency dependent settings */
257 if (clk_rate <= 27000000) {
258 pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 |
259 SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32);
260 pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) |
261 SUN8I_HDMI_PHY_PLL_CFG2_S(4);
262 ana_cfg1_end |= SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW;
263 ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4) |
264 SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(phy->rcal);
265 ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(3) |
266 SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(5);
267 } else if (clk_rate <= 74250000) {
268 pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 |
269 SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32);
270 pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) |
271 SUN8I_HDMI_PHY_PLL_CFG2_S(5);
272 ana_cfg1_end |= SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW;
273 ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4) |
274 SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(phy->rcal);
275 ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(5) |
276 SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(7);
277 } else if (clk_rate <= 148500000) {
278 pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 |
279 SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32);
280 pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) |
281 SUN8I_HDMI_PHY_PLL_CFG2_S(6);
282 ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK |
283 SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW |
284 SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(2);
285 ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(7) |
286 SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(9);
287 } else {
288 b_offset = 2;
289 pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(63);
290 pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(6) |
291 SUN8I_HDMI_PHY_PLL_CFG2_S(7);
292 ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK |
293 SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW |
294 SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4);
295 ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(9) |
296 SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13) |
297 SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP(3);
298 }
299
300 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
301 SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK, 0);
302
303 /*
304 * NOTE: We have to be careful not to overwrite PHY parent
305 * clock selection bit and clock divider.
306 */
307 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
308 (u32)~SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK,
309 pll_cfg1_init);
310 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG,
311 (u32)~SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK,
312 pll_cfg2_init);
313 usleep_range(10000, 15000);
314 regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG3_REG,
315 SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2);
316 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
317 SUN8I_HDMI_PHY_PLL_CFG1_PLLEN,
318 SUN8I_HDMI_PHY_PLL_CFG1_PLLEN);
319 msleep(100);
320
321 /* get B value */
322 regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val);
323 val = (val & SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK) >>
324 SUN8I_HDMI_PHY_ANA_STS_B_OUT_SHIFT;
325 val = min(val + b_offset, (u32)0x3f);
326
327 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
328 SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1 |
329 SUN8I_HDMI_PHY_PLL_CFG1_REG_OD,
330 SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1 |
331 SUN8I_HDMI_PHY_PLL_CFG1_REG_OD);
332 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
333 SUN8I_HDMI_PHY_PLL_CFG1_B_IN_MSK,
334 val << SUN8I_HDMI_PHY_PLL_CFG1_B_IN_SHIFT);
335 msleep(100);
336 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, ana_cfg1_end);
337 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG2_REG, ana_cfg2_init);
338 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG3_REG, ana_cfg3_init);
339
340 return 0;
341}
342
343static int sun8i_hdmi_phy_config(struct dw_hdmi *hdmi, void *data,
344 const struct drm_display_info *display,
345 const struct drm_display_mode *mode)
346{
347 struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data;
348 u32 val = 0;
349
350 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
351 val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC;
352
353 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
354 val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC;
355
356 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
357 SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK, val);
358
359 if (phy->variant->has_phy_clk)
360 clk_set_rate(phy->clk_phy, mode->crtc_clock * 1000);
361
362 return phy->variant->phy_config(hdmi, phy, mode->crtc_clock * 1000);
363};
364
365static void sun8i_hdmi_phy_disable_a83t(struct dw_hdmi *hdmi,
366 struct sun8i_hdmi_phy *phy)
367{
368 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
369 dw_hdmi_phy_gen2_pddq(hdmi, 1);
370
371 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
372 SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN, 0);
373}
374
375static void sun8i_hdmi_phy_disable_h3(struct dw_hdmi *hdmi,
376 struct sun8i_hdmi_phy *phy)
377{
378 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
379 SUN8I_HDMI_PHY_ANA_CFG1_LDOEN |
380 SUN8I_HDMI_PHY_ANA_CFG1_ENVBS |
381 SUN8I_HDMI_PHY_ANA_CFG1_ENBI);
382 regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, 0);
383}
384
385static void sun8i_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
386{
387 struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data;
388
389 phy->variant->phy_disable(hdmi, phy);
390}
391
392static const struct dw_hdmi_phy_ops sun8i_hdmi_phy_ops = {
393 .init = &sun8i_hdmi_phy_config,
394 .disable = &sun8i_hdmi_phy_disable,
395 .read_hpd = &dw_hdmi_phy_read_hpd,
396 .update_hpd = &dw_hdmi_phy_update_hpd,
397 .setup_hpd = &dw_hdmi_phy_setup_hpd,
398};
399
400static void sun8i_hdmi_phy_unlock(struct sun8i_hdmi_phy *phy)
401{
402 /* enable read access to HDMI controller */
403 regmap_write(phy->regs, SUN8I_HDMI_PHY_READ_EN_REG,
404 SUN8I_HDMI_PHY_READ_EN_MAGIC);
405
406 /* unscramble register offsets */
407 regmap_write(phy->regs, SUN8I_HDMI_PHY_UNSCRAMBLE_REG,
408 SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC);
409}
410
411static void sun50i_hdmi_phy_init_h6(struct sun8i_hdmi_phy *phy)
412{
413 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
414 SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN,
415 SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN);
416
417 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
418 0xffff0000, 0x80c00000);
419}
420
421static void sun8i_hdmi_phy_init_a83t(struct sun8i_hdmi_phy *phy)
422{
423 sun8i_hdmi_phy_unlock(phy);
424
425 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
426 SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK,
427 SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK);
428
429 /*
430 * Set PHY I2C address. It must match to the address set by
431 * dw_hdmi_phy_set_slave_addr().
432 */
433 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
434 SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK,
435 SUN8I_HDMI_PHY_DBG_CTRL_ADDR(I2C_ADDR));
436}
437
438static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy)
439{
440 unsigned int val;
441
442 sun8i_hdmi_phy_unlock(phy);
443
444 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 0);
445 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
446 SUN8I_HDMI_PHY_ANA_CFG1_ENBI,
447 SUN8I_HDMI_PHY_ANA_CFG1_ENBI);
448 udelay(5);
449 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
450 SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN,
451 SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN);
452 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
453 SUN8I_HDMI_PHY_ANA_CFG1_ENVBS,
454 SUN8I_HDMI_PHY_ANA_CFG1_ENVBS);
455 usleep_range(10, 20);
456 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
457 SUN8I_HDMI_PHY_ANA_CFG1_LDOEN,
458 SUN8I_HDMI_PHY_ANA_CFG1_LDOEN);
459 udelay(5);
460 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
461 SUN8I_HDMI_PHY_ANA_CFG1_CKEN,
462 SUN8I_HDMI_PHY_ANA_CFG1_CKEN);
463 usleep_range(40, 100);
464 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
465 SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL,
466 SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL);
467 usleep_range(100, 200);
468 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
469 SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG,
470 SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG);
471 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
472 SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 |
473 SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 |
474 SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2,
475 SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 |
476 SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 |
477 SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2);
478
479 /* wait for calibration to finish */
480 regmap_read_poll_timeout(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, val,
481 (val & SUN8I_HDMI_PHY_ANA_STS_RCALEND2D),
482 100, 2000);
483
484 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
485 SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK,
486 SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK);
487 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
488 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 |
489 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 |
490 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 |
491 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK,
492 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 |
493 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 |
494 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 |
495 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK);
496
497 /* enable DDC communication */
498 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG3_REG,
499 SUN8I_HDMI_PHY_ANA_CFG3_SCLEN |
500 SUN8I_HDMI_PHY_ANA_CFG3_SDAEN,
501 SUN8I_HDMI_PHY_ANA_CFG3_SCLEN |
502 SUN8I_HDMI_PHY_ANA_CFG3_SDAEN);
503
504 /* reset PHY PLL clock parent */
505 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
506 SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK, 0);
507
508 /* set HW control of CEC pins */
509 regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG, 0);
510
511 /* read calibration data */
512 regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val);
513 phy->rcal = (val & SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK) >> 2;
514}
515
516void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy)
517{
518 phy->variant->phy_init(phy);
519}
520
521void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy,
522 struct dw_hdmi_plat_data *plat_data)
523{
524 struct sun8i_hdmi_phy_variant *variant = phy->variant;
525
526 if (variant->is_custom_phy) {
527 plat_data->phy_ops = &sun8i_hdmi_phy_ops;
528 plat_data->phy_name = "sun8i_dw_hdmi_phy";
529 plat_data->phy_data = phy;
530 } else {
531 plat_data->mpll_cfg = variant->mpll_cfg;
532 plat_data->cur_ctr = variant->cur_ctr;
533 plat_data->phy_config = variant->phy_cfg;
534 }
535}
536
537static struct regmap_config sun8i_hdmi_phy_regmap_config = {
538 .reg_bits = 32,
539 .val_bits = 32,
540 .reg_stride = 4,
541 .max_register = SUN8I_HDMI_PHY_CEC_REG,
542 .name = "phy"
543};
544
545static const struct sun8i_hdmi_phy_variant sun8i_a83t_hdmi_phy = {
546 .is_custom_phy = true,
547 .phy_init = &sun8i_hdmi_phy_init_a83t,
548 .phy_disable = &sun8i_hdmi_phy_disable_a83t,
549 .phy_config = &sun8i_hdmi_phy_config_a83t,
550};
551
552static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = {
553 .has_phy_clk = true,
554 .is_custom_phy = true,
555 .phy_init = &sun8i_hdmi_phy_init_h3,
556 .phy_disable = &sun8i_hdmi_phy_disable_h3,
557 .phy_config = &sun8i_hdmi_phy_config_h3,
558};
559
560static const struct sun8i_hdmi_phy_variant sun8i_r40_hdmi_phy = {
561 .has_phy_clk = true,
562 .has_second_pll = true,
563 .is_custom_phy = true,
564 .phy_init = &sun8i_hdmi_phy_init_h3,
565 .phy_disable = &sun8i_hdmi_phy_disable_h3,
566 .phy_config = &sun8i_hdmi_phy_config_h3,
567};
568
569static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = {
570 .has_phy_clk = true,
571 .is_custom_phy = true,
572 .phy_init = &sun8i_hdmi_phy_init_h3,
573 .phy_disable = &sun8i_hdmi_phy_disable_h3,
574 .phy_config = &sun8i_hdmi_phy_config_h3,
575};
576
577static const struct sun8i_hdmi_phy_variant sun50i_h6_hdmi_phy = {
578 .cur_ctr = sun50i_h6_cur_ctr,
579 .mpll_cfg = sun50i_h6_mpll_cfg,
580 .phy_cfg = sun50i_h6_phy_config,
581 .phy_init = &sun50i_hdmi_phy_init_h6,
582};
583
584static const struct of_device_id sun8i_hdmi_phy_of_table[] = {
585 {
586 .compatible = "allwinner,sun8i-a83t-hdmi-phy",
587 .data = &sun8i_a83t_hdmi_phy,
588 },
589 {
590 .compatible = "allwinner,sun8i-h3-hdmi-phy",
591 .data = &sun8i_h3_hdmi_phy,
592 },
593 {
594 .compatible = "allwinner,sun8i-r40-hdmi-phy",
595 .data = &sun8i_r40_hdmi_phy,
596 },
597 {
598 .compatible = "allwinner,sun50i-a64-hdmi-phy",
599 .data = &sun50i_a64_hdmi_phy,
600 },
601 {
602 .compatible = "allwinner,sun50i-h6-hdmi-phy",
603 .data = &sun50i_h6_hdmi_phy,
604 },
605 { /* sentinel */ }
606};
607
608int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
609{
610 const struct of_device_id *match;
611 struct device *dev = hdmi->dev;
612 struct sun8i_hdmi_phy *phy;
613 struct resource res;
614 void __iomem *regs;
615 int ret;
616
617 match = of_match_node(sun8i_hdmi_phy_of_table, node);
618 if (!match) {
619 dev_err(dev, "Incompatible HDMI PHY\n");
620 return -EINVAL;
621 }
622
623 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
624 if (!phy)
625 return -ENOMEM;
626
627 phy->variant = (struct sun8i_hdmi_phy_variant *)match->data;
628
629 ret = of_address_to_resource(node, 0, &res);
630 if (ret) {
631 dev_err(dev, "phy: Couldn't get our resources\n");
632 return ret;
633 }
634
635 regs = devm_ioremap_resource(dev, &res);
636 if (IS_ERR(regs)) {
637 dev_err(dev, "Couldn't map the HDMI PHY registers\n");
638 return PTR_ERR(regs);
639 }
640
641 phy->regs = devm_regmap_init_mmio(dev, regs,
642 &sun8i_hdmi_phy_regmap_config);
643 if (IS_ERR(phy->regs)) {
644 dev_err(dev, "Couldn't create the HDMI PHY regmap\n");
645 return PTR_ERR(phy->regs);
646 }
647
648 phy->clk_bus = of_clk_get_by_name(node, "bus");
649 if (IS_ERR(phy->clk_bus)) {
650 dev_err(dev, "Could not get bus clock\n");
651 return PTR_ERR(phy->clk_bus);
652 }
653
654 phy->clk_mod = of_clk_get_by_name(node, "mod");
655 if (IS_ERR(phy->clk_mod)) {
656 dev_err(dev, "Could not get mod clock\n");
657 ret = PTR_ERR(phy->clk_mod);
658 goto err_put_clk_bus;
659 }
660
661 if (phy->variant->has_phy_clk) {
662 phy->clk_pll0 = of_clk_get_by_name(node, "pll-0");
663 if (IS_ERR(phy->clk_pll0)) {
664 dev_err(dev, "Could not get pll-0 clock\n");
665 ret = PTR_ERR(phy->clk_pll0);
666 goto err_put_clk_mod;
667 }
668
669 if (phy->variant->has_second_pll) {
670 phy->clk_pll1 = of_clk_get_by_name(node, "pll-1");
671 if (IS_ERR(phy->clk_pll1)) {
672 dev_err(dev, "Could not get pll-1 clock\n");
673 ret = PTR_ERR(phy->clk_pll1);
674 goto err_put_clk_pll0;
675 }
676 }
677 }
678
679 phy->rst_phy = of_reset_control_get_shared(node, "phy");
680 if (IS_ERR(phy->rst_phy)) {
681 dev_err(dev, "Could not get phy reset control\n");
682 ret = PTR_ERR(phy->rst_phy);
683 goto err_put_clk_pll1;
684 }
685
686 ret = reset_control_deassert(phy->rst_phy);
687 if (ret) {
688 dev_err(dev, "Cannot deassert phy reset control: %d\n", ret);
689 goto err_put_rst_phy;
690 }
691
692 ret = clk_prepare_enable(phy->clk_bus);
693 if (ret) {
694 dev_err(dev, "Cannot enable bus clock: %d\n", ret);
695 goto err_deassert_rst_phy;
696 }
697
698 ret = clk_prepare_enable(phy->clk_mod);
699 if (ret) {
700 dev_err(dev, "Cannot enable mod clock: %d\n", ret);
701 goto err_disable_clk_bus;
702 }
703
704 if (phy->variant->has_phy_clk) {
705 ret = sun8i_phy_clk_create(phy, dev,
706 phy->variant->has_second_pll);
707 if (ret) {
708 dev_err(dev, "Couldn't create the PHY clock\n");
709 goto err_disable_clk_mod;
710 }
711
712 clk_prepare_enable(phy->clk_phy);
713 }
714
715 hdmi->phy = phy;
716
717 return 0;
718
719err_disable_clk_mod:
720 clk_disable_unprepare(phy->clk_mod);
721err_disable_clk_bus:
722 clk_disable_unprepare(phy->clk_bus);
723err_deassert_rst_phy:
724 reset_control_assert(phy->rst_phy);
725err_put_rst_phy:
726 reset_control_put(phy->rst_phy);
727err_put_clk_pll1:
728 clk_put(phy->clk_pll1);
729err_put_clk_pll0:
730 clk_put(phy->clk_pll0);
731err_put_clk_mod:
732 clk_put(phy->clk_mod);
733err_put_clk_bus:
734 clk_put(phy->clk_bus);
735
736 return ret;
737}
738
739void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi)
740{
741 struct sun8i_hdmi_phy *phy = hdmi->phy;
742
743 clk_disable_unprepare(phy->clk_mod);
744 clk_disable_unprepare(phy->clk_bus);
745 clk_disable_unprepare(phy->clk_phy);
746
747 reset_control_assert(phy->rst_phy);
748
749 reset_control_put(phy->rst_phy);
750
751 clk_put(phy->clk_pll0);
752 clk_put(phy->clk_pll1);
753 clk_put(phy->clk_mod);
754 clk_put(phy->clk_bus);
755}