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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * rcar_du_crtc.c -- R-Car Display Unit CRTCs
4 *
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
6 *
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 */
9
10#include <linux/clk.h>
11#include <linux/mutex.h>
12#include <linux/platform_device.h>
13#include <linux/sys_soc.h>
14
15#include <drm/drm_atomic.h>
16#include <drm/drm_atomic_helper.h>
17#include <drm/drm_bridge.h>
18#include <drm/drm_crtc.h>
19#include <drm/drm_device.h>
20#include <drm/drm_fb_cma_helper.h>
21#include <drm/drm_gem_cma_helper.h>
22#include <drm/drm_plane_helper.h>
23#include <drm/drm_vblank.h>
24
25#include "rcar_cmm.h"
26#include "rcar_du_crtc.h"
27#include "rcar_du_drv.h"
28#include "rcar_du_encoder.h"
29#include "rcar_du_kms.h"
30#include "rcar_du_plane.h"
31#include "rcar_du_regs.h"
32#include "rcar_du_vsp.h"
33#include "rcar_lvds.h"
34
35static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
36{
37 struct rcar_du_device *rcdu = rcrtc->dev;
38
39 return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
40}
41
42static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
43{
44 struct rcar_du_device *rcdu = rcrtc->dev;
45
46 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
47}
48
49static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
50{
51 struct rcar_du_device *rcdu = rcrtc->dev;
52
53 rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
54 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
55}
56
57static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
58{
59 struct rcar_du_device *rcdu = rcrtc->dev;
60
61 rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
62 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
63}
64
65void rcar_du_crtc_dsysr_clr_set(struct rcar_du_crtc *rcrtc, u32 clr, u32 set)
66{
67 struct rcar_du_device *rcdu = rcrtc->dev;
68
69 rcrtc->dsysr = (rcrtc->dsysr & ~clr) | set;
70 rcar_du_write(rcdu, rcrtc->mmio_offset + DSYSR, rcrtc->dsysr);
71}
72
73/* -----------------------------------------------------------------------------
74 * Hardware Setup
75 */
76
77struct dpll_info {
78 unsigned int output;
79 unsigned int fdpll;
80 unsigned int n;
81 unsigned int m;
82};
83
84static void rcar_du_dpll_divider(struct rcar_du_crtc *rcrtc,
85 struct dpll_info *dpll,
86 unsigned long input,
87 unsigned long target)
88{
89 unsigned long best_diff = (unsigned long)-1;
90 unsigned long diff;
91 unsigned int fdpll;
92 unsigned int m;
93 unsigned int n;
94
95 /*
96 * fin fvco fout fclkout
97 * in --> [1/M] --> |PD| -> [LPF] -> [VCO] -> [1/P] -+-> [1/FDPLL] -> out
98 * +-> | | |
99 * | |
100 * +---------------- [1/N] <------------+
101 *
102 * fclkout = fvco / P / FDPLL -- (1)
103 *
104 * fin/M = fvco/P/N
105 *
106 * fvco = fin * P * N / M -- (2)
107 *
108 * (1) + (2) indicates
109 *
110 * fclkout = fin * N / M / FDPLL
111 *
112 * NOTES
113 * N : (n + 1)
114 * M : (m + 1)
115 * FDPLL : (fdpll + 1)
116 * P : 2
117 * 2kHz < fvco < 4096MHz
118 *
119 * To minimize the jitter,
120 * N : as large as possible
121 * M : as small as possible
122 */
123 for (m = 0; m < 4; m++) {
124 for (n = 119; n > 38; n--) {
125 /*
126 * This code only runs on 64-bit architectures, the
127 * unsigned long type can thus be used for 64-bit
128 * computation. It will still compile without any
129 * warning on 32-bit architectures.
130 *
131 * To optimize calculations, use fout instead of fvco
132 * to verify the VCO frequency constraint.
133 */
134 unsigned long fout = input * (n + 1) / (m + 1);
135
136 if (fout < 1000 || fout > 2048 * 1000 * 1000U)
137 continue;
138
139 for (fdpll = 1; fdpll < 32; fdpll++) {
140 unsigned long output;
141
142 output = fout / (fdpll + 1);
143 if (output >= 400 * 1000 * 1000)
144 continue;
145
146 diff = abs((long)output - (long)target);
147 if (best_diff > diff) {
148 best_diff = diff;
149 dpll->n = n;
150 dpll->m = m;
151 dpll->fdpll = fdpll;
152 dpll->output = output;
153 }
154
155 if (diff == 0)
156 goto done;
157 }
158 }
159 }
160
161done:
162 dev_dbg(rcrtc->dev->dev,
163 "output:%u, fdpll:%u, n:%u, m:%u, diff:%lu\n",
164 dpll->output, dpll->fdpll, dpll->n, dpll->m, best_diff);
165}
166
167struct du_clk_params {
168 struct clk *clk;
169 unsigned long rate;
170 unsigned long diff;
171 u32 escr;
172};
173
174static void rcar_du_escr_divider(struct clk *clk, unsigned long target,
175 u32 escr, struct du_clk_params *params)
176{
177 unsigned long rate;
178 unsigned long diff;
179 u32 div;
180
181 /*
182 * If the target rate has already been achieved perfectly we can't do
183 * better.
184 */
185 if (params->diff == 0)
186 return;
187
188 /*
189 * Compute the input clock rate and internal divisor values to obtain
190 * the clock rate closest to the target frequency.
191 */
192 rate = clk_round_rate(clk, target);
193 div = clamp(DIV_ROUND_CLOSEST(rate, target), 1UL, 64UL) - 1;
194 diff = abs(rate / (div + 1) - target);
195
196 /*
197 * Store the parameters if the resulting frequency is better than any
198 * previously calculated value.
199 */
200 if (diff < params->diff) {
201 params->clk = clk;
202 params->rate = rate;
203 params->diff = diff;
204 params->escr = escr | div;
205 }
206}
207
208static const struct soc_device_attribute rcar_du_r8a7795_es1[] = {
209 { .soc_id = "r8a7795", .revision = "ES1.*" },
210 { /* sentinel */ }
211};
212
213static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
214{
215 const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
216 struct rcar_du_device *rcdu = rcrtc->dev;
217 unsigned long mode_clock = mode->clock * 1000;
218 u32 dsmr;
219 u32 escr;
220
221 if (rcdu->info->dpll_mask & (1 << rcrtc->index)) {
222 unsigned long target = mode_clock;
223 struct dpll_info dpll = { 0 };
224 unsigned long extclk;
225 u32 dpllcr;
226 u32 div = 0;
227
228 /*
229 * DU channels that have a display PLL can't use the internal
230 * system clock, and have no internal clock divider.
231 */
232
233 /*
234 * The H3 ES1.x exhibits dot clock duty cycle stability issues.
235 * We can work around them by configuring the DPLL to twice the
236 * desired frequency, coupled with a /2 post-divider. Restrict
237 * the workaround to H3 ES1.x as ES2.0 and all other SoCs have
238 * no post-divider when a display PLL is present (as shown by
239 * the workaround breaking HDMI output on M3-W during testing).
240 */
241 if (soc_device_match(rcar_du_r8a7795_es1)) {
242 target *= 2;
243 div = 1;
244 }
245
246 extclk = clk_get_rate(rcrtc->extclock);
247 rcar_du_dpll_divider(rcrtc, &dpll, extclk, target);
248
249 dpllcr = DPLLCR_CODE | DPLLCR_CLKE
250 | DPLLCR_FDPLL(dpll.fdpll)
251 | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m)
252 | DPLLCR_STBY;
253
254 if (rcrtc->index == 1)
255 dpllcr |= DPLLCR_PLCS1
256 | DPLLCR_INCS_DOTCLKIN1;
257 else
258 dpllcr |= DPLLCR_PLCS0
259 | DPLLCR_INCS_DOTCLKIN0;
260
261 rcar_du_group_write(rcrtc->group, DPLLCR, dpllcr);
262
263 escr = ESCR_DCLKSEL_DCLKIN | div;
264 } else if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index)) {
265 /*
266 * Use the LVDS PLL output as the dot clock when outputting to
267 * the LVDS encoder on an SoC that supports this clock routing
268 * option. We use the clock directly in that case, without any
269 * additional divider.
270 */
271 escr = ESCR_DCLKSEL_DCLKIN;
272 } else {
273 struct du_clk_params params = { .diff = (unsigned long)-1 };
274
275 rcar_du_escr_divider(rcrtc->clock, mode_clock,
276 ESCR_DCLKSEL_CLKS, ¶ms);
277 if (rcrtc->extclock)
278 rcar_du_escr_divider(rcrtc->extclock, mode_clock,
279 ESCR_DCLKSEL_DCLKIN, ¶ms);
280
281 dev_dbg(rcrtc->dev->dev, "mode clock %lu %s rate %lu\n",
282 mode_clock, params.clk == rcrtc->clock ? "cpg" : "ext",
283 params.rate);
284
285 clk_set_rate(params.clk, params.rate);
286 escr = params.escr;
287 }
288
289 dev_dbg(rcrtc->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr);
290
291 rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
292 rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0);
293
294 /* Signal polarities */
295 dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
296 | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0)
297 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? DSMR_ODEV : 0)
298 | DSMR_DIPM_DISP | DSMR_CSPM;
299 rcar_du_crtc_write(rcrtc, DSMR, dsmr);
300
301 /* Display timings */
302 rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
303 rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
304 mode->hdisplay - 19);
305 rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
306 mode->hsync_start - 1);
307 rcar_du_crtc_write(rcrtc, HCR, mode->htotal - 1);
308
309 rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
310 mode->crtc_vsync_end - 2);
311 rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
312 mode->crtc_vsync_end +
313 mode->crtc_vdisplay - 2);
314 rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
315 mode->crtc_vsync_end +
316 mode->crtc_vsync_start - 1);
317 rcar_du_crtc_write(rcrtc, VCR, mode->crtc_vtotal - 1);
318
319 rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start - 1);
320 rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay);
321}
322
323static unsigned int plane_zpos(struct rcar_du_plane *plane)
324{
325 return plane->plane.state->normalized_zpos;
326}
327
328static const struct rcar_du_format_info *
329plane_format(struct rcar_du_plane *plane)
330{
331 return to_rcar_plane_state(plane->plane.state)->format;
332}
333
334static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc)
335{
336 struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
337 struct rcar_du_device *rcdu = rcrtc->dev;
338 unsigned int num_planes = 0;
339 unsigned int dptsr_planes;
340 unsigned int hwplanes = 0;
341 unsigned int prio = 0;
342 unsigned int i;
343 u32 dspr = 0;
344
345 for (i = 0; i < rcrtc->group->num_planes; ++i) {
346 struct rcar_du_plane *plane = &rcrtc->group->planes[i];
347 unsigned int j;
348
349 if (plane->plane.state->crtc != &rcrtc->crtc ||
350 !plane->plane.state->visible)
351 continue;
352
353 /* Insert the plane in the sorted planes array. */
354 for (j = num_planes++; j > 0; --j) {
355 if (plane_zpos(planes[j-1]) <= plane_zpos(plane))
356 break;
357 planes[j] = planes[j-1];
358 }
359
360 planes[j] = plane;
361 prio += plane_format(plane)->planes * 4;
362 }
363
364 for (i = 0; i < num_planes; ++i) {
365 struct rcar_du_plane *plane = planes[i];
366 struct drm_plane_state *state = plane->plane.state;
367 unsigned int index = to_rcar_plane_state(state)->hwindex;
368
369 prio -= 4;
370 dspr |= (index + 1) << prio;
371 hwplanes |= 1 << index;
372
373 if (plane_format(plane)->planes == 2) {
374 index = (index + 1) % 8;
375
376 prio -= 4;
377 dspr |= (index + 1) << prio;
378 hwplanes |= 1 << index;
379 }
380 }
381
382 /* If VSP+DU integration is enabled the plane assignment is fixed. */
383 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
384 if (rcdu->info->gen < 3) {
385 dspr = (rcrtc->index % 2) + 1;
386 hwplanes = 1 << (rcrtc->index % 2);
387 } else {
388 dspr = (rcrtc->index % 2) ? 3 : 1;
389 hwplanes = 1 << ((rcrtc->index % 2) ? 2 : 0);
390 }
391 }
392
393 /*
394 * Update the planes to display timing and dot clock generator
395 * associations.
396 *
397 * Updating the DPTSR register requires restarting the CRTC group,
398 * resulting in visible flicker. To mitigate the issue only update the
399 * association if needed by enabled planes. Planes being disabled will
400 * keep their current association.
401 */
402 mutex_lock(&rcrtc->group->lock);
403
404 dptsr_planes = rcrtc->index % 2 ? rcrtc->group->dptsr_planes | hwplanes
405 : rcrtc->group->dptsr_planes & ~hwplanes;
406
407 if (dptsr_planes != rcrtc->group->dptsr_planes) {
408 rcar_du_group_write(rcrtc->group, DPTSR,
409 (dptsr_planes << 16) | dptsr_planes);
410 rcrtc->group->dptsr_planes = dptsr_planes;
411
412 if (rcrtc->group->used_crtcs)
413 rcar_du_group_restart(rcrtc->group);
414 }
415
416 /* Restart the group if plane sources have changed. */
417 if (rcrtc->group->need_restart)
418 rcar_du_group_restart(rcrtc->group);
419
420 mutex_unlock(&rcrtc->group->lock);
421
422 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
423 dspr);
424}
425
426/* -----------------------------------------------------------------------------
427 * Page Flip
428 */
429
430void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
431{
432 struct drm_pending_vblank_event *event;
433 struct drm_device *dev = rcrtc->crtc.dev;
434 unsigned long flags;
435
436 spin_lock_irqsave(&dev->event_lock, flags);
437 event = rcrtc->event;
438 rcrtc->event = NULL;
439 spin_unlock_irqrestore(&dev->event_lock, flags);
440
441 if (event == NULL)
442 return;
443
444 spin_lock_irqsave(&dev->event_lock, flags);
445 drm_crtc_send_vblank_event(&rcrtc->crtc, event);
446 wake_up(&rcrtc->flip_wait);
447 spin_unlock_irqrestore(&dev->event_lock, flags);
448
449 drm_crtc_vblank_put(&rcrtc->crtc);
450}
451
452static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
453{
454 struct drm_device *dev = rcrtc->crtc.dev;
455 unsigned long flags;
456 bool pending;
457
458 spin_lock_irqsave(&dev->event_lock, flags);
459 pending = rcrtc->event != NULL;
460 spin_unlock_irqrestore(&dev->event_lock, flags);
461
462 return pending;
463}
464
465static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
466{
467 struct rcar_du_device *rcdu = rcrtc->dev;
468
469 if (wait_event_timeout(rcrtc->flip_wait,
470 !rcar_du_crtc_page_flip_pending(rcrtc),
471 msecs_to_jiffies(50)))
472 return;
473
474 dev_warn(rcdu->dev, "page flip timeout\n");
475
476 rcar_du_crtc_finish_page_flip(rcrtc);
477}
478
479/* -----------------------------------------------------------------------------
480 * Color Management Module (CMM)
481 */
482
483static int rcar_du_cmm_check(struct drm_crtc *crtc,
484 struct drm_crtc_state *state)
485{
486 struct drm_property_blob *drm_lut = state->gamma_lut;
487 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
488 struct device *dev = rcrtc->dev->dev;
489
490 if (!drm_lut)
491 return 0;
492
493 /* We only accept fully populated LUT tables. */
494 if (drm_color_lut_size(drm_lut) != CM2_LUT_SIZE) {
495 dev_err(dev, "invalid gamma lut size: %zu bytes\n",
496 drm_lut->length);
497 return -EINVAL;
498 }
499
500 return 0;
501}
502
503static void rcar_du_cmm_setup(struct drm_crtc *crtc)
504{
505 struct drm_property_blob *drm_lut = crtc->state->gamma_lut;
506 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
507 struct rcar_cmm_config cmm_config = {};
508
509 if (!rcrtc->cmm)
510 return;
511
512 if (drm_lut)
513 cmm_config.lut.table = (struct drm_color_lut *)drm_lut->data;
514
515 rcar_cmm_setup(rcrtc->cmm, &cmm_config);
516}
517
518/* -----------------------------------------------------------------------------
519 * Start/Stop and Suspend/Resume
520 */
521
522static void rcar_du_crtc_setup(struct rcar_du_crtc *rcrtc)
523{
524 /* Set display off and background to black */
525 rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
526 rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
527
528 /* Configure display timings and output routing */
529 rcar_du_crtc_set_display_timing(rcrtc);
530 rcar_du_group_set_routing(rcrtc->group);
531
532 /* Start with all planes disabled. */
533 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
534
535 /* Enable the VSP compositor. */
536 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
537 rcar_du_vsp_enable(rcrtc);
538
539 /* Turn vertical blanking interrupt reporting on. */
540 drm_crtc_vblank_on(&rcrtc->crtc);
541}
542
543static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
544{
545 int ret;
546
547 /*
548 * Guard against double-get, as the function is called from both the
549 * .atomic_enable() and .atomic_begin() handlers.
550 */
551 if (rcrtc->initialized)
552 return 0;
553
554 ret = clk_prepare_enable(rcrtc->clock);
555 if (ret < 0)
556 return ret;
557
558 ret = clk_prepare_enable(rcrtc->extclock);
559 if (ret < 0)
560 goto error_clock;
561
562 ret = rcar_du_group_get(rcrtc->group);
563 if (ret < 0)
564 goto error_group;
565
566 rcar_du_crtc_setup(rcrtc);
567 rcrtc->initialized = true;
568
569 return 0;
570
571error_group:
572 clk_disable_unprepare(rcrtc->extclock);
573error_clock:
574 clk_disable_unprepare(rcrtc->clock);
575 return ret;
576}
577
578static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
579{
580 rcar_du_group_put(rcrtc->group);
581
582 clk_disable_unprepare(rcrtc->extclock);
583 clk_disable_unprepare(rcrtc->clock);
584
585 rcrtc->initialized = false;
586}
587
588static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
589{
590 bool interlaced;
591
592 /*
593 * Select master sync mode. This enables display operation in master
594 * sync mode (with the HSYNC and VSYNC signals configured as outputs and
595 * actively driven).
596 */
597 interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
598 rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
599 (interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
600 DSYSR_TVM_MASTER);
601
602 rcar_du_group_start_stop(rcrtc->group, true);
603}
604
605static void rcar_du_crtc_disable_planes(struct rcar_du_crtc *rcrtc)
606{
607 struct rcar_du_device *rcdu = rcrtc->dev;
608 struct drm_crtc *crtc = &rcrtc->crtc;
609 u32 status;
610
611 /* Make sure vblank interrupts are enabled. */
612 drm_crtc_vblank_get(crtc);
613
614 /*
615 * Disable planes and calculate how many vertical blanking interrupts we
616 * have to wait for. If a vertical blanking interrupt has been triggered
617 * but not processed yet, we don't know whether it occurred before or
618 * after the planes got disabled. We thus have to wait for two vblank
619 * interrupts in that case.
620 */
621 spin_lock_irq(&rcrtc->vblank_lock);
622 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
623 status = rcar_du_crtc_read(rcrtc, DSSR);
624 rcrtc->vblank_count = status & DSSR_VBK ? 2 : 1;
625 spin_unlock_irq(&rcrtc->vblank_lock);
626
627 if (!wait_event_timeout(rcrtc->vblank_wait, rcrtc->vblank_count == 0,
628 msecs_to_jiffies(100)))
629 dev_warn(rcdu->dev, "vertical blanking timeout\n");
630
631 drm_crtc_vblank_put(crtc);
632}
633
634static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
635{
636 struct drm_crtc *crtc = &rcrtc->crtc;
637
638 /*
639 * Disable all planes and wait for the change to take effect. This is
640 * required as the plane enable registers are updated on vblank, and no
641 * vblank will occur once the CRTC is stopped. Disabling planes when
642 * starting the CRTC thus wouldn't be enough as it would start scanning
643 * out immediately from old frame buffers until the next vblank.
644 *
645 * This increases the CRTC stop delay, especially when multiple CRTCs
646 * are stopped in one operation as we now wait for one vblank per CRTC.
647 * Whether this can be improved needs to be researched.
648 */
649 rcar_du_crtc_disable_planes(rcrtc);
650
651 /*
652 * Disable vertical blanking interrupt reporting. We first need to wait
653 * for page flip completion before stopping the CRTC as userspace
654 * expects page flips to eventually complete.
655 */
656 rcar_du_crtc_wait_page_flip(rcrtc);
657 drm_crtc_vblank_off(crtc);
658
659 /* Disable the VSP compositor. */
660 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
661 rcar_du_vsp_disable(rcrtc);
662
663 if (rcrtc->cmm)
664 rcar_cmm_disable(rcrtc->cmm);
665
666 /*
667 * Select switch sync mode. This stops display operation and configures
668 * the HSYNC and VSYNC signals as inputs.
669 *
670 * TODO: Find another way to stop the display for DUs that don't support
671 * TVM sync.
672 */
673 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_TVM_SYNC))
674 rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_TVM_MASK,
675 DSYSR_TVM_SWITCH);
676
677 rcar_du_group_start_stop(rcrtc->group, false);
678}
679
680/* -----------------------------------------------------------------------------
681 * CRTC Functions
682 */
683
684static int rcar_du_crtc_atomic_check(struct drm_crtc *crtc,
685 struct drm_crtc_state *state)
686{
687 struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(state);
688 struct drm_encoder *encoder;
689 int ret;
690
691 ret = rcar_du_cmm_check(crtc, state);
692 if (ret)
693 return ret;
694
695 /* Store the routes from the CRTC output to the DU outputs. */
696 rstate->outputs = 0;
697
698 drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) {
699 struct rcar_du_encoder *renc;
700
701 /* Skip the writeback encoder. */
702 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
703 continue;
704
705 renc = to_rcar_encoder(encoder);
706 rstate->outputs |= BIT(renc->output);
707 }
708
709 return 0;
710}
711
712static void rcar_du_crtc_atomic_enable(struct drm_crtc *crtc,
713 struct drm_crtc_state *old_state)
714{
715 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
716 struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(crtc->state);
717 struct rcar_du_device *rcdu = rcrtc->dev;
718
719 if (rcrtc->cmm)
720 rcar_cmm_enable(rcrtc->cmm);
721 rcar_du_crtc_get(rcrtc);
722
723 /*
724 * On D3/E3 the dot clock is provided by the LVDS encoder attached to
725 * the DU channel. We need to enable its clock output explicitly if
726 * the LVDS output is disabled.
727 */
728 if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index) &&
729 rstate->outputs == BIT(RCAR_DU_OUTPUT_DPAD0)) {
730 struct rcar_du_encoder *encoder =
731 rcdu->encoders[RCAR_DU_OUTPUT_LVDS0 + rcrtc->index];
732 const struct drm_display_mode *mode =
733 &crtc->state->adjusted_mode;
734 struct drm_bridge *bridge;
735
736 bridge = drm_bridge_chain_get_first_bridge(&encoder->base);
737 rcar_lvds_clk_enable(bridge, mode->clock * 1000);
738 }
739
740 rcar_du_crtc_start(rcrtc);
741
742 /*
743 * TODO: The chip manual indicates that CMM tables should be written
744 * after the DU channel has been activated. Investigate the impact
745 * of this restriction on the first displayed frame.
746 */
747 rcar_du_cmm_setup(crtc);
748}
749
750static void rcar_du_crtc_atomic_disable(struct drm_crtc *crtc,
751 struct drm_crtc_state *old_state)
752{
753 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
754 struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(old_state);
755 struct rcar_du_device *rcdu = rcrtc->dev;
756
757 rcar_du_crtc_stop(rcrtc);
758 rcar_du_crtc_put(rcrtc);
759
760 if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index) &&
761 rstate->outputs == BIT(RCAR_DU_OUTPUT_DPAD0)) {
762 struct rcar_du_encoder *encoder =
763 rcdu->encoders[RCAR_DU_OUTPUT_LVDS0 + rcrtc->index];
764 struct drm_bridge *bridge;
765
766 /*
767 * Disable the LVDS clock output, see
768 * rcar_du_crtc_atomic_enable().
769 */
770 bridge = drm_bridge_chain_get_first_bridge(&encoder->base);
771 rcar_lvds_clk_disable(bridge);
772 }
773
774 spin_lock_irq(&crtc->dev->event_lock);
775 if (crtc->state->event) {
776 drm_crtc_send_vblank_event(crtc, crtc->state->event);
777 crtc->state->event = NULL;
778 }
779 spin_unlock_irq(&crtc->dev->event_lock);
780}
781
782static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc,
783 struct drm_crtc_state *old_crtc_state)
784{
785 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
786
787 WARN_ON(!crtc->state->enable);
788
789 /*
790 * If a mode set is in progress we can be called with the CRTC disabled.
791 * We thus need to first get and setup the CRTC in order to configure
792 * planes. We must *not* put the CRTC in .atomic_flush(), as it must be
793 * kept awake until the .atomic_enable() call that will follow. The get
794 * operation in .atomic_enable() will in that case be a no-op, and the
795 * CRTC will be put later in .atomic_disable().
796 *
797 * If a mode set is not in progress the CRTC is enabled, and the
798 * following get call will be a no-op. There is thus no need to balance
799 * it in .atomic_flush() either.
800 */
801 rcar_du_crtc_get(rcrtc);
802
803 /* If the active state changed, we let .atomic_enable handle CMM. */
804 if (crtc->state->color_mgmt_changed && !crtc->state->active_changed)
805 rcar_du_cmm_setup(crtc);
806
807 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
808 rcar_du_vsp_atomic_begin(rcrtc);
809}
810
811static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc,
812 struct drm_crtc_state *old_crtc_state)
813{
814 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
815 struct drm_device *dev = rcrtc->crtc.dev;
816 unsigned long flags;
817
818 rcar_du_crtc_update_planes(rcrtc);
819
820 if (crtc->state->event) {
821 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
822
823 spin_lock_irqsave(&dev->event_lock, flags);
824 rcrtc->event = crtc->state->event;
825 crtc->state->event = NULL;
826 spin_unlock_irqrestore(&dev->event_lock, flags);
827 }
828
829 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
830 rcar_du_vsp_atomic_flush(rcrtc);
831}
832
833static enum drm_mode_status
834rcar_du_crtc_mode_valid(struct drm_crtc *crtc,
835 const struct drm_display_mode *mode)
836{
837 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
838 struct rcar_du_device *rcdu = rcrtc->dev;
839 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
840 unsigned int vbp;
841
842 if (interlaced && !rcar_du_has(rcdu, RCAR_DU_FEATURE_INTERLACED))
843 return MODE_NO_INTERLACE;
844
845 /*
846 * The hardware requires a minimum combined horizontal sync and back
847 * porch of 20 pixels and a minimum vertical back porch of 3 lines.
848 */
849 if (mode->htotal - mode->hsync_start < 20)
850 return MODE_HBLANK_NARROW;
851
852 vbp = (mode->vtotal - mode->vsync_end) / (interlaced ? 2 : 1);
853 if (vbp < 3)
854 return MODE_VBLANK_NARROW;
855
856 return MODE_OK;
857}
858
859static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
860 .atomic_check = rcar_du_crtc_atomic_check,
861 .atomic_begin = rcar_du_crtc_atomic_begin,
862 .atomic_flush = rcar_du_crtc_atomic_flush,
863 .atomic_enable = rcar_du_crtc_atomic_enable,
864 .atomic_disable = rcar_du_crtc_atomic_disable,
865 .mode_valid = rcar_du_crtc_mode_valid,
866};
867
868static void rcar_du_crtc_crc_init(struct rcar_du_crtc *rcrtc)
869{
870 struct rcar_du_device *rcdu = rcrtc->dev;
871 const char **sources;
872 unsigned int count;
873 int i = -1;
874
875 /* CRC available only on Gen3 HW. */
876 if (rcdu->info->gen < 3)
877 return;
878
879 /* Reserve 1 for "auto" source. */
880 count = rcrtc->vsp->num_planes + 1;
881
882 sources = kmalloc_array(count, sizeof(*sources), GFP_KERNEL);
883 if (!sources)
884 return;
885
886 sources[0] = kstrdup("auto", GFP_KERNEL);
887 if (!sources[0])
888 goto error;
889
890 for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
891 struct drm_plane *plane = &rcrtc->vsp->planes[i].plane;
892 char name[16];
893
894 sprintf(name, "plane%u", plane->base.id);
895 sources[i + 1] = kstrdup(name, GFP_KERNEL);
896 if (!sources[i + 1])
897 goto error;
898 }
899
900 rcrtc->sources = sources;
901 rcrtc->sources_count = count;
902 return;
903
904error:
905 while (i >= 0) {
906 kfree(sources[i]);
907 i--;
908 }
909 kfree(sources);
910}
911
912static void rcar_du_crtc_crc_cleanup(struct rcar_du_crtc *rcrtc)
913{
914 unsigned int i;
915
916 if (!rcrtc->sources)
917 return;
918
919 for (i = 0; i < rcrtc->sources_count; i++)
920 kfree(rcrtc->sources[i]);
921 kfree(rcrtc->sources);
922
923 rcrtc->sources = NULL;
924 rcrtc->sources_count = 0;
925}
926
927static struct drm_crtc_state *
928rcar_du_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
929{
930 struct rcar_du_crtc_state *state;
931 struct rcar_du_crtc_state *copy;
932
933 if (WARN_ON(!crtc->state))
934 return NULL;
935
936 state = to_rcar_crtc_state(crtc->state);
937 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
938 if (copy == NULL)
939 return NULL;
940
941 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->state);
942
943 return ©->state;
944}
945
946static void rcar_du_crtc_atomic_destroy_state(struct drm_crtc *crtc,
947 struct drm_crtc_state *state)
948{
949 __drm_atomic_helper_crtc_destroy_state(state);
950 kfree(to_rcar_crtc_state(state));
951}
952
953static void rcar_du_crtc_cleanup(struct drm_crtc *crtc)
954{
955 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
956
957 rcar_du_crtc_crc_cleanup(rcrtc);
958
959 return drm_crtc_cleanup(crtc);
960}
961
962static void rcar_du_crtc_reset(struct drm_crtc *crtc)
963{
964 struct rcar_du_crtc_state *state;
965
966 if (crtc->state) {
967 rcar_du_crtc_atomic_destroy_state(crtc, crtc->state);
968 crtc->state = NULL;
969 }
970
971 state = kzalloc(sizeof(*state), GFP_KERNEL);
972 if (state == NULL)
973 return;
974
975 state->crc.source = VSP1_DU_CRC_NONE;
976 state->crc.index = 0;
977
978 __drm_atomic_helper_crtc_reset(crtc, &state->state);
979}
980
981static int rcar_du_crtc_enable_vblank(struct drm_crtc *crtc)
982{
983 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
984
985 rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
986 rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
987 rcrtc->vblank_enable = true;
988
989 return 0;
990}
991
992static void rcar_du_crtc_disable_vblank(struct drm_crtc *crtc)
993{
994 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
995
996 rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
997 rcrtc->vblank_enable = false;
998}
999
1000static int rcar_du_crtc_parse_crc_source(struct rcar_du_crtc *rcrtc,
1001 const char *source_name,
1002 enum vsp1_du_crc_source *source)
1003{
1004 unsigned int index;
1005 int ret;
1006
1007 /*
1008 * Parse the source name. Supported values are "plane%u" to compute the
1009 * CRC on an input plane (%u is the plane ID), and "auto" to compute the
1010 * CRC on the composer (VSP) output.
1011 */
1012
1013 if (!source_name) {
1014 *source = VSP1_DU_CRC_NONE;
1015 return 0;
1016 } else if (!strcmp(source_name, "auto")) {
1017 *source = VSP1_DU_CRC_OUTPUT;
1018 return 0;
1019 } else if (strstarts(source_name, "plane")) {
1020 unsigned int i;
1021
1022 *source = VSP1_DU_CRC_PLANE;
1023
1024 ret = kstrtouint(source_name + strlen("plane"), 10, &index);
1025 if (ret < 0)
1026 return ret;
1027
1028 for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
1029 if (index == rcrtc->vsp->planes[i].plane.base.id)
1030 return i;
1031 }
1032 }
1033
1034 return -EINVAL;
1035}
1036
1037static int rcar_du_crtc_verify_crc_source(struct drm_crtc *crtc,
1038 const char *source_name,
1039 size_t *values_cnt)
1040{
1041 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
1042 enum vsp1_du_crc_source source;
1043
1044 if (rcar_du_crtc_parse_crc_source(rcrtc, source_name, &source) < 0) {
1045 DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
1046 return -EINVAL;
1047 }
1048
1049 *values_cnt = 1;
1050 return 0;
1051}
1052
1053static const char *const *
1054rcar_du_crtc_get_crc_sources(struct drm_crtc *crtc, size_t *count)
1055{
1056 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
1057
1058 *count = rcrtc->sources_count;
1059 return rcrtc->sources;
1060}
1061
1062static int rcar_du_crtc_set_crc_source(struct drm_crtc *crtc,
1063 const char *source_name)
1064{
1065 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
1066 struct drm_modeset_acquire_ctx ctx;
1067 struct drm_crtc_state *crtc_state;
1068 struct drm_atomic_state *state;
1069 enum vsp1_du_crc_source source;
1070 unsigned int index;
1071 int ret;
1072
1073 ret = rcar_du_crtc_parse_crc_source(rcrtc, source_name, &source);
1074 if (ret < 0)
1075 return ret;
1076
1077 index = ret;
1078
1079 /* Perform an atomic commit to set the CRC source. */
1080 drm_modeset_acquire_init(&ctx, 0);
1081
1082 state = drm_atomic_state_alloc(crtc->dev);
1083 if (!state) {
1084 ret = -ENOMEM;
1085 goto unlock;
1086 }
1087
1088 state->acquire_ctx = &ctx;
1089
1090retry:
1091 crtc_state = drm_atomic_get_crtc_state(state, crtc);
1092 if (!IS_ERR(crtc_state)) {
1093 struct rcar_du_crtc_state *rcrtc_state;
1094
1095 rcrtc_state = to_rcar_crtc_state(crtc_state);
1096 rcrtc_state->crc.source = source;
1097 rcrtc_state->crc.index = index;
1098
1099 ret = drm_atomic_commit(state);
1100 } else {
1101 ret = PTR_ERR(crtc_state);
1102 }
1103
1104 if (ret == -EDEADLK) {
1105 drm_atomic_state_clear(state);
1106 drm_modeset_backoff(&ctx);
1107 goto retry;
1108 }
1109
1110 drm_atomic_state_put(state);
1111
1112unlock:
1113 drm_modeset_drop_locks(&ctx);
1114 drm_modeset_acquire_fini(&ctx);
1115
1116 return ret;
1117}
1118
1119static const struct drm_crtc_funcs crtc_funcs_gen2 = {
1120 .reset = rcar_du_crtc_reset,
1121 .destroy = drm_crtc_cleanup,
1122 .set_config = drm_atomic_helper_set_config,
1123 .page_flip = drm_atomic_helper_page_flip,
1124 .atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
1125 .atomic_destroy_state = rcar_du_crtc_atomic_destroy_state,
1126 .enable_vblank = rcar_du_crtc_enable_vblank,
1127 .disable_vblank = rcar_du_crtc_disable_vblank,
1128};
1129
1130static const struct drm_crtc_funcs crtc_funcs_gen3 = {
1131 .reset = rcar_du_crtc_reset,
1132 .destroy = rcar_du_crtc_cleanup,
1133 .set_config = drm_atomic_helper_set_config,
1134 .page_flip = drm_atomic_helper_page_flip,
1135 .atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
1136 .atomic_destroy_state = rcar_du_crtc_atomic_destroy_state,
1137 .enable_vblank = rcar_du_crtc_enable_vblank,
1138 .disable_vblank = rcar_du_crtc_disable_vblank,
1139 .set_crc_source = rcar_du_crtc_set_crc_source,
1140 .verify_crc_source = rcar_du_crtc_verify_crc_source,
1141 .get_crc_sources = rcar_du_crtc_get_crc_sources,
1142 .gamma_set = drm_atomic_helper_legacy_gamma_set,
1143};
1144
1145/* -----------------------------------------------------------------------------
1146 * Interrupt Handling
1147 */
1148
1149static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
1150{
1151 struct rcar_du_crtc *rcrtc = arg;
1152 struct rcar_du_device *rcdu = rcrtc->dev;
1153 irqreturn_t ret = IRQ_NONE;
1154 u32 status;
1155
1156 spin_lock(&rcrtc->vblank_lock);
1157
1158 status = rcar_du_crtc_read(rcrtc, DSSR);
1159 rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
1160
1161 if (status & DSSR_VBK) {
1162 /*
1163 * Wake up the vblank wait if the counter reaches 0. This must
1164 * be protected by the vblank_lock to avoid races in
1165 * rcar_du_crtc_disable_planes().
1166 */
1167 if (rcrtc->vblank_count) {
1168 if (--rcrtc->vblank_count == 0)
1169 wake_up(&rcrtc->vblank_wait);
1170 }
1171 }
1172
1173 spin_unlock(&rcrtc->vblank_lock);
1174
1175 if (status & DSSR_VBK) {
1176 if (rcdu->info->gen < 3) {
1177 drm_crtc_handle_vblank(&rcrtc->crtc);
1178 rcar_du_crtc_finish_page_flip(rcrtc);
1179 }
1180
1181 ret = IRQ_HANDLED;
1182 }
1183
1184 return ret;
1185}
1186
1187/* -----------------------------------------------------------------------------
1188 * Initialization
1189 */
1190
1191int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex,
1192 unsigned int hwindex)
1193{
1194 static const unsigned int mmio_offsets[] = {
1195 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET, DU3_REG_OFFSET
1196 };
1197
1198 struct rcar_du_device *rcdu = rgrp->dev;
1199 struct platform_device *pdev = to_platform_device(rcdu->dev);
1200 struct rcar_du_crtc *rcrtc = &rcdu->crtcs[swindex];
1201 struct drm_crtc *crtc = &rcrtc->crtc;
1202 struct drm_plane *primary;
1203 unsigned int irqflags;
1204 struct clk *clk;
1205 char clk_name[9];
1206 char *name;
1207 int irq;
1208 int ret;
1209
1210 /* Get the CRTC clock and the optional external clock. */
1211 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
1212 sprintf(clk_name, "du.%u", hwindex);
1213 name = clk_name;
1214 } else {
1215 name = NULL;
1216 }
1217
1218 rcrtc->clock = devm_clk_get(rcdu->dev, name);
1219 if (IS_ERR(rcrtc->clock)) {
1220 dev_err(rcdu->dev, "no clock for DU channel %u\n", hwindex);
1221 return PTR_ERR(rcrtc->clock);
1222 }
1223
1224 sprintf(clk_name, "dclkin.%u", hwindex);
1225 clk = devm_clk_get(rcdu->dev, clk_name);
1226 if (!IS_ERR(clk)) {
1227 rcrtc->extclock = clk;
1228 } else if (PTR_ERR(clk) == -EPROBE_DEFER) {
1229 return -EPROBE_DEFER;
1230 } else if (rcdu->info->dpll_mask & BIT(hwindex)) {
1231 /*
1232 * DU channels that have a display PLL can't use the internal
1233 * system clock and thus require an external clock.
1234 */
1235 ret = PTR_ERR(clk);
1236 dev_err(rcdu->dev, "can't get dclkin.%u: %d\n", hwindex, ret);
1237 return ret;
1238 }
1239
1240 init_waitqueue_head(&rcrtc->flip_wait);
1241 init_waitqueue_head(&rcrtc->vblank_wait);
1242 spin_lock_init(&rcrtc->vblank_lock);
1243
1244 rcrtc->dev = rcdu;
1245 rcrtc->group = rgrp;
1246 rcrtc->mmio_offset = mmio_offsets[hwindex];
1247 rcrtc->index = hwindex;
1248 rcrtc->dsysr = (rcrtc->index % 2 ? 0 : DSYSR_DRES) | DSYSR_TVM_TVSYNC;
1249
1250 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
1251 primary = &rcrtc->vsp->planes[rcrtc->vsp_pipe].plane;
1252 else
1253 primary = &rgrp->planes[swindex % 2].plane;
1254
1255 ret = drm_crtc_init_with_planes(rcdu->ddev, crtc, primary, NULL,
1256 rcdu->info->gen <= 2 ?
1257 &crtc_funcs_gen2 : &crtc_funcs_gen3,
1258 NULL);
1259 if (ret < 0)
1260 return ret;
1261
1262 /* CMM might be disabled for this CRTC. */
1263 if (rcdu->cmms[swindex]) {
1264 rcrtc->cmm = rcdu->cmms[swindex];
1265 rgrp->cmms_mask |= BIT(hwindex % 2);
1266
1267 drm_mode_crtc_set_gamma_size(crtc, CM2_LUT_SIZE);
1268 drm_crtc_enable_color_mgmt(crtc, 0, false, CM2_LUT_SIZE);
1269 }
1270
1271 drm_crtc_helper_add(crtc, &crtc_helper_funcs);
1272
1273 /* Register the interrupt handler. */
1274 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
1275 /* The IRQ's are associated with the CRTC (sw)index. */
1276 irq = platform_get_irq(pdev, swindex);
1277 irqflags = 0;
1278 } else {
1279 irq = platform_get_irq(pdev, 0);
1280 irqflags = IRQF_SHARED;
1281 }
1282
1283 if (irq < 0) {
1284 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", swindex);
1285 return irq;
1286 }
1287
1288 ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
1289 dev_name(rcdu->dev), rcrtc);
1290 if (ret < 0) {
1291 dev_err(rcdu->dev,
1292 "failed to register IRQ for CRTC %u\n", swindex);
1293 return ret;
1294 }
1295
1296 rcar_du_crtc_crc_init(rcrtc);
1297
1298 return 0;
1299}