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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013-2014 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 *
6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
7 */
8
9#include "adreno_gpu.h"
10
11#define ANY_ID 0xff
12
13bool hang_debug = false;
14MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
15module_param_named(hang_debug, hang_debug, bool, 0600);
16
17bool snapshot_debugbus = false;
18MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU devcoredump (if not fused off)");
19module_param_named(snapshot_debugbus, snapshot_debugbus, bool, 0600);
20
21static const struct adreno_info gpulist[] = {
22 {
23 .rev = ADRENO_REV(2, 0, 0, 0),
24 .revn = 200,
25 .name = "A200",
26 .fw = {
27 [ADRENO_FW_PM4] = "yamato_pm4.fw",
28 [ADRENO_FW_PFP] = "yamato_pfp.fw",
29 },
30 .gmem = SZ_256K,
31 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
32 .init = a2xx_gpu_init,
33 }, { /* a200 on i.mx51 has only 128kib gmem */
34 .rev = ADRENO_REV(2, 0, 0, 1),
35 .revn = 201,
36 .name = "A200",
37 .fw = {
38 [ADRENO_FW_PM4] = "yamato_pm4.fw",
39 [ADRENO_FW_PFP] = "yamato_pfp.fw",
40 },
41 .gmem = SZ_128K,
42 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
43 .init = a2xx_gpu_init,
44 }, {
45 .rev = ADRENO_REV(2, 2, 0, ANY_ID),
46 .revn = 220,
47 .name = "A220",
48 .fw = {
49 [ADRENO_FW_PM4] = "leia_pm4_470.fw",
50 [ADRENO_FW_PFP] = "leia_pfp_470.fw",
51 },
52 .gmem = SZ_512K,
53 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
54 .init = a2xx_gpu_init,
55 }, {
56 .rev = ADRENO_REV(3, 0, 5, ANY_ID),
57 .revn = 305,
58 .name = "A305",
59 .fw = {
60 [ADRENO_FW_PM4] = "a300_pm4.fw",
61 [ADRENO_FW_PFP] = "a300_pfp.fw",
62 },
63 .gmem = SZ_256K,
64 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
65 .init = a3xx_gpu_init,
66 }, {
67 .rev = ADRENO_REV(3, 0, 6, 0),
68 .revn = 307, /* because a305c is revn==306 */
69 .name = "A306",
70 .fw = {
71 [ADRENO_FW_PM4] = "a300_pm4.fw",
72 [ADRENO_FW_PFP] = "a300_pfp.fw",
73 },
74 .gmem = SZ_128K,
75 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
76 .init = a3xx_gpu_init,
77 }, {
78 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
79 .revn = 320,
80 .name = "A320",
81 .fw = {
82 [ADRENO_FW_PM4] = "a300_pm4.fw",
83 [ADRENO_FW_PFP] = "a300_pfp.fw",
84 },
85 .gmem = SZ_512K,
86 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
87 .init = a3xx_gpu_init,
88 }, {
89 .rev = ADRENO_REV(3, 3, 0, ANY_ID),
90 .revn = 330,
91 .name = "A330",
92 .fw = {
93 [ADRENO_FW_PM4] = "a330_pm4.fw",
94 [ADRENO_FW_PFP] = "a330_pfp.fw",
95 },
96 .gmem = SZ_1M,
97 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
98 .init = a3xx_gpu_init,
99 }, {
100 .rev = ADRENO_REV(4, 0, 5, ANY_ID),
101 .revn = 405,
102 .name = "A405",
103 .fw = {
104 [ADRENO_FW_PM4] = "a420_pm4.fw",
105 [ADRENO_FW_PFP] = "a420_pfp.fw",
106 },
107 .gmem = SZ_256K,
108 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
109 .init = a4xx_gpu_init,
110 }, {
111 .rev = ADRENO_REV(4, 2, 0, ANY_ID),
112 .revn = 420,
113 .name = "A420",
114 .fw = {
115 [ADRENO_FW_PM4] = "a420_pm4.fw",
116 [ADRENO_FW_PFP] = "a420_pfp.fw",
117 },
118 .gmem = (SZ_1M + SZ_512K),
119 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
120 .init = a4xx_gpu_init,
121 }, {
122 .rev = ADRENO_REV(4, 3, 0, ANY_ID),
123 .revn = 430,
124 .name = "A430",
125 .fw = {
126 [ADRENO_FW_PM4] = "a420_pm4.fw",
127 [ADRENO_FW_PFP] = "a420_pfp.fw",
128 },
129 .gmem = (SZ_1M + SZ_512K),
130 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
131 .init = a4xx_gpu_init,
132 }, {
133 .rev = ADRENO_REV(5, 1, 0, ANY_ID),
134 .revn = 510,
135 .name = "A510",
136 .fw = {
137 [ADRENO_FW_PM4] = "a530_pm4.fw",
138 [ADRENO_FW_PFP] = "a530_pfp.fw",
139 },
140 .gmem = SZ_256K,
141 /*
142 * Increase inactive period to 250 to avoid bouncing
143 * the GDSC which appears to make it grumpy
144 */
145 .inactive_period = 250,
146 .init = a5xx_gpu_init,
147 }, {
148 .rev = ADRENO_REV(5, 3, 0, 2),
149 .revn = 530,
150 .name = "A530",
151 .fw = {
152 [ADRENO_FW_PM4] = "a530_pm4.fw",
153 [ADRENO_FW_PFP] = "a530_pfp.fw",
154 [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2",
155 },
156 .gmem = SZ_1M,
157 /*
158 * Increase inactive period to 250 to avoid bouncing
159 * the GDSC which appears to make it grumpy
160 */
161 .inactive_period = 250,
162 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
163 ADRENO_QUIRK_FAULT_DETECT_MASK,
164 .init = a5xx_gpu_init,
165 .zapfw = "a530_zap.mdt",
166 }, {
167 .rev = ADRENO_REV(5, 4, 0, 2),
168 .revn = 540,
169 .name = "A540",
170 .fw = {
171 [ADRENO_FW_PM4] = "a530_pm4.fw",
172 [ADRENO_FW_PFP] = "a530_pfp.fw",
173 [ADRENO_FW_GPMU] = "a540_gpmu.fw2",
174 },
175 .gmem = SZ_1M,
176 /*
177 * Increase inactive period to 250 to avoid bouncing
178 * the GDSC which appears to make it grumpy
179 */
180 .inactive_period = 250,
181 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
182 .init = a5xx_gpu_init,
183 .zapfw = "a540_zap.mdt",
184 }, {
185 .rev = ADRENO_REV(6, 1, 8, ANY_ID),
186 .revn = 618,
187 .name = "A618",
188 .fw = {
189 [ADRENO_FW_SQE] = "a630_sqe.fw",
190 [ADRENO_FW_GMU] = "a630_gmu.bin",
191 },
192 .gmem = SZ_512K,
193 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
194 .init = a6xx_gpu_init,
195 }, {
196 .rev = ADRENO_REV(6, 3, 0, ANY_ID),
197 .revn = 630,
198 .name = "A630",
199 .fw = {
200 [ADRENO_FW_SQE] = "a630_sqe.fw",
201 [ADRENO_FW_GMU] = "a630_gmu.bin",
202 },
203 .gmem = SZ_1M,
204 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
205 .init = a6xx_gpu_init,
206 .zapfw = "a630_zap.mdt",
207 .hwcg = a630_hwcg,
208 }, {
209 .rev = ADRENO_REV(6, 4, 0, ANY_ID),
210 .revn = 640,
211 .name = "A640",
212 .fw = {
213 [ADRENO_FW_SQE] = "a630_sqe.fw",
214 [ADRENO_FW_GMU] = "a640_gmu.bin",
215 },
216 .gmem = SZ_1M,
217 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
218 .init = a6xx_gpu_init,
219 .zapfw = "a640_zap.mdt",
220 .hwcg = a640_hwcg,
221 }, {
222 .rev = ADRENO_REV(6, 5, 0, ANY_ID),
223 .revn = 650,
224 .name = "A650",
225 .fw = {
226 [ADRENO_FW_SQE] = "a650_sqe.fw",
227 [ADRENO_FW_GMU] = "a650_gmu.bin",
228 },
229 .gmem = SZ_1M + SZ_128K,
230 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
231 .init = a6xx_gpu_init,
232 .zapfw = "a650_zap.mdt",
233 .hwcg = a650_hwcg,
234 },
235};
236
237MODULE_FIRMWARE("qcom/a300_pm4.fw");
238MODULE_FIRMWARE("qcom/a300_pfp.fw");
239MODULE_FIRMWARE("qcom/a330_pm4.fw");
240MODULE_FIRMWARE("qcom/a330_pfp.fw");
241MODULE_FIRMWARE("qcom/a420_pm4.fw");
242MODULE_FIRMWARE("qcom/a420_pfp.fw");
243MODULE_FIRMWARE("qcom/a530_pm4.fw");
244MODULE_FIRMWARE("qcom/a530_pfp.fw");
245MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2");
246MODULE_FIRMWARE("qcom/a530_zap.mdt");
247MODULE_FIRMWARE("qcom/a530_zap.b00");
248MODULE_FIRMWARE("qcom/a530_zap.b01");
249MODULE_FIRMWARE("qcom/a530_zap.b02");
250MODULE_FIRMWARE("qcom/a630_sqe.fw");
251MODULE_FIRMWARE("qcom/a630_gmu.bin");
252MODULE_FIRMWARE("qcom/a630_zap.mbn");
253
254static inline bool _rev_match(uint8_t entry, uint8_t id)
255{
256 return (entry == ANY_ID) || (entry == id);
257}
258
259const struct adreno_info *adreno_info(struct adreno_rev rev)
260{
261 int i;
262
263 /* identify gpu: */
264 for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
265 const struct adreno_info *info = &gpulist[i];
266 if (_rev_match(info->rev.core, rev.core) &&
267 _rev_match(info->rev.major, rev.major) &&
268 _rev_match(info->rev.minor, rev.minor) &&
269 _rev_match(info->rev.patchid, rev.patchid))
270 return info;
271 }
272
273 return NULL;
274}
275
276struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
277{
278 struct msm_drm_private *priv = dev->dev_private;
279 struct platform_device *pdev = priv->gpu_pdev;
280 struct msm_gpu *gpu = NULL;
281 struct adreno_gpu *adreno_gpu;
282 int ret;
283
284 if (pdev)
285 gpu = platform_get_drvdata(pdev);
286
287 if (!gpu) {
288 dev_err_once(dev->dev, "no GPU device was found\n");
289 return NULL;
290 }
291
292 adreno_gpu = to_adreno_gpu(gpu);
293
294 /*
295 * The number one reason for HW init to fail is if the firmware isn't
296 * loaded yet. Try that first and don't bother continuing on
297 * otherwise
298 */
299
300 ret = adreno_load_fw(adreno_gpu);
301 if (ret)
302 return NULL;
303
304 /* Make sure pm runtime is active and reset any previous errors */
305 pm_runtime_set_active(&pdev->dev);
306
307 ret = pm_runtime_get_sync(&pdev->dev);
308 if (ret < 0) {
309 pm_runtime_put_sync(&pdev->dev);
310 DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret);
311 return NULL;
312 }
313
314 mutex_lock(&dev->struct_mutex);
315 ret = msm_gpu_hw_init(gpu);
316 mutex_unlock(&dev->struct_mutex);
317 pm_runtime_put_autosuspend(&pdev->dev);
318 if (ret) {
319 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
320 return NULL;
321 }
322
323#ifdef CONFIG_DEBUG_FS
324 if (gpu->funcs->debugfs_init) {
325 gpu->funcs->debugfs_init(gpu, dev->primary);
326 gpu->funcs->debugfs_init(gpu, dev->render);
327 }
328#endif
329
330 return gpu;
331}
332
333static void set_gpu_pdev(struct drm_device *dev,
334 struct platform_device *pdev)
335{
336 struct msm_drm_private *priv = dev->dev_private;
337 priv->gpu_pdev = pdev;
338}
339
340static int find_chipid(struct device *dev, struct adreno_rev *rev)
341{
342 struct device_node *node = dev->of_node;
343 const char *compat;
344 int ret;
345 u32 chipid;
346
347 /* first search the compat strings for qcom,adreno-XYZ.W: */
348 ret = of_property_read_string_index(node, "compatible", 0, &compat);
349 if (ret == 0) {
350 unsigned int r, patch;
351
352 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
353 sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
354 rev->core = r / 100;
355 r %= 100;
356 rev->major = r / 10;
357 r %= 10;
358 rev->minor = r;
359 rev->patchid = patch;
360
361 return 0;
362 }
363 }
364
365 /* and if that fails, fall back to legacy "qcom,chipid" property: */
366 ret = of_property_read_u32(node, "qcom,chipid", &chipid);
367 if (ret) {
368 DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
369 return ret;
370 }
371
372 rev->core = (chipid >> 24) & 0xff;
373 rev->major = (chipid >> 16) & 0xff;
374 rev->minor = (chipid >> 8) & 0xff;
375 rev->patchid = (chipid & 0xff);
376
377 dev_warn(dev, "Using legacy qcom,chipid binding!\n");
378 dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
379 rev->core, rev->major, rev->minor, rev->patchid);
380
381 return 0;
382}
383
384static int adreno_bind(struct device *dev, struct device *master, void *data)
385{
386 static struct adreno_platform_config config = {};
387 const struct adreno_info *info;
388 struct drm_device *drm = dev_get_drvdata(master);
389 struct msm_drm_private *priv = drm->dev_private;
390 struct msm_gpu *gpu;
391 int ret;
392
393 ret = find_chipid(dev, &config.rev);
394 if (ret)
395 return ret;
396
397 dev->platform_data = &config;
398 set_gpu_pdev(drm, to_platform_device(dev));
399
400 info = adreno_info(config.rev);
401
402 if (!info) {
403 dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
404 config.rev.core, config.rev.major,
405 config.rev.minor, config.rev.patchid);
406 return -ENXIO;
407 }
408
409 DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
410 config.rev.minor, config.rev.patchid);
411
412 priv->is_a2xx = config.rev.core == 2;
413
414 gpu = info->init(drm);
415 if (IS_ERR(gpu)) {
416 dev_warn(drm->dev, "failed to load adreno gpu\n");
417 return PTR_ERR(gpu);
418 }
419
420 dev_set_drvdata(dev, gpu);
421
422 return 0;
423}
424
425static void adreno_unbind(struct device *dev, struct device *master,
426 void *data)
427{
428 struct msm_gpu *gpu = dev_get_drvdata(dev);
429
430 pm_runtime_force_suspend(dev);
431 gpu->funcs->destroy(gpu);
432
433 set_gpu_pdev(dev_get_drvdata(master), NULL);
434}
435
436static const struct component_ops a3xx_ops = {
437 .bind = adreno_bind,
438 .unbind = adreno_unbind,
439};
440
441static void adreno_device_register_headless(void)
442{
443 /* on imx5, we don't have a top-level mdp/dpu node
444 * this creates a dummy node for the driver for that case
445 */
446 struct platform_device_info dummy_info = {
447 .parent = NULL,
448 .name = "msm",
449 .id = -1,
450 .res = NULL,
451 .num_res = 0,
452 .data = NULL,
453 .size_data = 0,
454 .dma_mask = ~0,
455 };
456 platform_device_register_full(&dummy_info);
457}
458
459static int adreno_probe(struct platform_device *pdev)
460{
461
462 int ret;
463
464 ret = component_add(&pdev->dev, &a3xx_ops);
465 if (ret)
466 return ret;
467
468 if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon"))
469 adreno_device_register_headless();
470
471 return 0;
472}
473
474static int adreno_remove(struct platform_device *pdev)
475{
476 component_del(&pdev->dev, &a3xx_ops);
477 return 0;
478}
479
480static const struct of_device_id dt_match[] = {
481 { .compatible = "qcom,adreno" },
482 { .compatible = "qcom,adreno-3xx" },
483 /* for compatibility with imx5 gpu: */
484 { .compatible = "amd,imageon" },
485 /* for backwards compat w/ downstream kgsl DT files: */
486 { .compatible = "qcom,kgsl-3d0" },
487 {}
488};
489
490#ifdef CONFIG_PM
491static int adreno_resume(struct device *dev)
492{
493 struct platform_device *pdev = to_platform_device(dev);
494 struct msm_gpu *gpu = platform_get_drvdata(pdev);
495
496 return gpu->funcs->pm_resume(gpu);
497}
498
499static int adreno_suspend(struct device *dev)
500{
501 struct platform_device *pdev = to_platform_device(dev);
502 struct msm_gpu *gpu = platform_get_drvdata(pdev);
503
504 return gpu->funcs->pm_suspend(gpu);
505}
506#endif
507
508static const struct dev_pm_ops adreno_pm_ops = {
509 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
510 SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL)
511};
512
513static struct platform_driver adreno_driver = {
514 .probe = adreno_probe,
515 .remove = adreno_remove,
516 .driver = {
517 .name = "adreno",
518 .of_match_table = dt_match,
519 .pm = &adreno_pm_ops,
520 },
521};
522
523void __init adreno_register(void)
524{
525 platform_driver_register(&adreno_driver);
526}
527
528void __exit adreno_unregister(void)
529{
530 platform_driver_unregister(&adreno_driver);
531}