1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Copyright (C) 2016 BayLibre, SAS
  4 * Author: Neil Armstrong <narmstrong@baylibre.com>
  5 * Copyright (C) 2014 Endless Mobile
  6 *
  7 * Written by:
  8 *     Jasper St. Pierre <jstpierre@mecheye.net>
  9 */
 10
 11#include <linux/component.h>
 12#include <linux/module.h>
 13#include <linux/of_graph.h>
 14#include <linux/sys_soc.h>
 15#include <linux/platform_device.h>
 16#include <linux/soc/amlogic/meson-canvas.h>
 17
 18#include <drm/drm_atomic_helper.h>
 19#include <drm/drm_drv.h>
 20#include <drm/drm_fb_helper.h>
 21#include <drm/drm_gem_cma_helper.h>
 22#include <drm/drm_gem_framebuffer_helper.h>
 23#include <drm/drm_irq.h>
 24#include <drm/drm_modeset_helper_vtables.h>
 25#include <drm/drm_probe_helper.h>
 26#include <drm/drm_vblank.h>
 27
 28#include "meson_crtc.h"
 29#include "meson_drv.h"
 30#include "meson_overlay.h"
 31#include "meson_plane.h"
 32#include "meson_osd_afbcd.h"
 33#include "meson_registers.h"
 34#include "meson_venc_cvbs.h"
 35#include "meson_viu.h"
 36#include "meson_vpp.h"
 37#include "meson_rdma.h"
 38
 39#define DRIVER_NAME "meson"
 40#define DRIVER_DESC "Amlogic Meson DRM driver"
 41
 42/**
 43 * DOC: Video Processing Unit
 44 *
 45 * VPU Handles the Global Video Processing, it includes management of the
 46 * clocks gates, blocks reset lines and power domains.
 47 *
 48 * What is missing :
 49 *
 50 * - Full reset of entire video processing HW blocks
 51 * - Scaling and setup of the VPU clock
 52 * - Bus clock gates
 53 * - Powering up video processing HW blocks
 54 * - Powering Up HDMI controller and PHY
 55 */
 56
 57static const struct drm_mode_config_funcs meson_mode_config_funcs = {
 58	.atomic_check        = drm_atomic_helper_check,
 59	.atomic_commit       = drm_atomic_helper_commit,
 60	.fb_create           = drm_gem_fb_create,
 61};
 62
 63static const struct drm_mode_config_helper_funcs meson_mode_config_helpers = {
 64	.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
 65};
 66
 67static irqreturn_t meson_irq(int irq, void *arg)
 68{
 69	struct drm_device *dev = arg;
 70	struct meson_drm *priv = dev->dev_private;
 71
 72	(void)readl_relaxed(priv->io_base + _REG(VENC_INTFLAG));
 73
 74	meson_crtc_irq(priv);
 75
 76	return IRQ_HANDLED;
 77}
 78
 79static int meson_dumb_create(struct drm_file *file, struct drm_device *dev,
 80			     struct drm_mode_create_dumb *args)
 81{
 82	/*
 83	 * We need 64bytes aligned stride, and PAGE aligned size
 84	 */
 85	args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), SZ_64);
 86	args->size = PAGE_ALIGN(args->pitch * args->height);
 87
 88	return drm_gem_cma_dumb_create_internal(file, dev, args);
 89}
 90
 91DEFINE_DRM_GEM_CMA_FOPS(fops);
 92
 93static struct drm_driver meson_driver = {
 94	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
 95
 96	/* IRQ */
 97	.irq_handler		= meson_irq,
 98
 99	/* CMA Ops */
100	DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE(meson_dumb_create),
101
102	/* Misc */
103	.fops			= &fops,
104	.name			= DRIVER_NAME,
105	.desc			= DRIVER_DESC,
106	.date			= "20161109",
107	.major			= 1,
108	.minor			= 0,
109};
110
111static bool meson_vpu_has_available_connectors(struct device *dev)
112{
113	struct device_node *ep, *remote;
114
115	/* Parses each endpoint and check if remote exists */
116	for_each_endpoint_of_node(dev->of_node, ep) {
117		/* If the endpoint node exists, consider it enabled */
118		remote = of_graph_get_remote_port(ep);
119		if (remote)
120			return true;
121	}
122
123	return false;
124}
125
126static struct regmap_config meson_regmap_config = {
127	.reg_bits       = 32,
128	.val_bits       = 32,
129	.reg_stride     = 4,
130	.max_register   = 0x1000,
131};
132
133static void meson_vpu_init(struct meson_drm *priv)
134{
135	u32 value;
136
137	/*
138	 * Slave dc0 and dc5 connected to master port 1.
139	 * By default other slaves are connected to master port 0.
140	 */
141	value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) |
142		VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1);
143	writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1));
144
145	/* Slave dc0 connected to master port 1 */
146	value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1);
147	writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2));
148
149	/* Slave dc4 and dc7 connected to master port 1 */
150	value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) |
151		VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1);
152	writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1));
153
154	/* Slave dc1 connected to master port 1 */
155	value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1);
156	writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
157}
158
159static void meson_remove_framebuffers(void)
160{
161	struct apertures_struct *ap;
162
163	ap = alloc_apertures(1);
164	if (!ap)
165		return;
166
167	/* The framebuffer can be located anywhere in RAM */
168	ap->ranges[0].base = 0;
169	ap->ranges[0].size = ~0;
170
171	drm_fb_helper_remove_conflicting_framebuffers(ap, "meson-drm-fb",
172						      false);
173	kfree(ap);
174}
175
176struct meson_drm_soc_attr {
177	struct meson_drm_soc_limits limits;
178	const struct soc_device_attribute *attrs;
179};
180
181static const struct meson_drm_soc_attr meson_drm_soc_attrs[] = {
182	/* S805X/S805Y HDMI PLL won't lock for HDMI PHY freq > 1,65GHz */
183	{
184		.limits = {
185			.max_hdmi_phy_freq = 1650000,
186		},
187		.attrs = (const struct soc_device_attribute []) {
188			{ .soc_id = "GXL (S805*)", },
189			{ /* sentinel */ },
190		}
191	},
192};
193
194static int meson_drv_bind_master(struct device *dev, bool has_components)
195{
196	struct platform_device *pdev = to_platform_device(dev);
197	const struct meson_drm_match_data *match;
198	struct meson_drm *priv;
199	struct drm_device *drm;
200	struct resource *res;
201	void __iomem *regs;
202	int ret, i;
203
204	/* Checks if an output connector is available */
205	if (!meson_vpu_has_available_connectors(dev)) {
206		dev_err(dev, "No output connector available\n");
207		return -ENODEV;
208	}
209
210	match = of_device_get_match_data(dev);
211	if (!match)
212		return -ENODEV;
213
214	drm = drm_dev_alloc(&meson_driver, dev);
215	if (IS_ERR(drm))
216		return PTR_ERR(drm);
217
218	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
219	if (!priv) {
220		ret = -ENOMEM;
221		goto free_drm;
222	}
223	drm->dev_private = priv;
224	priv->drm = drm;
225	priv->dev = dev;
226	priv->compat = match->compat;
227	priv->afbcd.ops = match->afbcd_ops;
228
229	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vpu");
230	regs = devm_ioremap_resource(dev, res);
231	if (IS_ERR(regs)) {
232		ret = PTR_ERR(regs);
233		goto free_drm;
234	}
235
236	priv->io_base = regs;
237
238	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi");
239	if (!res) {
240		ret = -EINVAL;
241		goto free_drm;
242	}
243	/* Simply ioremap since it may be a shared register zone */
244	regs = devm_ioremap(dev, res->start, resource_size(res));
245	if (!regs) {
246		ret = -EADDRNOTAVAIL;
247		goto free_drm;
248	}
249
250	priv->hhi = devm_regmap_init_mmio(dev, regs,
251					  &meson_regmap_config);
252	if (IS_ERR(priv->hhi)) {
253		dev_err(&pdev->dev, "Couldn't create the HHI regmap\n");
254		ret = PTR_ERR(priv->hhi);
255		goto free_drm;
256	}
257
258	priv->canvas = meson_canvas_get(dev);
259	if (IS_ERR(priv->canvas)) {
260		ret = PTR_ERR(priv->canvas);
261		goto free_drm;
262	}
263
264	ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1);
265	if (ret)
266		goto free_drm;
267	ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0);
268	if (ret) {
269		meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
270		goto free_drm;
271	}
272	ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_1);
273	if (ret) {
274		meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
275		meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
276		goto free_drm;
277	}
278	ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_2);
279	if (ret) {
280		meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
281		meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
282		meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
283		goto free_drm;
284	}
285
286	priv->vsync_irq = platform_get_irq(pdev, 0);
287
288	ret = drm_vblank_init(drm, 1);
289	if (ret)
290		goto free_drm;
291
292	/* Assign limits per soc revision/package */
293	for (i = 0 ; i < ARRAY_SIZE(meson_drm_soc_attrs) ; ++i) {
294		if (soc_device_match(meson_drm_soc_attrs[i].attrs)) {
295			priv->limits = &meson_drm_soc_attrs[i].limits;
296			break;
297		}
298	}
299
300	/* Remove early framebuffers (ie. simplefb) */
301	meson_remove_framebuffers();
302
303	ret = drmm_mode_config_init(drm);
304	if (ret)
305		goto free_drm;
306	drm->mode_config.max_width = 3840;
307	drm->mode_config.max_height = 2160;
308	drm->mode_config.funcs = &meson_mode_config_funcs;
309	drm->mode_config.helper_private	= &meson_mode_config_helpers;
310
311	/* Hardware Initialization */
312
313	meson_vpu_init(priv);
314	meson_venc_init(priv);
315	meson_vpp_init(priv);
316	meson_viu_init(priv);
317	if (priv->afbcd.ops) {
318		ret = priv->afbcd.ops->init(priv);
319		if (ret)
320			return ret;
321	}
322
323	/* Encoder Initialization */
324
325	ret = meson_venc_cvbs_create(priv);
326	if (ret)
327		goto free_drm;
328
329	if (has_components) {
330		ret = component_bind_all(drm->dev, drm);
331		if (ret) {
332			dev_err(drm->dev, "Couldn't bind all components\n");
333			goto free_drm;
334		}
335	}
336
337	ret = meson_plane_create(priv);
338	if (ret)
339		goto free_drm;
340
341	ret = meson_overlay_create(priv);
342	if (ret)
343		goto free_drm;
344
345	ret = meson_crtc_create(priv);
346	if (ret)
347		goto free_drm;
348
349	ret = drm_irq_install(drm, priv->vsync_irq);
350	if (ret)
351		goto free_drm;
352
353	drm_mode_config_reset(drm);
354
355	drm_kms_helper_poll_init(drm);
356
357	platform_set_drvdata(pdev, priv);
358
359	ret = drm_dev_register(drm, 0);
360	if (ret)
361		goto uninstall_irq;
362
363	drm_fbdev_generic_setup(drm, 32);
364
365	return 0;
366
367uninstall_irq:
368	drm_irq_uninstall(drm);
369free_drm:
370	drm_dev_put(drm);
371
372	return ret;
373}
374
375static int meson_drv_bind(struct device *dev)
376{
377	return meson_drv_bind_master(dev, true);
378}
379
380static void meson_drv_unbind(struct device *dev)
381{
382	struct meson_drm *priv = dev_get_drvdata(dev);
383	struct drm_device *drm = priv->drm;
384
385	if (priv->canvas) {
386		meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
387		meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
388		meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
389		meson_canvas_free(priv->canvas, priv->canvas_id_vd1_2);
390	}
391
392	if (priv->afbcd.ops) {
393		priv->afbcd.ops->reset(priv);
394		meson_rdma_free(priv);
395	}
396
397	drm_dev_unregister(drm);
398	drm_irq_uninstall(drm);
399	drm_kms_helper_poll_fini(drm);
400	drm_dev_put(drm);
401}
402
403static const struct component_master_ops meson_drv_master_ops = {
404	.bind	= meson_drv_bind,
405	.unbind	= meson_drv_unbind,
406};
407
408static int __maybe_unused meson_drv_pm_suspend(struct device *dev)
409{
410	struct meson_drm *priv = dev_get_drvdata(dev);
411
412	if (!priv)
413		return 0;
414
415	return drm_mode_config_helper_suspend(priv->drm);
416}
417
418static int __maybe_unused meson_drv_pm_resume(struct device *dev)
419{
420	struct meson_drm *priv = dev_get_drvdata(dev);
421
422	if (!priv)
423		return 0;
424
425	meson_vpu_init(priv);
426	meson_venc_init(priv);
427	meson_vpp_init(priv);
428	meson_viu_init(priv);
429	if (priv->afbcd.ops)
430		priv->afbcd.ops->init(priv);
431
432	return drm_mode_config_helper_resume(priv->drm);
433}
434
435static int compare_of(struct device *dev, void *data)
436{
437	DRM_DEBUG_DRIVER("Comparing of node %pOF with %pOF\n",
438			 dev->of_node, data);
439
440	return dev->of_node == data;
441}
442
443/* Possible connectors nodes to ignore */
444static const struct of_device_id connectors_match[] = {
445	{ .compatible = "composite-video-connector" },
446	{ .compatible = "svideo-connector" },
447	{ .compatible = "hdmi-connector" },
448	{ .compatible = "dvi-connector" },
449	{}
450};
451
452static int meson_probe_remote(struct platform_device *pdev,
453			      struct component_match **match,
454			      struct device_node *parent,
455			      struct device_node *remote)
456{
457	struct device_node *ep, *remote_node;
458	int count = 1;
459
460	/* If node is a connector, return and do not add to match table */
461	if (of_match_node(connectors_match, remote))
462		return 1;
463
464	component_match_add(&pdev->dev, match, compare_of, remote);
465
466	for_each_endpoint_of_node(remote, ep) {
467		remote_node = of_graph_get_remote_port_parent(ep);
468		if (!remote_node ||
469		    remote_node == parent || /* Ignore parent endpoint */
470		    !of_device_is_available(remote_node)) {
471			of_node_put(remote_node);
472			continue;
473		}
474
475		count += meson_probe_remote(pdev, match, remote, remote_node);
476
477		of_node_put(remote_node);
478	}
479
480	return count;
481}
482
483static int meson_drv_probe(struct platform_device *pdev)
484{
485	struct component_match *match = NULL;
486	struct device_node *np = pdev->dev.of_node;
487	struct device_node *ep, *remote;
488	int count = 0;
489
490	for_each_endpoint_of_node(np, ep) {
491		remote = of_graph_get_remote_port_parent(ep);
492		if (!remote || !of_device_is_available(remote)) {
493			of_node_put(remote);
494			continue;
495		}
496
497		count += meson_probe_remote(pdev, &match, np, remote);
498		of_node_put(remote);
499	}
500
501	if (count && !match)
502		return meson_drv_bind_master(&pdev->dev, false);
503
504	/* If some endpoints were found, initialize the nodes */
505	if (count) {
506		dev_info(&pdev->dev, "Queued %d outputs on vpu\n", count);
507
508		return component_master_add_with_match(&pdev->dev,
509						       &meson_drv_master_ops,
510						       match);
511	}
512
513	/* If no output endpoints were available, simply bail out */
514	return 0;
515};
516
517static struct meson_drm_match_data meson_drm_gxbb_data = {
518	.compat = VPU_COMPATIBLE_GXBB,
519};
520
521static struct meson_drm_match_data meson_drm_gxl_data = {
522	.compat = VPU_COMPATIBLE_GXL,
523};
524
525static struct meson_drm_match_data meson_drm_gxm_data = {
526	.compat = VPU_COMPATIBLE_GXM,
527	.afbcd_ops = &meson_afbcd_gxm_ops,
528};
529
530static struct meson_drm_match_data meson_drm_g12a_data = {
531	.compat = VPU_COMPATIBLE_G12A,
532	.afbcd_ops = &meson_afbcd_g12a_ops,
533};
534
535static const struct of_device_id dt_match[] = {
536	{ .compatible = "amlogic,meson-gxbb-vpu",
537	  .data       = (void *)&meson_drm_gxbb_data },
538	{ .compatible = "amlogic,meson-gxl-vpu",
539	  .data       = (void *)&meson_drm_gxl_data },
540	{ .compatible = "amlogic,meson-gxm-vpu",
541	  .data       = (void *)&meson_drm_gxm_data },
542	{ .compatible = "amlogic,meson-g12a-vpu",
543	  .data       = (void *)&meson_drm_g12a_data },
544	{}
545};
546MODULE_DEVICE_TABLE(of, dt_match);
547
548static const struct dev_pm_ops meson_drv_pm_ops = {
549	SET_SYSTEM_SLEEP_PM_OPS(meson_drv_pm_suspend, meson_drv_pm_resume)
550};
551
552static struct platform_driver meson_drm_platform_driver = {
553	.probe      = meson_drv_probe,
554	.driver     = {
555		.name	= "meson-drm",
556		.of_match_table = dt_match,
557		.pm = &meson_drv_pm_ops,
558	},
559};
560
561module_platform_driver(meson_drm_platform_driver);
562
563MODULE_AUTHOR("Jasper St. Pierre <jstpierre@mecheye.net>");
564MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
565MODULE_DESCRIPTION(DRIVER_DESC);
566MODULE_LICENSE("GPL");