Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0+
2#include <linux/clk.h>
3#include <linux/component.h>
4#include <linux/delay.h>
5#include <linux/io.h>
6#include <linux/mfd/syscon.h>
7#include <linux/module.h>
8#include <linux/of.h>
9#include <linux/platform_device.h>
10#include <linux/regmap.h>
11#include <linux/regulator/consumer.h>
12#include <video/mipi_display.h>
13
14#include <drm/drm_atomic_helper.h>
15#include <drm/drm_bridge.h>
16#include <drm/drm_device.h>
17#include <drm/drm_drv.h>
18#include <drm/drm_encoder.h>
19#include <drm/drm_mipi_dsi.h>
20#include <drm/drm_modeset_helper_vtables.h>
21#include <drm/drm_of.h>
22#include <drm/drm_panel.h>
23#include <drm/drm_print.h>
24#include <drm/drm_probe_helper.h>
25
26#include "mcde_drm.h"
27#include "mcde_dsi_regs.h"
28
29#define DSI_DEFAULT_LP_FREQ_HZ 19200000
30#define DSI_DEFAULT_HS_FREQ_HZ 420160000
31
32/* PRCMU DSI reset registers */
33#define PRCM_DSI_SW_RESET 0x324
34#define PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0)
35#define PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1)
36#define PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2)
37
38struct mcde_dsi {
39 struct device *dev;
40 struct mcde *mcde;
41 struct drm_bridge bridge;
42 struct drm_panel *panel;
43 struct drm_bridge *bridge_out;
44 struct mipi_dsi_host dsi_host;
45 struct mipi_dsi_device *mdsi;
46 struct clk *hs_clk;
47 struct clk *lp_clk;
48 unsigned long hs_freq;
49 unsigned long lp_freq;
50 bool unused;
51
52 void __iomem *regs;
53 struct regmap *prcmu;
54};
55
56static inline struct mcde_dsi *bridge_to_mcde_dsi(struct drm_bridge *bridge)
57{
58 return container_of(bridge, struct mcde_dsi, bridge);
59}
60
61static inline struct mcde_dsi *host_to_mcde_dsi(struct mipi_dsi_host *h)
62{
63 return container_of(h, struct mcde_dsi, dsi_host);
64}
65
66bool mcde_dsi_irq(struct mipi_dsi_device *mdsi)
67{
68 struct mcde_dsi *d;
69 u32 val;
70 bool te_received = false;
71
72 d = host_to_mcde_dsi(mdsi->host);
73
74 dev_dbg(d->dev, "%s called\n", __func__);
75
76 val = readl(d->regs + DSI_DIRECT_CMD_STS_FLAG);
77 if (val)
78 dev_dbg(d->dev, "DSI_DIRECT_CMD_STS_FLAG = %08x\n", val);
79 if (val & DSI_DIRECT_CMD_STS_WRITE_COMPLETED)
80 dev_dbg(d->dev, "direct command write completed\n");
81 if (val & DSI_DIRECT_CMD_STS_TE_RECEIVED) {
82 te_received = true;
83 dev_dbg(d->dev, "direct command TE received\n");
84 }
85 if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED)
86 dev_err(d->dev, "direct command ACK ERR received\n");
87 if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR)
88 dev_err(d->dev, "direct command read ERR received\n");
89 /* Mask off the ACK value and clear status */
90 writel(val, d->regs + DSI_DIRECT_CMD_STS_CLR);
91
92 val = readl(d->regs + DSI_CMD_MODE_STS_FLAG);
93 if (val)
94 dev_dbg(d->dev, "DSI_CMD_MODE_STS_FLAG = %08x\n", val);
95 if (val & DSI_CMD_MODE_STS_ERR_NO_TE)
96 /* This happens all the time (safe to ignore) */
97 dev_dbg(d->dev, "CMD mode no TE\n");
98 if (val & DSI_CMD_MODE_STS_ERR_TE_MISS)
99 /* This happens all the time (safe to ignore) */
100 dev_dbg(d->dev, "CMD mode TE miss\n");
101 if (val & DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN)
102 dev_err(d->dev, "CMD mode SD1 underrun\n");
103 if (val & DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN)
104 dev_err(d->dev, "CMD mode SD2 underrun\n");
105 if (val & DSI_CMD_MODE_STS_ERR_UNWANTED_RD)
106 dev_err(d->dev, "CMD mode unwanted RD\n");
107 writel(val, d->regs + DSI_CMD_MODE_STS_CLR);
108
109 val = readl(d->regs + DSI_DIRECT_CMD_RD_STS_FLAG);
110 if (val)
111 dev_dbg(d->dev, "DSI_DIRECT_CMD_RD_STS_FLAG = %08x\n", val);
112 writel(val, d->regs + DSI_DIRECT_CMD_RD_STS_CLR);
113
114 val = readl(d->regs + DSI_TG_STS_FLAG);
115 if (val)
116 dev_dbg(d->dev, "DSI_TG_STS_FLAG = %08x\n", val);
117 writel(val, d->regs + DSI_TG_STS_CLR);
118
119 val = readl(d->regs + DSI_VID_MODE_STS_FLAG);
120 if (val)
121 dev_dbg(d->dev, "DSI_VID_MODE_STS_FLAG = %08x\n", val);
122 if (val & DSI_VID_MODE_STS_VSG_RUNNING)
123 dev_dbg(d->dev, "VID mode VSG running\n");
124 if (val & DSI_VID_MODE_STS_ERR_MISSING_DATA)
125 dev_err(d->dev, "VID mode missing data\n");
126 if (val & DSI_VID_MODE_STS_ERR_MISSING_HSYNC)
127 dev_err(d->dev, "VID mode missing HSYNC\n");
128 if (val & DSI_VID_MODE_STS_ERR_MISSING_VSYNC)
129 dev_err(d->dev, "VID mode missing VSYNC\n");
130 if (val & DSI_VID_MODE_STS_REG_ERR_SMALL_LENGTH)
131 dev_err(d->dev, "VID mode less bytes than expected between two HSYNC\n");
132 if (val & DSI_VID_MODE_STS_REG_ERR_SMALL_HEIGHT)
133 dev_err(d->dev, "VID mode less lines than expected between two VSYNC\n");
134 if (val & (DSI_VID_MODE_STS_ERR_BURSTWRITE |
135 DSI_VID_MODE_STS_ERR_LINEWRITE |
136 DSI_VID_MODE_STS_ERR_LONGREAD))
137 dev_err(d->dev, "VID mode read/write error\n");
138 if (val & DSI_VID_MODE_STS_ERR_VRS_WRONG_LENGTH)
139 dev_err(d->dev, "VID mode received packets differ from expected size\n");
140 if (val & DSI_VID_MODE_STS_VSG_RECOVERY)
141 dev_err(d->dev, "VID mode VSG in recovery mode\n");
142 writel(val, d->regs + DSI_VID_MODE_STS_CLR);
143
144 return te_received;
145}
146
147static void mcde_dsi_attach_to_mcde(struct mcde_dsi *d)
148{
149 d->mcde->mdsi = d->mdsi;
150
151 d->mcde->video_mode = !!(d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO);
152 /* Enable use of the TE signal for all command mode panels */
153 d->mcde->te_sync = !d->mcde->video_mode;
154}
155
156static int mcde_dsi_host_attach(struct mipi_dsi_host *host,
157 struct mipi_dsi_device *mdsi)
158{
159 struct mcde_dsi *d = host_to_mcde_dsi(host);
160
161 if (mdsi->lanes < 1 || mdsi->lanes > 2) {
162 DRM_ERROR("dsi device params invalid, 1 or 2 lanes supported\n");
163 return -EINVAL;
164 }
165
166 dev_info(d->dev, "attached DSI device with %d lanes\n", mdsi->lanes);
167 /* MIPI_DSI_FMT_RGB88 etc */
168 dev_info(d->dev, "format %08x, %dbpp\n", mdsi->format,
169 mipi_dsi_pixel_format_to_bpp(mdsi->format));
170 dev_info(d->dev, "mode flags: %08lx\n", mdsi->mode_flags);
171
172 d->mdsi = mdsi;
173 if (d->mcde)
174 mcde_dsi_attach_to_mcde(d);
175
176 return 0;
177}
178
179static int mcde_dsi_host_detach(struct mipi_dsi_host *host,
180 struct mipi_dsi_device *mdsi)
181{
182 struct mcde_dsi *d = host_to_mcde_dsi(host);
183
184 d->mdsi = NULL;
185 if (d->mcde)
186 d->mcde->mdsi = NULL;
187
188 return 0;
189}
190
191#define MCDE_DSI_HOST_IS_READ(type) \
192 ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
193 (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
194 (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
195 (type == MIPI_DSI_DCS_READ))
196
197static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host,
198 const struct mipi_dsi_msg *msg)
199{
200 struct mcde_dsi *d = host_to_mcde_dsi(host);
201 const u32 loop_delay_us = 10; /* us */
202 const u8 *tx = msg->tx_buf;
203 u32 loop_counter;
204 size_t txlen = msg->tx_len;
205 size_t rxlen = msg->rx_len;
206 u32 val;
207 int ret;
208 int i;
209
210 if (txlen > 16) {
211 dev_err(d->dev,
212 "dunno how to write more than 16 bytes yet\n");
213 return -EIO;
214 }
215 if (rxlen > 4) {
216 dev_err(d->dev,
217 "dunno how to read more than 4 bytes yet\n");
218 return -EIO;
219 }
220
221 dev_dbg(d->dev,
222 "message to channel %d, write %zd bytes read %zd bytes\n",
223 msg->channel, txlen, rxlen);
224
225 /* Command "nature" */
226 if (MCDE_DSI_HOST_IS_READ(msg->type))
227 /* MCTL_MAIN_DATA_CTL already set up */
228 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_READ;
229 else
230 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_WRITE;
231 /*
232 * More than 2 bytes will not fit in a single packet, so it's
233 * time to set the "long not short" bit. One byte is used by
234 * the MIPI DCS command leaving just one byte for the payload
235 * in a short package.
236 */
237 if (mipi_dsi_packet_format_is_long(msg->type))
238 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT;
239 val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT;
240 val |= txlen << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT;
241 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN;
242 val |= msg->type << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT;
243 writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS);
244
245 /* MIPI DCS command is part of the data */
246 if (txlen > 0) {
247 val = 0;
248 for (i = 0; i < 4 && i < txlen; i++)
249 val |= tx[i] << (i * 8);
250 }
251 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT0);
252 if (txlen > 4) {
253 val = 0;
254 for (i = 0; i < 4 && (i + 4) < txlen; i++)
255 val |= tx[i + 4] << (i * 8);
256 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT1);
257 }
258 if (txlen > 8) {
259 val = 0;
260 for (i = 0; i < 4 && (i + 8) < txlen; i++)
261 val |= tx[i + 8] << (i * 8);
262 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT2);
263 }
264 if (txlen > 12) {
265 val = 0;
266 for (i = 0; i < 4 && (i + 12) < txlen; i++)
267 val |= tx[i + 12] << (i * 8);
268 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT3);
269 }
270
271 writel(~0, d->regs + DSI_DIRECT_CMD_STS_CLR);
272 writel(~0, d->regs + DSI_CMD_MODE_STS_CLR);
273 /* Send command */
274 writel(1, d->regs + DSI_DIRECT_CMD_SEND);
275
276 loop_counter = 1000 * 1000 / loop_delay_us;
277 if (MCDE_DSI_HOST_IS_READ(msg->type)) {
278 /* Read command */
279 while (!(readl(d->regs + DSI_DIRECT_CMD_STS) &
280 (DSI_DIRECT_CMD_STS_READ_COMPLETED |
281 DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR))
282 && --loop_counter)
283 usleep_range(loop_delay_us, (loop_delay_us * 3) / 2);
284 if (!loop_counter) {
285 dev_err(d->dev, "DSI read timeout!\n");
286 return -ETIME;
287 }
288 } else {
289 /* Writing only */
290 while (!(readl(d->regs + DSI_DIRECT_CMD_STS) &
291 DSI_DIRECT_CMD_STS_WRITE_COMPLETED)
292 && --loop_counter)
293 usleep_range(loop_delay_us, (loop_delay_us * 3) / 2);
294
295 if (!loop_counter) {
296 dev_err(d->dev, "DSI write timeout!\n");
297 return -ETIME;
298 }
299 }
300
301 val = readl(d->regs + DSI_DIRECT_CMD_STS);
302 if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR) {
303 dev_err(d->dev, "read completed with error\n");
304 writel(1, d->regs + DSI_DIRECT_CMD_RD_INIT);
305 return -EIO;
306 }
307 if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED) {
308 val >>= DSI_DIRECT_CMD_STS_ACK_VAL_SHIFT;
309 dev_err(d->dev, "error during transmission: %04x\n",
310 val);
311 return -EIO;
312 }
313
314 if (!MCDE_DSI_HOST_IS_READ(msg->type)) {
315 /* Return number of bytes written */
316 ret = txlen;
317 } else {
318 /* OK this is a read command, get the response */
319 u32 rdsz;
320 u32 rddat;
321 u8 *rx = msg->rx_buf;
322
323 rdsz = readl(d->regs + DSI_DIRECT_CMD_RD_PROPERTY);
324 rdsz &= DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_MASK;
325 rddat = readl(d->regs + DSI_DIRECT_CMD_RDDAT);
326 if (rdsz < rxlen) {
327 dev_err(d->dev, "read error, requested %zd got %d\n",
328 rxlen, rdsz);
329 return -EIO;
330 }
331 /* FIXME: read more than 4 bytes */
332 for (i = 0; i < 4 && i < rxlen; i++)
333 rx[i] = (rddat >> (i * 8)) & 0xff;
334 ret = rdsz;
335 }
336
337 writel(~0, d->regs + DSI_DIRECT_CMD_STS_CLR);
338 writel(~0, d->regs + DSI_CMD_MODE_STS_CLR);
339
340 return ret;
341}
342
343static const struct mipi_dsi_host_ops mcde_dsi_host_ops = {
344 .attach = mcde_dsi_host_attach,
345 .detach = mcde_dsi_host_detach,
346 .transfer = mcde_dsi_host_transfer,
347};
348
349/* This sends a direct (short) command to request TE */
350void mcde_dsi_te_request(struct mipi_dsi_device *mdsi)
351{
352 struct mcde_dsi *d;
353 u32 val;
354
355 d = host_to_mcde_dsi(mdsi->host);
356
357 /* Command "nature" TE request */
358 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TE_REQ;
359 val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT;
360 val |= 2 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT;
361 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN;
362 val |= MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM <<
363 DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT;
364 writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS);
365
366 /* Clear TE reveived and error status bits and enables them */
367 writel(DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR |
368 DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR,
369 d->regs + DSI_DIRECT_CMD_STS_CLR);
370 val = readl(d->regs + DSI_DIRECT_CMD_STS_CTL);
371 val |= DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN;
372 val |= DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN;
373 writel(val, d->regs + DSI_DIRECT_CMD_STS_CTL);
374
375 /* Clear and enable no TE or TE missing status */
376 writel(DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR |
377 DSI_CMD_MODE_STS_CLR_ERR_TE_MISS_CLR,
378 d->regs + DSI_CMD_MODE_STS_CLR);
379 val = readl(d->regs + DSI_CMD_MODE_STS_CTL);
380 val |= DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN;
381 val |= DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN;
382 writel(val, d->regs + DSI_CMD_MODE_STS_CTL);
383
384 /* Send this TE request command */
385 writel(1, d->regs + DSI_DIRECT_CMD_SEND);
386}
387
388static void mcde_dsi_setup_video_mode(struct mcde_dsi *d,
389 const struct drm_display_mode *mode)
390{
391 /* cpp, characters per pixel, number of bytes per pixel */
392 u8 cpp = mipi_dsi_pixel_format_to_bpp(d->mdsi->format) / 8;
393 u64 pclk;
394 u64 bpl;
395 int hfp;
396 int hbp;
397 int hsa;
398 u32 blkline_pck, line_duration;
399 u32 val;
400
401 val = 0;
402 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
403 val |= DSI_VID_MAIN_CTL_BURST_MODE;
404 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
405 val |= DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE;
406 val |= DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL;
407 }
408 /* RGB header and pixel mode */
409 switch (d->mdsi->format) {
410 case MIPI_DSI_FMT_RGB565:
411 val |= MIPI_DSI_PACKED_PIXEL_STREAM_16 <<
412 DSI_VID_MAIN_CTL_HEADER_SHIFT;
413 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_16BITS;
414 break;
415 case MIPI_DSI_FMT_RGB666_PACKED:
416 val |= MIPI_DSI_PACKED_PIXEL_STREAM_18 <<
417 DSI_VID_MAIN_CTL_HEADER_SHIFT;
418 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS;
419 break;
420 case MIPI_DSI_FMT_RGB666:
421 val |= MIPI_DSI_PIXEL_STREAM_3BYTE_18
422 << DSI_VID_MAIN_CTL_HEADER_SHIFT;
423 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS_LOOSE;
424 break;
425 case MIPI_DSI_FMT_RGB888:
426 val |= MIPI_DSI_PACKED_PIXEL_STREAM_24 <<
427 DSI_VID_MAIN_CTL_HEADER_SHIFT;
428 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_24BITS;
429 break;
430 default:
431 dev_err(d->dev, "unknown pixel mode\n");
432 return;
433 }
434
435 /* TODO: TVG (test video generator) could be enabled here */
436
437 /*
438 * During vertical blanking: go to LP mode
439 * Like with the EOL setting, if this is not set, the EOL area will be
440 * filled with NULL or blanking packets in the vblank area.
441 * FIXME: some Samsung phones and display panels such as s6e63m0 use
442 * DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_BLANKING here instead,
443 * figure out how to properly configure that from the panel.
444 */
445 val |= DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_0;
446 /*
447 * During EOL: go to LP mode. If this is not set, the EOL area will be
448 * filled with NULL or blanking packets.
449 */
450 val |= DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0;
451 /* Recovery mode 1 */
452 val |= 1 << DSI_VID_MAIN_CTL_RECOVERY_MODE_SHIFT;
453 /* All other fields zero */
454 writel(val, d->regs + DSI_VID_MAIN_CTL);
455
456 /* Vertical frame parameters are pretty straight-forward */
457 val = mode->vdisplay << DSI_VID_VSIZE_VACT_LENGTH_SHIFT;
458 /* vertical front porch */
459 val |= (mode->vsync_start - mode->vdisplay)
460 << DSI_VID_VSIZE_VFP_LENGTH_SHIFT;
461 /* vertical sync active */
462 val |= (mode->vsync_end - mode->vsync_start)
463 << DSI_VID_VSIZE_VSA_LENGTH_SHIFT;
464 /* vertical back porch */
465 val |= (mode->vtotal - mode->vsync_end)
466 << DSI_VID_VSIZE_VBP_LENGTH_SHIFT;
467 writel(val, d->regs + DSI_VID_VSIZE);
468
469 /*
470 * Horizontal frame parameters:
471 * horizontal resolution is given in pixels but must be re-calculated
472 * into bytes since this is what the hardware expects, these registers
473 * define the payload size of the packet.
474 *
475 * hfp = horizontal front porch in bytes
476 * hbp = horizontal back porch in bytes
477 * hsa = horizontal sync active in bytes
478 *
479 * 6 + 2 is HFP header + checksum
480 */
481 hfp = (mode->hsync_start - mode->hdisplay) * cpp - 6 - 2;
482 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
483 /*
484 * Use sync pulse for sync: explicit HSA time
485 * 6 is HBP header + checksum
486 * 4 is RGB header + checksum
487 */
488 hbp = (mode->htotal - mode->hsync_end) * cpp - 4 - 6;
489 /*
490 * 6 is HBP header + checksum
491 * 4 is HSW packet bytes
492 * 4 is RGB header + checksum
493 */
494 hsa = (mode->hsync_end - mode->hsync_start) * cpp - 4 - 4 - 6;
495 } else {
496 /*
497 * Use event for sync: HBP includes both back porch and sync
498 * 6 is HBP header + checksum
499 * 4 is HSW packet bytes
500 * 4 is RGB header + checksum
501 */
502 hbp = (mode->htotal - mode->hsync_start) * cpp - 4 - 4 - 6;
503 /* HSA is not present in this mode and set to 0 */
504 hsa = 0;
505 }
506 if (hfp < 0) {
507 dev_info(d->dev, "hfp negative, set to 0\n");
508 hfp = 0;
509 }
510 if (hbp < 0) {
511 dev_info(d->dev, "hbp negative, set to 0\n");
512 hbp = 0;
513 }
514 if (hsa < 0) {
515 dev_info(d->dev, "hsa negative, set to 0\n");
516 hsa = 0;
517 }
518 dev_dbg(d->dev, "hfp: %u, hbp: %u, hsa: %u bytes\n",
519 hfp, hbp, hsa);
520
521 /* Frame parameters: horizontal sync active */
522 val = hsa << DSI_VID_HSIZE1_HSA_LENGTH_SHIFT;
523 /* horizontal back porch */
524 val |= hbp << DSI_VID_HSIZE1_HBP_LENGTH_SHIFT;
525 /* horizontal front porch */
526 val |= hfp << DSI_VID_HSIZE1_HFP_LENGTH_SHIFT;
527 writel(val, d->regs + DSI_VID_HSIZE1);
528
529 /* RGB data length (visible bytes on one scanline) */
530 val = mode->hdisplay * cpp;
531 writel(val, d->regs + DSI_VID_HSIZE2);
532 dev_dbg(d->dev, "RGB length, visible area on a line: %u bytes\n", val);
533
534 /*
535 * Calculate the time between two pixels in picoseconds using
536 * the supplied refresh rate and total resolution including
537 * porches and sync.
538 */
539 /* (ps/s) / (pixels/s) = ps/pixels */
540 pclk = DIV_ROUND_UP_ULL(1000000000000, mode->clock);
541 dev_dbg(d->dev, "picoseconds between two pixels: %llu\n",
542 pclk);
543
544 /*
545 * How many bytes per line will this update frequency yield?
546 *
547 * Calculate the number of picoseconds for one scanline (1), then
548 * divide by 1000000000000 (2) to get in pixels per second we
549 * want to output.
550 *
551 * Multiply with number of bytes per second at this video display
552 * frequency (3) to get number of bytes transferred during this
553 * time. Notice that we use the frequency the display wants,
554 * not what we actually get from the DSI PLL, which is hs_freq.
555 *
556 * These arithmetics are done in a different order to avoid
557 * overflow.
558 */
559 bpl = pclk * mode->htotal; /* (1) picoseconds per line */
560 dev_dbg(d->dev, "picoseconds per line: %llu\n", bpl);
561 /* Multiply with bytes per second (3) */
562 bpl *= (d->mdsi->hs_rate / 8);
563 /* Pixels per second (2) */
564 bpl = DIV_ROUND_DOWN_ULL(bpl, 1000000); /* microseconds */
565 bpl = DIV_ROUND_DOWN_ULL(bpl, 1000000); /* seconds */
566 /* parallel transactions in all lanes */
567 bpl *= d->mdsi->lanes;
568 dev_dbg(d->dev,
569 "calculated bytes per line: %llu @ %d Hz with HS %lu Hz\n",
570 bpl, drm_mode_vrefresh(mode), d->mdsi->hs_rate);
571
572 /*
573 * 6 is header + checksum, header = 4 bytes, checksum = 2 bytes
574 * 4 is short packet for vsync/hsync
575 */
576 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
577 /* Set the event packet size to 0 (not used) */
578 writel(0, d->regs + DSI_VID_BLKSIZE1);
579 /*
580 * FIXME: isn't the hsync width in pixels? The porch and
581 * sync area size is in pixels here, but this -6
582 * seems to be for bytes. It looks like this in the vendor
583 * code though. Is it completely untested?
584 */
585 blkline_pck = bpl - (mode->hsync_end - mode->hsync_start) - 6;
586 val = blkline_pck << DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_SHIFT;
587 writel(val, d->regs + DSI_VID_BLKSIZE2);
588 } else {
589 /* Set the sync pulse packet size to 0 (not used) */
590 writel(0, d->regs + DSI_VID_BLKSIZE2);
591 /* Specifying payload size in bytes (-4-6 from manual) */
592 blkline_pck = bpl - 4 - 6;
593 if (blkline_pck > 0x1FFF)
594 dev_err(d->dev, "blkline_pck too big %d bytes\n",
595 blkline_pck);
596 val = blkline_pck << DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_SHIFT;
597 val &= DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_MASK;
598 writel(val, d->regs + DSI_VID_BLKSIZE1);
599 }
600
601 /*
602 * The line duration is used to scale back the frequency from
603 * the max frequency supported by the HS clock to the desired
604 * update frequency in vrefresh.
605 */
606 line_duration = blkline_pck + 6;
607 /*
608 * The datasheet contains this complex condition to decreasing
609 * the line duration by 1 under very specific circumstances.
610 * Here we also imply that LP is used during burst EOL.
611 */
612 if (d->mdsi->lanes == 2 && (hsa & 0x01) && (hfp & 0x01)
613 && (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST))
614 line_duration--;
615 line_duration = DIV_ROUND_CLOSEST(line_duration, d->mdsi->lanes);
616 dev_dbg(d->dev, "line duration %u bytes\n", line_duration);
617 val = line_duration << DSI_VID_DPHY_TIME_REG_LINE_DURATION_SHIFT;
618 /*
619 * This is the time to perform LP->HS on D-PHY
620 * FIXME: nowhere to get this from: DT property on the DSI?
621 * The manual says this is "system dependent".
622 * values like 48 and 72 seen in the vendor code.
623 */
624 val |= 48 << DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_SHIFT;
625 writel(val, d->regs + DSI_VID_DPHY_TIME);
626
627 /*
628 * See the manual figure 657 page 2203 for understanding the impact
629 * of the different burst mode settings.
630 */
631 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
632 int blkeol_pck, blkeol_duration;
633 /*
634 * Packet size at EOL for burst mode, this is only used
635 * if DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0 is NOT set,
636 * but we instead send NULL or blanking packets at EOL.
637 * This is given in number of bytes.
638 *
639 * See the manual page 2198 for the 13 reg_blkeol_pck bits.
640 */
641 blkeol_pck = bpl - (mode->htotal * cpp) - 6;
642 if (blkeol_pck < 0) {
643 dev_err(d->dev, "video block does not fit on line!\n");
644 dev_err(d->dev,
645 "calculated bytes per line: %llu @ %d Hz\n",
646 bpl, drm_mode_vrefresh(mode));
647 dev_err(d->dev,
648 "bytes per line (blkline_pck) %u bytes\n",
649 blkline_pck);
650 dev_err(d->dev,
651 "blkeol_pck becomes %d bytes\n", blkeol_pck);
652 return;
653 }
654 dev_dbg(d->dev, "BLKEOL packet: %d bytes\n", blkeol_pck);
655
656 val = readl(d->regs + DSI_VID_BLKSIZE1);
657 val &= ~DSI_VID_BLKSIZE1_BLKEOL_PCK_MASK;
658 val |= blkeol_pck << DSI_VID_BLKSIZE1_BLKEOL_PCK_SHIFT;
659 writel(val, d->regs + DSI_VID_BLKSIZE1);
660 /* Use the same value for exact burst limit */
661 val = blkeol_pck <<
662 DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_SHIFT;
663 val &= DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_MASK;
664 writel(val, d->regs + DSI_VID_VCA_SETTING2);
665 /*
666 * This BLKEOL duration is claimed to be the duration in clock
667 * cycles of the BLLP end-of-line (EOL) period for each line if
668 * DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0 is set.
669 *
670 * It is hard to trust the manuals' claim that this is in clock
671 * cycles as we mimic the behaviour of the vendor code, which
672 * appears to write a number of bytes that would have been
673 * transferred on a single lane.
674 *
675 * See the manual figure 657 page 2203 and page 2198 for the 13
676 * reg_blkeol_duration bits.
677 *
678 * FIXME: should this also be set up also for non-burst mode
679 * according to figure 565 page 2202?
680 */
681 blkeol_duration = DIV_ROUND_CLOSEST(blkeol_pck + 6,
682 d->mdsi->lanes);
683 dev_dbg(d->dev, "BLKEOL duration: %d clock cycles\n",
684 blkeol_duration);
685
686 val = readl(d->regs + DSI_VID_PCK_TIME);
687 val &= ~DSI_VID_PCK_TIME_BLKEOL_DURATION_MASK;
688 val |= blkeol_duration <<
689 DSI_VID_PCK_TIME_BLKEOL_DURATION_SHIFT;
690 writel(val, d->regs + DSI_VID_PCK_TIME);
691
692 /* Max burst limit, this is given in bytes */
693 val = readl(d->regs + DSI_VID_VCA_SETTING1);
694 val &= ~DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_MASK;
695 val |= (blkeol_pck - 6) <<
696 DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_SHIFT;
697 writel(val, d->regs + DSI_VID_VCA_SETTING1);
698 }
699
700 /* Maximum line limit */
701 val = readl(d->regs + DSI_VID_VCA_SETTING2);
702 val &= ~DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_MASK;
703 val |= (blkline_pck - 6) <<
704 DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_SHIFT;
705 writel(val, d->regs + DSI_VID_VCA_SETTING2);
706 dev_dbg(d->dev, "blkline pck: %d bytes\n", blkline_pck - 6);
707}
708
709static void mcde_dsi_start(struct mcde_dsi *d)
710{
711 unsigned long hs_freq;
712 u32 val;
713 int i;
714
715 /* No integration mode */
716 writel(0, d->regs + DSI_MCTL_INTEGRATION_MODE);
717
718 /* Enable the DSI port, from drivers/video/mcde/dsilink_v2.c */
719 val = DSI_MCTL_MAIN_DATA_CTL_LINK_EN |
720 DSI_MCTL_MAIN_DATA_CTL_BTA_EN |
721 DSI_MCTL_MAIN_DATA_CTL_READ_EN |
722 DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN;
723 if (d->mdsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)
724 val |= DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN;
725 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
726
727 /* Set a high command timeout, clear other fields */
728 val = 0x3ff << DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT;
729 writel(val, d->regs + DSI_CMD_MODE_CTL);
730
731 /*
732 * UI_X4 is described as "unit interval times four"
733 * I guess since DSI packets are 4 bytes wide, one unit
734 * is one byte.
735 */
736 hs_freq = clk_get_rate(d->hs_clk);
737 hs_freq /= 1000000; /* MHz */
738 val = 4000 / hs_freq;
739 dev_dbg(d->dev, "UI value: %d\n", val);
740 val <<= DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT;
741 val &= DSI_MCTL_DPHY_STATIC_UI_X4_MASK;
742 writel(val, d->regs + DSI_MCTL_DPHY_STATIC);
743
744 /*
745 * Enable clocking: 0x0f (something?) between each burst,
746 * enable the second lane if needed, enable continuous clock if
747 * needed, enable switch into ULPM (ultra-low power mode) on
748 * all the lines.
749 */
750 val = 0x0f << DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT;
751 if (d->mdsi->lanes == 2)
752 val |= DSI_MCTL_MAIN_PHY_CTL_LANE2_EN;
753 if (!(d->mdsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
754 val |= DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS;
755 val |= DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN |
756 DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN |
757 DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN;
758 writel(val, d->regs + DSI_MCTL_MAIN_PHY_CTL);
759
760 val = (1 << DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT) |
761 (1 << DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_SHIFT);
762 writel(val, d->regs + DSI_MCTL_ULPOUT_TIME);
763
764 writel(DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90,
765 d->regs + DSI_DPHY_LANES_TRIM);
766
767 /* High PHY timeout */
768 val = (0x0f << DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT) |
769 (0x3fff << DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_SHIFT) |
770 (0x3fff << DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_SHIFT);
771 writel(val, d->regs + DSI_MCTL_DPHY_TIMEOUT);
772
773 val = DSI_MCTL_MAIN_EN_PLL_START |
774 DSI_MCTL_MAIN_EN_CKLANE_EN |
775 DSI_MCTL_MAIN_EN_DAT1_EN |
776 DSI_MCTL_MAIN_EN_IF1_EN;
777 if (d->mdsi->lanes == 2)
778 val |= DSI_MCTL_MAIN_EN_DAT2_EN;
779 writel(val, d->regs + DSI_MCTL_MAIN_EN);
780
781 /* Wait for the PLL to lock and the clock and data lines to come up */
782 i = 0;
783 val = DSI_MCTL_MAIN_STS_PLL_LOCK |
784 DSI_MCTL_MAIN_STS_CLKLANE_READY |
785 DSI_MCTL_MAIN_STS_DAT1_READY;
786 if (d->mdsi->lanes == 2)
787 val |= DSI_MCTL_MAIN_STS_DAT2_READY;
788 while ((readl(d->regs + DSI_MCTL_MAIN_STS) & val) != val) {
789 /* Sleep for a millisecond */
790 usleep_range(1000, 1500);
791 if (i++ == 100) {
792 dev_warn(d->dev, "DSI lanes did not start up\n");
793 return;
794 }
795 }
796
797 /* TODO needed? */
798
799 /* Command mode, clear IF1 ID */
800 val = readl(d->regs + DSI_CMD_MODE_CTL);
801 /*
802 * If we enable low-power mode here, with
803 * val |= DSI_CMD_MODE_CTL_IF1_LP_EN
804 * then display updates become really slow.
805 */
806 val &= ~DSI_CMD_MODE_CTL_IF1_ID_MASK;
807 writel(val, d->regs + DSI_CMD_MODE_CTL);
808
809 /* Wait for DSI PHY to initialize */
810 usleep_range(100, 200);
811 dev_info(d->dev, "DSI link enabled\n");
812}
813
814
815static void mcde_dsi_bridge_enable(struct drm_bridge *bridge)
816{
817 struct mcde_dsi *d = bridge_to_mcde_dsi(bridge);
818 u32 val;
819
820 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
821 /* Enable video mode */
822 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);
823 val |= DSI_MCTL_MAIN_DATA_CTL_VID_EN;
824 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
825 }
826
827 dev_info(d->dev, "enable DSI master\n");
828};
829
830static void mcde_dsi_bridge_pre_enable(struct drm_bridge *bridge)
831{
832 struct mcde_dsi *d = bridge_to_mcde_dsi(bridge);
833 unsigned long hs_freq, lp_freq;
834 u32 val;
835 int ret;
836
837 /* Copy maximum clock frequencies */
838 if (d->mdsi->lp_rate)
839 lp_freq = d->mdsi->lp_rate;
840 else
841 lp_freq = DSI_DEFAULT_LP_FREQ_HZ;
842 if (d->mdsi->hs_rate)
843 hs_freq = d->mdsi->hs_rate;
844 else
845 hs_freq = DSI_DEFAULT_HS_FREQ_HZ;
846
847 /* Enable LP (Low Power, Energy Save, ES) and HS (High Speed) clocks */
848 d->lp_freq = clk_round_rate(d->lp_clk, lp_freq);
849 ret = clk_set_rate(d->lp_clk, d->lp_freq);
850 if (ret)
851 dev_err(d->dev, "failed to set LP clock rate %lu Hz\n",
852 d->lp_freq);
853
854 d->hs_freq = clk_round_rate(d->hs_clk, hs_freq);
855 ret = clk_set_rate(d->hs_clk, d->hs_freq);
856 if (ret)
857 dev_err(d->dev, "failed to set HS clock rate %lu Hz\n",
858 d->hs_freq);
859
860 /* Start clocks */
861 ret = clk_prepare_enable(d->lp_clk);
862 if (ret)
863 dev_err(d->dev, "failed to enable LP clock\n");
864 else
865 dev_info(d->dev, "DSI LP clock rate %lu Hz\n",
866 d->lp_freq);
867 ret = clk_prepare_enable(d->hs_clk);
868 if (ret)
869 dev_err(d->dev, "failed to enable HS clock\n");
870 else
871 dev_info(d->dev, "DSI HS clock rate %lu Hz\n",
872 d->hs_freq);
873
874 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
875 /* Put IF1 into video mode */
876 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);
877 val |= DSI_MCTL_MAIN_DATA_CTL_IF1_MODE;
878 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
879
880 /* Disable command mode on IF1 */
881 val = readl(d->regs + DSI_CMD_MODE_CTL);
882 val &= ~DSI_CMD_MODE_CTL_IF1_LP_EN;
883 writel(val, d->regs + DSI_CMD_MODE_CTL);
884
885 /* Enable some error interrupts */
886 val = readl(d->regs + DSI_VID_MODE_STS_CTL);
887 val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC;
888 val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA;
889 writel(val, d->regs + DSI_VID_MODE_STS_CTL);
890 } else {
891 /* Command mode, clear IF1 ID */
892 val = readl(d->regs + DSI_CMD_MODE_CTL);
893 /*
894 * If we enable low-power mode here with
895 * val |= DSI_CMD_MODE_CTL_IF1_LP_EN
896 * the display updates become really slow.
897 */
898 val &= ~DSI_CMD_MODE_CTL_IF1_ID_MASK;
899 writel(val, d->regs + DSI_CMD_MODE_CTL);
900 }
901}
902
903static void mcde_dsi_bridge_mode_set(struct drm_bridge *bridge,
904 const struct drm_display_mode *mode,
905 const struct drm_display_mode *adj)
906{
907 struct mcde_dsi *d = bridge_to_mcde_dsi(bridge);
908
909 if (!d->mdsi) {
910 dev_err(d->dev, "no DSI device attached to encoder!\n");
911 return;
912 }
913
914 dev_info(d->dev, "set DSI master to %dx%d %u Hz %s mode\n",
915 mode->hdisplay, mode->vdisplay, mode->clock * 1000,
916 (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) ? "VIDEO" : "CMD"
917 );
918
919 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO)
920 mcde_dsi_setup_video_mode(d, mode);
921}
922
923static void mcde_dsi_wait_for_command_mode_stop(struct mcde_dsi *d)
924{
925 u32 val;
926 int i;
927
928 /*
929 * Wait until we get out of command mode
930 * CSM = Command State Machine
931 */
932 i = 0;
933 val = DSI_CMD_MODE_STS_CSM_RUNNING;
934 while ((readl(d->regs + DSI_CMD_MODE_STS) & val) == val) {
935 /* Sleep for a millisecond */
936 usleep_range(1000, 2000);
937 if (i++ == 100) {
938 dev_warn(d->dev,
939 "could not get out of command mode\n");
940 return;
941 }
942 }
943}
944
945static void mcde_dsi_wait_for_video_mode_stop(struct mcde_dsi *d)
946{
947 u32 val;
948 int i;
949
950 /* Wait until we get out og video mode */
951 i = 0;
952 val = DSI_VID_MODE_STS_VSG_RUNNING;
953 while ((readl(d->regs + DSI_VID_MODE_STS) & val) == val) {
954 /* Sleep for a millisecond */
955 usleep_range(1000, 2000);
956 if (i++ == 100) {
957 dev_warn(d->dev,
958 "could not get out of video mode\n");
959 return;
960 }
961 }
962}
963
964static void mcde_dsi_bridge_disable(struct drm_bridge *bridge)
965{
966 struct mcde_dsi *d = bridge_to_mcde_dsi(bridge);
967 u32 val;
968
969 /* Disable all error interrupts */
970 writel(0, d->regs + DSI_VID_MODE_STS_CTL);
971
972 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
973 /* Stop video mode */
974 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);
975 val &= ~DSI_MCTL_MAIN_DATA_CTL_VID_EN;
976 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
977 mcde_dsi_wait_for_video_mode_stop(d);
978 } else {
979 /* Stop command mode */
980 mcde_dsi_wait_for_command_mode_stop(d);
981 }
982
983 /* Stop clocks */
984 clk_disable_unprepare(d->hs_clk);
985 clk_disable_unprepare(d->lp_clk);
986}
987
988static int mcde_dsi_bridge_attach(struct drm_bridge *bridge,
989 enum drm_bridge_attach_flags flags)
990{
991 struct mcde_dsi *d = bridge_to_mcde_dsi(bridge);
992 struct drm_device *drm = bridge->dev;
993 int ret;
994
995 if (!drm_core_check_feature(drm, DRIVER_ATOMIC)) {
996 dev_err(d->dev, "we need atomic updates\n");
997 return -ENOTSUPP;
998 }
999
1000 /* Attach the DSI bridge to the output (panel etc) bridge */
1001 ret = drm_bridge_attach(bridge->encoder, d->bridge_out, bridge, flags);
1002 if (ret) {
1003 dev_err(d->dev, "failed to attach the DSI bridge\n");
1004 return ret;
1005 }
1006
1007 return 0;
1008}
1009
1010static const struct drm_bridge_funcs mcde_dsi_bridge_funcs = {
1011 .attach = mcde_dsi_bridge_attach,
1012 .mode_set = mcde_dsi_bridge_mode_set,
1013 .disable = mcde_dsi_bridge_disable,
1014 .enable = mcde_dsi_bridge_enable,
1015 .pre_enable = mcde_dsi_bridge_pre_enable,
1016};
1017
1018static int mcde_dsi_bind(struct device *dev, struct device *master,
1019 void *data)
1020{
1021 struct drm_device *drm = data;
1022 struct mcde *mcde = to_mcde(drm);
1023 struct mcde_dsi *d = dev_get_drvdata(dev);
1024 struct device_node *child;
1025 struct drm_panel *panel = NULL;
1026 struct drm_bridge *bridge = NULL;
1027
1028 if (!of_get_available_child_count(dev->of_node)) {
1029 dev_info(dev, "unused DSI interface\n");
1030 d->unused = true;
1031 return 0;
1032 }
1033 d->mcde = mcde;
1034 /* If the display attached before binding, set this up */
1035 if (d->mdsi)
1036 mcde_dsi_attach_to_mcde(d);
1037
1038 /* Obtain the clocks */
1039 d->hs_clk = devm_clk_get(dev, "hs");
1040 if (IS_ERR(d->hs_clk)) {
1041 dev_err(dev, "unable to get HS clock\n");
1042 return PTR_ERR(d->hs_clk);
1043 }
1044
1045 d->lp_clk = devm_clk_get(dev, "lp");
1046 if (IS_ERR(d->lp_clk)) {
1047 dev_err(dev, "unable to get LP clock\n");
1048 return PTR_ERR(d->lp_clk);
1049 }
1050
1051 /* Assert RESET through the PRCMU, active low */
1052 /* FIXME: which DSI block? */
1053 regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET,
1054 PRCM_DSI_SW_RESET_DSI0_SW_RESETN, 0);
1055
1056 usleep_range(100, 200);
1057
1058 /* De-assert RESET again */
1059 regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET,
1060 PRCM_DSI_SW_RESET_DSI0_SW_RESETN,
1061 PRCM_DSI_SW_RESET_DSI0_SW_RESETN);
1062
1063 /* Start up the hardware */
1064 mcde_dsi_start(d);
1065
1066 /* Look for a panel as a child to this node */
1067 for_each_available_child_of_node(dev->of_node, child) {
1068 panel = of_drm_find_panel(child);
1069 if (IS_ERR(panel)) {
1070 dev_err(dev, "failed to find panel try bridge (%ld)\n",
1071 PTR_ERR(panel));
1072 panel = NULL;
1073
1074 bridge = of_drm_find_bridge(child);
1075 if (!bridge) {
1076 dev_err(dev, "failed to find bridge\n");
1077 return -EINVAL;
1078 }
1079 }
1080 }
1081 if (panel) {
1082 bridge = drm_panel_bridge_add_typed(panel,
1083 DRM_MODE_CONNECTOR_DSI);
1084 if (IS_ERR(bridge)) {
1085 dev_err(dev, "error adding panel bridge\n");
1086 return PTR_ERR(bridge);
1087 }
1088 dev_info(dev, "connected to panel\n");
1089 d->panel = panel;
1090 } else if (bridge) {
1091 /* TODO: AV8100 HDMI encoder goes here for example */
1092 dev_info(dev, "connected to non-panel bridge (unsupported)\n");
1093 return -ENODEV;
1094 } else {
1095 dev_err(dev, "no panel or bridge\n");
1096 return -ENODEV;
1097 }
1098
1099 d->bridge_out = bridge;
1100
1101 /* Create a bridge for this DSI channel */
1102 d->bridge.funcs = &mcde_dsi_bridge_funcs;
1103 d->bridge.of_node = dev->of_node;
1104 drm_bridge_add(&d->bridge);
1105
1106 /* TODO: first come first serve, use a list */
1107 mcde->bridge = &d->bridge;
1108
1109 dev_info(dev, "initialized MCDE DSI bridge\n");
1110
1111 return 0;
1112}
1113
1114static void mcde_dsi_unbind(struct device *dev, struct device *master,
1115 void *data)
1116{
1117 struct mcde_dsi *d = dev_get_drvdata(dev);
1118
1119 if (d->panel)
1120 drm_panel_bridge_remove(d->bridge_out);
1121 regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET,
1122 PRCM_DSI_SW_RESET_DSI0_SW_RESETN, 0);
1123}
1124
1125static const struct component_ops mcde_dsi_component_ops = {
1126 .bind = mcde_dsi_bind,
1127 .unbind = mcde_dsi_unbind,
1128};
1129
1130static int mcde_dsi_probe(struct platform_device *pdev)
1131{
1132 struct device *dev = &pdev->dev;
1133 struct mcde_dsi *d;
1134 struct mipi_dsi_host *host;
1135 struct resource *res;
1136 u32 dsi_id;
1137 int ret;
1138
1139 d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
1140 if (!d)
1141 return -ENOMEM;
1142 d->dev = dev;
1143 platform_set_drvdata(pdev, d);
1144
1145 /* Get a handle on the PRCMU so we can do reset */
1146 d->prcmu =
1147 syscon_regmap_lookup_by_compatible("stericsson,db8500-prcmu");
1148 if (IS_ERR(d->prcmu)) {
1149 dev_err(dev, "no PRCMU regmap\n");
1150 return PTR_ERR(d->prcmu);
1151 }
1152
1153 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1154 d->regs = devm_ioremap_resource(dev, res);
1155 if (IS_ERR(d->regs)) {
1156 dev_err(dev, "no DSI regs\n");
1157 return PTR_ERR(d->regs);
1158 }
1159
1160 dsi_id = readl(d->regs + DSI_ID_REG);
1161 dev_info(dev, "HW revision 0x%08x\n", dsi_id);
1162
1163 host = &d->dsi_host;
1164 host->dev = dev;
1165 host->ops = &mcde_dsi_host_ops;
1166 ret = mipi_dsi_host_register(host);
1167 if (ret < 0) {
1168 dev_err(dev, "failed to register DSI host: %d\n", ret);
1169 return ret;
1170 }
1171 dev_info(dev, "registered DSI host\n");
1172
1173 platform_set_drvdata(pdev, d);
1174 return component_add(dev, &mcde_dsi_component_ops);
1175}
1176
1177static int mcde_dsi_remove(struct platform_device *pdev)
1178{
1179 struct mcde_dsi *d = platform_get_drvdata(pdev);
1180
1181 component_del(&pdev->dev, &mcde_dsi_component_ops);
1182 mipi_dsi_host_unregister(&d->dsi_host);
1183
1184 return 0;
1185}
1186
1187static const struct of_device_id mcde_dsi_of_match[] = {
1188 {
1189 .compatible = "ste,mcde-dsi",
1190 },
1191 {},
1192};
1193
1194struct platform_driver mcde_dsi_driver = {
1195 .driver = {
1196 .name = "mcde-dsi",
1197 .of_match_table = of_match_ptr(mcde_dsi_of_match),
1198 },
1199 .probe = mcde_dsi_probe,
1200 .remove = mcde_dsi_remove,
1201};