1/*
  2 * Copyright © 2013 Intel Corporation
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice (including the next
 12 * paragraph) shall be included in all copies or substantial portions of the
 13 * Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 21 * IN THE SOFTWARE.
 22 *
 23 */
 24
 25#include <asm/iosf_mbi.h>
 26
 27#include "i915_drv.h"
 28#include "intel_sideband.h"
 29
 30/*
 31 * IOSF sideband, see VLV2_SidebandMsg_HAS.docx and
 32 * VLV_VLV2_PUNIT_HAS_0.8.docx
 33 */
 34
 35/* Standard MMIO read, non-posted */
 36#define SB_MRD_NP	0x00
 37/* Standard MMIO write, non-posted */
 38#define SB_MWR_NP	0x01
 39/* Private register read, double-word addressing, non-posted */
 40#define SB_CRRDDA_NP	0x06
 41/* Private register write, double-word addressing, non-posted */
 42#define SB_CRWRDA_NP	0x07
 43
 44static void ping(void *info)
 45{
 46}
 47
 48static void __vlv_punit_get(struct drm_i915_private *i915)
 49{
 50	iosf_mbi_punit_acquire();
 51
 52	/*
 53	 * Prevent the cpu from sleeping while we use this sideband, otherwise
 54	 * the punit may cause a machine hang. The issue appears to be isolated
 55	 * with changing the power state of the CPU package while changing
 56	 * the power state via the punit, and we have only observed it
 57	 * reliably on 4-core Baytail systems suggesting the issue is in the
 58	 * power delivery mechanism and likely to be be board/function
 59	 * specific. Hence we presume the workaround needs only be applied
 60	 * to the Valleyview P-unit and not all sideband communications.
 61	 */
 62	if (IS_VALLEYVIEW(i915)) {
 63		cpu_latency_qos_update_request(&i915->sb_qos, 0);
 64		on_each_cpu(ping, NULL, 1);
 65	}
 66}
 67
 68static void __vlv_punit_put(struct drm_i915_private *i915)
 69{
 70	if (IS_VALLEYVIEW(i915))
 71		cpu_latency_qos_update_request(&i915->sb_qos,
 72					       PM_QOS_DEFAULT_VALUE);
 73
 74	iosf_mbi_punit_release();
 75}
 76
 77void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports)
 78{
 79	if (ports & BIT(VLV_IOSF_SB_PUNIT))
 80		__vlv_punit_get(i915);
 81
 82	mutex_lock(&i915->sb_lock);
 83}
 84
 85void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports)
 86{
 87	mutex_unlock(&i915->sb_lock);
 88
 89	if (ports & BIT(VLV_IOSF_SB_PUNIT))
 90		__vlv_punit_put(i915);
 91}
 92
 93static int vlv_sideband_rw(struct drm_i915_private *i915,
 94			   u32 devfn, u32 port, u32 opcode,
 95			   u32 addr, u32 *val)
 96{
 97	struct intel_uncore *uncore = &i915->uncore;
 98	const bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP);
 99	int err;
100
101	lockdep_assert_held(&i915->sb_lock);
102	if (port == IOSF_PORT_PUNIT)
103		iosf_mbi_assert_punit_acquired();
104
105	/* Flush the previous comms, just in case it failed last time. */
106	if (intel_wait_for_register(uncore,
107				    VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
108				    5)) {
109		drm_dbg(&i915->drm, "IOSF sideband idle wait (%s) timed out\n",
110			is_read ? "read" : "write");
111		return -EAGAIN;
112	}
113
114	preempt_disable();
115
116	intel_uncore_write_fw(uncore, VLV_IOSF_ADDR, addr);
117	intel_uncore_write_fw(uncore, VLV_IOSF_DATA, is_read ? 0 : *val);
118	intel_uncore_write_fw(uncore, VLV_IOSF_DOORBELL_REQ,
119			      (devfn << IOSF_DEVFN_SHIFT) |
120			      (opcode << IOSF_OPCODE_SHIFT) |
121			      (port << IOSF_PORT_SHIFT) |
122			      (0xf << IOSF_BYTE_ENABLES_SHIFT) |
123			      (0 << IOSF_BAR_SHIFT) |
124			      IOSF_SB_BUSY);
125
126	if (__intel_wait_for_register_fw(uncore,
127					 VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
128					 10000, 0, NULL) == 0) {
129		if (is_read)
130			*val = intel_uncore_read_fw(uncore, VLV_IOSF_DATA);
131		err = 0;
132	} else {
133		drm_dbg(&i915->drm, "IOSF sideband finish wait (%s) timed out\n",
134			is_read ? "read" : "write");
135		err = -ETIMEDOUT;
136	}
137
138	preempt_enable();
139
140	return err;
141}
142
143u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr)
144{
145	u32 val = 0;
146
147	vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
148			SB_CRRDDA_NP, addr, &val);
149
150	return val;
151}
152
153int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)
154{
155	return vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
156			       SB_CRWRDA_NP, addr, &val);
157}
158
159u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg)
160{
161	u32 val = 0;
162
163	vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
164			SB_CRRDDA_NP, reg, &val);
165
166	return val;
167}
168
169void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val)
170{
171	vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
172			SB_CRWRDA_NP, reg, &val);
173}
174
175u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr)
176{
177	u32 val = 0;
178
179	vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_NC,
180			SB_CRRDDA_NP, addr, &val);
181
182	return val;
183}
184
185u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg)
186{
187	u32 val = 0;
188
189	vlv_sideband_rw(i915, PCI_DEVFN(0, 0), port,
190			SB_CRRDDA_NP, reg, &val);
191
192	return val;
193}
194
195void vlv_iosf_sb_write(struct drm_i915_private *i915,
196		       u8 port, u32 reg, u32 val)
197{
198	vlv_sideband_rw(i915, PCI_DEVFN(0, 0), port,
199			SB_CRWRDA_NP, reg, &val);
200}
201
202u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg)
203{
204	u32 val = 0;
205
206	vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
207			SB_CRRDDA_NP, reg, &val);
208
209	return val;
210}
211
212void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val)
213{
214	vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
215			SB_CRWRDA_NP, reg, &val);
216}
217
218u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg)
219{
220	u32 val = 0;
221
222	vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
223			SB_CRRDDA_NP, reg, &val);
224
225	return val;
226}
227
228void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val)
229{
230	vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
231			SB_CRWRDA_NP, reg, &val);
232}
233
234u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg)
235{
236	int port = i915->dpio_phy_iosf_port[DPIO_PHY(pipe)];
237	u32 val = 0;
238
239	vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MRD_NP, reg, &val);
240
241	/*
242	 * FIXME: There might be some registers where all 1's is a valid value,
243	 * so ideally we should check the register offset instead...
244	 */
245	drm_WARN(&i915->drm, val == 0xffffffff,
246		 "DPIO read pipe %c reg 0x%x == 0x%x\n",
247		 pipe_name(pipe), reg, val);
248
249	return val;
250}
251
252void vlv_dpio_write(struct drm_i915_private *i915,
253		    enum pipe pipe, int reg, u32 val)
254{
255	int port = i915->dpio_phy_iosf_port[DPIO_PHY(pipe)];
256
257	vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MWR_NP, reg, &val);
258}
259
260u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg)
261{
262	u32 val = 0;
263
264	vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
265			reg, &val);
266	return val;
267}
268
269void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val)
270{
271	vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
272			reg, &val);
273}
274
275/* SBI access */
276static int intel_sbi_rw(struct drm_i915_private *i915, u16 reg,
277			enum intel_sbi_destination destination,
278			u32 *val, bool is_read)
279{
280	struct intel_uncore *uncore = &i915->uncore;
281	u32 cmd;
282
283	lockdep_assert_held(&i915->sb_lock);
284
285	if (intel_wait_for_register_fw(uncore,
286				       SBI_CTL_STAT, SBI_BUSY, 0,
287				       100)) {
288		drm_err(&i915->drm,
289			"timeout waiting for SBI to become ready\n");
290		return -EBUSY;
291	}
292
293	intel_uncore_write_fw(uncore, SBI_ADDR, (u32)reg << 16);
294	intel_uncore_write_fw(uncore, SBI_DATA, is_read ? 0 : *val);
295
296	if (destination == SBI_ICLK)
297		cmd = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
298	else
299		cmd = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
300	if (!is_read)
301		cmd |= BIT(8);
302	intel_uncore_write_fw(uncore, SBI_CTL_STAT, cmd | SBI_BUSY);
303
304	if (__intel_wait_for_register_fw(uncore,
305					 SBI_CTL_STAT, SBI_BUSY, 0,
306					 100, 100, &cmd)) {
307		drm_err(&i915->drm,
308			"timeout waiting for SBI to complete read\n");
309		return -ETIMEDOUT;
310	}
311
312	if (cmd & SBI_RESPONSE_FAIL) {
313		drm_err(&i915->drm, "error during SBI read of reg %x\n", reg);
314		return -ENXIO;
315	}
316
317	if (is_read)
318		*val = intel_uncore_read_fw(uncore, SBI_DATA);
319
320	return 0;
321}
322
323u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
324		   enum intel_sbi_destination destination)
325{
326	u32 result = 0;
327
328	intel_sbi_rw(i915, reg, destination, &result, true);
329
330	return result;
331}
332
333void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
334		     enum intel_sbi_destination destination)
335{
336	intel_sbi_rw(i915, reg, destination, &value, false);
337}
338
339static int gen6_check_mailbox_status(u32 mbox)
340{
341	switch (mbox & GEN6_PCODE_ERROR_MASK) {
342	case GEN6_PCODE_SUCCESS:
343		return 0;
344	case GEN6_PCODE_UNIMPLEMENTED_CMD:
345		return -ENODEV;
346	case GEN6_PCODE_ILLEGAL_CMD:
347		return -ENXIO;
348	case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
349	case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
350		return -EOVERFLOW;
351	case GEN6_PCODE_TIMEOUT:
352		return -ETIMEDOUT;
353	default:
354		MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
355		return 0;
356	}
357}
358
359static int gen7_check_mailbox_status(u32 mbox)
360{
361	switch (mbox & GEN6_PCODE_ERROR_MASK) {
362	case GEN6_PCODE_SUCCESS:
363		return 0;
364	case GEN6_PCODE_ILLEGAL_CMD:
365		return -ENXIO;
366	case GEN7_PCODE_TIMEOUT:
367		return -ETIMEDOUT;
368	case GEN7_PCODE_ILLEGAL_DATA:
369		return -EINVAL;
370	case GEN11_PCODE_ILLEGAL_SUBCOMMAND:
371		return -ENXIO;
372	case GEN11_PCODE_LOCKED:
373		return -EBUSY;
374	case GEN11_PCODE_REJECTED:
375		return -EACCES;
376	case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
377		return -EOVERFLOW;
378	default:
379		MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
380		return 0;
381	}
382}
383
384static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
385				  u32 mbox, u32 *val, u32 *val1,
386				  int fast_timeout_us,
387				  int slow_timeout_ms,
388				  bool is_read)
389{
390	struct intel_uncore *uncore = &i915->uncore;
391
392	lockdep_assert_held(&i915->sb_lock);
393
394	/*
395	 * GEN6_PCODE_* are outside of the forcewake domain, we can
396	 * use te fw I915_READ variants to reduce the amount of work
397	 * required when reading/writing.
398	 */
399
400	if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
401		return -EAGAIN;
402
403	intel_uncore_write_fw(uncore, GEN6_PCODE_DATA, *val);
404	intel_uncore_write_fw(uncore, GEN6_PCODE_DATA1, val1 ? *val1 : 0);
405	intel_uncore_write_fw(uncore,
406			      GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
407
408	if (__intel_wait_for_register_fw(uncore,
409					 GEN6_PCODE_MAILBOX,
410					 GEN6_PCODE_READY, 0,
411					 fast_timeout_us,
412					 slow_timeout_ms,
413					 &mbox))
414		return -ETIMEDOUT;
415
416	if (is_read)
417		*val = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA);
418	if (is_read && val1)
419		*val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
420
421	if (INTEL_GEN(i915) > 6)
422		return gen7_check_mailbox_status(mbox);
423	else
424		return gen6_check_mailbox_status(mbox);
425}
426
427int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
428			   u32 *val, u32 *val1)
429{
430	int err;
431
432	mutex_lock(&i915->sb_lock);
433	err = __sandybridge_pcode_rw(i915, mbox, val, val1,
434				     500, 20,
435				     true);
436	mutex_unlock(&i915->sb_lock);
437
438	if (err) {
439		drm_dbg(&i915->drm,
440			"warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
441			mbox, __builtin_return_address(0), err);
442	}
443
444	return err;
445}
446
447int sandybridge_pcode_write_timeout(struct drm_i915_private *i915,
448				    u32 mbox, u32 val,
449				    int fast_timeout_us,
450				    int slow_timeout_ms)
451{
452	int err;
453
454	mutex_lock(&i915->sb_lock);
455	err = __sandybridge_pcode_rw(i915, mbox, &val, NULL,
456				     fast_timeout_us, slow_timeout_ms,
457				     false);
458	mutex_unlock(&i915->sb_lock);
459
460	if (err) {
461		drm_dbg(&i915->drm,
462			"warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
463			val, mbox, __builtin_return_address(0), err);
464	}
465
466	return err;
467}
468
469static bool skl_pcode_try_request(struct drm_i915_private *i915, u32 mbox,
470				  u32 request, u32 reply_mask, u32 reply,
471				  u32 *status)
472{
473	*status = __sandybridge_pcode_rw(i915, mbox, &request, NULL,
474					 500, 0,
475					 true);
476
477	return *status || ((request & reply_mask) == reply);
478}
479
480/**
481 * skl_pcode_request - send PCODE request until acknowledgment
482 * @i915: device private
483 * @mbox: PCODE mailbox ID the request is targeted for
484 * @request: request ID
485 * @reply_mask: mask used to check for request acknowledgment
486 * @reply: value used to check for request acknowledgment
487 * @timeout_base_ms: timeout for polling with preemption enabled
488 *
489 * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
490 * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
491 * The request is acknowledged once the PCODE reply dword equals @reply after
492 * applying @reply_mask. Polling is first attempted with preemption enabled
493 * for @timeout_base_ms and if this times out for another 50 ms with
494 * preemption disabled.
495 *
496 * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
497 * other error as reported by PCODE.
498 */
499int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
500		      u32 reply_mask, u32 reply, int timeout_base_ms)
501{
502	u32 status;
503	int ret;
504
505	mutex_lock(&i915->sb_lock);
506
507#define COND \
508	skl_pcode_try_request(i915, mbox, request, reply_mask, reply, &status)
509
510	/*
511	 * Prime the PCODE by doing a request first. Normally it guarantees
512	 * that a subsequent request, at most @timeout_base_ms later, succeeds.
513	 * _wait_for() doesn't guarantee when its passed condition is evaluated
514	 * first, so send the first request explicitly.
515	 */
516	if (COND) {
517		ret = 0;
518		goto out;
519	}
520	ret = _wait_for(COND, timeout_base_ms * 1000, 10, 10);
521	if (!ret)
522		goto out;
523
524	/*
525	 * The above can time out if the number of requests was low (2 in the
526	 * worst case) _and_ PCODE was busy for some reason even after a
527	 * (queued) request and @timeout_base_ms delay. As a workaround retry
528	 * the poll with preemption disabled to maximize the number of
529	 * requests. Increase the timeout from @timeout_base_ms to 50ms to
530	 * account for interrupts that could reduce the number of these
531	 * requests, and for any quirks of the PCODE firmware that delays
532	 * the request completion.
533	 */
534	drm_dbg_kms(&i915->drm,
535		    "PCODE timeout, retrying with preemption disabled\n");
536	drm_WARN_ON_ONCE(&i915->drm, timeout_base_ms > 3);
537	preempt_disable();
538	ret = wait_for_atomic(COND, 50);
539	preempt_enable();
540
541out:
542	mutex_unlock(&i915->sb_lock);
543	return ret ? ret : status;
544#undef COND
545}