1/*
  2 * SPDX-License-Identifier: MIT
  3 *
  4 * Copyright © 2017-2018 Intel Corporation
  5 */
  6
  7#ifndef __I915_PMU_H__
  8#define __I915_PMU_H__
  9
 10#include <linux/hrtimer.h>
 11#include <linux/perf_event.h>
 12#include <linux/spinlock_types.h>
 13#include <uapi/drm/i915_drm.h>
 14
 15struct drm_i915_private;
 16
 17enum {
 18	__I915_SAMPLE_FREQ_ACT = 0,
 19	__I915_SAMPLE_FREQ_REQ,
 20	__I915_SAMPLE_RC6,
 21	__I915_SAMPLE_RC6_LAST_REPORTED,
 22	__I915_NUM_PMU_SAMPLERS
 23};
 24
 25/**
 26 * How many different events we track in the global PMU mask.
 27 *
 28 * It is also used to know to needed number of event reference counters.
 29 */
 30#define I915_PMU_MASK_BITS \
 31	((1 << I915_PMU_SAMPLE_BITS) + \
 32	 (I915_PMU_LAST + 1 - __I915_PMU_OTHER(0)))
 33
 34#define I915_ENGINE_SAMPLE_COUNT (I915_SAMPLE_SEMA + 1)
 35
 36struct i915_pmu_sample {
 37	u64 cur;
 38};
 39
 40struct i915_pmu {
 41	/**
 42	 * @cpuhp: Struct used for CPU hotplug handling.
 43	 */
 44	struct {
 45		struct hlist_node node;
 46		enum cpuhp_state slot;
 47	} cpuhp;
 48	/**
 49	 * @base: PMU base.
 50	 */
 51	struct pmu base;
 52	/**
 53	 * @name: Name as registered with perf core.
 54	 */
 55	const char *name;
 56	/**
 57	 * @lock: Lock protecting enable mask and ref count handling.
 58	 */
 59	spinlock_t lock;
 60	/**
 61	 * @timer: Timer for internal i915 PMU sampling.
 62	 */
 63	struct hrtimer timer;
 64	/**
 65	 * @enable: Bitmask of all currently enabled events.
 66	 *
 67	 * Bits are derived from uAPI event numbers in a way that low 16 bits
 68	 * correspond to engine event _sample_ _type_ (I915_SAMPLE_QUEUED is
 69	 * bit 0), and higher bits correspond to other events (for instance
 70	 * I915_PMU_ACTUAL_FREQUENCY is bit 16 etc).
 71	 *
 72	 * In other words, low 16 bits are not per engine but per engine
 73	 * sampler type, while the upper bits are directly mapped to other
 74	 * event types.
 75	 */
 76	u64 enable;
 77
 78	/**
 79	 * @timer_last:
 80	 *
 81	 * Timestmap of the previous timer invocation.
 82	 */
 83	ktime_t timer_last;
 84
 85	/**
 86	 * @enable_count: Reference counts for the enabled events.
 87	 *
 88	 * Array indices are mapped in the same way as bits in the @enable field
 89	 * and they are used to control sampling on/off when multiple clients
 90	 * are using the PMU API.
 91	 */
 92	unsigned int enable_count[I915_PMU_MASK_BITS];
 93	/**
 94	 * @timer_enabled: Should the internal sampling timer be running.
 95	 */
 96	bool timer_enabled;
 97	/**
 98	 * @sample: Current and previous (raw) counters for sampling events.
 99	 *
100	 * These counters are updated from the i915 PMU sampling timer.
101	 *
102	 * Only global counters are held here, while the per-engine ones are in
103	 * struct intel_engine_cs.
104	 */
105	struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS];
106	/**
107	 * @sleep_last: Last time GT parked for RC6 estimation.
108	 */
109	ktime_t sleep_last;
110	/**
111	 * @events_attr_group: Device events attribute group.
112	 */
113	struct attribute_group events_attr_group;
114	/**
115	 * @i915_attr: Memory block holding device attributes.
116	 */
117	void *i915_attr;
118	/**
119	 * @pmu_attr: Memory block holding device attributes.
120	 */
121	void *pmu_attr;
122};
123
124#ifdef CONFIG_PERF_EVENTS
125void i915_pmu_register(struct drm_i915_private *i915);
126void i915_pmu_unregister(struct drm_i915_private *i915);
127void i915_pmu_gt_parked(struct drm_i915_private *i915);
128void i915_pmu_gt_unparked(struct drm_i915_private *i915);
129#else
130static inline void i915_pmu_register(struct drm_i915_private *i915) {}
131static inline void i915_pmu_unregister(struct drm_i915_private *i915) {}
132static inline void i915_pmu_gt_parked(struct drm_i915_private *i915) {}
133static inline void i915_pmu_gt_unparked(struct drm_i915_private *i915) {}
134#endif
135
136#endif