1/*
 2 * SPDX-License-Identifier: MIT
 3 *
 4 * Copyright © 2014-2018 Intel Corporation
 5 */
 6
 7#ifndef _INTEL_LRC_REG_H_
 8#define _INTEL_LRC_REG_H_
 9
10#include <linux/types.h>
11
12/* GEN8 to GEN12 Reg State Context */
13#define CTX_CONTEXT_CONTROL		(0x02 + 1)
14#define CTX_RING_HEAD			(0x04 + 1)
15#define CTX_RING_TAIL			(0x06 + 1)
16#define CTX_RING_START			(0x08 + 1)
17#define CTX_RING_CTL			(0x0a + 1)
18#define CTX_BB_STATE			(0x10 + 1)
19#define CTX_TIMESTAMP			(0x22 + 1)
20#define CTX_PDP3_UDW			(0x24 + 1)
21#define CTX_PDP3_LDW			(0x26 + 1)
22#define CTX_PDP2_UDW			(0x28 + 1)
23#define CTX_PDP2_LDW			(0x2a + 1)
24#define CTX_PDP1_UDW			(0x2c + 1)
25#define CTX_PDP1_LDW			(0x2e + 1)
26#define CTX_PDP0_UDW			(0x30 + 1)
27#define CTX_PDP0_LDW			(0x32 + 1)
28#define CTX_R_PWR_CLK_STATE		(0x42 + 1)
29
30#define GEN9_CTX_RING_MI_MODE		0x54
31
32#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
33	u32 *reg_state__ = (reg_state); \
34	const u64 addr__ = i915_page_dir_dma_addr((ppgtt), (n)); \
35	(reg_state__)[CTX_PDP ## n ## _UDW] = upper_32_bits(addr__); \
36	(reg_state__)[CTX_PDP ## n ## _LDW] = lower_32_bits(addr__); \
37} while (0)
38
39#define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
40	u32 *reg_state__ = (reg_state); \
41	const u64 addr__ = px_dma(ppgtt->pd); \
42	(reg_state__)[CTX_PDP0_UDW] = upper_32_bits(addr__); \
43	(reg_state__)[CTX_PDP0_LDW] = lower_32_bits(addr__); \
44} while (0)
45
46#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x17
47#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x26
48#define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x19
49#define GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x1A
50#define GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0xD
51
52#endif /* _INTEL_LRC_REG_H_ */