1/*
  2 * Copyright © 2014 Intel Corporation
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice (including the next
 12 * paragraph) shall be included in all copies or substantial portions of the
 13 * Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 21 * DEALINGS IN THE SOFTWARE.
 22 */
 23
 24#ifndef _INTEL_LRC_H_
 25#define _INTEL_LRC_H_
 26
 27#include <linux/types.h>
 28
 29struct drm_printer;
 30
 31struct drm_i915_private;
 32struct i915_gem_context;
 33struct i915_request;
 34struct intel_context;
 35struct intel_engine_cs;
 36
 37/* Execlists regs */
 38#define RING_ELSP(base)				_MMIO((base) + 0x230)
 39#define RING_EXECLIST_STATUS_LO(base)		_MMIO((base) + 0x234)
 40#define RING_EXECLIST_STATUS_HI(base)		_MMIO((base) + 0x234 + 4)
 41#define RING_CONTEXT_CONTROL(base)		_MMIO((base) + 0x244)
 42#define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	(1 << 3)
 43#define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)
 44#define   CTX_CTRL_RS_CTX_ENABLE		(1 << 1)
 45#define	  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT	(1 << 2)
 46#define	  GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE	(1 << 8)
 47#define RING_CONTEXT_STATUS_PTR(base)		_MMIO((base) + 0x3a0)
 48#define RING_EXECLIST_SQ_CONTENTS(base)		_MMIO((base) + 0x510)
 49#define RING_EXECLIST_CONTROL(base)		_MMIO((base) + 0x550)
 50
 51#define	  EL_CTRL_LOAD				(1 << 0)
 52
 53/* The docs specify that the write pointer wraps around after 5h, "After status
 54 * is written out to the last available status QW at offset 5h, this pointer
 55 * wraps to 0."
 56 *
 57 * Therefore, one must infer than even though there are 3 bits available, 6 and
 58 * 7 appear to be * reserved.
 59 */
 60#define GEN8_CSB_ENTRIES 6
 61#define GEN8_CSB_PTR_MASK 0x7
 62#define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
 63#define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
 64
 65#define GEN11_CSB_ENTRIES 12
 66#define GEN11_CSB_PTR_MASK 0xf
 67#define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8)
 68#define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0)
 69
 70#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
 71#define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
 72#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
 73/* in Gen12 ID 0x7FF is reserved to indicate idle */
 74#define GEN12_MAX_CONTEXT_HW_ID	(GEN11_MAX_CONTEXT_HW_ID - 1)
 75
 76enum {
 77	INTEL_CONTEXT_SCHEDULE_IN = 0,
 78	INTEL_CONTEXT_SCHEDULE_OUT,
 79	INTEL_CONTEXT_SCHEDULE_PREEMPTED,
 80};
 81
 82/* Logical Rings */
 83void intel_logical_ring_cleanup(struct intel_engine_cs *engine);
 84
 85int intel_execlists_submission_setup(struct intel_engine_cs *engine);
 86
 87/* Logical Ring Contexts */
 88/* At the start of the context image is its per-process HWS page */
 89#define LRC_PPHWSP_PN	(0)
 90#define LRC_PPHWSP_SZ	(1)
 91/* After the PPHWSP we have the logical state for the context */
 92#define LRC_STATE_PN	(LRC_PPHWSP_PN + LRC_PPHWSP_SZ)
 93#define LRC_STATE_OFFSET (LRC_STATE_PN * PAGE_SIZE)
 94
 95/* Space within PPHWSP reserved to be used as scratch */
 96#define LRC_PPHWSP_SCRATCH		0x34
 97#define LRC_PPHWSP_SCRATCH_ADDR		(LRC_PPHWSP_SCRATCH * sizeof(u32))
 98
 99void intel_execlists_set_default_submission(struct intel_engine_cs *engine);
100
101void intel_lr_context_reset(struct intel_engine_cs *engine,
102			    struct intel_context *ce,
103			    u32 head,
104			    bool scrub);
105
106void intel_execlists_show_requests(struct intel_engine_cs *engine,
107				   struct drm_printer *m,
108				   void (*show_request)(struct drm_printer *m,
109							struct i915_request *rq,
110							const char *prefix),
111				   unsigned int max);
112
113struct intel_context *
114intel_execlists_create_virtual(struct intel_engine_cs **siblings,
115			       unsigned int count);
116
117struct intel_context *
118intel_execlists_clone_virtual(struct intel_engine_cs *src);
119
120int intel_virtual_engine_attach_bond(struct intel_engine_cs *engine,
121				     const struct intel_engine_cs *master,
122				     const struct intel_engine_cs *sibling);
123
124struct intel_engine_cs *
125intel_virtual_engine_get_sibling(struct intel_engine_cs *engine,
126				 unsigned int sibling);
127
128bool
129intel_engine_in_execlists_submission_mode(const struct intel_engine_cs *engine);
130
131#endif /* _INTEL_LRC_H_ */