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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * MIPI Display Bus Interface (DBI) LCD controller support
4 *
5 * Copyright 2016 Noralf Trønnes
6 */
7
8#include <linux/debugfs.h>
9#include <linux/delay.h>
10#include <linux/dma-buf.h>
11#include <linux/gpio/consumer.h>
12#include <linux/module.h>
13#include <linux/regulator/consumer.h>
14#include <linux/spi/spi.h>
15
16#include <drm/drm_connector.h>
17#include <drm/drm_damage_helper.h>
18#include <drm/drm_drv.h>
19#include <drm/drm_gem_cma_helper.h>
20#include <drm/drm_format_helper.h>
21#include <drm/drm_fourcc.h>
22#include <drm/drm_gem_framebuffer_helper.h>
23#include <drm/drm_mipi_dbi.h>
24#include <drm/drm_modes.h>
25#include <drm/drm_probe_helper.h>
26#include <drm/drm_rect.h>
27#include <video/mipi_display.h>
28
29#define MIPI_DBI_MAX_SPI_READ_SPEED 2000000 /* 2MHz */
30
31#define DCS_POWER_MODE_DISPLAY BIT(2)
32#define DCS_POWER_MODE_DISPLAY_NORMAL_MODE BIT(3)
33#define DCS_POWER_MODE_SLEEP_MODE BIT(4)
34#define DCS_POWER_MODE_PARTIAL_MODE BIT(5)
35#define DCS_POWER_MODE_IDLE_MODE BIT(6)
36#define DCS_POWER_MODE_RESERVED_MASK (BIT(0) | BIT(1) | BIT(7))
37
38/**
39 * DOC: overview
40 *
41 * This library provides helpers for MIPI Display Bus Interface (DBI)
42 * compatible display controllers.
43 *
44 * Many controllers for tiny lcd displays are MIPI compliant and can use this
45 * library. If a controller uses registers 0x2A and 0x2B to set the area to
46 * update and uses register 0x2C to write to frame memory, it is most likely
47 * MIPI compliant.
48 *
49 * Only MIPI Type 1 displays are supported since a full frame memory is needed.
50 *
51 * There are 3 MIPI DBI implementation types:
52 *
53 * A. Motorola 6800 type parallel bus
54 *
55 * B. Intel 8080 type parallel bus
56 *
57 * C. SPI type with 3 options:
58 *
59 * 1. 9-bit with the Data/Command signal as the ninth bit
60 * 2. Same as above except it's sent as 16 bits
61 * 3. 8-bit with the Data/Command signal as a separate D/CX pin
62 *
63 * Currently mipi_dbi only supports Type C options 1 and 3 with
64 * mipi_dbi_spi_init().
65 */
66
67#define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \
68({ \
69 if (!len) \
70 DRM_DEBUG_DRIVER("cmd=%02x\n", cmd); \
71 else if (len <= 32) \
72 DRM_DEBUG_DRIVER("cmd=%02x, par=%*ph\n", cmd, (int)len, data);\
73 else \
74 DRM_DEBUG_DRIVER("cmd=%02x, len=%zu\n", cmd, len); \
75})
76
77static const u8 mipi_dbi_dcs_read_commands[] = {
78 MIPI_DCS_GET_DISPLAY_ID,
79 MIPI_DCS_GET_RED_CHANNEL,
80 MIPI_DCS_GET_GREEN_CHANNEL,
81 MIPI_DCS_GET_BLUE_CHANNEL,
82 MIPI_DCS_GET_DISPLAY_STATUS,
83 MIPI_DCS_GET_POWER_MODE,
84 MIPI_DCS_GET_ADDRESS_MODE,
85 MIPI_DCS_GET_PIXEL_FORMAT,
86 MIPI_DCS_GET_DISPLAY_MODE,
87 MIPI_DCS_GET_SIGNAL_MODE,
88 MIPI_DCS_GET_DIAGNOSTIC_RESULT,
89 MIPI_DCS_READ_MEMORY_START,
90 MIPI_DCS_READ_MEMORY_CONTINUE,
91 MIPI_DCS_GET_SCANLINE,
92 MIPI_DCS_GET_DISPLAY_BRIGHTNESS,
93 MIPI_DCS_GET_CONTROL_DISPLAY,
94 MIPI_DCS_GET_POWER_SAVE,
95 MIPI_DCS_GET_CABC_MIN_BRIGHTNESS,
96 MIPI_DCS_READ_DDB_START,
97 MIPI_DCS_READ_DDB_CONTINUE,
98 0, /* sentinel */
99};
100
101static bool mipi_dbi_command_is_read(struct mipi_dbi *dbi, u8 cmd)
102{
103 unsigned int i;
104
105 if (!dbi->read_commands)
106 return false;
107
108 for (i = 0; i < 0xff; i++) {
109 if (!dbi->read_commands[i])
110 return false;
111 if (cmd == dbi->read_commands[i])
112 return true;
113 }
114
115 return false;
116}
117
118/**
119 * mipi_dbi_command_read - MIPI DCS read command
120 * @dbi: MIPI DBI structure
121 * @cmd: Command
122 * @val: Value read
123 *
124 * Send MIPI DCS read command to the controller.
125 *
126 * Returns:
127 * Zero on success, negative error code on failure.
128 */
129int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val)
130{
131 if (!dbi->read_commands)
132 return -EACCES;
133
134 if (!mipi_dbi_command_is_read(dbi, cmd))
135 return -EINVAL;
136
137 return mipi_dbi_command_buf(dbi, cmd, val, 1);
138}
139EXPORT_SYMBOL(mipi_dbi_command_read);
140
141/**
142 * mipi_dbi_command_buf - MIPI DCS command with parameter(s) in an array
143 * @dbi: MIPI DBI structure
144 * @cmd: Command
145 * @data: Parameter buffer
146 * @len: Buffer length
147 *
148 * Returns:
149 * Zero on success, negative error code on failure.
150 */
151int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len)
152{
153 u8 *cmdbuf;
154 int ret;
155
156 /* SPI requires dma-safe buffers */
157 cmdbuf = kmemdup(&cmd, 1, GFP_KERNEL);
158 if (!cmdbuf)
159 return -ENOMEM;
160
161 mutex_lock(&dbi->cmdlock);
162 ret = dbi->command(dbi, cmdbuf, data, len);
163 mutex_unlock(&dbi->cmdlock);
164
165 kfree(cmdbuf);
166
167 return ret;
168}
169EXPORT_SYMBOL(mipi_dbi_command_buf);
170
171/* This should only be used by mipi_dbi_command() */
172int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, const u8 *data,
173 size_t len)
174{
175 u8 *buf;
176 int ret;
177
178 buf = kmemdup(data, len, GFP_KERNEL);
179 if (!buf)
180 return -ENOMEM;
181
182 ret = mipi_dbi_command_buf(dbi, cmd, buf, len);
183
184 kfree(buf);
185
186 return ret;
187}
188EXPORT_SYMBOL(mipi_dbi_command_stackbuf);
189
190/**
191 * mipi_dbi_buf_copy - Copy a framebuffer, transforming it if necessary
192 * @dst: The destination buffer
193 * @fb: The source framebuffer
194 * @clip: Clipping rectangle of the area to be copied
195 * @swap: When true, swap MSB/LSB of 16-bit values
196 *
197 * Returns:
198 * Zero on success, negative error code on failure.
199 */
200int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb,
201 struct drm_rect *clip, bool swap)
202{
203 struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0);
204 struct drm_gem_cma_object *cma_obj = to_drm_gem_cma_obj(gem);
205 struct dma_buf_attachment *import_attach = gem->import_attach;
206 struct drm_format_name_buf format_name;
207 void *src = cma_obj->vaddr;
208 int ret = 0;
209
210 if (import_attach) {
211 ret = dma_buf_begin_cpu_access(import_attach->dmabuf,
212 DMA_FROM_DEVICE);
213 if (ret)
214 return ret;
215 }
216
217 switch (fb->format->format) {
218 case DRM_FORMAT_RGB565:
219 if (swap)
220 drm_fb_swab(dst, src, fb, clip, !import_attach);
221 else
222 drm_fb_memcpy(dst, src, fb, clip);
223 break;
224 case DRM_FORMAT_XRGB8888:
225 drm_fb_xrgb8888_to_rgb565(dst, src, fb, clip, swap);
226 break;
227 default:
228 drm_err_once(fb->dev, "Format is not supported: %s\n",
229 drm_get_format_name(fb->format->format, &format_name));
230 return -EINVAL;
231 }
232
233 if (import_attach)
234 ret = dma_buf_end_cpu_access(import_attach->dmabuf,
235 DMA_FROM_DEVICE);
236 return ret;
237}
238EXPORT_SYMBOL(mipi_dbi_buf_copy);
239
240static void mipi_dbi_set_window_address(struct mipi_dbi_dev *dbidev,
241 unsigned int xs, unsigned int xe,
242 unsigned int ys, unsigned int ye)
243{
244 struct mipi_dbi *dbi = &dbidev->dbi;
245
246 xs += dbidev->left_offset;
247 xe += dbidev->left_offset;
248 ys += dbidev->top_offset;
249 ye += dbidev->top_offset;
250
251 mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, (xs >> 8) & 0xff,
252 xs & 0xff, (xe >> 8) & 0xff, xe & 0xff);
253 mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, (ys >> 8) & 0xff,
254 ys & 0xff, (ye >> 8) & 0xff, ye & 0xff);
255}
256
257static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect)
258{
259 struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0);
260 struct drm_gem_cma_object *cma_obj = to_drm_gem_cma_obj(gem);
261 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev);
262 unsigned int height = rect->y2 - rect->y1;
263 unsigned int width = rect->x2 - rect->x1;
264 struct mipi_dbi *dbi = &dbidev->dbi;
265 bool swap = dbi->swap_bytes;
266 int idx, ret = 0;
267 bool full;
268 void *tr;
269
270 if (WARN_ON(!fb))
271 return;
272
273 if (!drm_dev_enter(fb->dev, &idx))
274 return;
275
276 full = width == fb->width && height == fb->height;
277
278 DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect));
279
280 if (!dbi->dc || !full || swap ||
281 fb->format->format == DRM_FORMAT_XRGB8888) {
282 tr = dbidev->tx_buf;
283 ret = mipi_dbi_buf_copy(dbidev->tx_buf, fb, rect, swap);
284 if (ret)
285 goto err_msg;
286 } else {
287 tr = cma_obj->vaddr;
288 }
289
290 mipi_dbi_set_window_address(dbidev, rect->x1, rect->x2 - 1, rect->y1,
291 rect->y2 - 1);
292
293 ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr,
294 width * height * 2);
295err_msg:
296 if (ret)
297 drm_err_once(fb->dev, "Failed to update display %d\n", ret);
298
299 drm_dev_exit(idx);
300}
301
302/**
303 * mipi_dbi_pipe_update - Display pipe update helper
304 * @pipe: Simple display pipe
305 * @old_state: Old plane state
306 *
307 * This function handles framebuffer flushing and vblank events. Drivers can use
308 * this as their &drm_simple_display_pipe_funcs->update callback.
309 */
310void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe,
311 struct drm_plane_state *old_state)
312{
313 struct drm_plane_state *state = pipe->plane.state;
314 struct drm_rect rect;
315
316 if (!pipe->crtc.state->active)
317 return;
318
319 if (drm_atomic_helper_damage_merged(old_state, state, &rect))
320 mipi_dbi_fb_dirty(state->fb, &rect);
321}
322EXPORT_SYMBOL(mipi_dbi_pipe_update);
323
324/**
325 * mipi_dbi_enable_flush - MIPI DBI enable helper
326 * @dbidev: MIPI DBI device structure
327 * @crtc_state: CRTC state
328 * @plane_state: Plane state
329 *
330 * Flushes the whole framebuffer and enables the backlight. Drivers can use this
331 * in their &drm_simple_display_pipe_funcs->enable callback.
332 *
333 * Note: Drivers which don't use mipi_dbi_pipe_update() because they have custom
334 * framebuffer flushing, can't use this function since they both use the same
335 * flushing code.
336 */
337void mipi_dbi_enable_flush(struct mipi_dbi_dev *dbidev,
338 struct drm_crtc_state *crtc_state,
339 struct drm_plane_state *plane_state)
340{
341 struct drm_framebuffer *fb = plane_state->fb;
342 struct drm_rect rect = {
343 .x1 = 0,
344 .x2 = fb->width,
345 .y1 = 0,
346 .y2 = fb->height,
347 };
348 int idx;
349
350 if (!drm_dev_enter(&dbidev->drm, &idx))
351 return;
352
353 mipi_dbi_fb_dirty(fb, &rect);
354 backlight_enable(dbidev->backlight);
355
356 drm_dev_exit(idx);
357}
358EXPORT_SYMBOL(mipi_dbi_enable_flush);
359
360static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev)
361{
362 struct drm_device *drm = &dbidev->drm;
363 u16 height = drm->mode_config.min_height;
364 u16 width = drm->mode_config.min_width;
365 struct mipi_dbi *dbi = &dbidev->dbi;
366 size_t len = width * height * 2;
367 int idx;
368
369 if (!drm_dev_enter(drm, &idx))
370 return;
371
372 memset(dbidev->tx_buf, 0, len);
373
374 mipi_dbi_set_window_address(dbidev, 0, width - 1, 0, height - 1);
375 mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START,
376 (u8 *)dbidev->tx_buf, len);
377
378 drm_dev_exit(idx);
379}
380
381/**
382 * mipi_dbi_pipe_disable - MIPI DBI pipe disable helper
383 * @pipe: Display pipe
384 *
385 * This function disables backlight if present, if not the display memory is
386 * blanked. The regulator is disabled if in use. Drivers can use this as their
387 * &drm_simple_display_pipe_funcs->disable callback.
388 */
389void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe)
390{
391 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
392
393 DRM_DEBUG_KMS("\n");
394
395 if (dbidev->backlight)
396 backlight_disable(dbidev->backlight);
397 else
398 mipi_dbi_blank(dbidev);
399
400 if (dbidev->regulator)
401 regulator_disable(dbidev->regulator);
402}
403EXPORT_SYMBOL(mipi_dbi_pipe_disable);
404
405static int mipi_dbi_connector_get_modes(struct drm_connector *connector)
406{
407 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(connector->dev);
408 struct drm_display_mode *mode;
409
410 mode = drm_mode_duplicate(connector->dev, &dbidev->mode);
411 if (!mode) {
412 DRM_ERROR("Failed to duplicate mode\n");
413 return 0;
414 }
415
416 if (mode->name[0] == '\0')
417 drm_mode_set_name(mode);
418
419 mode->type |= DRM_MODE_TYPE_PREFERRED;
420 drm_mode_probed_add(connector, mode);
421
422 if (mode->width_mm) {
423 connector->display_info.width_mm = mode->width_mm;
424 connector->display_info.height_mm = mode->height_mm;
425 }
426
427 return 1;
428}
429
430static const struct drm_connector_helper_funcs mipi_dbi_connector_hfuncs = {
431 .get_modes = mipi_dbi_connector_get_modes,
432};
433
434static const struct drm_connector_funcs mipi_dbi_connector_funcs = {
435 .reset = drm_atomic_helper_connector_reset,
436 .fill_modes = drm_helper_probe_single_connector_modes,
437 .destroy = drm_connector_cleanup,
438 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
439 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
440};
441
442static int mipi_dbi_rotate_mode(struct drm_display_mode *mode,
443 unsigned int rotation)
444{
445 if (rotation == 0 || rotation == 180) {
446 return 0;
447 } else if (rotation == 90 || rotation == 270) {
448 swap(mode->hdisplay, mode->vdisplay);
449 swap(mode->hsync_start, mode->vsync_start);
450 swap(mode->hsync_end, mode->vsync_end);
451 swap(mode->htotal, mode->vtotal);
452 swap(mode->width_mm, mode->height_mm);
453 return 0;
454 } else {
455 return -EINVAL;
456 }
457}
458
459static const struct drm_mode_config_funcs mipi_dbi_mode_config_funcs = {
460 .fb_create = drm_gem_fb_create_with_dirty,
461 .atomic_check = drm_atomic_helper_check,
462 .atomic_commit = drm_atomic_helper_commit,
463};
464
465static const uint32_t mipi_dbi_formats[] = {
466 DRM_FORMAT_RGB565,
467 DRM_FORMAT_XRGB8888,
468};
469
470/**
471 * mipi_dbi_dev_init_with_formats - MIPI DBI device initialization with custom formats
472 * @dbidev: MIPI DBI device structure to initialize
473 * @funcs: Display pipe functions
474 * @formats: Array of supported formats (DRM_FORMAT\_\*).
475 * @format_count: Number of elements in @formats
476 * @mode: Display mode
477 * @rotation: Initial rotation in degrees Counter Clock Wise
478 * @tx_buf_size: Allocate a transmit buffer of this size.
479 *
480 * This function sets up a &drm_simple_display_pipe with a &drm_connector that
481 * has one fixed &drm_display_mode which is rotated according to @rotation.
482 * This mode is used to set the mode config min/max width/height properties.
483 *
484 * Use mipi_dbi_dev_init() if you don't need custom formats.
485 *
486 * Note:
487 * Some of the helper functions expects RGB565 to be the default format and the
488 * transmit buffer sized to fit that.
489 *
490 * Returns:
491 * Zero on success, negative error code on failure.
492 */
493int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev,
494 const struct drm_simple_display_pipe_funcs *funcs,
495 const uint32_t *formats, unsigned int format_count,
496 const struct drm_display_mode *mode,
497 unsigned int rotation, size_t tx_buf_size)
498{
499 static const uint64_t modifiers[] = {
500 DRM_FORMAT_MOD_LINEAR,
501 DRM_FORMAT_MOD_INVALID
502 };
503 struct drm_device *drm = &dbidev->drm;
504 int ret;
505
506 if (!dbidev->dbi.command)
507 return -EINVAL;
508
509 ret = drmm_mode_config_init(drm);
510 if (ret)
511 return ret;
512
513 dbidev->tx_buf = devm_kmalloc(drm->dev, tx_buf_size, GFP_KERNEL);
514 if (!dbidev->tx_buf)
515 return -ENOMEM;
516
517 drm_mode_copy(&dbidev->mode, mode);
518 ret = mipi_dbi_rotate_mode(&dbidev->mode, rotation);
519 if (ret) {
520 DRM_ERROR("Illegal rotation value %u\n", rotation);
521 return -EINVAL;
522 }
523
524 drm_connector_helper_add(&dbidev->connector, &mipi_dbi_connector_hfuncs);
525 ret = drm_connector_init(drm, &dbidev->connector, &mipi_dbi_connector_funcs,
526 DRM_MODE_CONNECTOR_SPI);
527 if (ret)
528 return ret;
529
530 ret = drm_simple_display_pipe_init(drm, &dbidev->pipe, funcs, formats, format_count,
531 modifiers, &dbidev->connector);
532 if (ret)
533 return ret;
534
535 drm_plane_enable_fb_damage_clips(&dbidev->pipe.plane);
536
537 drm->mode_config.funcs = &mipi_dbi_mode_config_funcs;
538 drm->mode_config.min_width = dbidev->mode.hdisplay;
539 drm->mode_config.max_width = dbidev->mode.hdisplay;
540 drm->mode_config.min_height = dbidev->mode.vdisplay;
541 drm->mode_config.max_height = dbidev->mode.vdisplay;
542 dbidev->rotation = rotation;
543
544 DRM_DEBUG_KMS("rotation = %u\n", rotation);
545
546 return 0;
547}
548EXPORT_SYMBOL(mipi_dbi_dev_init_with_formats);
549
550/**
551 * mipi_dbi_dev_init - MIPI DBI device initialization
552 * @dbidev: MIPI DBI device structure to initialize
553 * @funcs: Display pipe functions
554 * @mode: Display mode
555 * @rotation: Initial rotation in degrees Counter Clock Wise
556 *
557 * This function sets up a &drm_simple_display_pipe with a &drm_connector that
558 * has one fixed &drm_display_mode which is rotated according to @rotation.
559 * This mode is used to set the mode config min/max width/height properties.
560 * Additionally &mipi_dbi.tx_buf is allocated.
561 *
562 * Supported formats: Native RGB565 and emulated XRGB8888.
563 *
564 * Returns:
565 * Zero on success, negative error code on failure.
566 */
567int mipi_dbi_dev_init(struct mipi_dbi_dev *dbidev,
568 const struct drm_simple_display_pipe_funcs *funcs,
569 const struct drm_display_mode *mode, unsigned int rotation)
570{
571 size_t bufsize = mode->vdisplay * mode->hdisplay * sizeof(u16);
572
573 dbidev->drm.mode_config.preferred_depth = 16;
574
575 return mipi_dbi_dev_init_with_formats(dbidev, funcs, mipi_dbi_formats,
576 ARRAY_SIZE(mipi_dbi_formats), mode,
577 rotation, bufsize);
578}
579EXPORT_SYMBOL(mipi_dbi_dev_init);
580
581/**
582 * mipi_dbi_hw_reset - Hardware reset of controller
583 * @dbi: MIPI DBI structure
584 *
585 * Reset controller if the &mipi_dbi->reset gpio is set.
586 */
587void mipi_dbi_hw_reset(struct mipi_dbi *dbi)
588{
589 if (!dbi->reset)
590 return;
591
592 gpiod_set_value_cansleep(dbi->reset, 0);
593 usleep_range(20, 1000);
594 gpiod_set_value_cansleep(dbi->reset, 1);
595 msleep(120);
596}
597EXPORT_SYMBOL(mipi_dbi_hw_reset);
598
599/**
600 * mipi_dbi_display_is_on - Check if display is on
601 * @dbi: MIPI DBI structure
602 *
603 * This function checks the Power Mode register (if readable) to see if
604 * display output is turned on. This can be used to see if the bootloader
605 * has already turned on the display avoiding flicker when the pipeline is
606 * enabled.
607 *
608 * Returns:
609 * true if the display can be verified to be on, false otherwise.
610 */
611bool mipi_dbi_display_is_on(struct mipi_dbi *dbi)
612{
613 u8 val;
614
615 if (mipi_dbi_command_read(dbi, MIPI_DCS_GET_POWER_MODE, &val))
616 return false;
617
618 val &= ~DCS_POWER_MODE_RESERVED_MASK;
619
620 /* The poweron/reset value is 08h DCS_POWER_MODE_DISPLAY_NORMAL_MODE */
621 if (val != (DCS_POWER_MODE_DISPLAY |
622 DCS_POWER_MODE_DISPLAY_NORMAL_MODE | DCS_POWER_MODE_SLEEP_MODE))
623 return false;
624
625 DRM_DEBUG_DRIVER("Display is ON\n");
626
627 return true;
628}
629EXPORT_SYMBOL(mipi_dbi_display_is_on);
630
631static int mipi_dbi_poweron_reset_conditional(struct mipi_dbi_dev *dbidev, bool cond)
632{
633 struct device *dev = dbidev->drm.dev;
634 struct mipi_dbi *dbi = &dbidev->dbi;
635 int ret;
636
637 if (dbidev->regulator) {
638 ret = regulator_enable(dbidev->regulator);
639 if (ret) {
640 DRM_DEV_ERROR(dev, "Failed to enable regulator (%d)\n", ret);
641 return ret;
642 }
643 }
644
645 if (cond && mipi_dbi_display_is_on(dbi))
646 return 1;
647
648 mipi_dbi_hw_reset(dbi);
649 ret = mipi_dbi_command(dbi, MIPI_DCS_SOFT_RESET);
650 if (ret) {
651 DRM_DEV_ERROR(dev, "Failed to send reset command (%d)\n", ret);
652 if (dbidev->regulator)
653 regulator_disable(dbidev->regulator);
654 return ret;
655 }
656
657 /*
658 * If we did a hw reset, we know the controller is in Sleep mode and
659 * per MIPI DSC spec should wait 5ms after soft reset. If we didn't,
660 * we assume worst case and wait 120ms.
661 */
662 if (dbi->reset)
663 usleep_range(5000, 20000);
664 else
665 msleep(120);
666
667 return 0;
668}
669
670/**
671 * mipi_dbi_poweron_reset - MIPI DBI poweron and reset
672 * @dbidev: MIPI DBI device structure
673 *
674 * This function enables the regulator if used and does a hardware and software
675 * reset.
676 *
677 * Returns:
678 * Zero on success, or a negative error code.
679 */
680int mipi_dbi_poweron_reset(struct mipi_dbi_dev *dbidev)
681{
682 return mipi_dbi_poweron_reset_conditional(dbidev, false);
683}
684EXPORT_SYMBOL(mipi_dbi_poweron_reset);
685
686/**
687 * mipi_dbi_poweron_conditional_reset - MIPI DBI poweron and conditional reset
688 * @dbidev: MIPI DBI device structure
689 *
690 * This function enables the regulator if used and if the display is off, it
691 * does a hardware and software reset. If mipi_dbi_display_is_on() determines
692 * that the display is on, no reset is performed.
693 *
694 * Returns:
695 * Zero if the controller was reset, 1 if the display was already on, or a
696 * negative error code.
697 */
698int mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev *dbidev)
699{
700 return mipi_dbi_poweron_reset_conditional(dbidev, true);
701}
702EXPORT_SYMBOL(mipi_dbi_poweron_conditional_reset);
703
704#if IS_ENABLED(CONFIG_SPI)
705
706/**
707 * mipi_dbi_spi_cmd_max_speed - get the maximum SPI bus speed
708 * @spi: SPI device
709 * @len: The transfer buffer length.
710 *
711 * Many controllers have a max speed of 10MHz, but can be pushed way beyond
712 * that. Increase reliability by running pixel data at max speed and the rest
713 * at 10MHz, preventing transfer glitches from messing up the init settings.
714 */
715u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len)
716{
717 if (len > 64)
718 return 0; /* use default */
719
720 return min_t(u32, 10000000, spi->max_speed_hz);
721}
722EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed);
723
724static bool mipi_dbi_machine_little_endian(void)
725{
726#if defined(__LITTLE_ENDIAN)
727 return true;
728#else
729 return false;
730#endif
731}
732
733/*
734 * MIPI DBI Type C Option 1
735 *
736 * If the SPI controller doesn't have 9 bits per word support,
737 * use blocks of 9 bytes to send 8x 9-bit words using a 8-bit SPI transfer.
738 * Pad partial blocks with MIPI_DCS_NOP (zero).
739 * This is how the D/C bit (x) is added:
740 * x7654321
741 * 0x765432
742 * 10x76543
743 * 210x7654
744 * 3210x765
745 * 43210x76
746 * 543210x7
747 * 6543210x
748 * 76543210
749 */
750
751static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc,
752 const void *buf, size_t len,
753 unsigned int bpw)
754{
755 bool swap_bytes = (bpw == 16 && mipi_dbi_machine_little_endian());
756 size_t chunk, max_chunk = dbi->tx_buf9_len;
757 struct spi_device *spi = dbi->spi;
758 struct spi_transfer tr = {
759 .tx_buf = dbi->tx_buf9,
760 .bits_per_word = 8,
761 };
762 struct spi_message m;
763 const u8 *src = buf;
764 int i, ret;
765 u8 *dst;
766
767 if (drm_debug_enabled(DRM_UT_DRIVER))
768 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
769 __func__, dc, max_chunk);
770
771 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
772 spi_message_init_with_transfers(&m, &tr, 1);
773
774 if (!dc) {
775 if (WARN_ON_ONCE(len != 1))
776 return -EINVAL;
777
778 /* Command: pad no-op's (zeroes) at beginning of block */
779 dst = dbi->tx_buf9;
780 memset(dst, 0, 9);
781 dst[8] = *src;
782 tr.len = 9;
783
784 return spi_sync(spi, &m);
785 }
786
787 /* max with room for adding one bit per byte */
788 max_chunk = max_chunk / 9 * 8;
789 /* but no bigger than len */
790 max_chunk = min(max_chunk, len);
791 /* 8 byte blocks */
792 max_chunk = max_t(size_t, 8, max_chunk & ~0x7);
793
794 while (len) {
795 size_t added = 0;
796
797 chunk = min(len, max_chunk);
798 len -= chunk;
799 dst = dbi->tx_buf9;
800
801 if (chunk < 8) {
802 u8 val, carry = 0;
803
804 /* Data: pad no-op's (zeroes) at end of block */
805 memset(dst, 0, 9);
806
807 if (swap_bytes) {
808 for (i = 1; i < (chunk + 1); i++) {
809 val = src[1];
810 *dst++ = carry | BIT(8 - i) | (val >> i);
811 carry = val << (8 - i);
812 i++;
813 val = src[0];
814 *dst++ = carry | BIT(8 - i) | (val >> i);
815 carry = val << (8 - i);
816 src += 2;
817 }
818 *dst++ = carry;
819 } else {
820 for (i = 1; i < (chunk + 1); i++) {
821 val = *src++;
822 *dst++ = carry | BIT(8 - i) | (val >> i);
823 carry = val << (8 - i);
824 }
825 *dst++ = carry;
826 }
827
828 chunk = 8;
829 added = 1;
830 } else {
831 for (i = 0; i < chunk; i += 8) {
832 if (swap_bytes) {
833 *dst++ = BIT(7) | (src[1] >> 1);
834 *dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2);
835 *dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3);
836 *dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4);
837 *dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5);
838 *dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6);
839 *dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7);
840 *dst++ = (src[7] << 1) | BIT(0);
841 *dst++ = src[6];
842 } else {
843 *dst++ = BIT(7) | (src[0] >> 1);
844 *dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2);
845 *dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3);
846 *dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4);
847 *dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5);
848 *dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6);
849 *dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7);
850 *dst++ = (src[6] << 1) | BIT(0);
851 *dst++ = src[7];
852 }
853
854 src += 8;
855 added++;
856 }
857 }
858
859 tr.len = chunk + added;
860
861 ret = spi_sync(spi, &m);
862 if (ret)
863 return ret;
864 }
865
866 return 0;
867}
868
869static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc,
870 const void *buf, size_t len,
871 unsigned int bpw)
872{
873 struct spi_device *spi = dbi->spi;
874 struct spi_transfer tr = {
875 .bits_per_word = 9,
876 };
877 const u16 *src16 = buf;
878 const u8 *src8 = buf;
879 struct spi_message m;
880 size_t max_chunk;
881 u16 *dst16;
882 int ret;
883
884 if (!spi_is_bpw_supported(spi, 9))
885 return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw);
886
887 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
888 max_chunk = dbi->tx_buf9_len;
889 dst16 = dbi->tx_buf9;
890
891 if (drm_debug_enabled(DRM_UT_DRIVER))
892 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
893 __func__, dc, max_chunk);
894
895 max_chunk = min(max_chunk / 2, len);
896
897 spi_message_init_with_transfers(&m, &tr, 1);
898 tr.tx_buf = dst16;
899
900 while (len) {
901 size_t chunk = min(len, max_chunk);
902 unsigned int i;
903
904 if (bpw == 16 && mipi_dbi_machine_little_endian()) {
905 for (i = 0; i < (chunk * 2); i += 2) {
906 dst16[i] = *src16 >> 8;
907 dst16[i + 1] = *src16++ & 0xFF;
908 if (dc) {
909 dst16[i] |= 0x0100;
910 dst16[i + 1] |= 0x0100;
911 }
912 }
913 } else {
914 for (i = 0; i < chunk; i++) {
915 dst16[i] = *src8++;
916 if (dc)
917 dst16[i] |= 0x0100;
918 }
919 }
920
921 tr.len = chunk * 2;
922 len -= chunk;
923
924 ret = spi_sync(spi, &m);
925 if (ret)
926 return ret;
927 }
928
929 return 0;
930}
931
932static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd,
933 u8 *parameters, size_t num)
934{
935 unsigned int bpw = (*cmd == MIPI_DCS_WRITE_MEMORY_START) ? 16 : 8;
936 int ret;
937
938 if (mipi_dbi_command_is_read(dbi, *cmd))
939 return -EOPNOTSUPP;
940
941 MIPI_DBI_DEBUG_COMMAND(*cmd, parameters, num);
942
943 ret = mipi_dbi_spi1_transfer(dbi, 0, cmd, 1, 8);
944 if (ret || !num)
945 return ret;
946
947 return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw);
948}
949
950/* MIPI DBI Type C Option 3 */
951
952static int mipi_dbi_typec3_command_read(struct mipi_dbi *dbi, u8 *cmd,
953 u8 *data, size_t len)
954{
955 struct spi_device *spi = dbi->spi;
956 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED,
957 spi->max_speed_hz / 2);
958 struct spi_transfer tr[2] = {
959 {
960 .speed_hz = speed_hz,
961 .tx_buf = cmd,
962 .len = 1,
963 }, {
964 .speed_hz = speed_hz,
965 .len = len,
966 },
967 };
968 struct spi_message m;
969 u8 *buf;
970 int ret;
971
972 if (!len)
973 return -EINVAL;
974
975 /*
976 * Support non-standard 24-bit and 32-bit Nokia read commands which
977 * start with a dummy clock, so we need to read an extra byte.
978 */
979 if (*cmd == MIPI_DCS_GET_DISPLAY_ID ||
980 *cmd == MIPI_DCS_GET_DISPLAY_STATUS) {
981 if (!(len == 3 || len == 4))
982 return -EINVAL;
983
984 tr[1].len = len + 1;
985 }
986
987 buf = kmalloc(tr[1].len, GFP_KERNEL);
988 if (!buf)
989 return -ENOMEM;
990
991 tr[1].rx_buf = buf;
992 gpiod_set_value_cansleep(dbi->dc, 0);
993
994 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr));
995 ret = spi_sync(spi, &m);
996 if (ret)
997 goto err_free;
998
999 if (tr[1].len == len) {
1000 memcpy(data, buf, len);
1001 } else {
1002 unsigned int i;
1003
1004 for (i = 0; i < len; i++)
1005 data[i] = (buf[i] << 1) | (buf[i + 1] >> 7);
1006 }
1007
1008 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len);
1009
1010err_free:
1011 kfree(buf);
1012
1013 return ret;
1014}
1015
1016static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd,
1017 u8 *par, size_t num)
1018{
1019 struct spi_device *spi = dbi->spi;
1020 unsigned int bpw = 8;
1021 u32 speed_hz;
1022 int ret;
1023
1024 if (mipi_dbi_command_is_read(dbi, *cmd))
1025 return mipi_dbi_typec3_command_read(dbi, cmd, par, num);
1026
1027 MIPI_DBI_DEBUG_COMMAND(*cmd, par, num);
1028
1029 gpiod_set_value_cansleep(dbi->dc, 0);
1030 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1);
1031 ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, cmd, 1);
1032 if (ret || !num)
1033 return ret;
1034
1035 if (*cmd == MIPI_DCS_WRITE_MEMORY_START && !dbi->swap_bytes)
1036 bpw = 16;
1037
1038 gpiod_set_value_cansleep(dbi->dc, 1);
1039 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num);
1040
1041 return mipi_dbi_spi_transfer(spi, speed_hz, bpw, par, num);
1042}
1043
1044/**
1045 * mipi_dbi_spi_init - Initialize MIPI DBI SPI interface
1046 * @spi: SPI device
1047 * @dbi: MIPI DBI structure to initialize
1048 * @dc: D/C gpio (optional)
1049 *
1050 * This function sets &mipi_dbi->command, enables &mipi_dbi->read_commands for the
1051 * usual read commands. It should be followed by a call to mipi_dbi_dev_init() or
1052 * a driver-specific init.
1053 *
1054 * If @dc is set, a Type C Option 3 interface is assumed, if not
1055 * Type C Option 1.
1056 *
1057 * If the SPI master driver doesn't support the necessary bits per word,
1058 * the following transformation is used:
1059 *
1060 * - 9-bit: reorder buffer as 9x 8-bit words, padded with no-op command.
1061 * - 16-bit: if big endian send as 8-bit, if little endian swap bytes
1062 *
1063 * Returns:
1064 * Zero on success, negative error code on failure.
1065 */
1066int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi,
1067 struct gpio_desc *dc)
1068{
1069 struct device *dev = &spi->dev;
1070 int ret;
1071
1072 /*
1073 * Even though it's not the SPI device that does DMA (the master does),
1074 * the dma mask is necessary for the dma_alloc_wc() in
1075 * drm_gem_cma_create(). The dma_addr returned will be a physical
1076 * address which might be different from the bus address, but this is
1077 * not a problem since the address will not be used.
1078 * The virtual address is used in the transfer and the SPI core
1079 * re-maps it on the SPI master device using the DMA streaming API
1080 * (spi_map_buf()).
1081 */
1082 if (!dev->coherent_dma_mask) {
1083 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
1084 if (ret) {
1085 dev_warn(dev, "Failed to set dma mask %d\n", ret);
1086 return ret;
1087 }
1088 }
1089
1090 dbi->spi = spi;
1091 dbi->read_commands = mipi_dbi_dcs_read_commands;
1092
1093 if (dc) {
1094 dbi->command = mipi_dbi_typec3_command;
1095 dbi->dc = dc;
1096 if (mipi_dbi_machine_little_endian() && !spi_is_bpw_supported(spi, 16))
1097 dbi->swap_bytes = true;
1098 } else {
1099 dbi->command = mipi_dbi_typec1_command;
1100 dbi->tx_buf9_len = SZ_16K;
1101 dbi->tx_buf9 = devm_kmalloc(dev, dbi->tx_buf9_len, GFP_KERNEL);
1102 if (!dbi->tx_buf9)
1103 return -ENOMEM;
1104 }
1105
1106 mutex_init(&dbi->cmdlock);
1107
1108 DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000);
1109
1110 return 0;
1111}
1112EXPORT_SYMBOL(mipi_dbi_spi_init);
1113
1114/**
1115 * mipi_dbi_spi_transfer - SPI transfer helper
1116 * @spi: SPI device
1117 * @speed_hz: Override speed (optional)
1118 * @bpw: Bits per word
1119 * @buf: Buffer to transfer
1120 * @len: Buffer length
1121 *
1122 * This SPI transfer helper breaks up the transfer of @buf into chunks which
1123 * the SPI controller driver can handle.
1124 *
1125 * Returns:
1126 * Zero on success, negative error code on failure.
1127 */
1128int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz,
1129 u8 bpw, const void *buf, size_t len)
1130{
1131 size_t max_chunk = spi_max_transfer_size(spi);
1132 struct spi_transfer tr = {
1133 .bits_per_word = bpw,
1134 .speed_hz = speed_hz,
1135 };
1136 struct spi_message m;
1137 size_t chunk;
1138 int ret;
1139
1140 spi_message_init_with_transfers(&m, &tr, 1);
1141
1142 while (len) {
1143 chunk = min(len, max_chunk);
1144
1145 tr.tx_buf = buf;
1146 tr.len = chunk;
1147 buf += chunk;
1148 len -= chunk;
1149
1150 ret = spi_sync(spi, &m);
1151 if (ret)
1152 return ret;
1153 }
1154
1155 return 0;
1156}
1157EXPORT_SYMBOL(mipi_dbi_spi_transfer);
1158
1159#endif /* CONFIG_SPI */
1160
1161#ifdef CONFIG_DEBUG_FS
1162
1163static ssize_t mipi_dbi_debugfs_command_write(struct file *file,
1164 const char __user *ubuf,
1165 size_t count, loff_t *ppos)
1166{
1167 struct seq_file *m = file->private_data;
1168 struct mipi_dbi_dev *dbidev = m->private;
1169 u8 val, cmd = 0, parameters[64];
1170 char *buf, *pos, *token;
1171 int i, ret, idx;
1172
1173 if (!drm_dev_enter(&dbidev->drm, &idx))
1174 return -ENODEV;
1175
1176 buf = memdup_user_nul(ubuf, count);
1177 if (IS_ERR(buf)) {
1178 ret = PTR_ERR(buf);
1179 goto err_exit;
1180 }
1181
1182 /* strip trailing whitespace */
1183 for (i = count - 1; i > 0; i--)
1184 if (isspace(buf[i]))
1185 buf[i] = '\0';
1186 else
1187 break;
1188 i = 0;
1189 pos = buf;
1190 while (pos) {
1191 token = strsep(&pos, " ");
1192 if (!token) {
1193 ret = -EINVAL;
1194 goto err_free;
1195 }
1196
1197 ret = kstrtou8(token, 16, &val);
1198 if (ret < 0)
1199 goto err_free;
1200
1201 if (token == buf)
1202 cmd = val;
1203 else
1204 parameters[i++] = val;
1205
1206 if (i == 64) {
1207 ret = -E2BIG;
1208 goto err_free;
1209 }
1210 }
1211
1212 ret = mipi_dbi_command_buf(&dbidev->dbi, cmd, parameters, i);
1213
1214err_free:
1215 kfree(buf);
1216err_exit:
1217 drm_dev_exit(idx);
1218
1219 return ret < 0 ? ret : count;
1220}
1221
1222static int mipi_dbi_debugfs_command_show(struct seq_file *m, void *unused)
1223{
1224 struct mipi_dbi_dev *dbidev = m->private;
1225 struct mipi_dbi *dbi = &dbidev->dbi;
1226 u8 cmd, val[4];
1227 int ret, idx;
1228 size_t len;
1229
1230 if (!drm_dev_enter(&dbidev->drm, &idx))
1231 return -ENODEV;
1232
1233 for (cmd = 0; cmd < 255; cmd++) {
1234 if (!mipi_dbi_command_is_read(dbi, cmd))
1235 continue;
1236
1237 switch (cmd) {
1238 case MIPI_DCS_READ_MEMORY_START:
1239 case MIPI_DCS_READ_MEMORY_CONTINUE:
1240 len = 2;
1241 break;
1242 case MIPI_DCS_GET_DISPLAY_ID:
1243 len = 3;
1244 break;
1245 case MIPI_DCS_GET_DISPLAY_STATUS:
1246 len = 4;
1247 break;
1248 default:
1249 len = 1;
1250 break;
1251 }
1252
1253 seq_printf(m, "%02x: ", cmd);
1254 ret = mipi_dbi_command_buf(dbi, cmd, val, len);
1255 if (ret) {
1256 seq_puts(m, "XX\n");
1257 continue;
1258 }
1259 seq_printf(m, "%*phN\n", (int)len, val);
1260 }
1261
1262 drm_dev_exit(idx);
1263
1264 return 0;
1265}
1266
1267static int mipi_dbi_debugfs_command_open(struct inode *inode,
1268 struct file *file)
1269{
1270 return single_open(file, mipi_dbi_debugfs_command_show,
1271 inode->i_private);
1272}
1273
1274static const struct file_operations mipi_dbi_debugfs_command_fops = {
1275 .owner = THIS_MODULE,
1276 .open = mipi_dbi_debugfs_command_open,
1277 .read = seq_read,
1278 .llseek = seq_lseek,
1279 .release = single_release,
1280 .write = mipi_dbi_debugfs_command_write,
1281};
1282
1283/**
1284 * mipi_dbi_debugfs_init - Create debugfs entries
1285 * @minor: DRM minor
1286 *
1287 * This function creates a 'command' debugfs file for sending commands to the
1288 * controller or getting the read command values.
1289 * Drivers can use this as their &drm_driver->debugfs_init callback.
1290 *
1291 */
1292void mipi_dbi_debugfs_init(struct drm_minor *minor)
1293{
1294 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(minor->dev);
1295 umode_t mode = S_IFREG | S_IWUSR;
1296
1297 if (dbidev->dbi.read_commands)
1298 mode |= S_IRUGO;
1299 debugfs_create_file("command", mode, minor->debugfs_root, dbidev,
1300 &mipi_dbi_debugfs_command_fops);
1301}
1302EXPORT_SYMBOL(mipi_dbi_debugfs_init);
1303
1304#endif
1305
1306MODULE_LICENSE("GPL");