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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/firmware.h>
24#include <linux/module.h>
25#include <linux/pci.h>
26#include <linux/reboot.h>
27
28#define SMU_11_0_PARTIAL_PPTABLE
29#define SWSMU_CODE_LAYER_L3
30
31#include "amdgpu.h"
32#include "amdgpu_smu.h"
33#include "atomfirmware.h"
34#include "amdgpu_atomfirmware.h"
35#include "amdgpu_atombios.h"
36#include "smu_v11_0.h"
37#include "soc15_common.h"
38#include "atom.h"
39#include "amdgpu_ras.h"
40#include "smu_cmn.h"
41
42#include "asic_reg/thm/thm_11_0_2_offset.h"
43#include "asic_reg/thm/thm_11_0_2_sh_mask.h"
44#include "asic_reg/mp/mp_11_0_offset.h"
45#include "asic_reg/mp/mp_11_0_sh_mask.h"
46#include "asic_reg/smuio/smuio_11_0_0_offset.h"
47#include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
48
49/*
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
53 */
54#undef pr_err
55#undef pr_warn
56#undef pr_info
57#undef pr_debug
58
59MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
60MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
61MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
62MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
63MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
64MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
65
66#define SMU11_VOLTAGE_SCALE 4
67
68#define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms
69
70int smu_v11_0_init_microcode(struct smu_context *smu)
71{
72 struct amdgpu_device *adev = smu->adev;
73 const char *chip_name;
74 char fw_name[30];
75 int err = 0;
76 const struct smc_firmware_header_v1_0 *hdr;
77 const struct common_firmware_header *header;
78 struct amdgpu_firmware_info *ucode = NULL;
79
80 switch (adev->asic_type) {
81 case CHIP_ARCTURUS:
82 chip_name = "arcturus";
83 break;
84 case CHIP_NAVI10:
85 chip_name = "navi10";
86 break;
87 case CHIP_NAVI14:
88 chip_name = "navi14";
89 break;
90 case CHIP_NAVI12:
91 chip_name = "navi12";
92 break;
93 case CHIP_SIENNA_CICHLID:
94 chip_name = "sienna_cichlid";
95 break;
96 case CHIP_NAVY_FLOUNDER:
97 chip_name = "navy_flounder";
98 break;
99 default:
100 dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
101 return -EINVAL;
102 }
103
104 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
105
106 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
107 if (err)
108 goto out;
109 err = amdgpu_ucode_validate(adev->pm.fw);
110 if (err)
111 goto out;
112
113 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
114 amdgpu_ucode_print_smc_hdr(&hdr->header);
115 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
116
117 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
118 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
119 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
120 ucode->fw = adev->pm.fw;
121 header = (const struct common_firmware_header *)ucode->fw->data;
122 adev->firmware.fw_size +=
123 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
124 }
125
126out:
127 if (err) {
128 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
129 fw_name);
130 release_firmware(adev->pm.fw);
131 adev->pm.fw = NULL;
132 }
133 return err;
134}
135
136void smu_v11_0_fini_microcode(struct smu_context *smu)
137{
138 struct amdgpu_device *adev = smu->adev;
139
140 release_firmware(adev->pm.fw);
141 adev->pm.fw = NULL;
142 adev->pm.fw_version = 0;
143}
144
145int smu_v11_0_load_microcode(struct smu_context *smu)
146{
147 struct amdgpu_device *adev = smu->adev;
148 const uint32_t *src;
149 const struct smc_firmware_header_v1_0 *hdr;
150 uint32_t addr_start = MP1_SRAM;
151 uint32_t i;
152 uint32_t smc_fw_size;
153 uint32_t mp1_fw_flags;
154
155 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
156 src = (const uint32_t *)(adev->pm.fw->data +
157 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
158 smc_fw_size = hdr->header.ucode_size_bytes;
159
160 for (i = 1; i < smc_fw_size/4 - 1; i++) {
161 WREG32_PCIE(addr_start, src[i]);
162 addr_start += 4;
163 }
164
165 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
166 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
167 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
168 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
169
170 for (i = 0; i < adev->usec_timeout; i++) {
171 mp1_fw_flags = RREG32_PCIE(MP1_Public |
172 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
173 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
174 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
175 break;
176 udelay(1);
177 }
178
179 if (i == adev->usec_timeout)
180 return -ETIME;
181
182 return 0;
183}
184
185int smu_v11_0_check_fw_status(struct smu_context *smu)
186{
187 struct amdgpu_device *adev = smu->adev;
188 uint32_t mp1_fw_flags;
189
190 mp1_fw_flags = RREG32_PCIE(MP1_Public |
191 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
192
193 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
194 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
195 return 0;
196
197 return -EIO;
198}
199
200int smu_v11_0_check_fw_version(struct smu_context *smu)
201{
202 uint32_t if_version = 0xff, smu_version = 0xff;
203 uint16_t smu_major;
204 uint8_t smu_minor, smu_debug;
205 int ret = 0;
206
207 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
208 if (ret)
209 return ret;
210
211 smu_major = (smu_version >> 16) & 0xffff;
212 smu_minor = (smu_version >> 8) & 0xff;
213 smu_debug = (smu_version >> 0) & 0xff;
214
215 switch (smu->adev->asic_type) {
216 case CHIP_ARCTURUS:
217 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
218 break;
219 case CHIP_NAVI10:
220 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
221 break;
222 case CHIP_NAVI12:
223 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
224 break;
225 case CHIP_NAVI14:
226 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
227 break;
228 case CHIP_SIENNA_CICHLID:
229 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
230 break;
231 case CHIP_NAVY_FLOUNDER:
232 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
233 break;
234 default:
235 dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
236 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
237 break;
238 }
239
240 /*
241 * 1. if_version mismatch is not critical as our fw is designed
242 * to be backward compatible.
243 * 2. New fw usually brings some optimizations. But that's visible
244 * only on the paired driver.
245 * Considering above, we just leave user a warning message instead
246 * of halt driver loading.
247 */
248 if (if_version != smu->smc_driver_if_version) {
249 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
250 "smu fw version = 0x%08x (%d.%d.%d)\n",
251 smu->smc_driver_if_version, if_version,
252 smu_version, smu_major, smu_minor, smu_debug);
253 dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
254 }
255
256 return ret;
257}
258
259static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
260{
261 struct amdgpu_device *adev = smu->adev;
262 uint32_t ppt_offset_bytes;
263 const struct smc_firmware_header_v2_0 *v2;
264
265 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
266
267 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
268 *size = le32_to_cpu(v2->ppt_size_bytes);
269 *table = (uint8_t *)v2 + ppt_offset_bytes;
270
271 return 0;
272}
273
274static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
275 uint32_t *size, uint32_t pptable_id)
276{
277 struct amdgpu_device *adev = smu->adev;
278 const struct smc_firmware_header_v2_1 *v2_1;
279 struct smc_soft_pptable_entry *entries;
280 uint32_t pptable_count = 0;
281 int i = 0;
282
283 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
284 entries = (struct smc_soft_pptable_entry *)
285 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
286 pptable_count = le32_to_cpu(v2_1->pptable_count);
287 for (i = 0; i < pptable_count; i++) {
288 if (le32_to_cpu(entries[i].id) == pptable_id) {
289 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
290 *size = le32_to_cpu(entries[i].ppt_size_bytes);
291 break;
292 }
293 }
294
295 if (i == pptable_count)
296 return -EINVAL;
297
298 return 0;
299}
300
301int smu_v11_0_setup_pptable(struct smu_context *smu)
302{
303 struct amdgpu_device *adev = smu->adev;
304 const struct smc_firmware_header_v1_0 *hdr;
305 int ret, index;
306 uint32_t size = 0;
307 uint16_t atom_table_size;
308 uint8_t frev, crev;
309 void *table;
310 uint16_t version_major, version_minor;
311
312 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
313 version_major = le16_to_cpu(hdr->header.header_version_major);
314 version_minor = le16_to_cpu(hdr->header.header_version_minor);
315 if ((version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) ||
316 adev->asic_type == CHIP_NAVY_FLOUNDER) {
317 dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
318 switch (version_minor) {
319 case 0:
320 ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
321 break;
322 case 1:
323 ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
324 smu->smu_table.boot_values.pp_table_id);
325 break;
326 default:
327 ret = -EINVAL;
328 break;
329 }
330 if (ret)
331 return ret;
332
333 } else {
334 dev_info(adev->dev, "use vbios provided pptable\n");
335 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
336 powerplayinfo);
337
338 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
339 (uint8_t **)&table);
340 if (ret)
341 return ret;
342 size = atom_table_size;
343 }
344
345 if (!smu->smu_table.power_play_table)
346 smu->smu_table.power_play_table = table;
347 if (!smu->smu_table.power_play_table_size)
348 smu->smu_table.power_play_table_size = size;
349
350 return 0;
351}
352
353int smu_v11_0_init_smc_tables(struct smu_context *smu)
354{
355 struct smu_table_context *smu_table = &smu->smu_table;
356 struct smu_table *tables = smu_table->tables;
357 int ret = 0;
358
359 smu_table->driver_pptable =
360 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
361 if (!smu_table->driver_pptable) {
362 ret = -ENOMEM;
363 goto err0_out;
364 }
365
366 smu_table->max_sustainable_clocks =
367 kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL);
368 if (!smu_table->max_sustainable_clocks) {
369 ret = -ENOMEM;
370 goto err1_out;
371 }
372
373 /* Arcturus does not support OVERDRIVE */
374 if (tables[SMU_TABLE_OVERDRIVE].size) {
375 smu_table->overdrive_table =
376 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
377 if (!smu_table->overdrive_table) {
378 ret = -ENOMEM;
379 goto err2_out;
380 }
381
382 smu_table->boot_overdrive_table =
383 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
384 if (!smu_table->boot_overdrive_table) {
385 ret = -ENOMEM;
386 goto err3_out;
387 }
388 }
389
390 return 0;
391
392err3_out:
393 kfree(smu_table->overdrive_table);
394err2_out:
395 kfree(smu_table->max_sustainable_clocks);
396err1_out:
397 kfree(smu_table->driver_pptable);
398err0_out:
399 return ret;
400}
401
402int smu_v11_0_fini_smc_tables(struct smu_context *smu)
403{
404 struct smu_table_context *smu_table = &smu->smu_table;
405 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
406
407 kfree(smu_table->boot_overdrive_table);
408 kfree(smu_table->overdrive_table);
409 kfree(smu_table->max_sustainable_clocks);
410 kfree(smu_table->driver_pptable);
411 smu_table->boot_overdrive_table = NULL;
412 smu_table->overdrive_table = NULL;
413 smu_table->max_sustainable_clocks = NULL;
414 smu_table->driver_pptable = NULL;
415 kfree(smu_table->hardcode_pptable);
416 smu_table->hardcode_pptable = NULL;
417
418 kfree(smu_table->metrics_table);
419 kfree(smu_table->watermarks_table);
420 smu_table->metrics_table = NULL;
421 smu_table->watermarks_table = NULL;
422 smu_table->metrics_time = 0;
423
424 kfree(smu_dpm->dpm_context);
425 kfree(smu_dpm->golden_dpm_context);
426 kfree(smu_dpm->dpm_current_power_state);
427 kfree(smu_dpm->dpm_request_power_state);
428 smu_dpm->dpm_context = NULL;
429 smu_dpm->golden_dpm_context = NULL;
430 smu_dpm->dpm_context_size = 0;
431 smu_dpm->dpm_current_power_state = NULL;
432 smu_dpm->dpm_request_power_state = NULL;
433
434 return 0;
435}
436
437int smu_v11_0_init_power(struct smu_context *smu)
438{
439 struct smu_power_context *smu_power = &smu->smu_power;
440
441 if (smu_power->power_context || smu_power->power_context_size != 0)
442 return -EINVAL;
443
444 smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
445 GFP_KERNEL);
446 if (!smu_power->power_context)
447 return -ENOMEM;
448 smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
449
450 return 0;
451}
452
453int smu_v11_0_fini_power(struct smu_context *smu)
454{
455 struct smu_power_context *smu_power = &smu->smu_power;
456
457 if (!smu_power->power_context || smu_power->power_context_size == 0)
458 return -EINVAL;
459
460 kfree(smu_power->power_context);
461 smu_power->power_context = NULL;
462 smu_power->power_context_size = 0;
463
464 return 0;
465}
466
467static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
468 uint8_t clk_id,
469 uint8_t syspll_id,
470 uint32_t *clk_freq)
471{
472 struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
473 struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
474 int ret, index;
475
476 input.clk_id = clk_id;
477 input.syspll_id = syspll_id;
478 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
479 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
480 getsmuclockinfo);
481
482 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
483 (uint32_t *)&input);
484 if (ret)
485 return -EINVAL;
486
487 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
488 *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
489
490 return 0;
491}
492
493int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
494{
495 int ret, index;
496 uint16_t size;
497 uint8_t frev, crev;
498 struct atom_common_table_header *header;
499 struct atom_firmware_info_v3_3 *v_3_3;
500 struct atom_firmware_info_v3_1 *v_3_1;
501
502 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
503 firmwareinfo);
504
505 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
506 (uint8_t **)&header);
507 if (ret)
508 return ret;
509
510 if (header->format_revision != 3) {
511 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n");
512 return -EINVAL;
513 }
514
515 switch (header->content_revision) {
516 case 0:
517 case 1:
518 case 2:
519 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
520 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
521 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
522 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
523 smu->smu_table.boot_values.socclk = 0;
524 smu->smu_table.boot_values.dcefclk = 0;
525 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
526 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
527 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
528 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
529 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
530 smu->smu_table.boot_values.pp_table_id = 0;
531 break;
532 case 3:
533 default:
534 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
535 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
536 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
537 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
538 smu->smu_table.boot_values.socclk = 0;
539 smu->smu_table.boot_values.dcefclk = 0;
540 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
541 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
542 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
543 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
544 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
545 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
546 }
547
548 smu->smu_table.boot_values.format_revision = header->format_revision;
549 smu->smu_table.boot_values.content_revision = header->content_revision;
550
551 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
552 (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
553 (uint8_t)0,
554 &smu->smu_table.boot_values.socclk);
555
556 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
557 (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
558 (uint8_t)0,
559 &smu->smu_table.boot_values.dcefclk);
560
561 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
562 (uint8_t)SMU11_SYSPLL0_ECLK_ID,
563 (uint8_t)0,
564 &smu->smu_table.boot_values.eclk);
565
566 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
567 (uint8_t)SMU11_SYSPLL0_VCLK_ID,
568 (uint8_t)0,
569 &smu->smu_table.boot_values.vclk);
570
571 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
572 (uint8_t)SMU11_SYSPLL0_DCLK_ID,
573 (uint8_t)0,
574 &smu->smu_table.boot_values.dclk);
575
576 if ((smu->smu_table.boot_values.format_revision == 3) &&
577 (smu->smu_table.boot_values.content_revision >= 2))
578 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
579 (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
580 (uint8_t)SMU11_SYSPLL1_2_ID,
581 &smu->smu_table.boot_values.fclk);
582
583 return 0;
584}
585
586int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
587{
588 struct smu_table_context *smu_table = &smu->smu_table;
589 struct smu_table *memory_pool = &smu_table->memory_pool;
590 int ret = 0;
591 uint64_t address;
592 uint32_t address_low, address_high;
593
594 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
595 return ret;
596
597 address = (uintptr_t)memory_pool->cpu_addr;
598 address_high = (uint32_t)upper_32_bits(address);
599 address_low = (uint32_t)lower_32_bits(address);
600
601 ret = smu_cmn_send_smc_msg_with_param(smu,
602 SMU_MSG_SetSystemVirtualDramAddrHigh,
603 address_high,
604 NULL);
605 if (ret)
606 return ret;
607 ret = smu_cmn_send_smc_msg_with_param(smu,
608 SMU_MSG_SetSystemVirtualDramAddrLow,
609 address_low,
610 NULL);
611 if (ret)
612 return ret;
613
614 address = memory_pool->mc_address;
615 address_high = (uint32_t)upper_32_bits(address);
616 address_low = (uint32_t)lower_32_bits(address);
617
618 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
619 address_high, NULL);
620 if (ret)
621 return ret;
622 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
623 address_low, NULL);
624 if (ret)
625 return ret;
626 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
627 (uint32_t)memory_pool->size, NULL);
628 if (ret)
629 return ret;
630
631 return ret;
632}
633
634int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
635{
636 int ret;
637
638 ret = smu_cmn_send_smc_msg_with_param(smu,
639 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
640 if (ret)
641 dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!");
642
643 return ret;
644}
645
646int smu_v11_0_set_driver_table_location(struct smu_context *smu)
647{
648 struct smu_table *driver_table = &smu->smu_table.driver_table;
649 int ret = 0;
650
651 if (driver_table->mc_address) {
652 ret = smu_cmn_send_smc_msg_with_param(smu,
653 SMU_MSG_SetDriverDramAddrHigh,
654 upper_32_bits(driver_table->mc_address),
655 NULL);
656 if (!ret)
657 ret = smu_cmn_send_smc_msg_with_param(smu,
658 SMU_MSG_SetDriverDramAddrLow,
659 lower_32_bits(driver_table->mc_address),
660 NULL);
661 }
662
663 return ret;
664}
665
666int smu_v11_0_set_tool_table_location(struct smu_context *smu)
667{
668 int ret = 0;
669 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
670
671 if (tool_table->mc_address) {
672 ret = smu_cmn_send_smc_msg_with_param(smu,
673 SMU_MSG_SetToolsDramAddrHigh,
674 upper_32_bits(tool_table->mc_address),
675 NULL);
676 if (!ret)
677 ret = smu_cmn_send_smc_msg_with_param(smu,
678 SMU_MSG_SetToolsDramAddrLow,
679 lower_32_bits(tool_table->mc_address),
680 NULL);
681 }
682
683 return ret;
684}
685
686int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
687{
688 int ret = 0;
689 struct amdgpu_device *adev = smu->adev;
690
691 /* Navy_Flounder do not support to change display num currently */
692 if (adev->asic_type == CHIP_NAVY_FLOUNDER)
693 return 0;
694
695 if (!smu->pm_enabled)
696 return ret;
697
698 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
699 return ret;
700}
701
702
703int smu_v11_0_set_allowed_mask(struct smu_context *smu)
704{
705 struct smu_feature *feature = &smu->smu_feature;
706 int ret = 0;
707 uint32_t feature_mask[2];
708
709 mutex_lock(&feature->mutex);
710 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
711 goto failed;
712
713 bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
714
715 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
716 feature_mask[1], NULL);
717 if (ret)
718 goto failed;
719
720 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
721 feature_mask[0], NULL);
722 if (ret)
723 goto failed;
724
725failed:
726 mutex_unlock(&feature->mutex);
727 return ret;
728}
729
730int smu_v11_0_system_features_control(struct smu_context *smu,
731 bool en)
732{
733 struct smu_feature *feature = &smu->smu_feature;
734 uint32_t feature_mask[2];
735 int ret = 0;
736
737 ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
738 SMU_MSG_DisableAllSmuFeatures), NULL);
739 if (ret)
740 return ret;
741
742 bitmap_zero(feature->enabled, feature->feature_num);
743 bitmap_zero(feature->supported, feature->feature_num);
744
745 if (en) {
746 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
747 if (ret)
748 return ret;
749
750 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
751 feature->feature_num);
752 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
753 feature->feature_num);
754 }
755
756 return ret;
757}
758
759int smu_v11_0_notify_display_change(struct smu_context *smu)
760{
761 int ret = 0;
762
763 if (!smu->pm_enabled)
764 return ret;
765
766 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
767 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
768 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
769
770 return ret;
771}
772
773static int
774smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
775 enum smu_clk_type clock_select)
776{
777 int ret = 0;
778 int clk_id;
779
780 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
781 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
782 return 0;
783
784 clk_id = smu_cmn_to_asic_specific_index(smu,
785 CMN2ASIC_MAPPING_CLK,
786 clock_select);
787 if (clk_id < 0)
788 return -EINVAL;
789
790 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
791 clk_id << 16, clock);
792 if (ret) {
793 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
794 return ret;
795 }
796
797 if (*clock != 0)
798 return 0;
799
800 /* if DC limit is zero, return AC limit */
801 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
802 clk_id << 16, clock);
803 if (ret) {
804 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
805 return ret;
806 }
807
808 return 0;
809}
810
811int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
812{
813 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
814 smu->smu_table.max_sustainable_clocks;
815 int ret = 0;
816
817 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
818 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
819 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
820 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
821 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
822 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
823
824 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
825 ret = smu_v11_0_get_max_sustainable_clock(smu,
826 &(max_sustainable_clocks->uclock),
827 SMU_UCLK);
828 if (ret) {
829 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
830 __func__);
831 return ret;
832 }
833 }
834
835 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
836 ret = smu_v11_0_get_max_sustainable_clock(smu,
837 &(max_sustainable_clocks->soc_clock),
838 SMU_SOCCLK);
839 if (ret) {
840 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
841 __func__);
842 return ret;
843 }
844 }
845
846 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
847 ret = smu_v11_0_get_max_sustainable_clock(smu,
848 &(max_sustainable_clocks->dcef_clock),
849 SMU_DCEFCLK);
850 if (ret) {
851 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
852 __func__);
853 return ret;
854 }
855
856 ret = smu_v11_0_get_max_sustainable_clock(smu,
857 &(max_sustainable_clocks->display_clock),
858 SMU_DISPCLK);
859 if (ret) {
860 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
861 __func__);
862 return ret;
863 }
864 ret = smu_v11_0_get_max_sustainable_clock(smu,
865 &(max_sustainable_clocks->phy_clock),
866 SMU_PHYCLK);
867 if (ret) {
868 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
869 __func__);
870 return ret;
871 }
872 ret = smu_v11_0_get_max_sustainable_clock(smu,
873 &(max_sustainable_clocks->pixel_clock),
874 SMU_PIXCLK);
875 if (ret) {
876 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
877 __func__);
878 return ret;
879 }
880 }
881
882 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
883 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
884
885 return 0;
886}
887
888int smu_v11_0_get_current_power_limit(struct smu_context *smu,
889 uint32_t *power_limit)
890{
891 int power_src;
892 int ret = 0;
893
894 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
895 return -EINVAL;
896
897 power_src = smu_cmn_to_asic_specific_index(smu,
898 CMN2ASIC_MAPPING_PWR,
899 smu->adev->pm.ac_power ?
900 SMU_POWER_SOURCE_AC :
901 SMU_POWER_SOURCE_DC);
902 if (power_src < 0)
903 return -EINVAL;
904
905 ret = smu_cmn_send_smc_msg_with_param(smu,
906 SMU_MSG_GetPptLimit,
907 power_src << 16,
908 power_limit);
909 if (ret)
910 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
911
912 return ret;
913}
914
915int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
916{
917 int ret = 0;
918
919 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
920 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
921 return -EOPNOTSUPP;
922 }
923
924 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
925 if (ret) {
926 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
927 return ret;
928 }
929
930 smu->current_power_limit = n;
931
932 return 0;
933}
934
935int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
936{
937 if (smu->smu_table.thermal_controller_type)
938 return amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
939
940 return 0;
941}
942
943int smu_v11_0_disable_thermal_alert(struct smu_context *smu)
944{
945 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
946}
947
948static uint16_t convert_to_vddc(uint8_t vid)
949{
950 return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
951}
952
953int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
954{
955 struct amdgpu_device *adev = smu->adev;
956 uint32_t vdd = 0, val_vid = 0;
957
958 if (!value)
959 return -EINVAL;
960 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
961 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
962 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
963
964 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
965
966 *value = vdd;
967
968 return 0;
969
970}
971
972int
973smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
974 struct pp_display_clock_request
975 *clock_req)
976{
977 enum amd_pp_clock_type clk_type = clock_req->clock_type;
978 int ret = 0;
979 enum smu_clk_type clk_select = 0;
980 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
981
982 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
983 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
984 switch (clk_type) {
985 case amd_pp_dcef_clock:
986 clk_select = SMU_DCEFCLK;
987 break;
988 case amd_pp_disp_clock:
989 clk_select = SMU_DISPCLK;
990 break;
991 case amd_pp_pixel_clock:
992 clk_select = SMU_PIXCLK;
993 break;
994 case amd_pp_phy_clock:
995 clk_select = SMU_PHYCLK;
996 break;
997 case amd_pp_mem_clock:
998 clk_select = SMU_UCLK;
999 break;
1000 default:
1001 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1002 ret = -EINVAL;
1003 break;
1004 }
1005
1006 if (ret)
1007 goto failed;
1008
1009 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1010 return 0;
1011
1012 ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1013
1014 if(clk_select == SMU_UCLK)
1015 smu->hard_min_uclk_req_from_dal = clk_freq;
1016 }
1017
1018failed:
1019 return ret;
1020}
1021
1022int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1023{
1024 int ret = 0;
1025 struct amdgpu_device *adev = smu->adev;
1026
1027 switch (adev->asic_type) {
1028 case CHIP_NAVI10:
1029 case CHIP_NAVI14:
1030 case CHIP_NAVI12:
1031 case CHIP_SIENNA_CICHLID:
1032 case CHIP_NAVY_FLOUNDER:
1033 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1034 return 0;
1035 if (enable)
1036 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
1037 else
1038 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
1039 break;
1040 default:
1041 break;
1042 }
1043
1044 return ret;
1045}
1046
1047uint32_t
1048smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1049{
1050 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1051 return AMD_FAN_CTRL_MANUAL;
1052 else
1053 return AMD_FAN_CTRL_AUTO;
1054}
1055
1056static int
1057smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1058{
1059 int ret = 0;
1060
1061 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1062 return 0;
1063
1064 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1065 if (ret)
1066 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1067 __func__, (auto_fan_control ? "Start" : "Stop"));
1068
1069 return ret;
1070}
1071
1072static int
1073smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1074{
1075 struct amdgpu_device *adev = smu->adev;
1076
1077 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1078 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1079 CG_FDO_CTRL2, TMIN, 0));
1080 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1081 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1082 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1083
1084 return 0;
1085}
1086
1087int
1088smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1089{
1090 struct amdgpu_device *adev = smu->adev;
1091 uint32_t duty100, duty;
1092 uint64_t tmp64;
1093
1094 if (speed > 100)
1095 speed = 100;
1096
1097 if (smu_v11_0_auto_fan_control(smu, 0))
1098 return -EINVAL;
1099
1100 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1101 CG_FDO_CTRL1, FMAX_DUTY100);
1102 if (!duty100)
1103 return -EINVAL;
1104
1105 tmp64 = (uint64_t)speed * duty100;
1106 do_div(tmp64, 100);
1107 duty = (uint32_t)tmp64;
1108
1109 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1110 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1111 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1112
1113 return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1114}
1115
1116int
1117smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1118 uint32_t mode)
1119{
1120 int ret = 0;
1121
1122 switch (mode) {
1123 case AMD_FAN_CTRL_NONE:
1124 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1125 break;
1126 case AMD_FAN_CTRL_MANUAL:
1127 ret = smu_v11_0_auto_fan_control(smu, 0);
1128 break;
1129 case AMD_FAN_CTRL_AUTO:
1130 ret = smu_v11_0_auto_fan_control(smu, 1);
1131 break;
1132 default:
1133 break;
1134 }
1135
1136 if (ret) {
1137 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1138 return -EINVAL;
1139 }
1140
1141 return ret;
1142}
1143
1144int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1145 uint32_t speed)
1146{
1147 struct amdgpu_device *adev = smu->adev;
1148 int ret;
1149 uint32_t tach_period, crystal_clock_freq;
1150
1151 if (!speed)
1152 return -EINVAL;
1153
1154 ret = smu_v11_0_auto_fan_control(smu, 0);
1155 if (ret)
1156 return ret;
1157
1158 crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1159 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1160 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1161 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1162 CG_TACH_CTRL, TARGET_PERIOD,
1163 tach_period));
1164
1165 ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1166
1167 return ret;
1168}
1169
1170int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1171 uint32_t pstate)
1172{
1173 int ret = 0;
1174 ret = smu_cmn_send_smc_msg_with_param(smu,
1175 SMU_MSG_SetXgmiMode,
1176 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1177 NULL);
1178 return ret;
1179}
1180
1181static int smu_v11_0_set_irq_state(struct amdgpu_device *adev,
1182 struct amdgpu_irq_src *source,
1183 unsigned tyep,
1184 enum amdgpu_interrupt_state state)
1185{
1186 struct smu_context *smu = &adev->smu;
1187 uint32_t low, high;
1188 uint32_t val = 0;
1189
1190 switch (state) {
1191 case AMDGPU_IRQ_STATE_DISABLE:
1192 /* For THM irqs */
1193 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1194 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1195 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1196 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1197
1198 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1199
1200 /* For MP1 SW irqs */
1201 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1202 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1203 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1204
1205 break;
1206 case AMDGPU_IRQ_STATE_ENABLE:
1207 /* For THM irqs */
1208 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1209 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1210 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1211 smu->thermal_range.software_shutdown_temp);
1212
1213 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1214 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1215 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1216 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1217 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1218 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1219 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1220 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1221 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1222
1223 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1224 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1225 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1226 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1227
1228 /* For MP1 SW irqs */
1229 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT);
1230 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1231 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1232 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val);
1233
1234 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1235 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1236 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1237
1238 break;
1239 default:
1240 break;
1241 }
1242
1243 return 0;
1244}
1245
1246static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu)
1247{
1248 return smu_cmn_send_smc_msg(smu,
1249 SMU_MSG_ReenableAcDcInterrupt,
1250 NULL);
1251}
1252
1253#define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1254#define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1255
1256#define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1257
1258static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1259 struct amdgpu_irq_src *source,
1260 struct amdgpu_iv_entry *entry)
1261{
1262 struct smu_context *smu = &adev->smu;
1263 uint32_t client_id = entry->client_id;
1264 uint32_t src_id = entry->src_id;
1265 /*
1266 * ctxid is used to distinguish different
1267 * events for SMCToHost interrupt.
1268 */
1269 uint32_t ctxid = entry->src_data[0];
1270 uint32_t data;
1271
1272 if (client_id == SOC15_IH_CLIENTID_THM) {
1273 switch (src_id) {
1274 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1275 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1276 /*
1277 * SW CTF just occurred.
1278 * Try to do a graceful shutdown to prevent further damage.
1279 */
1280 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1281 orderly_poweroff(true);
1282 break;
1283 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1284 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1285 break;
1286 default:
1287 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1288 src_id);
1289 break;
1290 }
1291 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1292 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1293 /*
1294 * HW CTF just occurred. Shutdown to prevent further damage.
1295 */
1296 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1297 orderly_poweroff(true);
1298 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1299 if (src_id == 0xfe) {
1300 /* ACK SMUToHost interrupt */
1301 data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1302 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1303 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data);
1304
1305 switch (ctxid) {
1306 case 0x3:
1307 dev_dbg(adev->dev, "Switched to AC mode!\n");
1308 smu_v11_0_ack_ac_dc_interrupt(&adev->smu);
1309 break;
1310 case 0x4:
1311 dev_dbg(adev->dev, "Switched to DC mode!\n");
1312 smu_v11_0_ack_ac_dc_interrupt(&adev->smu);
1313 break;
1314 case 0x7:
1315 if (!atomic_read(&adev->throttling_logging_enabled))
1316 return 0;
1317
1318 if (__ratelimit(&adev->throttling_logging_rs))
1319 schedule_work(&smu->throttling_logging_work);
1320
1321 break;
1322 }
1323 }
1324 }
1325
1326 return 0;
1327}
1328
1329static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1330{
1331 .set = smu_v11_0_set_irq_state,
1332 .process = smu_v11_0_irq_process,
1333};
1334
1335int smu_v11_0_register_irq_handler(struct smu_context *smu)
1336{
1337 struct amdgpu_device *adev = smu->adev;
1338 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1339 int ret = 0;
1340
1341 irq_src->num_types = 1;
1342 irq_src->funcs = &smu_v11_0_irq_funcs;
1343
1344 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1345 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1346 irq_src);
1347 if (ret)
1348 return ret;
1349
1350 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1351 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1352 irq_src);
1353 if (ret)
1354 return ret;
1355
1356 /* Register CTF(GPIO_19) interrupt */
1357 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1358 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1359 irq_src);
1360 if (ret)
1361 return ret;
1362
1363 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1364 0xfe,
1365 irq_src);
1366 if (ret)
1367 return ret;
1368
1369 return ret;
1370}
1371
1372int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1373 struct pp_smu_nv_clock_table *max_clocks)
1374{
1375 struct smu_table_context *table_context = &smu->smu_table;
1376 struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1377
1378 if (!max_clocks || !table_context->max_sustainable_clocks)
1379 return -EINVAL;
1380
1381 sustainable_clocks = table_context->max_sustainable_clocks;
1382
1383 max_clocks->dcfClockInKhz =
1384 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1385 max_clocks->displayClockInKhz =
1386 (unsigned int) sustainable_clocks->display_clock * 1000;
1387 max_clocks->phyClockInKhz =
1388 (unsigned int) sustainable_clocks->phy_clock * 1000;
1389 max_clocks->pixelClockInKhz =
1390 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1391 max_clocks->uClockInKhz =
1392 (unsigned int) sustainable_clocks->uclock * 1000;
1393 max_clocks->socClockInKhz =
1394 (unsigned int) sustainable_clocks->soc_clock * 1000;
1395 max_clocks->dscClockInKhz = 0;
1396 max_clocks->dppClockInKhz = 0;
1397 max_clocks->fabricClockInKhz = 0;
1398
1399 return 0;
1400}
1401
1402int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1403{
1404 int ret = 0;
1405
1406 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1407
1408 return ret;
1409}
1410
1411static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1412{
1413 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL);
1414}
1415
1416bool smu_v11_0_baco_is_support(struct smu_context *smu)
1417{
1418 struct smu_baco_context *smu_baco = &smu->smu_baco;
1419 bool baco_support;
1420
1421 mutex_lock(&smu_baco->mutex);
1422 baco_support = smu_baco->platform_support;
1423 mutex_unlock(&smu_baco->mutex);
1424
1425 if (!baco_support)
1426 return false;
1427
1428 /* Arcturus does not support this bit mask */
1429 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1430 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1431 return false;
1432
1433 return true;
1434}
1435
1436enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1437{
1438 struct smu_baco_context *smu_baco = &smu->smu_baco;
1439 enum smu_baco_state baco_state;
1440
1441 mutex_lock(&smu_baco->mutex);
1442 baco_state = smu_baco->state;
1443 mutex_unlock(&smu_baco->mutex);
1444
1445 return baco_state;
1446}
1447
1448int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1449{
1450 struct smu_baco_context *smu_baco = &smu->smu_baco;
1451 struct amdgpu_device *adev = smu->adev;
1452 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1453 uint32_t data;
1454 int ret = 0;
1455
1456 if (smu_v11_0_baco_get_state(smu) == state)
1457 return 0;
1458
1459 mutex_lock(&smu_baco->mutex);
1460
1461 if (state == SMU_BACO_STATE_ENTER) {
1462 if (!ras || !ras->supported) {
1463 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1464 data |= 0x80000000;
1465 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1466
1467 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL);
1468 } else {
1469 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL);
1470 }
1471 } else {
1472 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL);
1473 if (ret)
1474 goto out;
1475
1476 /* clear vbios scratch 6 and 7 for coming asic reinit */
1477 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1478 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1479 }
1480 if (ret)
1481 goto out;
1482
1483 smu_baco->state = state;
1484out:
1485 mutex_unlock(&smu_baco->mutex);
1486 return ret;
1487}
1488
1489int smu_v11_0_baco_enter(struct smu_context *smu)
1490{
1491 struct amdgpu_device *adev = smu->adev;
1492 int ret = 0;
1493
1494 /* Arcturus does not need this audio workaround */
1495 if (adev->asic_type != CHIP_ARCTURUS) {
1496 ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1497 if (ret)
1498 return ret;
1499 }
1500
1501 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1502 if (ret)
1503 return ret;
1504
1505 msleep(10);
1506
1507 return ret;
1508}
1509
1510int smu_v11_0_baco_exit(struct smu_context *smu)
1511{
1512 int ret = 0;
1513
1514 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1515 if (ret)
1516 return ret;
1517
1518 return ret;
1519}
1520
1521int smu_v11_0_mode1_reset(struct smu_context *smu)
1522{
1523 int ret = 0;
1524
1525 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1526 if (!ret)
1527 msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS);
1528
1529 return ret;
1530}
1531
1532int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1533 uint32_t *min, uint32_t *max)
1534{
1535 int ret = 0, clk_id = 0;
1536 uint32_t param = 0;
1537 uint32_t clock_limit;
1538
1539 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1540 switch (clk_type) {
1541 case SMU_MCLK:
1542 case SMU_UCLK:
1543 clock_limit = smu->smu_table.boot_values.uclk;
1544 break;
1545 case SMU_GFXCLK:
1546 case SMU_SCLK:
1547 clock_limit = smu->smu_table.boot_values.gfxclk;
1548 break;
1549 case SMU_SOCCLK:
1550 clock_limit = smu->smu_table.boot_values.socclk;
1551 break;
1552 default:
1553 clock_limit = 0;
1554 break;
1555 }
1556
1557 /* clock in Mhz unit */
1558 if (min)
1559 *min = clock_limit / 100;
1560 if (max)
1561 *max = clock_limit / 100;
1562
1563 return 0;
1564 }
1565
1566 clk_id = smu_cmn_to_asic_specific_index(smu,
1567 CMN2ASIC_MAPPING_CLK,
1568 clk_type);
1569 if (clk_id < 0) {
1570 ret = -EINVAL;
1571 goto failed;
1572 }
1573 param = (clk_id & 0xffff) << 16;
1574
1575 if (max) {
1576 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1577 if (ret)
1578 goto failed;
1579 }
1580
1581 if (min) {
1582 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1583 if (ret)
1584 goto failed;
1585 }
1586
1587failed:
1588 return ret;
1589}
1590
1591int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
1592 enum smu_clk_type clk_type,
1593 uint32_t min,
1594 uint32_t max)
1595{
1596 struct amdgpu_device *adev = smu->adev;
1597 int ret = 0, clk_id = 0;
1598 uint32_t param;
1599
1600 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1601 return 0;
1602
1603 clk_id = smu_cmn_to_asic_specific_index(smu,
1604 CMN2ASIC_MAPPING_CLK,
1605 clk_type);
1606 if (clk_id < 0)
1607 return clk_id;
1608
1609 if (clk_type == SMU_GFXCLK)
1610 amdgpu_gfx_off_ctrl(adev, false);
1611
1612 if (max > 0) {
1613 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1614 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1615 param, NULL);
1616 if (ret)
1617 goto out;
1618 }
1619
1620 if (min > 0) {
1621 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1622 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1623 param, NULL);
1624 if (ret)
1625 goto out;
1626 }
1627
1628out:
1629 if (clk_type == SMU_GFXCLK)
1630 amdgpu_gfx_off_ctrl(adev, true);
1631
1632 return ret;
1633}
1634
1635int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
1636 enum smu_clk_type clk_type,
1637 uint32_t min,
1638 uint32_t max)
1639{
1640 int ret = 0, clk_id = 0;
1641 uint32_t param;
1642
1643 if (min <= 0 && max <= 0)
1644 return -EINVAL;
1645
1646 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1647 return 0;
1648
1649 clk_id = smu_cmn_to_asic_specific_index(smu,
1650 CMN2ASIC_MAPPING_CLK,
1651 clk_type);
1652 if (clk_id < 0)
1653 return clk_id;
1654
1655 if (max > 0) {
1656 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1657 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1658 param, NULL);
1659 if (ret)
1660 return ret;
1661 }
1662
1663 if (min > 0) {
1664 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1665 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1666 param, NULL);
1667 if (ret)
1668 return ret;
1669 }
1670
1671 return ret;
1672}
1673
1674int smu_v11_0_set_performance_level(struct smu_context *smu,
1675 enum amd_dpm_forced_level level)
1676{
1677 struct smu_11_0_dpm_context *dpm_context =
1678 smu->smu_dpm.dpm_context;
1679 struct smu_11_0_dpm_table *gfx_table =
1680 &dpm_context->dpm_tables.gfx_table;
1681 struct smu_11_0_dpm_table *mem_table =
1682 &dpm_context->dpm_tables.uclk_table;
1683 struct smu_11_0_dpm_table *soc_table =
1684 &dpm_context->dpm_tables.soc_table;
1685 struct smu_umd_pstate_table *pstate_table =
1686 &smu->pstate_table;
1687 struct amdgpu_device *adev = smu->adev;
1688 uint32_t sclk_min = 0, sclk_max = 0;
1689 uint32_t mclk_min = 0, mclk_max = 0;
1690 uint32_t socclk_min = 0, socclk_max = 0;
1691 int ret = 0;
1692
1693 switch (level) {
1694 case AMD_DPM_FORCED_LEVEL_HIGH:
1695 sclk_min = sclk_max = gfx_table->max;
1696 mclk_min = mclk_max = mem_table->max;
1697 socclk_min = socclk_max = soc_table->max;
1698 break;
1699 case AMD_DPM_FORCED_LEVEL_LOW:
1700 sclk_min = sclk_max = gfx_table->min;
1701 mclk_min = mclk_max = mem_table->min;
1702 socclk_min = socclk_max = soc_table->min;
1703 break;
1704 case AMD_DPM_FORCED_LEVEL_AUTO:
1705 sclk_min = gfx_table->min;
1706 sclk_max = gfx_table->max;
1707 mclk_min = mem_table->min;
1708 mclk_max = mem_table->max;
1709 socclk_min = soc_table->min;
1710 socclk_max = soc_table->max;
1711 break;
1712 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1713 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1714 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1715 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1716 break;
1717 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1718 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1719 break;
1720 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1721 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1722 break;
1723 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1724 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1725 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1726 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1727 break;
1728 case AMD_DPM_FORCED_LEVEL_MANUAL:
1729 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1730 return 0;
1731 default:
1732 dev_err(adev->dev, "Invalid performance level %d\n", level);
1733 return -EINVAL;
1734 }
1735
1736 /*
1737 * Separate MCLK and SOCCLK soft min/max settings are not allowed
1738 * on Arcturus.
1739 */
1740 if (adev->asic_type == CHIP_ARCTURUS) {
1741 mclk_min = mclk_max = 0;
1742 socclk_min = socclk_max = 0;
1743 }
1744
1745 if (sclk_min && sclk_max) {
1746 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1747 SMU_GFXCLK,
1748 sclk_min,
1749 sclk_max);
1750 if (ret)
1751 return ret;
1752 }
1753
1754 if (mclk_min && mclk_max) {
1755 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1756 SMU_MCLK,
1757 mclk_min,
1758 mclk_max);
1759 if (ret)
1760 return ret;
1761 }
1762
1763 if (socclk_min && socclk_max) {
1764 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1765 SMU_SOCCLK,
1766 socclk_min,
1767 socclk_max);
1768 if (ret)
1769 return ret;
1770 }
1771
1772 return ret;
1773}
1774
1775int smu_v11_0_set_power_source(struct smu_context *smu,
1776 enum smu_power_src_type power_src)
1777{
1778 int pwr_source;
1779
1780 pwr_source = smu_cmn_to_asic_specific_index(smu,
1781 CMN2ASIC_MAPPING_PWR,
1782 (uint32_t)power_src);
1783 if (pwr_source < 0)
1784 return -EINVAL;
1785
1786 return smu_cmn_send_smc_msg_with_param(smu,
1787 SMU_MSG_NotifyPowerSource,
1788 pwr_source,
1789 NULL);
1790}
1791
1792int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
1793 enum smu_clk_type clk_type,
1794 uint16_t level,
1795 uint32_t *value)
1796{
1797 int ret = 0, clk_id = 0;
1798 uint32_t param;
1799
1800 if (!value)
1801 return -EINVAL;
1802
1803 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1804 return 0;
1805
1806 clk_id = smu_cmn_to_asic_specific_index(smu,
1807 CMN2ASIC_MAPPING_CLK,
1808 clk_type);
1809 if (clk_id < 0)
1810 return clk_id;
1811
1812 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1813
1814 ret = smu_cmn_send_smc_msg_with_param(smu,
1815 SMU_MSG_GetDpmFreqByIndex,
1816 param,
1817 value);
1818 if (ret)
1819 return ret;
1820
1821 /*
1822 * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
1823 * now, we un-support it
1824 */
1825 *value = *value & 0x7fffffff;
1826
1827 return ret;
1828}
1829
1830int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
1831 enum smu_clk_type clk_type,
1832 uint32_t *value)
1833{
1834 return smu_v11_0_get_dpm_freq_by_index(smu,
1835 clk_type,
1836 0xff,
1837 value);
1838}
1839
1840int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
1841 enum smu_clk_type clk_type,
1842 struct smu_11_0_dpm_table *single_dpm_table)
1843{
1844 int ret = 0;
1845 uint32_t clk;
1846 int i;
1847
1848 ret = smu_v11_0_get_dpm_level_count(smu,
1849 clk_type,
1850 &single_dpm_table->count);
1851 if (ret) {
1852 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1853 return ret;
1854 }
1855
1856 for (i = 0; i < single_dpm_table->count; i++) {
1857 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1858 clk_type,
1859 i,
1860 &clk);
1861 if (ret) {
1862 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1863 return ret;
1864 }
1865
1866 single_dpm_table->dpm_levels[i].value = clk;
1867 single_dpm_table->dpm_levels[i].enabled = true;
1868
1869 if (i == 0)
1870 single_dpm_table->min = clk;
1871 else if (i == single_dpm_table->count - 1)
1872 single_dpm_table->max = clk;
1873 }
1874
1875 return 0;
1876}
1877
1878int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
1879 enum smu_clk_type clk_type,
1880 uint32_t *min_value,
1881 uint32_t *max_value)
1882{
1883 uint32_t level_count = 0;
1884 int ret = 0;
1885
1886 if (!min_value && !max_value)
1887 return -EINVAL;
1888
1889 if (min_value) {
1890 /* by default, level 0 clock value as min value */
1891 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1892 clk_type,
1893 0,
1894 min_value);
1895 if (ret)
1896 return ret;
1897 }
1898
1899 if (max_value) {
1900 ret = smu_v11_0_get_dpm_level_count(smu,
1901 clk_type,
1902 &level_count);
1903 if (ret)
1904 return ret;
1905
1906 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1907 clk_type,
1908 level_count - 1,
1909 max_value);
1910 if (ret)
1911 return ret;
1912 }
1913
1914 return ret;
1915}