1/*
 2 * Copyright 2020 Advanced Micro Devices, Inc.
 3 *
 4 * Permission is hereby granted, free of charge, to any person obtaining a
 5 * copy of this software and associated documentation files (the "Software"),
 6 * to deal in the Software without restriction, including without limitation
 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 8 * and/or sell copies of the Software, and to permit persons to whom the
 9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __SMU_CMN_H__
24#define __SMU_CMN_H__
25
26#include "amdgpu_smu.h"
27
28#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) || defined(SWSMU_CODE_LAYER_L4)
29int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
30				    enum smu_message_type msg,
31				    uint32_t param,
32				    uint32_t *read_arg);
33
34int smu_cmn_send_smc_msg(struct smu_context *smu,
35			 enum smu_message_type msg,
36			 uint32_t *read_arg);
37
38int smu_cmn_to_asic_specific_index(struct smu_context *smu,
39				   enum smu_cmn2asic_mapping_type type,
40				   uint32_t index);
41
42int smu_cmn_feature_is_supported(struct smu_context *smu,
43				 enum smu_feature_mask mask);
44
45int smu_cmn_feature_is_enabled(struct smu_context *smu,
46			       enum smu_feature_mask mask);
47
48bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
49				enum smu_clk_type clk_type);
50
51int smu_cmn_get_enabled_mask(struct smu_context *smu,
52			     uint32_t *feature_mask,
53			     uint32_t num);
54
55int smu_cmn_feature_set_enabled(struct smu_context *smu,
56				enum smu_feature_mask mask,
57				bool enable);
58
59size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
60				   char *buf);
61
62int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
63				uint64_t new_mask);
64
65int smu_cmn_disable_all_features_with_exception(struct smu_context *smu,
66						enum smu_feature_mask mask);
67
68int smu_cmn_get_smc_version(struct smu_context *smu,
69			    uint32_t *if_version,
70			    uint32_t *smu_version);
71
72int smu_cmn_update_table(struct smu_context *smu,
73			 enum smu_table_id table_index,
74			 int argument,
75			 void *table_data,
76			 bool drv2smu);
77
78int smu_cmn_write_watermarks_table(struct smu_context *smu);
79
80int smu_cmn_write_pptable(struct smu_context *smu);
81
82#endif
83#endif