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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22#ifndef __AMDGPU_SMU_H__
23#define __AMDGPU_SMU_H__
24
25#include "amdgpu.h"
26#include "kgd_pp_interface.h"
27#include "dm_pp_interface.h"
28#include "dm_pp_smu.h"
29#include "smu_types.h"
30
31#define SMU_THERMAL_MINIMUM_ALERT_TEMP 0
32#define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255
33#define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
34
35struct smu_hw_power_state {
36 unsigned int magic;
37};
38
39struct smu_power_state;
40
41enum smu_state_ui_label {
42 SMU_STATE_UI_LABEL_NONE,
43 SMU_STATE_UI_LABEL_BATTERY,
44 SMU_STATE_UI_TABEL_MIDDLE_LOW,
45 SMU_STATE_UI_LABEL_BALLANCED,
46 SMU_STATE_UI_LABEL_MIDDLE_HIGHT,
47 SMU_STATE_UI_LABEL_PERFORMANCE,
48 SMU_STATE_UI_LABEL_BACO,
49};
50
51enum smu_state_classification_flag {
52 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001,
53 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002,
54 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004,
55 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008,
56 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010,
57 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020,
58 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040,
59 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080,
60 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100,
61 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200,
62 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400,
63 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800,
64 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000,
65 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000,
66 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000,
67 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000,
68 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000,
69 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000,
70 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000,
71 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000,
72 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000,
73};
74
75struct smu_state_classification_block {
76 enum smu_state_ui_label ui_label;
77 enum smu_state_classification_flag flags;
78 int bios_index;
79 bool temporary_state;
80 bool to_be_deleted;
81};
82
83struct smu_state_pcie_block {
84 unsigned int lanes;
85};
86
87enum smu_refreshrate_source {
88 SMU_REFRESHRATE_SOURCE_EDID,
89 SMU_REFRESHRATE_SOURCE_EXPLICIT
90};
91
92struct smu_state_display_block {
93 bool disable_frame_modulation;
94 bool limit_refreshrate;
95 enum smu_refreshrate_source refreshrate_source;
96 int explicit_refreshrate;
97 int edid_refreshrate_index;
98 bool enable_vari_bright;
99};
100
101struct smu_state_memroy_block {
102 bool dll_off;
103 uint8_t m3arb;
104 uint8_t unused[3];
105};
106
107struct smu_state_software_algorithm_block {
108 bool disable_load_balancing;
109 bool enable_sleep_for_timestamps;
110};
111
112struct smu_temperature_range {
113 int min;
114 int max;
115 int edge_emergency_max;
116 int hotspot_min;
117 int hotspot_crit_max;
118 int hotspot_emergency_max;
119 int mem_min;
120 int mem_crit_max;
121 int mem_emergency_max;
122 int software_shutdown_temp;
123};
124
125struct smu_state_validation_block {
126 bool single_display_only;
127 bool disallow_on_dc;
128 uint8_t supported_power_levels;
129};
130
131struct smu_uvd_clocks {
132 uint32_t vclk;
133 uint32_t dclk;
134};
135
136/**
137* Structure to hold a SMU Power State.
138*/
139struct smu_power_state {
140 uint32_t id;
141 struct list_head ordered_list;
142 struct list_head all_states_list;
143
144 struct smu_state_classification_block classification;
145 struct smu_state_validation_block validation;
146 struct smu_state_pcie_block pcie;
147 struct smu_state_display_block display;
148 struct smu_state_memroy_block memory;
149 struct smu_state_software_algorithm_block software;
150 struct smu_uvd_clocks uvd_clocks;
151 struct smu_hw_power_state hardware;
152};
153
154enum smu_power_src_type
155{
156 SMU_POWER_SOURCE_AC,
157 SMU_POWER_SOURCE_DC,
158 SMU_POWER_SOURCE_COUNT,
159};
160
161enum smu_memory_pool_size
162{
163 SMU_MEMORY_POOL_SIZE_ZERO = 0,
164 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
165 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
166 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000,
167 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
168};
169
170#define SMU_TABLE_INIT(tables, table_id, s, a, d) \
171 do { \
172 tables[table_id].size = s; \
173 tables[table_id].align = a; \
174 tables[table_id].domain = d; \
175 } while (0)
176
177struct smu_table {
178 uint64_t size;
179 uint32_t align;
180 uint8_t domain;
181 uint64_t mc_address;
182 void *cpu_addr;
183 struct amdgpu_bo *bo;
184};
185
186enum smu_perf_level_designation {
187 PERF_LEVEL_ACTIVITY,
188 PERF_LEVEL_POWER_CONTAINMENT,
189};
190
191struct smu_performance_level {
192 uint32_t core_clock;
193 uint32_t memory_clock;
194 uint32_t vddc;
195 uint32_t vddci;
196 uint32_t non_local_mem_freq;
197 uint32_t non_local_mem_width;
198};
199
200struct smu_clock_info {
201 uint32_t min_mem_clk;
202 uint32_t max_mem_clk;
203 uint32_t min_eng_clk;
204 uint32_t max_eng_clk;
205 uint32_t min_bus_bandwidth;
206 uint32_t max_bus_bandwidth;
207};
208
209struct smu_bios_boot_up_values
210{
211 uint32_t revision;
212 uint32_t gfxclk;
213 uint32_t uclk;
214 uint32_t socclk;
215 uint32_t dcefclk;
216 uint32_t eclk;
217 uint32_t vclk;
218 uint32_t dclk;
219 uint16_t vddc;
220 uint16_t vddci;
221 uint16_t mvddc;
222 uint16_t vdd_gfx;
223 uint8_t cooling_id;
224 uint32_t pp_table_id;
225 uint32_t format_revision;
226 uint32_t content_revision;
227 uint32_t fclk;
228};
229
230enum smu_table_id
231{
232 SMU_TABLE_PPTABLE = 0,
233 SMU_TABLE_WATERMARKS,
234 SMU_TABLE_CUSTOM_DPM,
235 SMU_TABLE_DPMCLOCKS,
236 SMU_TABLE_AVFS,
237 SMU_TABLE_AVFS_PSM_DEBUG,
238 SMU_TABLE_AVFS_FUSE_OVERRIDE,
239 SMU_TABLE_PMSTATUSLOG,
240 SMU_TABLE_SMU_METRICS,
241 SMU_TABLE_DRIVER_SMU_CONFIG,
242 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
243 SMU_TABLE_OVERDRIVE,
244 SMU_TABLE_I2C_COMMANDS,
245 SMU_TABLE_PACE,
246 SMU_TABLE_COUNT,
247};
248
249struct smu_table_context
250{
251 void *power_play_table;
252 uint32_t power_play_table_size;
253 void *hardcode_pptable;
254 unsigned long metrics_time;
255 void *metrics_table;
256 void *clocks_table;
257 void *watermarks_table;
258
259 void *max_sustainable_clocks;
260 struct smu_bios_boot_up_values boot_values;
261 void *driver_pptable;
262 struct smu_table tables[SMU_TABLE_COUNT];
263 /*
264 * The driver table is just a staging buffer for
265 * uploading/downloading content from the SMU.
266 *
267 * And the table_id for SMU_MSG_TransferTableSmu2Dram/
268 * SMU_MSG_TransferTableDram2Smu instructs SMU
269 * which content driver is interested.
270 */
271 struct smu_table driver_table;
272 struct smu_table memory_pool;
273 uint8_t thermal_controller_type;
274
275 void *overdrive_table;
276 void *boot_overdrive_table;
277};
278
279struct smu_dpm_context {
280 uint32_t dpm_context_size;
281 void *dpm_context;
282 void *golden_dpm_context;
283 bool enable_umd_pstate;
284 enum amd_dpm_forced_level dpm_level;
285 enum amd_dpm_forced_level saved_dpm_level;
286 enum amd_dpm_forced_level requested_dpm_level;
287 struct smu_power_state *dpm_request_power_state;
288 struct smu_power_state *dpm_current_power_state;
289 struct mclock_latency_table *mclk_latency_table;
290};
291
292struct smu_power_gate {
293 bool uvd_gated;
294 bool vce_gated;
295 atomic_t vcn_gated;
296 atomic_t jpeg_gated;
297 struct mutex vcn_gate_lock;
298 struct mutex jpeg_gate_lock;
299};
300
301struct smu_power_context {
302 void *power_context;
303 uint32_t power_context_size;
304 struct smu_power_gate power_gate;
305};
306
307
308#define SMU_FEATURE_MAX (64)
309struct smu_feature
310{
311 uint32_t feature_num;
312 DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
313 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
314 DECLARE_BITMAP(enabled, SMU_FEATURE_MAX);
315 struct mutex mutex;
316};
317
318struct smu_clocks {
319 uint32_t engine_clock;
320 uint32_t memory_clock;
321 uint32_t bus_bandwidth;
322 uint32_t engine_clock_in_sr;
323 uint32_t dcef_clock;
324 uint32_t dcef_clock_in_sr;
325};
326
327#define MAX_REGULAR_DPM_NUM 16
328struct mclk_latency_entries {
329 uint32_t frequency;
330 uint32_t latency;
331};
332struct mclock_latency_table {
333 uint32_t count;
334 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM];
335};
336
337enum smu_reset_mode
338{
339 SMU_RESET_MODE_0,
340 SMU_RESET_MODE_1,
341 SMU_RESET_MODE_2,
342};
343
344enum smu_baco_state
345{
346 SMU_BACO_STATE_ENTER = 0,
347 SMU_BACO_STATE_EXIT,
348};
349
350struct smu_baco_context
351{
352 struct mutex mutex;
353 uint32_t state;
354 bool platform_support;
355};
356
357struct pstates_clk_freq {
358 uint32_t min;
359 uint32_t standard;
360 uint32_t peak;
361};
362
363struct smu_umd_pstate_table {
364 struct pstates_clk_freq gfxclk_pstate;
365 struct pstates_clk_freq socclk_pstate;
366 struct pstates_clk_freq uclk_pstate;
367 struct pstates_clk_freq vclk_pstate;
368 struct pstates_clk_freq dclk_pstate;
369};
370
371struct cmn2asic_msg_mapping {
372 int valid_mapping;
373 int map_to;
374 int valid_in_vf;
375};
376
377struct cmn2asic_mapping {
378 int valid_mapping;
379 int map_to;
380};
381
382#define WORKLOAD_POLICY_MAX 7
383struct smu_context
384{
385 struct amdgpu_device *adev;
386 struct amdgpu_irq_src irq_source;
387
388 const struct pptable_funcs *ppt_funcs;
389 const struct cmn2asic_msg_mapping *message_map;
390 const struct cmn2asic_mapping *clock_map;
391 const struct cmn2asic_mapping *feature_map;
392 const struct cmn2asic_mapping *table_map;
393 const struct cmn2asic_mapping *pwr_src_map;
394 const struct cmn2asic_mapping *workload_map;
395 struct mutex mutex;
396 struct mutex sensor_lock;
397 struct mutex metrics_lock;
398 struct mutex message_lock;
399 uint64_t pool_size;
400
401 struct smu_table_context smu_table;
402 struct smu_dpm_context smu_dpm;
403 struct smu_power_context smu_power;
404 struct smu_feature smu_feature;
405 struct amd_pp_display_configuration *display_config;
406 struct smu_baco_context smu_baco;
407 struct smu_temperature_range thermal_range;
408 void *od_settings;
409#if defined(CONFIG_DEBUG_FS)
410 struct dentry *debugfs_sclk;
411#endif
412
413 struct smu_umd_pstate_table pstate_table;
414 uint32_t pstate_sclk;
415 uint32_t pstate_mclk;
416
417 bool od_enabled;
418 uint32_t current_power_limit;
419 uint32_t max_power_limit;
420
421 /* soft pptable */
422 uint32_t ppt_offset_bytes;
423 uint32_t ppt_size_bytes;
424 uint8_t *ppt_start_addr;
425
426 bool support_power_containment;
427 bool disable_watermark;
428
429#define WATERMARKS_EXIST (1 << 0)
430#define WATERMARKS_LOADED (1 << 1)
431 uint32_t watermarks_bitmap;
432 uint32_t hard_min_uclk_req_from_dal;
433 bool disable_uclk_switch;
434
435 uint32_t workload_mask;
436 uint32_t workload_prority[WORKLOAD_POLICY_MAX];
437 uint32_t workload_setting[WORKLOAD_POLICY_MAX];
438 uint32_t power_profile_mode;
439 uint32_t default_power_profile_mode;
440 bool pm_enabled;
441 bool is_apu;
442
443 uint32_t smc_driver_if_version;
444 uint32_t smc_fw_if_version;
445 uint32_t smc_fw_version;
446
447 bool uploading_custom_pp_table;
448 bool dc_controlled_by_gpio;
449
450 struct work_struct throttling_logging_work;
451};
452
453struct i2c_adapter;
454
455struct pptable_funcs {
456 int (*run_btc)(struct smu_context *smu);
457 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
458 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
459 int (*set_default_dpm_table)(struct smu_context *smu);
460 int (*set_power_state)(struct smu_context *smu);
461 int (*populate_umd_state_clk)(struct smu_context *smu);
462 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
463 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
464 int (*set_default_od8_settings)(struct smu_context *smu);
465 int (*get_od_percentage)(struct smu_context *smu, enum smu_clk_type clk_type);
466 int (*set_od_percentage)(struct smu_context *smu,
467 enum smu_clk_type clk_type,
468 uint32_t value);
469 int (*od_edit_dpm_table)(struct smu_context *smu,
470 enum PP_OD_DPM_TABLE_COMMAND type,
471 long *input, uint32_t size);
472 int (*get_clock_by_type_with_latency)(struct smu_context *smu,
473 enum smu_clk_type clk_type,
474 struct
475 pp_clock_levels_with_latency
476 *clocks);
477 int (*get_clock_by_type_with_voltage)(struct smu_context *smu,
478 enum amd_pp_clock_type type,
479 struct
480 pp_clock_levels_with_voltage
481 *clocks);
482 int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
483 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
484 int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable);
485 int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable);
486 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
487 void *data, uint32_t *size);
488 int (*pre_display_config_changed)(struct smu_context *smu);
489 int (*display_config_changed)(struct smu_context *smu);
490 int (*apply_clocks_adjust_rules)(struct smu_context *smu);
491 int (*notify_smc_display_config)(struct smu_context *smu);
492 int (*set_cpu_power_state)(struct smu_context *smu);
493 bool (*is_dpm_running)(struct smu_context *smu);
494 int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
495 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
496 int (*set_watermarks_table)(struct smu_context *smu,
497 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
498 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
499 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
500 int (*set_default_od_settings)(struct smu_context *smu);
501 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
502 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
503 void (*dump_pptable)(struct smu_context *smu);
504 int (*get_power_limit)(struct smu_context *smu);
505 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
506 int (*allow_xgmi_power_down)(struct smu_context *smu, bool en);
507 int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
508 int (*i2c_init)(struct smu_context *smu, struct i2c_adapter *control);
509 void (*i2c_fini)(struct smu_context *smu, struct i2c_adapter *control);
510 void (*get_unique_id)(struct smu_context *smu);
511 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);
512 int (*init_microcode)(struct smu_context *smu);
513 int (*load_microcode)(struct smu_context *smu);
514 void (*fini_microcode)(struct smu_context *smu);
515 int (*init_smc_tables)(struct smu_context *smu);
516 int (*fini_smc_tables)(struct smu_context *smu);
517 int (*init_power)(struct smu_context *smu);
518 int (*fini_power)(struct smu_context *smu);
519 int (*check_fw_status)(struct smu_context *smu);
520 int (*setup_pptable)(struct smu_context *smu);
521 int (*get_vbios_bootup_values)(struct smu_context *smu);
522 int (*check_fw_version)(struct smu_context *smu);
523 int (*powergate_sdma)(struct smu_context *smu, bool gate);
524 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
525 int (*write_pptable)(struct smu_context *smu);
526 int (*set_driver_table_location)(struct smu_context *smu);
527 int (*set_tool_table_location)(struct smu_context *smu);
528 int (*notify_memory_pool_location)(struct smu_context *smu);
529 int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu);
530 int (*system_features_control)(struct smu_context *smu, bool en);
531 int (*send_smc_msg_with_param)(struct smu_context *smu,
532 enum smu_message_type msg, uint32_t param, uint32_t *read_arg);
533 int (*send_smc_msg)(struct smu_context *smu,
534 enum smu_message_type msg,
535 uint32_t *read_arg);
536 int (*init_display_count)(struct smu_context *smu, uint32_t count);
537 int (*set_allowed_mask)(struct smu_context *smu);
538 int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
539 int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask);
540 int (*disable_all_features_with_exception)(struct smu_context *smu, enum smu_feature_mask mask);
541 int (*notify_display_change)(struct smu_context *smu);
542 int (*set_power_limit)(struct smu_context *smu, uint32_t n);
543 int (*init_max_sustainable_clocks)(struct smu_context *smu);
544 int (*enable_thermal_alert)(struct smu_context *smu);
545 int (*disable_thermal_alert)(struct smu_context *smu);
546 int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk);
547 int (*set_active_display_count)(struct smu_context *smu, uint32_t count);
548 int (*store_cc6_data)(struct smu_context *smu, uint32_t separation_time,
549 bool cc6_disable, bool pstate_disable,
550 bool pstate_switch_disable);
551 int (*get_clock_by_type)(struct smu_context *smu,
552 enum amd_pp_clock_type type,
553 struct amd_pp_clocks *clocks);
554 int (*get_max_high_clocks)(struct smu_context *smu,
555 struct amd_pp_simple_clock_info *clocks);
556 int (*display_clock_voltage_request)(struct smu_context *smu, struct
557 pp_display_clock_request
558 *clock_req);
559 int (*get_dal_power_level)(struct smu_context *smu,
560 struct amd_pp_simple_clock_info *clocks);
561 int (*get_perf_level)(struct smu_context *smu,
562 enum smu_perf_level_designation designation,
563 struct smu_performance_level *level);
564 int (*get_current_shallow_sleep_clocks)(struct smu_context *smu,
565 struct smu_clock_info *clocks);
566 int (*notify_smu_enable_pwe)(struct smu_context *smu);
567 int (*conv_power_profile_to_pplib_workload)(int power_profile);
568 uint32_t (*get_fan_control_mode)(struct smu_context *smu);
569 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
570 int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
571 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
572 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
573 int (*gfx_off_control)(struct smu_context *smu, bool enable);
574 uint32_t (*get_gfx_off_status)(struct smu_context *smu);
575 int (*register_irq_handler)(struct smu_context *smu);
576 int (*set_azalia_d3_pme)(struct smu_context *smu);
577 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);
578 bool (*baco_is_support)(struct smu_context *smu);
579 enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
580 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
581 int (*baco_enter)(struct smu_context *smu);
582 int (*baco_exit)(struct smu_context *smu);
583 bool (*mode1_reset_is_support)(struct smu_context *smu);
584 int (*mode1_reset)(struct smu_context *smu);
585 int (*mode2_reset)(struct smu_context *smu);
586 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
587 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
588 int (*disable_umc_cdr_12gbps_workaround)(struct smu_context *smu);
589 int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src);
590 void (*log_thermal_throttling_event)(struct smu_context *smu);
591 size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf);
592 int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask);
593};
594
595typedef enum {
596 METRICS_CURR_GFXCLK,
597 METRICS_CURR_SOCCLK,
598 METRICS_CURR_UCLK,
599 METRICS_CURR_VCLK,
600 METRICS_CURR_VCLK1,
601 METRICS_CURR_DCLK,
602 METRICS_CURR_DCLK1,
603 METRICS_CURR_FCLK,
604 METRICS_CURR_DCEFCLK,
605 METRICS_AVERAGE_GFXCLK,
606 METRICS_AVERAGE_SOCCLK,
607 METRICS_AVERAGE_FCLK,
608 METRICS_AVERAGE_UCLK,
609 METRICS_AVERAGE_VCLK,
610 METRICS_AVERAGE_DCLK,
611 METRICS_AVERAGE_GFXACTIVITY,
612 METRICS_AVERAGE_MEMACTIVITY,
613 METRICS_AVERAGE_VCNACTIVITY,
614 METRICS_AVERAGE_SOCKETPOWER,
615 METRICS_TEMPERATURE_EDGE,
616 METRICS_TEMPERATURE_HOTSPOT,
617 METRICS_TEMPERATURE_MEM,
618 METRICS_TEMPERATURE_VRGFX,
619 METRICS_TEMPERATURE_VRSOC,
620 METRICS_TEMPERATURE_VRMEM,
621 METRICS_THROTTLER_STATUS,
622 METRICS_CURR_FANSPEED,
623} MetricsMember_t;
624
625enum smu_cmn2asic_mapping_type {
626 CMN2ASIC_MAPPING_MSG,
627 CMN2ASIC_MAPPING_CLK,
628 CMN2ASIC_MAPPING_FEATURE,
629 CMN2ASIC_MAPPING_TABLE,
630 CMN2ASIC_MAPPING_PWR,
631 CMN2ASIC_MAPPING_WORKLOAD,
632};
633
634#define MSG_MAP(msg, index, valid_in_vf) \
635 [SMU_MSG_##msg] = {1, (index), (valid_in_vf)}
636
637#define CLK_MAP(clk, index) \
638 [SMU_##clk] = {1, (index)}
639
640#define FEA_MAP(fea) \
641 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT}
642
643#define TAB_MAP(tab) \
644 [SMU_TABLE_##tab] = {1, TABLE_##tab}
645
646#define TAB_MAP_VALID(tab) \
647 [SMU_TABLE_##tab] = {1, TABLE_##tab}
648
649#define TAB_MAP_INVALID(tab) \
650 [SMU_TABLE_##tab] = {0, TABLE_##tab}
651
652#define PWR_MAP(tab) \
653 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab}
654
655#define WORKLOAD_MAP(profile, workload) \
656 [profile] = {1, (workload)}
657
658#if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)
659int smu_load_microcode(struct smu_context *smu);
660
661int smu_check_fw_status(struct smu_context *smu);
662
663int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
664
665int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);
666
667int smu_get_power_limit(struct smu_context *smu,
668 uint32_t *limit,
669 bool max_setting);
670
671int smu_set_power_limit(struct smu_context *smu, uint32_t limit);
672int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
673int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type);
674int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value);
675
676int smu_od_edit_dpm_table(struct smu_context *smu,
677 enum PP_OD_DPM_TABLE_COMMAND type,
678 long *input, uint32_t size);
679
680int smu_read_sensor(struct smu_context *smu,
681 enum amd_pp_sensors sensor,
682 void *data, uint32_t *size);
683int smu_get_power_profile_mode(struct smu_context *smu, char *buf);
684
685int smu_set_power_profile_mode(struct smu_context *smu,
686 long *param,
687 uint32_t param_size,
688 bool lock_needed);
689int smu_get_fan_control_mode(struct smu_context *smu);
690int smu_set_fan_control_mode(struct smu_context *smu, int value);
691int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed);
692int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
693int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed);
694
695int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk);
696int smu_set_active_display_count(struct smu_context *smu, uint32_t count);
697
698int smu_get_clock_by_type(struct smu_context *smu,
699 enum amd_pp_clock_type type,
700 struct amd_pp_clocks *clocks);
701
702int smu_get_max_high_clocks(struct smu_context *smu,
703 struct amd_pp_simple_clock_info *clocks);
704
705int smu_get_clock_by_type_with_latency(struct smu_context *smu,
706 enum smu_clk_type clk_type,
707 struct pp_clock_levels_with_latency *clocks);
708
709int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
710 enum amd_pp_clock_type type,
711 struct pp_clock_levels_with_voltage *clocks);
712
713int smu_display_clock_voltage_request(struct smu_context *smu,
714 struct pp_display_clock_request *clock_req);
715int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch);
716int smu_notify_smu_enable_pwe(struct smu_context *smu);
717
718int smu_set_xgmi_pstate(struct smu_context *smu,
719 uint32_t pstate);
720
721int smu_set_azalia_d3_pme(struct smu_context *smu);
722
723bool smu_baco_is_support(struct smu_context *smu);
724
725int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state);
726
727int smu_baco_enter(struct smu_context *smu);
728int smu_baco_exit(struct smu_context *smu);
729
730bool smu_mode1_reset_is_support(struct smu_context *smu);
731int smu_mode1_reset(struct smu_context *smu);
732int smu_mode2_reset(struct smu_context *smu);
733
734extern const struct amd_ip_funcs smu_ip_funcs;
735
736extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
737extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
738
739bool is_support_sw_smu(struct amdgpu_device *adev);
740int smu_reset(struct smu_context *smu);
741int smu_sys_get_pp_table(struct smu_context *smu, void **table);
742int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
743int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info);
744enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
745int smu_write_watermarks_table(struct smu_context *smu);
746int smu_set_watermarks_for_clock_ranges(
747 struct smu_context *smu,
748 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
749
750/* smu to display interface */
751extern int smu_display_configuration_change(struct smu_context *smu, const
752 struct amd_pp_display_configuration
753 *display_config);
754extern int smu_get_current_clocks(struct smu_context *smu,
755 struct amd_pp_clock_info *clocks);
756extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
757extern int smu_handle_task(struct smu_context *smu,
758 enum amd_dpm_forced_level level,
759 enum amd_pp_task task_id,
760 bool lock_needed);
761int smu_switch_power_profile(struct smu_context *smu,
762 enum PP_SMC_POWER_PROFILE type,
763 bool en);
764int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
765 uint32_t *min, uint32_t *max);
766int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
767 uint32_t min, uint32_t max);
768enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
769int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
770int smu_set_display_count(struct smu_context *smu, uint32_t count);
771int smu_set_ac_dc(struct smu_context *smu);
772size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
773int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
774int smu_force_clk_levels(struct smu_context *smu,
775 enum smu_clk_type clk_type,
776 uint32_t mask);
777int smu_set_mp1_state(struct smu_context *smu,
778 enum pp_mp1_state mp1_state);
779int smu_set_df_cstate(struct smu_context *smu,
780 enum pp_df_cstate state);
781int smu_allow_xgmi_power_down(struct smu_context *smu, bool en);
782
783int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
784 struct pp_smu_nv_clock_table *max_clocks);
785
786int smu_get_uclk_dpm_states(struct smu_context *smu,
787 unsigned int *clock_values_in_khz,
788 unsigned int *num_states);
789
790int smu_get_dpm_clock_table(struct smu_context *smu,
791 struct dpm_clocks *clock_table);
792
793int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value);
794
795#endif
796#endif