1/*
 2 * Copyright 2019 Advanced Micro Devices, Inc.
 3 *
 4 * Permission is hereby granted, free of charge, to any person obtaining a
 5 * copy of this software and associated documentation files (the "Software"),
 6 * to deal in the Software without restriction, including without limitation
 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 8 * and/or sell copies of the Software, and to permit persons to whom the
 9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
27#define AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
28
29struct drm_crtc;
30struct dm_crtc_state;
31
32enum amdgpu_dm_pipe_crc_source {
33	AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0,
34	AMDGPU_DM_PIPE_CRC_SOURCE_CRTC,
35	AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER,
36	AMDGPU_DM_PIPE_CRC_SOURCE_DPRX,
37	AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER,
38	AMDGPU_DM_PIPE_CRC_SOURCE_MAX,
39	AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1,
40};
41
42static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source)
43{
44	return (source > AMDGPU_DM_PIPE_CRC_SOURCE_NONE) &&
45	       (source < AMDGPU_DM_PIPE_CRC_SOURCE_MAX);
46}
47
48/* amdgpu_dm_crc.c */
49#ifdef CONFIG_DEBUG_FS
50int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
51					struct dm_crtc_state *dm_crtc_state,
52					enum amdgpu_dm_pipe_crc_source source);
53int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
54int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
55				     const char *src_name,
56				     size_t *values_cnt);
57const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
58						  size_t *count);
59void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
60#else
61#define amdgpu_dm_crtc_set_crc_source NULL
62#define amdgpu_dm_crtc_verify_crc_source NULL
63#define amdgpu_dm_crtc_get_crc_sources NULL
64#define amdgpu_dm_crtc_handle_crc_irq(x)
65#endif
66
67#endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */