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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include "amdgpu.h"
26#include "amdgpu_vcn.h"
27#include "amdgpu_pm.h"
28#include "soc15.h"
29#include "soc15d.h"
30#include "vcn_v2_0.h"
31#include "mmsch_v3_0.h"
32
33#include "vcn/vcn_3_0_0_offset.h"
34#include "vcn/vcn_3_0_0_sh_mask.h"
35#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
36
37#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27
38#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f
39#define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10
40#define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11
41#define mmUVD_NO_OP_INTERNAL_OFFSET 0x29
42#define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66
43#define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d
44
45#define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431
46#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4
47#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5
48#define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c
49
50#define VCN_INSTANCES_SIENNA_CICHLID 2
51
52static int amdgpu_ih_clientid_vcns[] = {
53 SOC15_IH_CLIENTID_VCN,
54 SOC15_IH_CLIENTID_VCN1
55};
56
57static int amdgpu_ucode_id_vcns[] = {
58 AMDGPU_UCODE_ID_VCN,
59 AMDGPU_UCODE_ID_VCN1
60};
61
62static int vcn_v3_0_start_sriov(struct amdgpu_device *adev);
63static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
64static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev);
65static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev);
66static int vcn_v3_0_set_powergating_state(void *handle,
67 enum amd_powergating_state state);
68static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
69 int inst_idx, struct dpg_pause_state *new_state);
70
71static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring);
72static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring);
73
74/**
75 * vcn_v3_0_early_init - set function pointers
76 *
77 * @handle: amdgpu_device pointer
78 *
79 * Set ring and irq function pointers
80 */
81static int vcn_v3_0_early_init(void *handle)
82{
83 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
84
85 if (amdgpu_sriov_vf(adev)) {
86 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
87 adev->vcn.harvest_config = 0;
88 adev->vcn.num_enc_rings = 1;
89
90 } else {
91 if (adev->asic_type == CHIP_SIENNA_CICHLID) {
92 u32 harvest;
93 int i;
94
95 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
96 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
97 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING);
98 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
99 adev->vcn.harvest_config |= 1 << i;
100 }
101
102 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |
103 AMDGPU_VCN_HARVEST_VCN1))
104 /* both instances are harvested, disable the block */
105 return -ENOENT;
106 } else
107 adev->vcn.num_vcn_inst = 1;
108
109 adev->vcn.num_enc_rings = 2;
110 }
111
112 vcn_v3_0_set_dec_ring_funcs(adev);
113 vcn_v3_0_set_enc_ring_funcs(adev);
114 vcn_v3_0_set_irq_funcs(adev);
115
116 return 0;
117}
118
119/**
120 * vcn_v3_0_sw_init - sw init for VCN block
121 *
122 * @handle: amdgpu_device pointer
123 *
124 * Load firmware and sw initialization
125 */
126static int vcn_v3_0_sw_init(void *handle)
127{
128 struct amdgpu_ring *ring;
129 int i, j, r;
130 int vcn_doorbell_index = 0;
131 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
132
133 r = amdgpu_vcn_sw_init(adev);
134 if (r)
135 return r;
136
137 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
138 const struct common_firmware_header *hdr;
139 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
140 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
141 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
142 adev->firmware.fw_size +=
143 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
144
145 if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) {
146 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1;
147 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw;
148 adev->firmware.fw_size +=
149 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
150 }
151 DRM_INFO("PSP loading VCN firmware\n");
152 }
153
154 r = amdgpu_vcn_resume(adev);
155 if (r)
156 return r;
157
158 if (amdgpu_sriov_vf(adev)) {
159 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1;
160 /* get DWORD offset */
161 vcn_doorbell_index = vcn_doorbell_index << 1;
162 }
163
164 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
165 if (adev->vcn.harvest_config & (1 << i))
166 continue;
167
168 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
169 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
170 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
171 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
172 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
173 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
174
175 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
176 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9);
177 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
178 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0);
179 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
180 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1);
181 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
182 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD);
183 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
184 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP);
185
186 /* VCN DEC TRAP */
187 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
188 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq);
189 if (r)
190 return r;
191
192 ring = &adev->vcn.inst[i].ring_dec;
193 ring->use_doorbell = true;
194 if (amdgpu_sriov_vf(adev)) {
195 ring->doorbell_index = vcn_doorbell_index;
196 /* NOTE: increment so next VCN engine use next DOORBELL DWORD */
197 vcn_doorbell_index++;
198 } else {
199 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i;
200 }
201 if (i != 0)
202 ring->no_scheduler = true;
203 sprintf(ring->name, "vcn_dec_%d", i);
204 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
205 AMDGPU_RING_PRIO_DEFAULT);
206 if (r)
207 return r;
208
209 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
210 /* VCN ENC TRAP */
211 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
212 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
213 if (r)
214 return r;
215
216 ring = &adev->vcn.inst[i].ring_enc[j];
217 ring->use_doorbell = true;
218 if (amdgpu_sriov_vf(adev)) {
219 ring->doorbell_index = vcn_doorbell_index;
220 /* NOTE: increment so next VCN engine use next DOORBELL DWORD */
221 vcn_doorbell_index++;
222 } else {
223 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i;
224 }
225 if (i != 1)
226 ring->no_scheduler = true;
227 sprintf(ring->name, "vcn_enc_%d.%d", i, j);
228 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
229 AMDGPU_RING_PRIO_DEFAULT);
230 if (r)
231 return r;
232 }
233 }
234
235 if (amdgpu_sriov_vf(adev)) {
236 r = amdgpu_virt_alloc_mm_table(adev);
237 if (r)
238 return r;
239 }
240 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
241 adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode;
242
243 return 0;
244}
245
246/**
247 * vcn_v3_0_sw_fini - sw fini for VCN block
248 *
249 * @handle: amdgpu_device pointer
250 *
251 * VCN suspend and free up sw allocation
252 */
253static int vcn_v3_0_sw_fini(void *handle)
254{
255 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
256 int r;
257
258 if (amdgpu_sriov_vf(adev))
259 amdgpu_virt_free_mm_table(adev);
260
261 r = amdgpu_vcn_suspend(adev);
262 if (r)
263 return r;
264
265 r = amdgpu_vcn_sw_fini(adev);
266
267 return r;
268}
269
270/**
271 * vcn_v3_0_hw_init - start and test VCN block
272 *
273 * @handle: amdgpu_device pointer
274 *
275 * Initialize the hardware, boot up the VCPU and do some testing
276 */
277static int vcn_v3_0_hw_init(void *handle)
278{
279 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
280 struct amdgpu_ring *ring;
281 int i, j, r;
282
283 if (amdgpu_sriov_vf(adev)) {
284 r = vcn_v3_0_start_sriov(adev);
285 if (r)
286 goto done;
287
288 /* initialize VCN dec and enc ring buffers */
289 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
290 if (adev->vcn.harvest_config & (1 << i))
291 continue;
292
293 ring = &adev->vcn.inst[i].ring_dec;
294 ring->wptr = 0;
295 ring->wptr_old = 0;
296 vcn_v3_0_dec_ring_set_wptr(ring);
297 ring->sched.ready = true;
298
299 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
300 ring = &adev->vcn.inst[i].ring_enc[j];
301 ring->wptr = 0;
302 ring->wptr_old = 0;
303 vcn_v3_0_enc_ring_set_wptr(ring);
304 ring->sched.ready = true;
305 }
306 }
307 } else {
308 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
309 if (adev->vcn.harvest_config & (1 << i))
310 continue;
311
312 ring = &adev->vcn.inst[i].ring_dec;
313
314 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
315 ring->doorbell_index, i);
316
317 r = amdgpu_ring_test_helper(ring);
318 if (r)
319 goto done;
320
321 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
322 ring = &adev->vcn.inst[i].ring_enc[j];
323 r = amdgpu_ring_test_helper(ring);
324 if (r)
325 goto done;
326 }
327 }
328 }
329
330done:
331 if (!r)
332 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
333 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
334
335 return r;
336}
337
338/**
339 * vcn_v3_0_hw_fini - stop the hardware block
340 *
341 * @handle: amdgpu_device pointer
342 *
343 * Stop the VCN block, mark ring as not ready any more
344 */
345static int vcn_v3_0_hw_fini(void *handle)
346{
347 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
348 struct amdgpu_ring *ring;
349 int i, j;
350
351 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
352 if (adev->vcn.harvest_config & (1 << i))
353 continue;
354
355 ring = &adev->vcn.inst[i].ring_dec;
356
357 if (!amdgpu_sriov_vf(adev)) {
358 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
359 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
360 RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
361 vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
362 }
363 }
364 ring->sched.ready = false;
365
366 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
367 ring = &adev->vcn.inst[i].ring_enc[j];
368 ring->sched.ready = false;
369 }
370 }
371
372 return 0;
373}
374
375/**
376 * vcn_v3_0_suspend - suspend VCN block
377 *
378 * @handle: amdgpu_device pointer
379 *
380 * HW fini and suspend VCN block
381 */
382static int vcn_v3_0_suspend(void *handle)
383{
384 int r;
385 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
386
387 r = vcn_v3_0_hw_fini(adev);
388 if (r)
389 return r;
390
391 r = amdgpu_vcn_suspend(adev);
392
393 return r;
394}
395
396/**
397 * vcn_v3_0_resume - resume VCN block
398 *
399 * @handle: amdgpu_device pointer
400 *
401 * Resume firmware and hw init VCN block
402 */
403static int vcn_v3_0_resume(void *handle)
404{
405 int r;
406 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
407
408 r = amdgpu_vcn_resume(adev);
409 if (r)
410 return r;
411
412 r = vcn_v3_0_hw_init(adev);
413
414 return r;
415}
416
417/**
418 * vcn_v3_0_mc_resume - memory controller programming
419 *
420 * @adev: amdgpu_device pointer
421 * @inst: instance number
422 *
423 * Let the VCN memory controller know it's offsets
424 */
425static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst)
426{
427 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
428 uint32_t offset;
429
430 /* cache window 0: fw */
431 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
432 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
433 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));
434 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
435 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));
436 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0);
437 offset = 0;
438 } else {
439 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
440 lower_32_bits(adev->vcn.inst[inst].gpu_addr));
441 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
442 upper_32_bits(adev->vcn.inst[inst].gpu_addr));
443 offset = size;
444 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0,
445 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
446 }
447 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size);
448
449 /* cache window 1: stack */
450 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
451 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
452 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
453 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
454 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0);
455 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
456
457 /* cache window 2: context */
458 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
459 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
460 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
461 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
462 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0);
463 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
464}
465
466static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
467{
468 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
469 uint32_t offset;
470
471 /* cache window 0: fw */
472 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
473 if (!indirect) {
474 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
475 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
476 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
477 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
478 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
479 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
480 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
481 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
482 } else {
483 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
484 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
485 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
486 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
487 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
488 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
489 }
490 offset = 0;
491 } else {
492 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
493 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
494 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
495 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
496 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
497 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
498 offset = size;
499 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
500 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0),
501 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
502 }
503
504 if (!indirect)
505 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
506 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
507 else
508 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
509 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
510
511 /* cache window 1: stack */
512 if (!indirect) {
513 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
514 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
515 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
516 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
517 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
518 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
519 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
520 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
521 } else {
522 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
523 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
524 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
525 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
526 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
527 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
528 }
529 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
530 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
531
532 /* cache window 2: context */
533 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
534 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
535 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
536 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
537 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
538 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
539 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
540 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
541 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
542 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
543
544 /* non-cache window */
545 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
546 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
547 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
548 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
549 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
550 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
551 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
552 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
553}
554
555static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
556{
557 uint32_t data = 0;
558
559 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
560 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
561 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
562 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
563 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
564 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
565 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
566 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
567 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
568 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
569 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
570 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
571 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
572 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
573 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
574
575 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
576 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS,
577 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF);
578 } else {
579 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
580 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
581 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
582 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
583 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
584 | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
585 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
586 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
587 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
588 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
589 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
590 | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
591 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
592 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
593 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
594 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF);
595 }
596
597 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
598 data &= ~0x103;
599 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
600 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
601 UVD_POWER_STATUS__UVD_PG_EN_MASK;
602
603 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);
604}
605
606static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst)
607{
608 uint32_t data;
609
610 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
611 /* Before power off, this indicator has to be turned on */
612 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
613 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
614 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
615 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);
616
617 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
618 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
619 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
620 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
621 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
622 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
623 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
624 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
625 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
626 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
627 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
628 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
629 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
630 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
631 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
632
633 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
634 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
635 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
636 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
637 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
638 | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT
639 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT
640 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
641 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
642 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
643 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT
644 | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT
645 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT
646 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT);
647 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF);
648 }
649}
650
651/**
652 * vcn_v3_0_disable_clock_gating - disable VCN clock gating
653 *
654 * @adev: amdgpu_device pointer
655 * @inst: instance number
656 *
657 * Disable clock gating for VCN block
658 */
659static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
660{
661 uint32_t data;
662
663 /* VCN disable CGC */
664 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
665 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
666 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
667 else
668 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
669 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
670 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
671 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
672
673 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE);
674 data &= ~(UVD_CGC_GATE__SYS_MASK
675 | UVD_CGC_GATE__UDEC_MASK
676 | UVD_CGC_GATE__MPEG2_MASK
677 | UVD_CGC_GATE__REGS_MASK
678 | UVD_CGC_GATE__RBC_MASK
679 | UVD_CGC_GATE__LMI_MC_MASK
680 | UVD_CGC_GATE__LMI_UMC_MASK
681 | UVD_CGC_GATE__IDCT_MASK
682 | UVD_CGC_GATE__MPRD_MASK
683 | UVD_CGC_GATE__MPC_MASK
684 | UVD_CGC_GATE__LBSI_MASK
685 | UVD_CGC_GATE__LRBBM_MASK
686 | UVD_CGC_GATE__UDEC_RE_MASK
687 | UVD_CGC_GATE__UDEC_CM_MASK
688 | UVD_CGC_GATE__UDEC_IT_MASK
689 | UVD_CGC_GATE__UDEC_DB_MASK
690 | UVD_CGC_GATE__UDEC_MP_MASK
691 | UVD_CGC_GATE__WCB_MASK
692 | UVD_CGC_GATE__VCPU_MASK
693 | UVD_CGC_GATE__MMSCH_MASK);
694
695 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data);
696
697 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF);
698
699 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
700 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
701 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
702 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
703 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
704 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
705 | UVD_CGC_CTRL__SYS_MODE_MASK
706 | UVD_CGC_CTRL__UDEC_MODE_MASK
707 | UVD_CGC_CTRL__MPEG2_MODE_MASK
708 | UVD_CGC_CTRL__REGS_MODE_MASK
709 | UVD_CGC_CTRL__RBC_MODE_MASK
710 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
711 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
712 | UVD_CGC_CTRL__IDCT_MODE_MASK
713 | UVD_CGC_CTRL__MPRD_MODE_MASK
714 | UVD_CGC_CTRL__MPC_MODE_MASK
715 | UVD_CGC_CTRL__LBSI_MODE_MASK
716 | UVD_CGC_CTRL__LRBBM_MODE_MASK
717 | UVD_CGC_CTRL__WCB_MODE_MASK
718 | UVD_CGC_CTRL__VCPU_MODE_MASK
719 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
720 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
721
722 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE);
723 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
724 | UVD_SUVD_CGC_GATE__SIT_MASK
725 | UVD_SUVD_CGC_GATE__SMP_MASK
726 | UVD_SUVD_CGC_GATE__SCM_MASK
727 | UVD_SUVD_CGC_GATE__SDB_MASK
728 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
729 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
730 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
731 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
732 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
733 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
734 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
735 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
736 | UVD_SUVD_CGC_GATE__SCLR_MASK
737 | UVD_SUVD_CGC_GATE__ENT_MASK
738 | UVD_SUVD_CGC_GATE__IME_MASK
739 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
740 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
741 | UVD_SUVD_CGC_GATE__SITE_MASK
742 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
743 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
744 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
745 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
746 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK
747 | UVD_SUVD_CGC_GATE__EFC_MASK
748 | UVD_SUVD_CGC_GATE__SAOE_MASK
749 | UVD_SUVD_CGC_GATE__SRE_AV1_MASK
750 | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK
751 | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK
752 | UVD_SUVD_CGC_GATE__SCM_AV1_MASK
753 | UVD_SUVD_CGC_GATE__SMPA_MASK);
754 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data);
755
756 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2);
757 data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK
758 | UVD_SUVD_CGC_GATE2__MPBE1_MASK
759 | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK
760 | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK
761 | UVD_SUVD_CGC_GATE2__MPC1_MASK);
762 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data);
763
764 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);
765 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
766 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
767 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
768 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
769 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
770 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
771 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
772 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
773 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
774 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK
775 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK
776 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK
777 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK
778 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK
779 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK
780 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK
781 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK
782 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK
783 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK);
784 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
785}
786
787static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
788 uint8_t sram_sel, int inst_idx, uint8_t indirect)
789{
790 uint32_t reg_data = 0;
791
792 /* enable sw clock gating control */
793 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
794 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
795 else
796 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
797 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
798 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
799 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
800 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
801 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
802 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
803 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
804 UVD_CGC_CTRL__SYS_MODE_MASK |
805 UVD_CGC_CTRL__UDEC_MODE_MASK |
806 UVD_CGC_CTRL__MPEG2_MODE_MASK |
807 UVD_CGC_CTRL__REGS_MODE_MASK |
808 UVD_CGC_CTRL__RBC_MODE_MASK |
809 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
810 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
811 UVD_CGC_CTRL__IDCT_MODE_MASK |
812 UVD_CGC_CTRL__MPRD_MODE_MASK |
813 UVD_CGC_CTRL__MPC_MODE_MASK |
814 UVD_CGC_CTRL__LBSI_MODE_MASK |
815 UVD_CGC_CTRL__LRBBM_MODE_MASK |
816 UVD_CGC_CTRL__WCB_MODE_MASK |
817 UVD_CGC_CTRL__VCPU_MODE_MASK |
818 UVD_CGC_CTRL__MMSCH_MODE_MASK);
819 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
820 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
821
822 /* turn off clock gating */
823 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
824 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);
825
826 /* turn on SUVD clock gating */
827 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
828 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
829
830 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
831 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
832 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
833}
834
835/**
836 * vcn_v3_0_enable_clock_gating - enable VCN clock gating
837 *
838 * @adev: amdgpu_device pointer
839 * @inst: instance number
840 *
841 * Enable clock gating for VCN block
842 */
843static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst)
844{
845 uint32_t data;
846
847 /* enable VCN CGC */
848 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
849 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
850 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
851 else
852 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
853 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
854 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
855 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
856
857 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
858 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
859 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
860 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
861 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
862 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
863 | UVD_CGC_CTRL__SYS_MODE_MASK
864 | UVD_CGC_CTRL__UDEC_MODE_MASK
865 | UVD_CGC_CTRL__MPEG2_MODE_MASK
866 | UVD_CGC_CTRL__REGS_MODE_MASK
867 | UVD_CGC_CTRL__RBC_MODE_MASK
868 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
869 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
870 | UVD_CGC_CTRL__IDCT_MODE_MASK
871 | UVD_CGC_CTRL__MPRD_MODE_MASK
872 | UVD_CGC_CTRL__MPC_MODE_MASK
873 | UVD_CGC_CTRL__LBSI_MODE_MASK
874 | UVD_CGC_CTRL__LRBBM_MODE_MASK
875 | UVD_CGC_CTRL__WCB_MODE_MASK
876 | UVD_CGC_CTRL__VCPU_MODE_MASK
877 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
878 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
879
880 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);
881 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
882 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
883 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
884 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
885 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
886 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
887 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
888 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
889 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
890 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK
891 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK
892 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK
893 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK
894 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK
895 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK
896 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK
897 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK
898 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK
899 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK);
900 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
901}
902
903static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
904{
905 struct amdgpu_ring *ring;
906 uint32_t rb_bufsz, tmp;
907
908 /* disable register anti-hang mechanism */
909 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,
910 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
911 /* enable dynamic power gating mode */
912 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS);
913 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
914 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
915 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp);
916
917 if (indirect)
918 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t*)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
919
920 /* enable clock gating */
921 vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
922
923 /* enable VCPU clock */
924 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
925 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
926 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
927 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
928 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
929
930 /* disable master interupt */
931 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
932 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);
933
934 /* setup mmUVD_LMI_CTRL */
935 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
936 UVD_LMI_CTRL__REQ_MODE_MASK |
937 UVD_LMI_CTRL__CRC_RESET_MASK |
938 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
939 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
940 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
941 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
942 0x00100000L);
943 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
944 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);
945
946 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
947 VCN, inst_idx, mmUVD_MPC_CNTL),
948 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
949
950 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
951 VCN, inst_idx, mmUVD_MPC_SET_MUXA0),
952 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
953 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
954 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
955 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
956
957 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
958 VCN, inst_idx, mmUVD_MPC_SET_MUXB0),
959 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
960 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
961 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
962 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
963
964 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
965 VCN, inst_idx, mmUVD_MPC_SET_MUX),
966 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
967 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
968 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
969
970 vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect);
971
972 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
973 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
974 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
975 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
976
977 /* enable LMI MC and UMC channels */
978 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
979 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect);
980
981 /* unblock VCPU register access */
982 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
983 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
984
985 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
986 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
987 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
988 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
989
990 /* enable master interrupt */
991 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
992 VCN, inst_idx, mmUVD_MASTINT_EN),
993 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
994
995 /* add nop to workaround PSP size check */
996 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
997 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
998
999 if (indirect)
1000 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
1001 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
1002 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
1003
1004 ring = &adev->vcn.inst[inst_idx].ring_dec;
1005 /* force RBC into idle state */
1006 rb_bufsz = order_base_2(ring->ring_size);
1007 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1008 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1009 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1010 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1011 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1012 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp);
1013
1014 /* set the write pointer delay */
1015 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0);
1016
1017 /* set the wb address */
1018 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR,
1019 (upper_32_bits(ring->gpu_addr) >> 2));
1020
1021 /* programm the RB_BASE for ring buffer */
1022 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1023 lower_32_bits(ring->gpu_addr));
1024 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1025 upper_32_bits(ring->gpu_addr));
1026
1027 /* Initialize the ring buffer's read and write pointers */
1028 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0);
1029
1030 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0);
1031
1032 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);
1033 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,
1034 lower_32_bits(ring->wptr));
1035
1036 return 0;
1037}
1038
1039static int vcn_v3_0_start(struct amdgpu_device *adev)
1040{
1041 struct amdgpu_ring *ring;
1042 uint32_t rb_bufsz, tmp;
1043 int i, j, k, r;
1044
1045 if (adev->pm.dpm_enabled)
1046 amdgpu_dpm_enable_uvd(adev, true);
1047
1048 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1049 if (adev->vcn.harvest_config & (1 << i))
1050 continue;
1051
1052 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG){
1053 r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
1054 continue;
1055 }
1056
1057 /* disable VCN power gating */
1058 vcn_v3_0_disable_static_power_gating(adev, i);
1059
1060 /* set VCN status busy */
1061 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
1062 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);
1063
1064 /*SW clock gating */
1065 vcn_v3_0_disable_clock_gating(adev, i);
1066
1067 /* enable VCPU clock */
1068 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1069 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
1070
1071 /* disable master interrupt */
1072 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,
1073 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1074
1075 /* enable LMI MC and UMC channels */
1076 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,
1077 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1078
1079 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
1080 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1081 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1082 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
1083
1084 /* setup mmUVD_LMI_CTRL */
1085 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);
1086 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp |
1087 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1088 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1089 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1090 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
1091
1092 /* setup mmUVD_MPC_CNTL */
1093 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);
1094 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1095 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1096 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);
1097
1098 /* setup UVD_MPC_SET_MUXA0 */
1099 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,
1100 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1101 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1102 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1103 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1104
1105 /* setup UVD_MPC_SET_MUXB0 */
1106 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,
1107 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1108 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1109 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1110 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1111
1112 /* setup mmUVD_MPC_SET_MUX */
1113 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,
1114 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1115 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1116 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1117
1118 vcn_v3_0_mc_resume(adev, i);
1119
1120 /* VCN global tiling registers */
1121 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG,
1122 adev->gfx.config.gb_addr_config);
1123
1124 /* unblock VCPU register access */
1125 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,
1126 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1127
1128 /* release VCPU reset to boot */
1129 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1130 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1131
1132 for (j = 0; j < 10; ++j) {
1133 uint32_t status;
1134
1135 for (k = 0; k < 100; ++k) {
1136 status = RREG32_SOC15(VCN, i, mmUVD_STATUS);
1137 if (status & 2)
1138 break;
1139 mdelay(10);
1140 }
1141 r = 0;
1142 if (status & 2)
1143 break;
1144
1145 DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i);
1146 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1147 UVD_VCPU_CNTL__BLK_RST_MASK,
1148 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1149 mdelay(10);
1150 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1151 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1152
1153 mdelay(10);
1154 r = -1;
1155 }
1156
1157 if (r) {
1158 DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i);
1159 return r;
1160 }
1161
1162 /* enable master interrupt */
1163 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),
1164 UVD_MASTINT_EN__VCPU_EN_MASK,
1165 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1166
1167 /* clear the busy bit of VCN_STATUS */
1168 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,
1169 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1170
1171 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0);
1172
1173 ring = &adev->vcn.inst[i].ring_dec;
1174 /* force RBC into idle state */
1175 rb_bufsz = order_base_2(ring->ring_size);
1176 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1177 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1178 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1179 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1180 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1181 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);
1182
1183 /* programm the RB_BASE for ring buffer */
1184 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1185 lower_32_bits(ring->gpu_addr));
1186 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1187 upper_32_bits(ring->gpu_addr));
1188
1189 /* Initialize the ring buffer's read and write pointers */
1190 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);
1191
1192 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
1193 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,
1194 lower_32_bits(ring->wptr));
1195 ring = &adev->vcn.inst[i].ring_enc[0];
1196 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1197 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1198 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
1199 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1200 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);
1201
1202 ring = &adev->vcn.inst[i].ring_enc[1];
1203 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1204 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1205 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1206 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1207 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
1208 }
1209
1210 return 0;
1211}
1212
1213static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
1214{
1215 int i, j;
1216 struct amdgpu_ring *ring;
1217 uint64_t cache_addr;
1218 uint64_t rb_addr;
1219 uint64_t ctx_addr;
1220 uint32_t param, resp, expected;
1221 uint32_t offset, cache_size;
1222 uint32_t tmp, timeout;
1223 uint32_t id;
1224
1225 struct amdgpu_mm_table *table = &adev->virt.mm_table;
1226 uint32_t *table_loc;
1227 uint32_t table_size;
1228 uint32_t size, size_dw;
1229
1230 struct mmsch_v3_0_cmd_direct_write
1231 direct_wt = { {0} };
1232 struct mmsch_v3_0_cmd_direct_read_modify_write
1233 direct_rd_mod_wt = { {0} };
1234 struct mmsch_v3_0_cmd_direct_polling
1235 direct_poll = { {0} };
1236 struct mmsch_v3_0_cmd_end end = { {0} };
1237 struct mmsch_v3_0_init_header header;
1238
1239 direct_wt.cmd_header.command_type =
1240 MMSCH_COMMAND__DIRECT_REG_WRITE;
1241 direct_rd_mod_wt.cmd_header.command_type =
1242 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1243 direct_poll.cmd_header.command_type =
1244 MMSCH_COMMAND__DIRECT_REG_POLLING;
1245 end.cmd_header.command_type =
1246 MMSCH_COMMAND__END;
1247
1248 header.version = MMSCH_VERSION;
1249 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2;
1250 for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) {
1251 header.inst[i].init_status = 0;
1252 header.inst[i].table_offset = 0;
1253 header.inst[i].table_size = 0;
1254 }
1255
1256 table_loc = (uint32_t *)table->cpu_addr;
1257 table_loc += header.total_size;
1258 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1259 if (adev->vcn.harvest_config & (1 << i))
1260 continue;
1261
1262 table_size = 0;
1263
1264 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i,
1265 mmUVD_STATUS),
1266 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
1267
1268 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
1269
1270 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1271 id = amdgpu_ucode_id_vcns[i];
1272 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1273 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1274 adev->firmware.ucode[id].tmr_mc_addr_lo);
1275 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1276 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1277 adev->firmware.ucode[id].tmr_mc_addr_hi);
1278 offset = 0;
1279 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1280 mmUVD_VCPU_CACHE_OFFSET0),
1281 0);
1282 } else {
1283 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1284 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1285 lower_32_bits(adev->vcn.inst[i].gpu_addr));
1286 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1287 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1288 upper_32_bits(adev->vcn.inst[i].gpu_addr));
1289 offset = cache_size;
1290 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1291 mmUVD_VCPU_CACHE_OFFSET0),
1292 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
1293 }
1294
1295 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1296 mmUVD_VCPU_CACHE_SIZE0),
1297 cache_size);
1298
1299 cache_addr = adev->vcn.inst[i].gpu_addr + offset;
1300 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1301 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1302 lower_32_bits(cache_addr));
1303 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1304 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1305 upper_32_bits(cache_addr));
1306 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1307 mmUVD_VCPU_CACHE_OFFSET1),
1308 0);
1309 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1310 mmUVD_VCPU_CACHE_SIZE1),
1311 AMDGPU_VCN_STACK_SIZE);
1312
1313 cache_addr = adev->vcn.inst[i].gpu_addr + offset +
1314 AMDGPU_VCN_STACK_SIZE;
1315 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1316 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1317 lower_32_bits(cache_addr));
1318 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1319 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1320 upper_32_bits(cache_addr));
1321 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1322 mmUVD_VCPU_CACHE_OFFSET2),
1323 0);
1324 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1325 mmUVD_VCPU_CACHE_SIZE2),
1326 AMDGPU_VCN_CONTEXT_SIZE);
1327
1328 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
1329 ring = &adev->vcn.inst[i].ring_enc[j];
1330 ring->wptr = 0;
1331 rb_addr = ring->gpu_addr;
1332 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1333 mmUVD_RB_BASE_LO),
1334 lower_32_bits(rb_addr));
1335 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1336 mmUVD_RB_BASE_HI),
1337 upper_32_bits(rb_addr));
1338 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1339 mmUVD_RB_SIZE),
1340 ring->ring_size / 4);
1341 }
1342
1343 ring = &adev->vcn.inst[i].ring_dec;
1344 ring->wptr = 0;
1345 rb_addr = ring->gpu_addr;
1346 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1347 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
1348 lower_32_bits(rb_addr));
1349 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1350 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
1351 upper_32_bits(rb_addr));
1352 /* force RBC into idle state */
1353 tmp = order_base_2(ring->ring_size);
1354 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
1355 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1356 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1357 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1358 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1359 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1360 mmUVD_RBC_RB_CNTL),
1361 tmp);
1362
1363 /* add end packet */
1364 MMSCH_V3_0_INSERT_END();
1365
1366 /* refine header */
1367 header.inst[i].init_status = 1;
1368 header.inst[i].table_offset = header.total_size;
1369 header.inst[i].table_size = table_size;
1370 header.total_size += table_size;
1371 }
1372
1373 /* Update init table header in memory */
1374 size = sizeof(struct mmsch_v3_0_init_header);
1375 table_loc = (uint32_t *)table->cpu_addr;
1376 memcpy((void *)table_loc, &header, size);
1377
1378 /* message MMSCH (in VCN[0]) to initialize this client
1379 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1380 * of memory descriptor location
1381 */
1382 ctx_addr = table->gpu_addr;
1383 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
1384 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
1385
1386 /* 2, update vmid of descriptor */
1387 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID);
1388 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1389 /* use domain0 for MM scheduler */
1390 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1391 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp);
1392
1393 /* 3, notify mmsch about the size of this descriptor */
1394 size = header.total_size;
1395 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size);
1396
1397 /* 4, set resp to zero */
1398 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
1399
1400 /* 5, kick off the initialization and wait until
1401 * MMSCH_VF_MAILBOX_RESP becomes non-zero
1402 */
1403 param = 0x10000001;
1404 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param);
1405 tmp = 0;
1406 timeout = 1000;
1407 resp = 0;
1408 expected = param + 1;
1409 while (resp != expected) {
1410 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);
1411 if (resp == expected)
1412 break;
1413
1414 udelay(10);
1415 tmp = tmp + 10;
1416 if (tmp >= timeout) {
1417 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
1418 " waiting for mmMMSCH_VF_MAILBOX_RESP "\
1419 "(expected=0x%08x, readback=0x%08x)\n",
1420 tmp, expected, resp);
1421 return -EBUSY;
1422 }
1423 }
1424
1425 return 0;
1426}
1427
1428static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1429{
1430 uint32_t tmp;
1431
1432 /* Wait for power status to be 1 */
1433 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
1434 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1435
1436 /* wait for read ptr to be equal to write ptr */
1437 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);
1438 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1439
1440 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);
1441 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1442
1443 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1444 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1445
1446 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
1447 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1448
1449 /* disable dynamic power gating mode */
1450 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,
1451 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1452
1453 return 0;
1454}
1455
1456static int vcn_v3_0_stop(struct amdgpu_device *adev)
1457{
1458 uint32_t tmp;
1459 int i, r = 0;
1460
1461 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1462 if (adev->vcn.harvest_config & (1 << i))
1463 continue;
1464
1465 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1466 r = vcn_v3_0_stop_dpg_mode(adev, i);
1467 continue;
1468 }
1469
1470 /* wait for vcn idle */
1471 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1472 if (r)
1473 return r;
1474
1475 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1476 UVD_LMI_STATUS__READ_CLEAN_MASK |
1477 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1478 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1479 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
1480 if (r)
1481 return r;
1482
1483 /* disable LMI UMC channel */
1484 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
1485 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1486 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);
1487 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1488 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1489 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
1490 if (r)
1491 return r;
1492
1493 /* block VCPU register access */
1494 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),
1495 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
1496 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1497
1498 /* reset VCPU */
1499 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1500 UVD_VCPU_CNTL__BLK_RST_MASK,
1501 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1502
1503 /* disable VCPU clock */
1504 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1505 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1506
1507 /* apply soft reset */
1508 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
1509 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1510 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
1511 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
1512 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1513 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
1514
1515 /* clear status */
1516 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
1517
1518 /* apply HW clock gating */
1519 vcn_v3_0_enable_clock_gating(adev, i);
1520
1521 /* enable VCN power gating */
1522 vcn_v3_0_enable_static_power_gating(adev, i);
1523 }
1524
1525 if (adev->pm.dpm_enabled)
1526 amdgpu_dpm_enable_uvd(adev, false);
1527
1528 return 0;
1529}
1530
1531static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
1532 int inst_idx, struct dpg_pause_state *new_state)
1533{
1534 struct amdgpu_ring *ring;
1535 uint32_t reg_data = 0;
1536 int ret_code;
1537
1538 /* pause/unpause if state is changed */
1539 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1540 DRM_DEBUG("dpg pause state changed %d -> %d",
1541 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
1542 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) &
1543 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1544
1545 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1546 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,
1547 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1548
1549 if (!ret_code) {
1550 /* pause DPG */
1551 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1552 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1553
1554 /* wait for ACK */
1555 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE,
1556 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1557 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1558
1559 /* Restore */
1560 ring = &adev->vcn.inst[inst_idx].ring_enc[0];
1561 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);
1562 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1563 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);
1564 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1565 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1566
1567 ring = &adev->vcn.inst[inst_idx].ring_enc[1];
1568 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1569 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1570 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);
1571 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1572 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1573
1574 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,
1575 RREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1576
1577 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,
1578 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1579 }
1580 } else {
1581 /* unpause dpg, no need to wait */
1582 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1583 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1584 }
1585 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1586 }
1587
1588 return 0;
1589}
1590
1591/**
1592 * vcn_v3_0_dec_ring_get_rptr - get read pointer
1593 *
1594 * @ring: amdgpu_ring pointer
1595 *
1596 * Returns the current hardware read pointer
1597 */
1598static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1599{
1600 struct amdgpu_device *adev = ring->adev;
1601
1602 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);
1603}
1604
1605/**
1606 * vcn_v3_0_dec_ring_get_wptr - get write pointer
1607 *
1608 * @ring: amdgpu_ring pointer
1609 *
1610 * Returns the current hardware write pointer
1611 */
1612static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1613{
1614 struct amdgpu_device *adev = ring->adev;
1615
1616 if (ring->use_doorbell)
1617 return adev->wb.wb[ring->wptr_offs];
1618 else
1619 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);
1620}
1621
1622/**
1623 * vcn_v3_0_dec_ring_set_wptr - set write pointer
1624 *
1625 * @ring: amdgpu_ring pointer
1626 *
1627 * Commits the write pointer to the hardware
1628 */
1629static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1630{
1631 struct amdgpu_device *adev = ring->adev;
1632
1633 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1634 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2,
1635 lower_32_bits(ring->wptr) | 0x80000000);
1636
1637 if (ring->use_doorbell) {
1638 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1639 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1640 } else {
1641 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1642 }
1643}
1644
1645static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = {
1646 .type = AMDGPU_RING_TYPE_VCN_DEC,
1647 .align_mask = 0xf,
1648 .vmhub = AMDGPU_MMHUB_0,
1649 .get_rptr = vcn_v3_0_dec_ring_get_rptr,
1650 .get_wptr = vcn_v3_0_dec_ring_get_wptr,
1651 .set_wptr = vcn_v3_0_dec_ring_set_wptr,
1652 .emit_frame_size =
1653 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1654 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1655 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
1656 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
1657 6,
1658 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
1659 .emit_ib = vcn_v2_0_dec_ring_emit_ib,
1660 .emit_fence = vcn_v2_0_dec_ring_emit_fence,
1661 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
1662 .test_ring = vcn_v2_0_dec_ring_test_ring,
1663 .test_ib = amdgpu_vcn_dec_ring_test_ib,
1664 .insert_nop = vcn_v2_0_dec_ring_insert_nop,
1665 .insert_start = vcn_v2_0_dec_ring_insert_start,
1666 .insert_end = vcn_v2_0_dec_ring_insert_end,
1667 .pad_ib = amdgpu_ring_generic_pad_ib,
1668 .begin_use = amdgpu_vcn_ring_begin_use,
1669 .end_use = amdgpu_vcn_ring_end_use,
1670 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
1671 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
1672 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1673};
1674
1675/**
1676 * vcn_v3_0_enc_ring_get_rptr - get enc read pointer
1677 *
1678 * @ring: amdgpu_ring pointer
1679 *
1680 * Returns the current hardware enc read pointer
1681 */
1682static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1683{
1684 struct amdgpu_device *adev = ring->adev;
1685
1686 if (ring == &adev->vcn.inst[ring->me].ring_enc[0])
1687 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);
1688 else
1689 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2);
1690}
1691
1692/**
1693 * vcn_v3_0_enc_ring_get_wptr - get enc write pointer
1694 *
1695 * @ring: amdgpu_ring pointer
1696 *
1697 * Returns the current hardware enc write pointer
1698 */
1699static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1700{
1701 struct amdgpu_device *adev = ring->adev;
1702
1703 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
1704 if (ring->use_doorbell)
1705 return adev->wb.wb[ring->wptr_offs];
1706 else
1707 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);
1708 } else {
1709 if (ring->use_doorbell)
1710 return adev->wb.wb[ring->wptr_offs];
1711 else
1712 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);
1713 }
1714}
1715
1716/**
1717 * vcn_v3_0_enc_ring_set_wptr - set enc write pointer
1718 *
1719 * @ring: amdgpu_ring pointer
1720 *
1721 * Commits the enc write pointer to the hardware
1722 */
1723static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1724{
1725 struct amdgpu_device *adev = ring->adev;
1726
1727 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
1728 if (ring->use_doorbell) {
1729 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1730 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1731 } else {
1732 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1733 }
1734 } else {
1735 if (ring->use_doorbell) {
1736 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1737 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1738 } else {
1739 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1740 }
1741 }
1742}
1743
1744static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = {
1745 .type = AMDGPU_RING_TYPE_VCN_ENC,
1746 .align_mask = 0x3f,
1747 .nop = VCN_ENC_CMD_NO_OP,
1748 .vmhub = AMDGPU_MMHUB_0,
1749 .get_rptr = vcn_v3_0_enc_ring_get_rptr,
1750 .get_wptr = vcn_v3_0_enc_ring_get_wptr,
1751 .set_wptr = vcn_v3_0_enc_ring_set_wptr,
1752 .emit_frame_size =
1753 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1754 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1755 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1756 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1757 1, /* vcn_v2_0_enc_ring_insert_end */
1758 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1759 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1760 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1761 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
1762 .test_ring = amdgpu_vcn_enc_ring_test_ring,
1763 .test_ib = amdgpu_vcn_enc_ring_test_ib,
1764 .insert_nop = amdgpu_ring_insert_nop,
1765 .insert_end = vcn_v2_0_enc_ring_insert_end,
1766 .pad_ib = amdgpu_ring_generic_pad_ib,
1767 .begin_use = amdgpu_vcn_ring_begin_use,
1768 .end_use = amdgpu_vcn_ring_end_use,
1769 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
1770 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
1771 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1772};
1773
1774static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)
1775{
1776 int i;
1777
1778 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1779 if (adev->vcn.harvest_config & (1 << i))
1780 continue;
1781
1782 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs;
1783 adev->vcn.inst[i].ring_dec.me = i;
1784 DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i);
1785 }
1786}
1787
1788static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1789{
1790 int i, j;
1791
1792 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1793 if (adev->vcn.harvest_config & (1 << i))
1794 continue;
1795
1796 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
1797 adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs;
1798 adev->vcn.inst[i].ring_enc[j].me = i;
1799 }
1800 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i);
1801 }
1802}
1803
1804static bool vcn_v3_0_is_idle(void *handle)
1805{
1806 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1807 int i, ret = 1;
1808
1809 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1810 if (adev->vcn.harvest_config & (1 << i))
1811 continue;
1812
1813 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
1814 }
1815
1816 return ret;
1817}
1818
1819static int vcn_v3_0_wait_for_idle(void *handle)
1820{
1821 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1822 int i, ret = 0;
1823
1824 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1825 if (adev->vcn.harvest_config & (1 << i))
1826 continue;
1827
1828 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
1829 UVD_STATUS__IDLE);
1830 if (ret)
1831 return ret;
1832 }
1833
1834 return ret;
1835}
1836
1837static int vcn_v3_0_set_clockgating_state(void *handle,
1838 enum amd_clockgating_state state)
1839{
1840 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1841 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1842 int i;
1843
1844 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1845 if (adev->vcn.harvest_config & (1 << i))
1846 continue;
1847
1848 if (enable) {
1849 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE)
1850 return -EBUSY;
1851 vcn_v3_0_enable_clock_gating(adev, i);
1852 } else {
1853 vcn_v3_0_disable_clock_gating(adev, i);
1854 }
1855 }
1856
1857 return 0;
1858}
1859
1860static int vcn_v3_0_set_powergating_state(void *handle,
1861 enum amd_powergating_state state)
1862{
1863 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1864 int ret;
1865
1866 /* for SRIOV, guest should not control VCN Power-gating
1867 * MMSCH FW should control Power-gating and clock-gating
1868 * guest should avoid touching CGC and PG
1869 */
1870 if (amdgpu_sriov_vf(adev)) {
1871 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
1872 return 0;
1873 }
1874
1875 if(state == adev->vcn.cur_state)
1876 return 0;
1877
1878 if (state == AMD_PG_STATE_GATE)
1879 ret = vcn_v3_0_stop(adev);
1880 else
1881 ret = vcn_v3_0_start(adev);
1882
1883 if(!ret)
1884 adev->vcn.cur_state = state;
1885
1886 return ret;
1887}
1888
1889static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev,
1890 struct amdgpu_irq_src *source,
1891 unsigned type,
1892 enum amdgpu_interrupt_state state)
1893{
1894 return 0;
1895}
1896
1897static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev,
1898 struct amdgpu_irq_src *source,
1899 struct amdgpu_iv_entry *entry)
1900{
1901 uint32_t ip_instance;
1902
1903 switch (entry->client_id) {
1904 case SOC15_IH_CLIENTID_VCN:
1905 ip_instance = 0;
1906 break;
1907 case SOC15_IH_CLIENTID_VCN1:
1908 ip_instance = 1;
1909 break;
1910 default:
1911 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
1912 return 0;
1913 }
1914
1915 DRM_DEBUG("IH: VCN TRAP\n");
1916
1917 switch (entry->src_id) {
1918 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
1919 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);
1920 break;
1921 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
1922 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
1923 break;
1924 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
1925 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
1926 break;
1927 default:
1928 DRM_ERROR("Unhandled interrupt: %d %d\n",
1929 entry->src_id, entry->src_data[0]);
1930 break;
1931 }
1932
1933 return 0;
1934}
1935
1936static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = {
1937 .set = vcn_v3_0_set_interrupt_state,
1938 .process = vcn_v3_0_process_interrupt,
1939};
1940
1941static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1942{
1943 int i;
1944
1945 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1946 if (adev->vcn.harvest_config & (1 << i))
1947 continue;
1948
1949 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
1950 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs;
1951 }
1952}
1953
1954static const struct amd_ip_funcs vcn_v3_0_ip_funcs = {
1955 .name = "vcn_v3_0",
1956 .early_init = vcn_v3_0_early_init,
1957 .late_init = NULL,
1958 .sw_init = vcn_v3_0_sw_init,
1959 .sw_fini = vcn_v3_0_sw_fini,
1960 .hw_init = vcn_v3_0_hw_init,
1961 .hw_fini = vcn_v3_0_hw_fini,
1962 .suspend = vcn_v3_0_suspend,
1963 .resume = vcn_v3_0_resume,
1964 .is_idle = vcn_v3_0_is_idle,
1965 .wait_for_idle = vcn_v3_0_wait_for_idle,
1966 .check_soft_reset = NULL,
1967 .pre_soft_reset = NULL,
1968 .soft_reset = NULL,
1969 .post_soft_reset = NULL,
1970 .set_clockgating_state = vcn_v3_0_set_clockgating_state,
1971 .set_powergating_state = vcn_v3_0_set_powergating_state,
1972};
1973
1974const struct amdgpu_ip_block_version vcn_v3_0_ip_block =
1975{
1976 .type = AMD_IP_BLOCK_TYPE_VCN,
1977 .major = 3,
1978 .minor = 0,
1979 .rev = 0,
1980 .funcs = &vcn_v3_0_ip_funcs,
1981};