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1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26#ifndef __AMDGPU_GMC_H__
27#define __AMDGPU_GMC_H__
28
29#include <linux/types.h>
30
31#include "amdgpu_irq.h"
32
33/* VA hole for 48bit addresses on Vega10 */
34#define AMDGPU_GMC_HOLE_START 0x0000800000000000ULL
35#define AMDGPU_GMC_HOLE_END 0xffff800000000000ULL
36
37/*
38 * Hardware is programmed as if the hole doesn't exists with start and end
39 * address values.
40 *
41 * This mask is used to remove the upper 16bits of the VA and so come up with
42 * the linear addr value.
43 */
44#define AMDGPU_GMC_HOLE_MASK 0x0000ffffffffffffULL
45
46/*
47 * Ring size as power of two for the log of recent faults.
48 */
49#define AMDGPU_GMC_FAULT_RING_ORDER 8
50#define AMDGPU_GMC_FAULT_RING_SIZE (1 << AMDGPU_GMC_FAULT_RING_ORDER)
51
52/*
53 * Hash size as power of two for the log of recent faults
54 */
55#define AMDGPU_GMC_FAULT_HASH_ORDER 8
56#define AMDGPU_GMC_FAULT_HASH_SIZE (1 << AMDGPU_GMC_FAULT_HASH_ORDER)
57
58/*
59 * Number of IH timestamp ticks until a fault is considered handled
60 */
61#define AMDGPU_GMC_FAULT_TIMEOUT 5000ULL
62
63struct firmware;
64
65/*
66 * GMC page fault information
67 */
68struct amdgpu_gmc_fault {
69 uint64_t timestamp;
70 uint64_t next:AMDGPU_GMC_FAULT_RING_ORDER;
71 uint64_t key:52;
72};
73
74/*
75 * VMHUB structures, functions & helpers
76 */
77struct amdgpu_vmhub {
78 uint32_t ctx0_ptb_addr_lo32;
79 uint32_t ctx0_ptb_addr_hi32;
80 uint32_t vm_inv_eng0_sem;
81 uint32_t vm_inv_eng0_req;
82 uint32_t vm_inv_eng0_ack;
83 uint32_t vm_context0_cntl;
84 uint32_t vm_l2_pro_fault_status;
85 uint32_t vm_l2_pro_fault_cntl;
86
87 /*
88 * store the register distances between two continuous context domain
89 * and invalidation engine.
90 */
91 uint32_t ctx_distance;
92 uint32_t ctx_addr_distance; /* include LO32/HI32 */
93 uint32_t eng_distance;
94 uint32_t eng_addr_distance; /* include LO32/HI32 */
95};
96
97/*
98 * GPU MC structures, functions & helpers
99 */
100struct amdgpu_gmc_funcs {
101 /* flush the vm tlb via mmio */
102 void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,
103 uint32_t vmhub, uint32_t flush_type);
104 /* flush the vm tlb via pasid */
105 int (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid,
106 uint32_t flush_type, bool all_hub);
107 /* flush the vm tlb via ring */
108 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
109 uint64_t pd_addr);
110 /* Change the VMID -> PASID mapping */
111 void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid,
112 unsigned pasid);
113 /* enable/disable PRT support */
114 void (*set_prt)(struct amdgpu_device *adev, bool enable);
115 /* map mtype to hardware flags */
116 uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags);
117 /* get the pde for a given mc addr */
118 void (*get_vm_pde)(struct amdgpu_device *adev, int level,
119 u64 *dst, u64 *flags);
120 /* get the pte flags to use for a BO VA mapping */
121 void (*get_vm_pte)(struct amdgpu_device *adev,
122 struct amdgpu_bo_va_mapping *mapping,
123 uint64_t *flags);
124};
125
126struct amdgpu_xgmi {
127 /* from psp */
128 u64 node_id;
129 u64 hive_id;
130 /* fixed per family */
131 u64 node_segment_size;
132 /* physical node (0-3) */
133 unsigned physical_node_id;
134 /* number of nodes (0-4) */
135 unsigned num_physical_nodes;
136 /* gpu list in the same hive */
137 struct list_head head;
138 bool supported;
139 struct ras_common_if *ras_if;
140};
141
142struct amdgpu_gmc {
143 /* FB's physical address in MMIO space (for CPU to
144 * map FB). This is different compared to the agp/
145 * gart/vram_start/end field as the later is from
146 * GPU's view and aper_base is from CPU's view.
147 */
148 resource_size_t aper_size;
149 resource_size_t aper_base;
150 /* for some chips with <= 32MB we need to lie
151 * about vram size near mc fb location */
152 u64 mc_vram_size;
153 u64 visible_vram_size;
154 /* AGP aperture start and end in MC address space
155 * Driver find a hole in the MC address space
156 * to place AGP by setting MC_VM_AGP_BOT/TOP registers
157 * Under VMID0, logical address == MC address. AGP
158 * aperture maps to physical bus or IOVA addressed.
159 * AGP aperture is used to simulate FB in ZFB case.
160 * AGP aperture is also used for page table in system
161 * memory (mainly for APU).
162 *
163 */
164 u64 agp_size;
165 u64 agp_start;
166 u64 agp_end;
167 /* GART aperture start and end in MC address space
168 * Driver find a hole in the MC address space
169 * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR
170 * registers
171 * Under VMID0, logical address inside GART aperture will
172 * be translated through gpuvm gart page table to access
173 * paged system memory
174 */
175 u64 gart_size;
176 u64 gart_start;
177 u64 gart_end;
178 /* Frame buffer aperture of this GPU device. Different from
179 * fb_start (see below), this only covers the local GPU device.
180 * Driver get fb_start from MC_VM_FB_LOCATION_BASE (set by vbios)
181 * and calculate vram_start of this local device by adding an
182 * offset inside the XGMI hive.
183 * Under VMID0, logical address == MC address
184 */
185 u64 vram_start;
186 u64 vram_end;
187 /* FB region , it's same as local vram region in single GPU, in XGMI
188 * configuration, this region covers all GPUs in the same hive ,
189 * each GPU in the hive has the same view of this FB region .
190 * GPU0's vram starts at offset (0 * segment size) ,
191 * GPU1 starts at offset (1 * segment size), etc.
192 */
193 u64 fb_start;
194 u64 fb_end;
195 unsigned vram_width;
196 u64 real_vram_size;
197 int vram_mtrr;
198 u64 mc_mask;
199 const struct firmware *fw; /* MC firmware */
200 uint32_t fw_version;
201 struct amdgpu_irq_src vm_fault;
202 uint32_t vram_type;
203 uint8_t vram_vendor;
204 uint32_t srbm_soft_reset;
205 bool prt_warning;
206 uint64_t stolen_size;
207 uint32_t sdpif_register;
208 /* apertures */
209 u64 shared_aperture_start;
210 u64 shared_aperture_end;
211 u64 private_aperture_start;
212 u64 private_aperture_end;
213 /* protects concurrent invalidation */
214 spinlock_t invalidate_lock;
215 bool translate_further;
216 struct kfd_vm_fault_info *vm_fault_info;
217 atomic_t vm_fault_info_updated;
218
219 struct amdgpu_gmc_fault fault_ring[AMDGPU_GMC_FAULT_RING_SIZE];
220 struct {
221 uint64_t idx:AMDGPU_GMC_FAULT_RING_ORDER;
222 } fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE];
223 uint64_t last_fault:AMDGPU_GMC_FAULT_RING_ORDER;
224
225 bool tmz_enabled;
226
227 const struct amdgpu_gmc_funcs *gmc_funcs;
228
229 struct amdgpu_xgmi xgmi;
230 struct amdgpu_irq_src ecc_irq;
231};
232
233#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
234#define amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, type, allhub) \
235 ((adev)->gmc.gmc_funcs->flush_gpu_tlb_pasid \
236 ((adev), (pasid), (type), (allhub)))
237#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
238#define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
239#define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags))
240#define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
241#define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapping), (flags))
242
243/**
244 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR
245 *
246 * @adev: amdgpu_device pointer
247 *
248 * Returns:
249 * True if full VRAM is visible through the BAR
250 */
251static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
252{
253 WARN_ON(gmc->real_vram_size < gmc->visible_vram_size);
254
255 return (gmc->real_vram_size == gmc->visible_vram_size);
256}
257
258/**
259 * amdgpu_gmc_sign_extend - sign extend the given gmc address
260 *
261 * @addr: address to extend
262 */
263static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr)
264{
265 if (addr >= AMDGPU_GMC_HOLE_START)
266 addr |= AMDGPU_GMC_HOLE_END;
267
268 return addr;
269}
270
271void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
272 uint64_t *addr, uint64_t *flags);
273int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
274 uint32_t gpu_page_idx, uint64_t addr,
275 uint64_t flags);
276uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
277uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo);
278void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
279 u64 base);
280void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
281 struct amdgpu_gmc *mc);
282void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
283 struct amdgpu_gmc *mc);
284bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
285 uint16_t pasid, uint64_t timestamp);
286int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev);
287void amdgpu_gmc_ras_fini(struct amdgpu_device *adev);
288int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev);
289
290extern void amdgpu_gmc_tmz_set(struct amdgpu_device *adev);
291
292#endif