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1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
28#include <linux/pci.h>
29#include <linux/mc146818rtc.h>
30#include <linux/compiler.h>
31#include <linux/acpi.h>
32#include <linux/module.h>
33#include <linux/syscore_ops.h>
34#include <linux/msi.h>
35#include <linux/htirq.h>
36#include <linux/freezer.h>
37#include <linux/kthread.h>
38#include <linux/jiffies.h> /* time_after() */
39#include <linux/slab.h>
40#ifdef CONFIG_ACPI
41#include <acpi/acpi_bus.h>
42#endif
43#include <linux/bootmem.h>
44#include <linux/dmar.h>
45#include <linux/hpet.h>
46
47#include <asm/idle.h>
48#include <asm/io.h>
49#include <asm/smp.h>
50#include <asm/cpu.h>
51#include <asm/desc.h>
52#include <asm/proto.h>
53#include <asm/acpi.h>
54#include <asm/dma.h>
55#include <asm/timer.h>
56#include <asm/i8259.h>
57#include <asm/msidef.h>
58#include <asm/hypertransport.h>
59#include <asm/setup.h>
60#include <asm/irq_remapping.h>
61#include <asm/hpet.h>
62#include <asm/hw_irq.h>
63
64#include <asm/apic.h>
65
66#define __apicdebuginit(type) static type __init
67#define for_each_irq_pin(entry, head) \
68 for (entry = head; entry; entry = entry->next)
69
70/*
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
73 */
74int sis_apic_bug = -1;
75
76static DEFINE_RAW_SPINLOCK(ioapic_lock);
77static DEFINE_RAW_SPINLOCK(vector_lock);
78
79static struct ioapic {
80 /*
81 * # of IRQ routing registers
82 */
83 int nr_registers;
84 /*
85 * Saved state during suspend/resume, or while enabling intr-remap.
86 */
87 struct IO_APIC_route_entry *saved_registers;
88 /* I/O APIC config */
89 struct mpc_ioapic mp_config;
90 /* IO APIC gsi routing info */
91 struct mp_ioapic_gsi gsi_config;
92 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
93} ioapics[MAX_IO_APICS];
94
95#define mpc_ioapic_ver(id) ioapics[id].mp_config.apicver
96
97int mpc_ioapic_id(int id)
98{
99 return ioapics[id].mp_config.apicid;
100}
101
102unsigned int mpc_ioapic_addr(int id)
103{
104 return ioapics[id].mp_config.apicaddr;
105}
106
107struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int id)
108{
109 return &ioapics[id].gsi_config;
110}
111
112int nr_ioapics;
113
114/* The one past the highest gsi number used */
115u32 gsi_top;
116
117/* MP IRQ source entries */
118struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
119
120/* # of MP IRQ source entries */
121int mp_irq_entries;
122
123/* GSI interrupts */
124static int nr_irqs_gsi = NR_IRQS_LEGACY;
125
126#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
127int mp_bus_id_to_type[MAX_MP_BUSSES];
128#endif
129
130DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
131
132int skip_ioapic_setup;
133
134/**
135 * disable_ioapic_support() - disables ioapic support at runtime
136 */
137void disable_ioapic_support(void)
138{
139#ifdef CONFIG_PCI
140 noioapicquirk = 1;
141 noioapicreroute = -1;
142#endif
143 skip_ioapic_setup = 1;
144}
145
146static int __init parse_noapic(char *str)
147{
148 /* disable IO-APIC */
149 disable_ioapic_support();
150 return 0;
151}
152early_param("noapic", parse_noapic);
153
154static int io_apic_setup_irq_pin(unsigned int irq, int node,
155 struct io_apic_irq_attr *attr);
156
157/* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
158void mp_save_irq(struct mpc_intsrc *m)
159{
160 int i;
161
162 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
163 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
164 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
165 m->srcbusirq, m->dstapic, m->dstirq);
166
167 for (i = 0; i < mp_irq_entries; i++) {
168 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
169 return;
170 }
171
172 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
173 if (++mp_irq_entries == MAX_IRQ_SOURCES)
174 panic("Max # of irq sources exceeded!!\n");
175}
176
177struct irq_pin_list {
178 int apic, pin;
179 struct irq_pin_list *next;
180};
181
182static struct irq_pin_list *alloc_irq_pin_list(int node)
183{
184 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
185}
186
187
188/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
189#ifdef CONFIG_SPARSE_IRQ
190static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
191#else
192static struct irq_cfg irq_cfgx[NR_IRQS];
193#endif
194
195int __init arch_early_irq_init(void)
196{
197 struct irq_cfg *cfg;
198 int count, node, i;
199
200 if (!legacy_pic->nr_legacy_irqs) {
201 nr_irqs_gsi = 0;
202 io_apic_irqs = ~0UL;
203 }
204
205 for (i = 0; i < nr_ioapics; i++) {
206 ioapics[i].saved_registers =
207 kzalloc(sizeof(struct IO_APIC_route_entry) *
208 ioapics[i].nr_registers, GFP_KERNEL);
209 if (!ioapics[i].saved_registers)
210 pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
211 }
212
213 cfg = irq_cfgx;
214 count = ARRAY_SIZE(irq_cfgx);
215 node = cpu_to_node(0);
216
217 /* Make sure the legacy interrupts are marked in the bitmap */
218 irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs);
219
220 for (i = 0; i < count; i++) {
221 irq_set_chip_data(i, &cfg[i]);
222 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
223 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
224 /*
225 * For legacy IRQ's, start with assigning irq0 to irq15 to
226 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
227 */
228 if (i < legacy_pic->nr_legacy_irqs) {
229 cfg[i].vector = IRQ0_VECTOR + i;
230 cpumask_set_cpu(0, cfg[i].domain);
231 }
232 }
233
234 return 0;
235}
236
237#ifdef CONFIG_SPARSE_IRQ
238static struct irq_cfg *irq_cfg(unsigned int irq)
239{
240 return irq_get_chip_data(irq);
241}
242
243static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
244{
245 struct irq_cfg *cfg;
246
247 cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
248 if (!cfg)
249 return NULL;
250 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
251 goto out_cfg;
252 if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
253 goto out_domain;
254 return cfg;
255out_domain:
256 free_cpumask_var(cfg->domain);
257out_cfg:
258 kfree(cfg);
259 return NULL;
260}
261
262static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
263{
264 if (!cfg)
265 return;
266 irq_set_chip_data(at, NULL);
267 free_cpumask_var(cfg->domain);
268 free_cpumask_var(cfg->old_domain);
269 kfree(cfg);
270}
271
272#else
273
274struct irq_cfg *irq_cfg(unsigned int irq)
275{
276 return irq < nr_irqs ? irq_cfgx + irq : NULL;
277}
278
279static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
280{
281 return irq_cfgx + irq;
282}
283
284static inline void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) { }
285
286#endif
287
288static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
289{
290 int res = irq_alloc_desc_at(at, node);
291 struct irq_cfg *cfg;
292
293 if (res < 0) {
294 if (res != -EEXIST)
295 return NULL;
296 cfg = irq_get_chip_data(at);
297 if (cfg)
298 return cfg;
299 }
300
301 cfg = alloc_irq_cfg(at, node);
302 if (cfg)
303 irq_set_chip_data(at, cfg);
304 else
305 irq_free_desc(at);
306 return cfg;
307}
308
309static int alloc_irq_from(unsigned int from, int node)
310{
311 return irq_alloc_desc_from(from, node);
312}
313
314static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
315{
316 free_irq_cfg(at, cfg);
317 irq_free_desc(at);
318}
319
320struct io_apic {
321 unsigned int index;
322 unsigned int unused[3];
323 unsigned int data;
324 unsigned int unused2[11];
325 unsigned int eoi;
326};
327
328static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
329{
330 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
331 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
332}
333
334static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
335{
336 struct io_apic __iomem *io_apic = io_apic_base(apic);
337 writel(vector, &io_apic->eoi);
338}
339
340static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
341{
342 struct io_apic __iomem *io_apic = io_apic_base(apic);
343 writel(reg, &io_apic->index);
344 return readl(&io_apic->data);
345}
346
347static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
348{
349 struct io_apic __iomem *io_apic = io_apic_base(apic);
350 writel(reg, &io_apic->index);
351 writel(value, &io_apic->data);
352}
353
354/*
355 * Re-write a value: to be used for read-modify-write
356 * cycles where the read already set up the index register.
357 *
358 * Older SiS APIC requires we rewrite the index register
359 */
360static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
361{
362 struct io_apic __iomem *io_apic = io_apic_base(apic);
363
364 if (sis_apic_bug)
365 writel(reg, &io_apic->index);
366 writel(value, &io_apic->data);
367}
368
369static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
370{
371 struct irq_pin_list *entry;
372 unsigned long flags;
373
374 raw_spin_lock_irqsave(&ioapic_lock, flags);
375 for_each_irq_pin(entry, cfg->irq_2_pin) {
376 unsigned int reg;
377 int pin;
378
379 pin = entry->pin;
380 reg = io_apic_read(entry->apic, 0x10 + pin*2);
381 /* Is the remote IRR bit set? */
382 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
383 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
384 return true;
385 }
386 }
387 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
388
389 return false;
390}
391
392union entry_union {
393 struct { u32 w1, w2; };
394 struct IO_APIC_route_entry entry;
395};
396
397static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
398{
399 union entry_union eu;
400 unsigned long flags;
401 raw_spin_lock_irqsave(&ioapic_lock, flags);
402 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
403 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
404 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
405 return eu.entry;
406}
407
408/*
409 * When we write a new IO APIC routing entry, we need to write the high
410 * word first! If the mask bit in the low word is clear, we will enable
411 * the interrupt, and we need to make sure the entry is fully populated
412 * before that happens.
413 */
414static void
415__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
416{
417 union entry_union eu = {{0, 0}};
418
419 eu.entry = e;
420 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
421 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
422}
423
424static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
425{
426 unsigned long flags;
427 raw_spin_lock_irqsave(&ioapic_lock, flags);
428 __ioapic_write_entry(apic, pin, e);
429 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
430}
431
432/*
433 * When we mask an IO APIC routing entry, we need to write the low
434 * word first, in order to set the mask bit before we change the
435 * high bits!
436 */
437static void ioapic_mask_entry(int apic, int pin)
438{
439 unsigned long flags;
440 union entry_union eu = { .entry.mask = 1 };
441
442 raw_spin_lock_irqsave(&ioapic_lock, flags);
443 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
444 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
445 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
446}
447
448/*
449 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
450 * shared ISA-space IRQs, so we have to support them. We are super
451 * fast in the common case, and fast for shared ISA-space IRQs.
452 */
453static int
454__add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
455{
456 struct irq_pin_list **last, *entry;
457
458 /* don't allow duplicates */
459 last = &cfg->irq_2_pin;
460 for_each_irq_pin(entry, cfg->irq_2_pin) {
461 if (entry->apic == apic && entry->pin == pin)
462 return 0;
463 last = &entry->next;
464 }
465
466 entry = alloc_irq_pin_list(node);
467 if (!entry) {
468 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
469 node, apic, pin);
470 return -ENOMEM;
471 }
472 entry->apic = apic;
473 entry->pin = pin;
474
475 *last = entry;
476 return 0;
477}
478
479static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
480{
481 if (__add_pin_to_irq_node(cfg, node, apic, pin))
482 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
483}
484
485/*
486 * Reroute an IRQ to a different pin.
487 */
488static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
489 int oldapic, int oldpin,
490 int newapic, int newpin)
491{
492 struct irq_pin_list *entry;
493
494 for_each_irq_pin(entry, cfg->irq_2_pin) {
495 if (entry->apic == oldapic && entry->pin == oldpin) {
496 entry->apic = newapic;
497 entry->pin = newpin;
498 /* every one is different, right? */
499 return;
500 }
501 }
502
503 /* old apic/pin didn't exist, so just add new ones */
504 add_pin_to_irq_node(cfg, node, newapic, newpin);
505}
506
507static void __io_apic_modify_irq(struct irq_pin_list *entry,
508 int mask_and, int mask_or,
509 void (*final)(struct irq_pin_list *entry))
510{
511 unsigned int reg, pin;
512
513 pin = entry->pin;
514 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
515 reg &= mask_and;
516 reg |= mask_or;
517 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
518 if (final)
519 final(entry);
520}
521
522static void io_apic_modify_irq(struct irq_cfg *cfg,
523 int mask_and, int mask_or,
524 void (*final)(struct irq_pin_list *entry))
525{
526 struct irq_pin_list *entry;
527
528 for_each_irq_pin(entry, cfg->irq_2_pin)
529 __io_apic_modify_irq(entry, mask_and, mask_or, final);
530}
531
532static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry)
533{
534 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER,
535 IO_APIC_REDIR_MASKED, NULL);
536}
537
538static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry)
539{
540 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED,
541 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
542}
543
544static void io_apic_sync(struct irq_pin_list *entry)
545{
546 /*
547 * Synchronize the IO-APIC and the CPU by doing
548 * a dummy read from the IO-APIC
549 */
550 struct io_apic __iomem *io_apic;
551 io_apic = io_apic_base(entry->apic);
552 readl(&io_apic->data);
553}
554
555static void mask_ioapic(struct irq_cfg *cfg)
556{
557 unsigned long flags;
558
559 raw_spin_lock_irqsave(&ioapic_lock, flags);
560 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
561 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
562}
563
564static void mask_ioapic_irq(struct irq_data *data)
565{
566 mask_ioapic(data->chip_data);
567}
568
569static void __unmask_ioapic(struct irq_cfg *cfg)
570{
571 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
572}
573
574static void unmask_ioapic(struct irq_cfg *cfg)
575{
576 unsigned long flags;
577
578 raw_spin_lock_irqsave(&ioapic_lock, flags);
579 __unmask_ioapic(cfg);
580 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
581}
582
583static void unmask_ioapic_irq(struct irq_data *data)
584{
585 unmask_ioapic(data->chip_data);
586}
587
588static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
589{
590 struct IO_APIC_route_entry entry;
591
592 /* Check delivery_mode to be sure we're not clearing an SMI pin */
593 entry = ioapic_read_entry(apic, pin);
594 if (entry.delivery_mode == dest_SMI)
595 return;
596 /*
597 * Disable it in the IO-APIC irq-routing table:
598 */
599 ioapic_mask_entry(apic, pin);
600}
601
602static void clear_IO_APIC (void)
603{
604 int apic, pin;
605
606 for (apic = 0; apic < nr_ioapics; apic++)
607 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
608 clear_IO_APIC_pin(apic, pin);
609}
610
611#ifdef CONFIG_X86_32
612/*
613 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
614 * specific CPU-side IRQs.
615 */
616
617#define MAX_PIRQS 8
618static int pirq_entries[MAX_PIRQS] = {
619 [0 ... MAX_PIRQS - 1] = -1
620};
621
622static int __init ioapic_pirq_setup(char *str)
623{
624 int i, max;
625 int ints[MAX_PIRQS+1];
626
627 get_options(str, ARRAY_SIZE(ints), ints);
628
629 apic_printk(APIC_VERBOSE, KERN_INFO
630 "PIRQ redirection, working around broken MP-BIOS.\n");
631 max = MAX_PIRQS;
632 if (ints[0] < MAX_PIRQS)
633 max = ints[0];
634
635 for (i = 0; i < max; i++) {
636 apic_printk(APIC_VERBOSE, KERN_DEBUG
637 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
638 /*
639 * PIRQs are mapped upside down, usually.
640 */
641 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
642 }
643 return 1;
644}
645
646__setup("pirq=", ioapic_pirq_setup);
647#endif /* CONFIG_X86_32 */
648
649/*
650 * Saves all the IO-APIC RTE's
651 */
652int save_ioapic_entries(void)
653{
654 int apic, pin;
655 int err = 0;
656
657 for (apic = 0; apic < nr_ioapics; apic++) {
658 if (!ioapics[apic].saved_registers) {
659 err = -ENOMEM;
660 continue;
661 }
662
663 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
664 ioapics[apic].saved_registers[pin] =
665 ioapic_read_entry(apic, pin);
666 }
667
668 return err;
669}
670
671/*
672 * Mask all IO APIC entries.
673 */
674void mask_ioapic_entries(void)
675{
676 int apic, pin;
677
678 for (apic = 0; apic < nr_ioapics; apic++) {
679 if (!ioapics[apic].saved_registers)
680 continue;
681
682 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
683 struct IO_APIC_route_entry entry;
684
685 entry = ioapics[apic].saved_registers[pin];
686 if (!entry.mask) {
687 entry.mask = 1;
688 ioapic_write_entry(apic, pin, entry);
689 }
690 }
691 }
692}
693
694/*
695 * Restore IO APIC entries which was saved in the ioapic structure.
696 */
697int restore_ioapic_entries(void)
698{
699 int apic, pin;
700
701 for (apic = 0; apic < nr_ioapics; apic++) {
702 if (!ioapics[apic].saved_registers)
703 continue;
704
705 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
706 ioapic_write_entry(apic, pin,
707 ioapics[apic].saved_registers[pin]);
708 }
709 return 0;
710}
711
712/*
713 * Find the IRQ entry number of a certain pin.
714 */
715static int find_irq_entry(int apic, int pin, int type)
716{
717 int i;
718
719 for (i = 0; i < mp_irq_entries; i++)
720 if (mp_irqs[i].irqtype == type &&
721 (mp_irqs[i].dstapic == mpc_ioapic_id(apic) ||
722 mp_irqs[i].dstapic == MP_APIC_ALL) &&
723 mp_irqs[i].dstirq == pin)
724 return i;
725
726 return -1;
727}
728
729/*
730 * Find the pin to which IRQ[irq] (ISA) is connected
731 */
732static int __init find_isa_irq_pin(int irq, int type)
733{
734 int i;
735
736 for (i = 0; i < mp_irq_entries; i++) {
737 int lbus = mp_irqs[i].srcbus;
738
739 if (test_bit(lbus, mp_bus_not_pci) &&
740 (mp_irqs[i].irqtype == type) &&
741 (mp_irqs[i].srcbusirq == irq))
742
743 return mp_irqs[i].dstirq;
744 }
745 return -1;
746}
747
748static int __init find_isa_irq_apic(int irq, int type)
749{
750 int i;
751
752 for (i = 0; i < mp_irq_entries; i++) {
753 int lbus = mp_irqs[i].srcbus;
754
755 if (test_bit(lbus, mp_bus_not_pci) &&
756 (mp_irqs[i].irqtype == type) &&
757 (mp_irqs[i].srcbusirq == irq))
758 break;
759 }
760 if (i < mp_irq_entries) {
761 int apic;
762 for(apic = 0; apic < nr_ioapics; apic++) {
763 if (mpc_ioapic_id(apic) == mp_irqs[i].dstapic)
764 return apic;
765 }
766 }
767
768 return -1;
769}
770
771#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
772/*
773 * EISA Edge/Level control register, ELCR
774 */
775static int EISA_ELCR(unsigned int irq)
776{
777 if (irq < legacy_pic->nr_legacy_irqs) {
778 unsigned int port = 0x4d0 + (irq >> 3);
779 return (inb(port) >> (irq & 7)) & 1;
780 }
781 apic_printk(APIC_VERBOSE, KERN_INFO
782 "Broken MPtable reports ISA irq %d\n", irq);
783 return 0;
784}
785
786#endif
787
788/* ISA interrupts are always polarity zero edge triggered,
789 * when listed as conforming in the MP table. */
790
791#define default_ISA_trigger(idx) (0)
792#define default_ISA_polarity(idx) (0)
793
794/* EISA interrupts are always polarity zero and can be edge or level
795 * trigger depending on the ELCR value. If an interrupt is listed as
796 * EISA conforming in the MP table, that means its trigger type must
797 * be read in from the ELCR */
798
799#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
800#define default_EISA_polarity(idx) default_ISA_polarity(idx)
801
802/* PCI interrupts are always polarity one level triggered,
803 * when listed as conforming in the MP table. */
804
805#define default_PCI_trigger(idx) (1)
806#define default_PCI_polarity(idx) (1)
807
808/* MCA interrupts are always polarity zero level triggered,
809 * when listed as conforming in the MP table. */
810
811#define default_MCA_trigger(idx) (1)
812#define default_MCA_polarity(idx) default_ISA_polarity(idx)
813
814static int irq_polarity(int idx)
815{
816 int bus = mp_irqs[idx].srcbus;
817 int polarity;
818
819 /*
820 * Determine IRQ line polarity (high active or low active):
821 */
822 switch (mp_irqs[idx].irqflag & 3)
823 {
824 case 0: /* conforms, ie. bus-type dependent polarity */
825 if (test_bit(bus, mp_bus_not_pci))
826 polarity = default_ISA_polarity(idx);
827 else
828 polarity = default_PCI_polarity(idx);
829 break;
830 case 1: /* high active */
831 {
832 polarity = 0;
833 break;
834 }
835 case 2: /* reserved */
836 {
837 printk(KERN_WARNING "broken BIOS!!\n");
838 polarity = 1;
839 break;
840 }
841 case 3: /* low active */
842 {
843 polarity = 1;
844 break;
845 }
846 default: /* invalid */
847 {
848 printk(KERN_WARNING "broken BIOS!!\n");
849 polarity = 1;
850 break;
851 }
852 }
853 return polarity;
854}
855
856static int irq_trigger(int idx)
857{
858 int bus = mp_irqs[idx].srcbus;
859 int trigger;
860
861 /*
862 * Determine IRQ trigger mode (edge or level sensitive):
863 */
864 switch ((mp_irqs[idx].irqflag>>2) & 3)
865 {
866 case 0: /* conforms, ie. bus-type dependent */
867 if (test_bit(bus, mp_bus_not_pci))
868 trigger = default_ISA_trigger(idx);
869 else
870 trigger = default_PCI_trigger(idx);
871#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
872 switch (mp_bus_id_to_type[bus]) {
873 case MP_BUS_ISA: /* ISA pin */
874 {
875 /* set before the switch */
876 break;
877 }
878 case MP_BUS_EISA: /* EISA pin */
879 {
880 trigger = default_EISA_trigger(idx);
881 break;
882 }
883 case MP_BUS_PCI: /* PCI pin */
884 {
885 /* set before the switch */
886 break;
887 }
888 case MP_BUS_MCA: /* MCA pin */
889 {
890 trigger = default_MCA_trigger(idx);
891 break;
892 }
893 default:
894 {
895 printk(KERN_WARNING "broken BIOS!!\n");
896 trigger = 1;
897 break;
898 }
899 }
900#endif
901 break;
902 case 1: /* edge */
903 {
904 trigger = 0;
905 break;
906 }
907 case 2: /* reserved */
908 {
909 printk(KERN_WARNING "broken BIOS!!\n");
910 trigger = 1;
911 break;
912 }
913 case 3: /* level */
914 {
915 trigger = 1;
916 break;
917 }
918 default: /* invalid */
919 {
920 printk(KERN_WARNING "broken BIOS!!\n");
921 trigger = 0;
922 break;
923 }
924 }
925 return trigger;
926}
927
928static int pin_2_irq(int idx, int apic, int pin)
929{
930 int irq;
931 int bus = mp_irqs[idx].srcbus;
932 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic);
933
934 /*
935 * Debugging check, we are in big trouble if this message pops up!
936 */
937 if (mp_irqs[idx].dstirq != pin)
938 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
939
940 if (test_bit(bus, mp_bus_not_pci)) {
941 irq = mp_irqs[idx].srcbusirq;
942 } else {
943 u32 gsi = gsi_cfg->gsi_base + pin;
944
945 if (gsi >= NR_IRQS_LEGACY)
946 irq = gsi;
947 else
948 irq = gsi_top + gsi;
949 }
950
951#ifdef CONFIG_X86_32
952 /*
953 * PCI IRQ command line redirection. Yes, limits are hardcoded.
954 */
955 if ((pin >= 16) && (pin <= 23)) {
956 if (pirq_entries[pin-16] != -1) {
957 if (!pirq_entries[pin-16]) {
958 apic_printk(APIC_VERBOSE, KERN_DEBUG
959 "disabling PIRQ%d\n", pin-16);
960 } else {
961 irq = pirq_entries[pin-16];
962 apic_printk(APIC_VERBOSE, KERN_DEBUG
963 "using PIRQ%d -> IRQ %d\n",
964 pin-16, irq);
965 }
966 }
967 }
968#endif
969
970 return irq;
971}
972
973/*
974 * Find a specific PCI IRQ entry.
975 * Not an __init, possibly needed by modules
976 */
977int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
978 struct io_apic_irq_attr *irq_attr)
979{
980 int apic, i, best_guess = -1;
981
982 apic_printk(APIC_DEBUG,
983 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
984 bus, slot, pin);
985 if (test_bit(bus, mp_bus_not_pci)) {
986 apic_printk(APIC_VERBOSE,
987 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
988 return -1;
989 }
990 for (i = 0; i < mp_irq_entries; i++) {
991 int lbus = mp_irqs[i].srcbus;
992
993 for (apic = 0; apic < nr_ioapics; apic++)
994 if (mpc_ioapic_id(apic) == mp_irqs[i].dstapic ||
995 mp_irqs[i].dstapic == MP_APIC_ALL)
996 break;
997
998 if (!test_bit(lbus, mp_bus_not_pci) &&
999 !mp_irqs[i].irqtype &&
1000 (bus == lbus) &&
1001 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1002 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1003
1004 if (!(apic || IO_APIC_IRQ(irq)))
1005 continue;
1006
1007 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1008 set_io_apic_irq_attr(irq_attr, apic,
1009 mp_irqs[i].dstirq,
1010 irq_trigger(i),
1011 irq_polarity(i));
1012 return irq;
1013 }
1014 /*
1015 * Use the first all-but-pin matching entry as a
1016 * best-guess fuzzy result for broken mptables.
1017 */
1018 if (best_guess < 0) {
1019 set_io_apic_irq_attr(irq_attr, apic,
1020 mp_irqs[i].dstirq,
1021 irq_trigger(i),
1022 irq_polarity(i));
1023 best_guess = irq;
1024 }
1025 }
1026 }
1027 return best_guess;
1028}
1029EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1030
1031void lock_vector_lock(void)
1032{
1033 /* Used to the online set of cpus does not change
1034 * during assign_irq_vector.
1035 */
1036 raw_spin_lock(&vector_lock);
1037}
1038
1039void unlock_vector_lock(void)
1040{
1041 raw_spin_unlock(&vector_lock);
1042}
1043
1044static int
1045__assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1046{
1047 /*
1048 * NOTE! The local APIC isn't very good at handling
1049 * multiple interrupts at the same interrupt level.
1050 * As the interrupt level is determined by taking the
1051 * vector number and shifting that right by 4, we
1052 * want to spread these out a bit so that they don't
1053 * all fall in the same interrupt level.
1054 *
1055 * Also, we've got to be careful not to trash gate
1056 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1057 */
1058 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1059 static int current_offset = VECTOR_OFFSET_START % 8;
1060 unsigned int old_vector;
1061 int cpu, err;
1062 cpumask_var_t tmp_mask;
1063
1064 if (cfg->move_in_progress)
1065 return -EBUSY;
1066
1067 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1068 return -ENOMEM;
1069
1070 old_vector = cfg->vector;
1071 if (old_vector) {
1072 cpumask_and(tmp_mask, mask, cpu_online_mask);
1073 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1074 if (!cpumask_empty(tmp_mask)) {
1075 free_cpumask_var(tmp_mask);
1076 return 0;
1077 }
1078 }
1079
1080 /* Only try and allocate irqs on cpus that are present */
1081 err = -ENOSPC;
1082 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1083 int new_cpu;
1084 int vector, offset;
1085
1086 apic->vector_allocation_domain(cpu, tmp_mask);
1087
1088 vector = current_vector;
1089 offset = current_offset;
1090next:
1091 vector += 8;
1092 if (vector >= first_system_vector) {
1093 /* If out of vectors on large boxen, must share them. */
1094 offset = (offset + 1) % 8;
1095 vector = FIRST_EXTERNAL_VECTOR + offset;
1096 }
1097 if (unlikely(current_vector == vector))
1098 continue;
1099
1100 if (test_bit(vector, used_vectors))
1101 goto next;
1102
1103 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1104 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1105 goto next;
1106 /* Found one! */
1107 current_vector = vector;
1108 current_offset = offset;
1109 if (old_vector) {
1110 cfg->move_in_progress = 1;
1111 cpumask_copy(cfg->old_domain, cfg->domain);
1112 }
1113 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1114 per_cpu(vector_irq, new_cpu)[vector] = irq;
1115 cfg->vector = vector;
1116 cpumask_copy(cfg->domain, tmp_mask);
1117 err = 0;
1118 break;
1119 }
1120 free_cpumask_var(tmp_mask);
1121 return err;
1122}
1123
1124int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1125{
1126 int err;
1127 unsigned long flags;
1128
1129 raw_spin_lock_irqsave(&vector_lock, flags);
1130 err = __assign_irq_vector(irq, cfg, mask);
1131 raw_spin_unlock_irqrestore(&vector_lock, flags);
1132 return err;
1133}
1134
1135static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1136{
1137 int cpu, vector;
1138
1139 BUG_ON(!cfg->vector);
1140
1141 vector = cfg->vector;
1142 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1143 per_cpu(vector_irq, cpu)[vector] = -1;
1144
1145 cfg->vector = 0;
1146 cpumask_clear(cfg->domain);
1147
1148 if (likely(!cfg->move_in_progress))
1149 return;
1150 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1151 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1152 vector++) {
1153 if (per_cpu(vector_irq, cpu)[vector] != irq)
1154 continue;
1155 per_cpu(vector_irq, cpu)[vector] = -1;
1156 break;
1157 }
1158 }
1159 cfg->move_in_progress = 0;
1160}
1161
1162void __setup_vector_irq(int cpu)
1163{
1164 /* Initialize vector_irq on a new cpu */
1165 int irq, vector;
1166 struct irq_cfg *cfg;
1167
1168 /*
1169 * vector_lock will make sure that we don't run into irq vector
1170 * assignments that might be happening on another cpu in parallel,
1171 * while we setup our initial vector to irq mappings.
1172 */
1173 raw_spin_lock(&vector_lock);
1174 /* Mark the inuse vectors */
1175 for_each_active_irq(irq) {
1176 cfg = irq_get_chip_data(irq);
1177 if (!cfg)
1178 continue;
1179 /*
1180 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1181 * will be part of the irq_cfg's domain.
1182 */
1183 if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
1184 cpumask_set_cpu(cpu, cfg->domain);
1185
1186 if (!cpumask_test_cpu(cpu, cfg->domain))
1187 continue;
1188 vector = cfg->vector;
1189 per_cpu(vector_irq, cpu)[vector] = irq;
1190 }
1191 /* Mark the free vectors */
1192 for (vector = 0; vector < NR_VECTORS; ++vector) {
1193 irq = per_cpu(vector_irq, cpu)[vector];
1194 if (irq < 0)
1195 continue;
1196
1197 cfg = irq_cfg(irq);
1198 if (!cpumask_test_cpu(cpu, cfg->domain))
1199 per_cpu(vector_irq, cpu)[vector] = -1;
1200 }
1201 raw_spin_unlock(&vector_lock);
1202}
1203
1204static struct irq_chip ioapic_chip;
1205static struct irq_chip ir_ioapic_chip;
1206
1207#ifdef CONFIG_X86_32
1208static inline int IO_APIC_irq_trigger(int irq)
1209{
1210 int apic, idx, pin;
1211
1212 for (apic = 0; apic < nr_ioapics; apic++) {
1213 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1214 idx = find_irq_entry(apic, pin, mp_INT);
1215 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1216 return irq_trigger(idx);
1217 }
1218 }
1219 /*
1220 * nonexistent IRQs are edge default
1221 */
1222 return 0;
1223}
1224#else
1225static inline int IO_APIC_irq_trigger(int irq)
1226{
1227 return 1;
1228}
1229#endif
1230
1231static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
1232 unsigned long trigger)
1233{
1234 struct irq_chip *chip = &ioapic_chip;
1235 irq_flow_handler_t hdl;
1236 bool fasteoi;
1237
1238 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1239 trigger == IOAPIC_LEVEL) {
1240 irq_set_status_flags(irq, IRQ_LEVEL);
1241 fasteoi = true;
1242 } else {
1243 irq_clear_status_flags(irq, IRQ_LEVEL);
1244 fasteoi = false;
1245 }
1246
1247 if (irq_remapped(cfg)) {
1248 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
1249 chip = &ir_ioapic_chip;
1250 fasteoi = trigger != 0;
1251 }
1252
1253 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1254 irq_set_chip_and_handler_name(irq, chip, hdl,
1255 fasteoi ? "fasteoi" : "edge");
1256}
1257
1258static int setup_ioapic_entry(int apic_id, int irq,
1259 struct IO_APIC_route_entry *entry,
1260 unsigned int destination, int trigger,
1261 int polarity, int vector, int pin)
1262{
1263 /*
1264 * add it to the IO-APIC irq-routing table:
1265 */
1266 memset(entry,0,sizeof(*entry));
1267
1268 if (intr_remapping_enabled) {
1269 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1270 struct irte irte;
1271 struct IR_IO_APIC_route_entry *ir_entry =
1272 (struct IR_IO_APIC_route_entry *) entry;
1273 int index;
1274
1275 if (!iommu)
1276 panic("No mapping iommu for ioapic %d\n", apic_id);
1277
1278 index = alloc_irte(iommu, irq, 1);
1279 if (index < 0)
1280 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1281
1282 prepare_irte(&irte, vector, destination);
1283
1284 /* Set source-id of interrupt request */
1285 set_ioapic_sid(&irte, apic_id);
1286
1287 modify_irte(irq, &irte);
1288
1289 ir_entry->index2 = (index >> 15) & 0x1;
1290 ir_entry->zero = 0;
1291 ir_entry->format = 1;
1292 ir_entry->index = (index & 0x7fff);
1293 /*
1294 * IO-APIC RTE will be configured with virtual vector.
1295 * irq handler will do the explicit EOI to the io-apic.
1296 */
1297 ir_entry->vector = pin;
1298
1299 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: "
1300 "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
1301 "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
1302 "Avail:%X Vector:%02X Dest:%08X "
1303 "SID:%04X SQ:%X SVT:%X)\n",
1304 apic_id, irte.present, irte.fpd, irte.dst_mode,
1305 irte.redir_hint, irte.trigger_mode, irte.dlvry_mode,
1306 irte.avail, irte.vector, irte.dest_id,
1307 irte.sid, irte.sq, irte.svt);
1308 } else {
1309 entry->delivery_mode = apic->irq_delivery_mode;
1310 entry->dest_mode = apic->irq_dest_mode;
1311 entry->dest = destination;
1312 entry->vector = vector;
1313 }
1314
1315 entry->mask = 0; /* enable IRQ */
1316 entry->trigger = trigger;
1317 entry->polarity = polarity;
1318
1319 /* Mask level triggered irqs.
1320 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1321 */
1322 if (trigger)
1323 entry->mask = 1;
1324 return 0;
1325}
1326
1327static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq,
1328 struct irq_cfg *cfg, int trigger, int polarity)
1329{
1330 struct IO_APIC_route_entry entry;
1331 unsigned int dest;
1332
1333 if (!IO_APIC_IRQ(irq))
1334 return;
1335 /*
1336 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1337 * controllers like 8259. Now that IO-APIC can handle this irq, update
1338 * the cfg->domain.
1339 */
1340 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1341 apic->vector_allocation_domain(0, cfg->domain);
1342
1343 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1344 return;
1345
1346 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1347
1348 apic_printk(APIC_VERBOSE,KERN_DEBUG
1349 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1350 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1351 apic_id, mpc_ioapic_id(apic_id), pin, cfg->vector,
1352 irq, trigger, polarity, dest);
1353
1354
1355 if (setup_ioapic_entry(mpc_ioapic_id(apic_id), irq, &entry,
1356 dest, trigger, polarity, cfg->vector, pin)) {
1357 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1358 mpc_ioapic_id(apic_id), pin);
1359 __clear_irq_vector(irq, cfg);
1360 return;
1361 }
1362
1363 ioapic_register_intr(irq, cfg, trigger);
1364 if (irq < legacy_pic->nr_legacy_irqs)
1365 legacy_pic->mask(irq);
1366
1367 ioapic_write_entry(apic_id, pin, entry);
1368}
1369
1370static bool __init io_apic_pin_not_connected(int idx, int apic_id, int pin)
1371{
1372 if (idx != -1)
1373 return false;
1374
1375 apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
1376 mpc_ioapic_id(apic_id), pin);
1377 return true;
1378}
1379
1380static void __init __io_apic_setup_irqs(unsigned int apic_id)
1381{
1382 int idx, node = cpu_to_node(0);
1383 struct io_apic_irq_attr attr;
1384 unsigned int pin, irq;
1385
1386 for (pin = 0; pin < ioapics[apic_id].nr_registers; pin++) {
1387 idx = find_irq_entry(apic_id, pin, mp_INT);
1388 if (io_apic_pin_not_connected(idx, apic_id, pin))
1389 continue;
1390
1391 irq = pin_2_irq(idx, apic_id, pin);
1392
1393 if ((apic_id > 0) && (irq > 16))
1394 continue;
1395
1396 /*
1397 * Skip the timer IRQ if there's a quirk handler
1398 * installed and if it returns 1:
1399 */
1400 if (apic->multi_timer_check &&
1401 apic->multi_timer_check(apic_id, irq))
1402 continue;
1403
1404 set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx),
1405 irq_polarity(idx));
1406
1407 io_apic_setup_irq_pin(irq, node, &attr);
1408 }
1409}
1410
1411static void __init setup_IO_APIC_irqs(void)
1412{
1413 unsigned int apic_id;
1414
1415 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1416
1417 for (apic_id = 0; apic_id < nr_ioapics; apic_id++)
1418 __io_apic_setup_irqs(apic_id);
1419}
1420
1421/*
1422 * for the gsit that is not in first ioapic
1423 * but could not use acpi_register_gsi()
1424 * like some special sci in IBM x3330
1425 */
1426void setup_IO_APIC_irq_extra(u32 gsi)
1427{
1428 int apic_id = 0, pin, idx, irq, node = cpu_to_node(0);
1429 struct io_apic_irq_attr attr;
1430
1431 /*
1432 * Convert 'gsi' to 'ioapic.pin'.
1433 */
1434 apic_id = mp_find_ioapic(gsi);
1435 if (apic_id < 0)
1436 return;
1437
1438 pin = mp_find_ioapic_pin(apic_id, gsi);
1439 idx = find_irq_entry(apic_id, pin, mp_INT);
1440 if (idx == -1)
1441 return;
1442
1443 irq = pin_2_irq(idx, apic_id, pin);
1444
1445 /* Only handle the non legacy irqs on secondary ioapics */
1446 if (apic_id == 0 || irq < NR_IRQS_LEGACY)
1447 return;
1448
1449 set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx),
1450 irq_polarity(idx));
1451
1452 io_apic_setup_irq_pin_once(irq, node, &attr);
1453}
1454
1455/*
1456 * Set up the timer pin, possibly with the 8259A-master behind.
1457 */
1458static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1459 int vector)
1460{
1461 struct IO_APIC_route_entry entry;
1462
1463 if (intr_remapping_enabled)
1464 return;
1465
1466 memset(&entry, 0, sizeof(entry));
1467
1468 /*
1469 * We use logical delivery to get the timer IRQ
1470 * to the first CPU.
1471 */
1472 entry.dest_mode = apic->irq_dest_mode;
1473 entry.mask = 0; /* don't mask IRQ for edge */
1474 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1475 entry.delivery_mode = apic->irq_delivery_mode;
1476 entry.polarity = 0;
1477 entry.trigger = 0;
1478 entry.vector = vector;
1479
1480 /*
1481 * The timer IRQ doesn't have to know that behind the
1482 * scene we may have a 8259A-master in AEOI mode ...
1483 */
1484 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
1485 "edge");
1486
1487 /*
1488 * Add it to the IO-APIC irq-routing table:
1489 */
1490 ioapic_write_entry(apic_id, pin, entry);
1491}
1492
1493
1494__apicdebuginit(void) print_IO_APIC(void)
1495{
1496 int apic, i;
1497 union IO_APIC_reg_00 reg_00;
1498 union IO_APIC_reg_01 reg_01;
1499 union IO_APIC_reg_02 reg_02;
1500 union IO_APIC_reg_03 reg_03;
1501 unsigned long flags;
1502 struct irq_cfg *cfg;
1503 unsigned int irq;
1504
1505 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1506 for (i = 0; i < nr_ioapics; i++)
1507 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1508 mpc_ioapic_id(i), ioapics[i].nr_registers);
1509
1510 /*
1511 * We are a bit conservative about what we expect. We have to
1512 * know about every hardware change ASAP.
1513 */
1514 printk(KERN_INFO "testing the IO APIC.......................\n");
1515
1516 for (apic = 0; apic < nr_ioapics; apic++) {
1517
1518 raw_spin_lock_irqsave(&ioapic_lock, flags);
1519 reg_00.raw = io_apic_read(apic, 0);
1520 reg_01.raw = io_apic_read(apic, 1);
1521 if (reg_01.bits.version >= 0x10)
1522 reg_02.raw = io_apic_read(apic, 2);
1523 if (reg_01.bits.version >= 0x20)
1524 reg_03.raw = io_apic_read(apic, 3);
1525 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1526
1527 printk("\n");
1528 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(apic));
1529 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1530 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1531 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1532 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1533
1534 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1535 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1536 reg_01.bits.entries);
1537
1538 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1539 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1540 reg_01.bits.version);
1541
1542 /*
1543 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1544 * but the value of reg_02 is read as the previous read register
1545 * value, so ignore it if reg_02 == reg_01.
1546 */
1547 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1548 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1549 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1550 }
1551
1552 /*
1553 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1554 * or reg_03, but the value of reg_0[23] is read as the previous read
1555 * register value, so ignore it if reg_03 == reg_0[12].
1556 */
1557 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1558 reg_03.raw != reg_01.raw) {
1559 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1560 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1561 }
1562
1563 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1564
1565 if (intr_remapping_enabled) {
1566 printk(KERN_DEBUG " NR Indx Fmt Mask Trig IRR"
1567 " Pol Stat Indx2 Zero Vect:\n");
1568 } else {
1569 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1570 " Stat Dmod Deli Vect:\n");
1571 }
1572
1573 for (i = 0; i <= reg_01.bits.entries; i++) {
1574 if (intr_remapping_enabled) {
1575 struct IO_APIC_route_entry entry;
1576 struct IR_IO_APIC_route_entry *ir_entry;
1577
1578 entry = ioapic_read_entry(apic, i);
1579 ir_entry = (struct IR_IO_APIC_route_entry *) &entry;
1580 printk(KERN_DEBUG " %02x %04X ",
1581 i,
1582 ir_entry->index
1583 );
1584 printk("%1d %1d %1d %1d %1d "
1585 "%1d %1d %X %02X\n",
1586 ir_entry->format,
1587 ir_entry->mask,
1588 ir_entry->trigger,
1589 ir_entry->irr,
1590 ir_entry->polarity,
1591 ir_entry->delivery_status,
1592 ir_entry->index2,
1593 ir_entry->zero,
1594 ir_entry->vector
1595 );
1596 } else {
1597 struct IO_APIC_route_entry entry;
1598
1599 entry = ioapic_read_entry(apic, i);
1600 printk(KERN_DEBUG " %02x %02X ",
1601 i,
1602 entry.dest
1603 );
1604 printk("%1d %1d %1d %1d %1d "
1605 "%1d %1d %02X\n",
1606 entry.mask,
1607 entry.trigger,
1608 entry.irr,
1609 entry.polarity,
1610 entry.delivery_status,
1611 entry.dest_mode,
1612 entry.delivery_mode,
1613 entry.vector
1614 );
1615 }
1616 }
1617 }
1618
1619 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1620 for_each_active_irq(irq) {
1621 struct irq_pin_list *entry;
1622
1623 cfg = irq_get_chip_data(irq);
1624 if (!cfg)
1625 continue;
1626 entry = cfg->irq_2_pin;
1627 if (!entry)
1628 continue;
1629 printk(KERN_DEBUG "IRQ%d ", irq);
1630 for_each_irq_pin(entry, cfg->irq_2_pin)
1631 printk("-> %d:%d", entry->apic, entry->pin);
1632 printk("\n");
1633 }
1634
1635 printk(KERN_INFO ".................................... done.\n");
1636
1637 return;
1638}
1639
1640__apicdebuginit(void) print_APIC_field(int base)
1641{
1642 int i;
1643
1644 printk(KERN_DEBUG);
1645
1646 for (i = 0; i < 8; i++)
1647 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1648
1649 printk(KERN_CONT "\n");
1650}
1651
1652__apicdebuginit(void) print_local_APIC(void *dummy)
1653{
1654 unsigned int i, v, ver, maxlvt;
1655 u64 icr;
1656
1657 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1658 smp_processor_id(), hard_smp_processor_id());
1659 v = apic_read(APIC_ID);
1660 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1661 v = apic_read(APIC_LVR);
1662 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1663 ver = GET_APIC_VERSION(v);
1664 maxlvt = lapic_get_maxlvt();
1665
1666 v = apic_read(APIC_TASKPRI);
1667 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1668
1669 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1670 if (!APIC_XAPIC(ver)) {
1671 v = apic_read(APIC_ARBPRI);
1672 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1673 v & APIC_ARBPRI_MASK);
1674 }
1675 v = apic_read(APIC_PROCPRI);
1676 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1677 }
1678
1679 /*
1680 * Remote read supported only in the 82489DX and local APIC for
1681 * Pentium processors.
1682 */
1683 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1684 v = apic_read(APIC_RRR);
1685 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1686 }
1687
1688 v = apic_read(APIC_LDR);
1689 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1690 if (!x2apic_enabled()) {
1691 v = apic_read(APIC_DFR);
1692 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1693 }
1694 v = apic_read(APIC_SPIV);
1695 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1696
1697 printk(KERN_DEBUG "... APIC ISR field:\n");
1698 print_APIC_field(APIC_ISR);
1699 printk(KERN_DEBUG "... APIC TMR field:\n");
1700 print_APIC_field(APIC_TMR);
1701 printk(KERN_DEBUG "... APIC IRR field:\n");
1702 print_APIC_field(APIC_IRR);
1703
1704 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1705 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1706 apic_write(APIC_ESR, 0);
1707
1708 v = apic_read(APIC_ESR);
1709 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1710 }
1711
1712 icr = apic_icr_read();
1713 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1714 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1715
1716 v = apic_read(APIC_LVTT);
1717 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1718
1719 if (maxlvt > 3) { /* PC is LVT#4. */
1720 v = apic_read(APIC_LVTPC);
1721 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1722 }
1723 v = apic_read(APIC_LVT0);
1724 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1725 v = apic_read(APIC_LVT1);
1726 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1727
1728 if (maxlvt > 2) { /* ERR is LVT#3. */
1729 v = apic_read(APIC_LVTERR);
1730 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1731 }
1732
1733 v = apic_read(APIC_TMICT);
1734 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1735 v = apic_read(APIC_TMCCT);
1736 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1737 v = apic_read(APIC_TDCR);
1738 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1739
1740 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1741 v = apic_read(APIC_EFEAT);
1742 maxlvt = (v >> 16) & 0xff;
1743 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1744 v = apic_read(APIC_ECTRL);
1745 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1746 for (i = 0; i < maxlvt; i++) {
1747 v = apic_read(APIC_EILVTn(i));
1748 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1749 }
1750 }
1751 printk("\n");
1752}
1753
1754__apicdebuginit(void) print_local_APICs(int maxcpu)
1755{
1756 int cpu;
1757
1758 if (!maxcpu)
1759 return;
1760
1761 preempt_disable();
1762 for_each_online_cpu(cpu) {
1763 if (cpu >= maxcpu)
1764 break;
1765 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1766 }
1767 preempt_enable();
1768}
1769
1770__apicdebuginit(void) print_PIC(void)
1771{
1772 unsigned int v;
1773 unsigned long flags;
1774
1775 if (!legacy_pic->nr_legacy_irqs)
1776 return;
1777
1778 printk(KERN_DEBUG "\nprinting PIC contents\n");
1779
1780 raw_spin_lock_irqsave(&i8259A_lock, flags);
1781
1782 v = inb(0xa1) << 8 | inb(0x21);
1783 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1784
1785 v = inb(0xa0) << 8 | inb(0x20);
1786 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1787
1788 outb(0x0b,0xa0);
1789 outb(0x0b,0x20);
1790 v = inb(0xa0) << 8 | inb(0x20);
1791 outb(0x0a,0xa0);
1792 outb(0x0a,0x20);
1793
1794 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1795
1796 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1797
1798 v = inb(0x4d1) << 8 | inb(0x4d0);
1799 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1800}
1801
1802static int __initdata show_lapic = 1;
1803static __init int setup_show_lapic(char *arg)
1804{
1805 int num = -1;
1806
1807 if (strcmp(arg, "all") == 0) {
1808 show_lapic = CONFIG_NR_CPUS;
1809 } else {
1810 get_option(&arg, &num);
1811 if (num >= 0)
1812 show_lapic = num;
1813 }
1814
1815 return 1;
1816}
1817__setup("show_lapic=", setup_show_lapic);
1818
1819__apicdebuginit(int) print_ICs(void)
1820{
1821 if (apic_verbosity == APIC_QUIET)
1822 return 0;
1823
1824 print_PIC();
1825
1826 /* don't print out if apic is not there */
1827 if (!cpu_has_apic && !apic_from_smp_config())
1828 return 0;
1829
1830 print_local_APICs(show_lapic);
1831 print_IO_APIC();
1832
1833 return 0;
1834}
1835
1836late_initcall(print_ICs);
1837
1838
1839/* Where if anywhere is the i8259 connect in external int mode */
1840static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1841
1842void __init enable_IO_APIC(void)
1843{
1844 int i8259_apic, i8259_pin;
1845 int apic;
1846
1847 if (!legacy_pic->nr_legacy_irqs)
1848 return;
1849
1850 for(apic = 0; apic < nr_ioapics; apic++) {
1851 int pin;
1852 /* See if any of the pins is in ExtINT mode */
1853 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1854 struct IO_APIC_route_entry entry;
1855 entry = ioapic_read_entry(apic, pin);
1856
1857 /* If the interrupt line is enabled and in ExtInt mode
1858 * I have found the pin where the i8259 is connected.
1859 */
1860 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1861 ioapic_i8259.apic = apic;
1862 ioapic_i8259.pin = pin;
1863 goto found_i8259;
1864 }
1865 }
1866 }
1867 found_i8259:
1868 /* Look to see what if the MP table has reported the ExtINT */
1869 /* If we could not find the appropriate pin by looking at the ioapic
1870 * the i8259 probably is not connected the ioapic but give the
1871 * mptable a chance anyway.
1872 */
1873 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1874 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1875 /* Trust the MP table if nothing is setup in the hardware */
1876 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1877 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1878 ioapic_i8259.pin = i8259_pin;
1879 ioapic_i8259.apic = i8259_apic;
1880 }
1881 /* Complain if the MP table and the hardware disagree */
1882 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1883 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1884 {
1885 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1886 }
1887
1888 /*
1889 * Do not trust the IO-APIC being empty at bootup
1890 */
1891 clear_IO_APIC();
1892}
1893
1894/*
1895 * Not an __init, needed by the reboot code
1896 */
1897void disable_IO_APIC(void)
1898{
1899 /*
1900 * Clear the IO-APIC before rebooting:
1901 */
1902 clear_IO_APIC();
1903
1904 if (!legacy_pic->nr_legacy_irqs)
1905 return;
1906
1907 /*
1908 * If the i8259 is routed through an IOAPIC
1909 * Put that IOAPIC in virtual wire mode
1910 * so legacy interrupts can be delivered.
1911 *
1912 * With interrupt-remapping, for now we will use virtual wire A mode,
1913 * as virtual wire B is little complex (need to configure both
1914 * IOAPIC RTE as well as interrupt-remapping table entry).
1915 * As this gets called during crash dump, keep this simple for now.
1916 */
1917 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1918 struct IO_APIC_route_entry entry;
1919
1920 memset(&entry, 0, sizeof(entry));
1921 entry.mask = 0; /* Enabled */
1922 entry.trigger = 0; /* Edge */
1923 entry.irr = 0;
1924 entry.polarity = 0; /* High */
1925 entry.delivery_status = 0;
1926 entry.dest_mode = 0; /* Physical */
1927 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1928 entry.vector = 0;
1929 entry.dest = read_apic_id();
1930
1931 /*
1932 * Add it to the IO-APIC irq-routing table:
1933 */
1934 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1935 }
1936
1937 /*
1938 * Use virtual wire A mode when interrupt remapping is enabled.
1939 */
1940 if (cpu_has_apic || apic_from_smp_config())
1941 disconnect_bsp_APIC(!intr_remapping_enabled &&
1942 ioapic_i8259.pin != -1);
1943}
1944
1945#ifdef CONFIG_X86_32
1946/*
1947 * function to set the IO-APIC physical IDs based on the
1948 * values stored in the MPC table.
1949 *
1950 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1951 */
1952void __init setup_ioapic_ids_from_mpc_nocheck(void)
1953{
1954 union IO_APIC_reg_00 reg_00;
1955 physid_mask_t phys_id_present_map;
1956 int apic_id;
1957 int i;
1958 unsigned char old_id;
1959 unsigned long flags;
1960
1961 /*
1962 * This is broken; anything with a real cpu count has to
1963 * circumvent this idiocy regardless.
1964 */
1965 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1966
1967 /*
1968 * Set the IOAPIC ID to the value stored in the MPC table.
1969 */
1970 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1971
1972 /* Read the register 0 value */
1973 raw_spin_lock_irqsave(&ioapic_lock, flags);
1974 reg_00.raw = io_apic_read(apic_id, 0);
1975 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1976
1977 old_id = mpc_ioapic_id(apic_id);
1978
1979 if (mpc_ioapic_id(apic_id) >= get_physical_broadcast()) {
1980 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1981 apic_id, mpc_ioapic_id(apic_id));
1982 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1983 reg_00.bits.ID);
1984 ioapics[apic_id].mp_config.apicid = reg_00.bits.ID;
1985 }
1986
1987 /*
1988 * Sanity check, is the ID really free? Every APIC in a
1989 * system must have a unique ID or we get lots of nice
1990 * 'stuck on smp_invalidate_needed IPI wait' messages.
1991 */
1992 if (apic->check_apicid_used(&phys_id_present_map,
1993 mpc_ioapic_id(apic_id))) {
1994 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1995 apic_id, mpc_ioapic_id(apic_id));
1996 for (i = 0; i < get_physical_broadcast(); i++)
1997 if (!physid_isset(i, phys_id_present_map))
1998 break;
1999 if (i >= get_physical_broadcast())
2000 panic("Max APIC ID exceeded!\n");
2001 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2002 i);
2003 physid_set(i, phys_id_present_map);
2004 ioapics[apic_id].mp_config.apicid = i;
2005 } else {
2006 physid_mask_t tmp;
2007 apic->apicid_to_cpu_present(mpc_ioapic_id(apic_id),
2008 &tmp);
2009 apic_printk(APIC_VERBOSE, "Setting %d in the "
2010 "phys_id_present_map\n",
2011 mpc_ioapic_id(apic_id));
2012 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2013 }
2014
2015 /*
2016 * We need to adjust the IRQ routing table
2017 * if the ID changed.
2018 */
2019 if (old_id != mpc_ioapic_id(apic_id))
2020 for (i = 0; i < mp_irq_entries; i++)
2021 if (mp_irqs[i].dstapic == old_id)
2022 mp_irqs[i].dstapic
2023 = mpc_ioapic_id(apic_id);
2024
2025 /*
2026 * Update the ID register according to the right value
2027 * from the MPC table if they are different.
2028 */
2029 if (mpc_ioapic_id(apic_id) == reg_00.bits.ID)
2030 continue;
2031
2032 apic_printk(APIC_VERBOSE, KERN_INFO
2033 "...changing IO-APIC physical APIC ID to %d ...",
2034 mpc_ioapic_id(apic_id));
2035
2036 reg_00.bits.ID = mpc_ioapic_id(apic_id);
2037 raw_spin_lock_irqsave(&ioapic_lock, flags);
2038 io_apic_write(apic_id, 0, reg_00.raw);
2039 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2040
2041 /*
2042 * Sanity check
2043 */
2044 raw_spin_lock_irqsave(&ioapic_lock, flags);
2045 reg_00.raw = io_apic_read(apic_id, 0);
2046 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2047 if (reg_00.bits.ID != mpc_ioapic_id(apic_id))
2048 printk("could not set ID!\n");
2049 else
2050 apic_printk(APIC_VERBOSE, " ok.\n");
2051 }
2052}
2053
2054void __init setup_ioapic_ids_from_mpc(void)
2055{
2056
2057 if (acpi_ioapic)
2058 return;
2059 /*
2060 * Don't check I/O APIC IDs for xAPIC systems. They have
2061 * no meaning without the serial APIC bus.
2062 */
2063 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2064 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2065 return;
2066 setup_ioapic_ids_from_mpc_nocheck();
2067}
2068#endif
2069
2070int no_timer_check __initdata;
2071
2072static int __init notimercheck(char *s)
2073{
2074 no_timer_check = 1;
2075 return 1;
2076}
2077__setup("no_timer_check", notimercheck);
2078
2079/*
2080 * There is a nasty bug in some older SMP boards, their mptable lies
2081 * about the timer IRQ. We do the following to work around the situation:
2082 *
2083 * - timer IRQ defaults to IO-APIC IRQ
2084 * - if this function detects that timer IRQs are defunct, then we fall
2085 * back to ISA timer IRQs
2086 */
2087static int __init timer_irq_works(void)
2088{
2089 unsigned long t1 = jiffies;
2090 unsigned long flags;
2091
2092 if (no_timer_check)
2093 return 1;
2094
2095 local_save_flags(flags);
2096 local_irq_enable();
2097 /* Let ten ticks pass... */
2098 mdelay((10 * 1000) / HZ);
2099 local_irq_restore(flags);
2100
2101 /*
2102 * Expect a few ticks at least, to be sure some possible
2103 * glue logic does not lock up after one or two first
2104 * ticks in a non-ExtINT mode. Also the local APIC
2105 * might have cached one ExtINT interrupt. Finally, at
2106 * least one tick may be lost due to delays.
2107 */
2108
2109 /* jiffies wrap? */
2110 if (time_after(jiffies, t1 + 4))
2111 return 1;
2112 return 0;
2113}
2114
2115/*
2116 * In the SMP+IOAPIC case it might happen that there are an unspecified
2117 * number of pending IRQ events unhandled. These cases are very rare,
2118 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2119 * better to do it this way as thus we do not have to be aware of
2120 * 'pending' interrupts in the IRQ path, except at this point.
2121 */
2122/*
2123 * Edge triggered needs to resend any interrupt
2124 * that was delayed but this is now handled in the device
2125 * independent code.
2126 */
2127
2128/*
2129 * Starting up a edge-triggered IO-APIC interrupt is
2130 * nasty - we need to make sure that we get the edge.
2131 * If it is already asserted for some reason, we need
2132 * return 1 to indicate that is was pending.
2133 *
2134 * This is not complete - we should be able to fake
2135 * an edge even if it isn't on the 8259A...
2136 */
2137
2138static unsigned int startup_ioapic_irq(struct irq_data *data)
2139{
2140 int was_pending = 0, irq = data->irq;
2141 unsigned long flags;
2142
2143 raw_spin_lock_irqsave(&ioapic_lock, flags);
2144 if (irq < legacy_pic->nr_legacy_irqs) {
2145 legacy_pic->mask(irq);
2146 if (legacy_pic->irq_pending(irq))
2147 was_pending = 1;
2148 }
2149 __unmask_ioapic(data->chip_data);
2150 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2151
2152 return was_pending;
2153}
2154
2155static int ioapic_retrigger_irq(struct irq_data *data)
2156{
2157 struct irq_cfg *cfg = data->chip_data;
2158 unsigned long flags;
2159
2160 raw_spin_lock_irqsave(&vector_lock, flags);
2161 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2162 raw_spin_unlock_irqrestore(&vector_lock, flags);
2163
2164 return 1;
2165}
2166
2167/*
2168 * Level and edge triggered IO-APIC interrupts need different handling,
2169 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2170 * handled with the level-triggered descriptor, but that one has slightly
2171 * more overhead. Level-triggered interrupts cannot be handled with the
2172 * edge-triggered handler, without risking IRQ storms and other ugly
2173 * races.
2174 */
2175
2176#ifdef CONFIG_SMP
2177void send_cleanup_vector(struct irq_cfg *cfg)
2178{
2179 cpumask_var_t cleanup_mask;
2180
2181 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2182 unsigned int i;
2183 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2184 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2185 } else {
2186 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2187 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2188 free_cpumask_var(cleanup_mask);
2189 }
2190 cfg->move_in_progress = 0;
2191}
2192
2193static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2194{
2195 int apic, pin;
2196 struct irq_pin_list *entry;
2197 u8 vector = cfg->vector;
2198
2199 for_each_irq_pin(entry, cfg->irq_2_pin) {
2200 unsigned int reg;
2201
2202 apic = entry->apic;
2203 pin = entry->pin;
2204 /*
2205 * With interrupt-remapping, destination information comes
2206 * from interrupt-remapping table entry.
2207 */
2208 if (!irq_remapped(cfg))
2209 io_apic_write(apic, 0x11 + pin*2, dest);
2210 reg = io_apic_read(apic, 0x10 + pin*2);
2211 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2212 reg |= vector;
2213 io_apic_modify(apic, 0x10 + pin*2, reg);
2214 }
2215}
2216
2217/*
2218 * Either sets data->affinity to a valid value, and returns
2219 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2220 * leaves data->affinity untouched.
2221 */
2222int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2223 unsigned int *dest_id)
2224{
2225 struct irq_cfg *cfg = data->chip_data;
2226
2227 if (!cpumask_intersects(mask, cpu_online_mask))
2228 return -1;
2229
2230 if (assign_irq_vector(data->irq, data->chip_data, mask))
2231 return -1;
2232
2233 cpumask_copy(data->affinity, mask);
2234
2235 *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain);
2236 return 0;
2237}
2238
2239static int
2240ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2241 bool force)
2242{
2243 unsigned int dest, irq = data->irq;
2244 unsigned long flags;
2245 int ret;
2246
2247 raw_spin_lock_irqsave(&ioapic_lock, flags);
2248 ret = __ioapic_set_affinity(data, mask, &dest);
2249 if (!ret) {
2250 /* Only the high 8 bits are valid. */
2251 dest = SET_APIC_LOGICAL_ID(dest);
2252 __target_IO_APIC_irq(irq, dest, data->chip_data);
2253 }
2254 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2255 return ret;
2256}
2257
2258#ifdef CONFIG_INTR_REMAP
2259
2260/*
2261 * Migrate the IO-APIC irq in the presence of intr-remapping.
2262 *
2263 * For both level and edge triggered, irq migration is a simple atomic
2264 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2265 *
2266 * For level triggered, we eliminate the io-apic RTE modification (with the
2267 * updated vector information), by using a virtual vector (io-apic pin number).
2268 * Real vector that is used for interrupting cpu will be coming from
2269 * the interrupt-remapping table entry.
2270 */
2271static int
2272ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2273 bool force)
2274{
2275 struct irq_cfg *cfg = data->chip_data;
2276 unsigned int dest, irq = data->irq;
2277 struct irte irte;
2278
2279 if (!cpumask_intersects(mask, cpu_online_mask))
2280 return -EINVAL;
2281
2282 if (get_irte(irq, &irte))
2283 return -EBUSY;
2284
2285 if (assign_irq_vector(irq, cfg, mask))
2286 return -EBUSY;
2287
2288 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2289
2290 irte.vector = cfg->vector;
2291 irte.dest_id = IRTE_DEST(dest);
2292
2293 /*
2294 * Modified the IRTE and flushes the Interrupt entry cache.
2295 */
2296 modify_irte(irq, &irte);
2297
2298 if (cfg->move_in_progress)
2299 send_cleanup_vector(cfg);
2300
2301 cpumask_copy(data->affinity, mask);
2302 return 0;
2303}
2304
2305#else
2306static inline int
2307ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2308 bool force)
2309{
2310 return 0;
2311}
2312#endif
2313
2314asmlinkage void smp_irq_move_cleanup_interrupt(void)
2315{
2316 unsigned vector, me;
2317
2318 ack_APIC_irq();
2319 exit_idle();
2320 irq_enter();
2321
2322 me = smp_processor_id();
2323 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2324 unsigned int irq;
2325 unsigned int irr;
2326 struct irq_desc *desc;
2327 struct irq_cfg *cfg;
2328 irq = __this_cpu_read(vector_irq[vector]);
2329
2330 if (irq == -1)
2331 continue;
2332
2333 desc = irq_to_desc(irq);
2334 if (!desc)
2335 continue;
2336
2337 cfg = irq_cfg(irq);
2338 raw_spin_lock(&desc->lock);
2339
2340 /*
2341 * Check if the irq migration is in progress. If so, we
2342 * haven't received the cleanup request yet for this irq.
2343 */
2344 if (cfg->move_in_progress)
2345 goto unlock;
2346
2347 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2348 goto unlock;
2349
2350 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2351 /*
2352 * Check if the vector that needs to be cleanedup is
2353 * registered at the cpu's IRR. If so, then this is not
2354 * the best time to clean it up. Lets clean it up in the
2355 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2356 * to myself.
2357 */
2358 if (irr & (1 << (vector % 32))) {
2359 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2360 goto unlock;
2361 }
2362 __this_cpu_write(vector_irq[vector], -1);
2363unlock:
2364 raw_spin_unlock(&desc->lock);
2365 }
2366
2367 irq_exit();
2368}
2369
2370static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
2371{
2372 unsigned me;
2373
2374 if (likely(!cfg->move_in_progress))
2375 return;
2376
2377 me = smp_processor_id();
2378
2379 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2380 send_cleanup_vector(cfg);
2381}
2382
2383static void irq_complete_move(struct irq_cfg *cfg)
2384{
2385 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
2386}
2387
2388void irq_force_complete_move(int irq)
2389{
2390 struct irq_cfg *cfg = irq_get_chip_data(irq);
2391
2392 if (!cfg)
2393 return;
2394
2395 __irq_complete_move(cfg, cfg->vector);
2396}
2397#else
2398static inline void irq_complete_move(struct irq_cfg *cfg) { }
2399#endif
2400
2401static void ack_apic_edge(struct irq_data *data)
2402{
2403 irq_complete_move(data->chip_data);
2404 irq_move_irq(data);
2405 ack_APIC_irq();
2406}
2407
2408atomic_t irq_mis_count;
2409
2410/*
2411 * IO-APIC versions below 0x20 don't support EOI register.
2412 * For the record, here is the information about various versions:
2413 * 0Xh 82489DX
2414 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2415 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2416 * 30h-FFh Reserved
2417 *
2418 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2419 * version as 0x2. This is an error with documentation and these ICH chips
2420 * use io-apic's of version 0x20.
2421 *
2422 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2423 * Otherwise, we simulate the EOI message manually by changing the trigger
2424 * mode to edge and then back to level, with RTE being masked during this.
2425*/
2426static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2427{
2428 struct irq_pin_list *entry;
2429 unsigned long flags;
2430
2431 raw_spin_lock_irqsave(&ioapic_lock, flags);
2432 for_each_irq_pin(entry, cfg->irq_2_pin) {
2433 if (mpc_ioapic_ver(entry->apic) >= 0x20) {
2434 /*
2435 * Intr-remapping uses pin number as the virtual vector
2436 * in the RTE. Actual vector is programmed in
2437 * intr-remapping table entry. Hence for the io-apic
2438 * EOI we use the pin number.
2439 */
2440 if (irq_remapped(cfg))
2441 io_apic_eoi(entry->apic, entry->pin);
2442 else
2443 io_apic_eoi(entry->apic, cfg->vector);
2444 } else {
2445 __mask_and_edge_IO_APIC_irq(entry);
2446 __unmask_and_level_IO_APIC_irq(entry);
2447 }
2448 }
2449 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2450}
2451
2452static void ack_apic_level(struct irq_data *data)
2453{
2454 struct irq_cfg *cfg = data->chip_data;
2455 int i, do_unmask_irq = 0, irq = data->irq;
2456 unsigned long v;
2457
2458 irq_complete_move(cfg);
2459#ifdef CONFIG_GENERIC_PENDING_IRQ
2460 /* If we are moving the irq we need to mask it */
2461 if (unlikely(irqd_is_setaffinity_pending(data))) {
2462 do_unmask_irq = 1;
2463 mask_ioapic(cfg);
2464 }
2465#endif
2466
2467 /*
2468 * It appears there is an erratum which affects at least version 0x11
2469 * of I/O APIC (that's the 82093AA and cores integrated into various
2470 * chipsets). Under certain conditions a level-triggered interrupt is
2471 * erroneously delivered as edge-triggered one but the respective IRR
2472 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2473 * message but it will never arrive and further interrupts are blocked
2474 * from the source. The exact reason is so far unknown, but the
2475 * phenomenon was observed when two consecutive interrupt requests
2476 * from a given source get delivered to the same CPU and the source is
2477 * temporarily disabled in between.
2478 *
2479 * A workaround is to simulate an EOI message manually. We achieve it
2480 * by setting the trigger mode to edge and then to level when the edge
2481 * trigger mode gets detected in the TMR of a local APIC for a
2482 * level-triggered interrupt. We mask the source for the time of the
2483 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2484 * The idea is from Manfred Spraul. --macro
2485 *
2486 * Also in the case when cpu goes offline, fixup_irqs() will forward
2487 * any unhandled interrupt on the offlined cpu to the new cpu
2488 * destination that is handling the corresponding interrupt. This
2489 * interrupt forwarding is done via IPI's. Hence, in this case also
2490 * level-triggered io-apic interrupt will be seen as an edge
2491 * interrupt in the IRR. And we can't rely on the cpu's EOI
2492 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2493 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2494 * supporting EOI register, we do an explicit EOI to clear the
2495 * remote IRR and on IO-APIC's which don't have an EOI register,
2496 * we use the above logic (mask+edge followed by unmask+level) from
2497 * Manfred Spraul to clear the remote IRR.
2498 */
2499 i = cfg->vector;
2500 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2501
2502 /*
2503 * We must acknowledge the irq before we move it or the acknowledge will
2504 * not propagate properly.
2505 */
2506 ack_APIC_irq();
2507
2508 /*
2509 * Tail end of clearing remote IRR bit (either by delivering the EOI
2510 * message via io-apic EOI register write or simulating it using
2511 * mask+edge followed by unnask+level logic) manually when the
2512 * level triggered interrupt is seen as the edge triggered interrupt
2513 * at the cpu.
2514 */
2515 if (!(v & (1 << (i & 0x1f)))) {
2516 atomic_inc(&irq_mis_count);
2517
2518 eoi_ioapic_irq(irq, cfg);
2519 }
2520
2521 /* Now we can move and renable the irq */
2522 if (unlikely(do_unmask_irq)) {
2523 /* Only migrate the irq if the ack has been received.
2524 *
2525 * On rare occasions the broadcast level triggered ack gets
2526 * delayed going to ioapics, and if we reprogram the
2527 * vector while Remote IRR is still set the irq will never
2528 * fire again.
2529 *
2530 * To prevent this scenario we read the Remote IRR bit
2531 * of the ioapic. This has two effects.
2532 * - On any sane system the read of the ioapic will
2533 * flush writes (and acks) going to the ioapic from
2534 * this cpu.
2535 * - We get to see if the ACK has actually been delivered.
2536 *
2537 * Based on failed experiments of reprogramming the
2538 * ioapic entry from outside of irq context starting
2539 * with masking the ioapic entry and then polling until
2540 * Remote IRR was clear before reprogramming the
2541 * ioapic I don't trust the Remote IRR bit to be
2542 * completey accurate.
2543 *
2544 * However there appears to be no other way to plug
2545 * this race, so if the Remote IRR bit is not
2546 * accurate and is causing problems then it is a hardware bug
2547 * and you can go talk to the chipset vendor about it.
2548 */
2549 if (!io_apic_level_ack_pending(cfg))
2550 irq_move_masked_irq(data);
2551 unmask_ioapic(cfg);
2552 }
2553}
2554
2555#ifdef CONFIG_INTR_REMAP
2556static void ir_ack_apic_edge(struct irq_data *data)
2557{
2558 ack_APIC_irq();
2559}
2560
2561static void ir_ack_apic_level(struct irq_data *data)
2562{
2563 ack_APIC_irq();
2564 eoi_ioapic_irq(data->irq, data->chip_data);
2565}
2566#endif /* CONFIG_INTR_REMAP */
2567
2568static struct irq_chip ioapic_chip __read_mostly = {
2569 .name = "IO-APIC",
2570 .irq_startup = startup_ioapic_irq,
2571 .irq_mask = mask_ioapic_irq,
2572 .irq_unmask = unmask_ioapic_irq,
2573 .irq_ack = ack_apic_edge,
2574 .irq_eoi = ack_apic_level,
2575#ifdef CONFIG_SMP
2576 .irq_set_affinity = ioapic_set_affinity,
2577#endif
2578 .irq_retrigger = ioapic_retrigger_irq,
2579};
2580
2581static struct irq_chip ir_ioapic_chip __read_mostly = {
2582 .name = "IR-IO-APIC",
2583 .irq_startup = startup_ioapic_irq,
2584 .irq_mask = mask_ioapic_irq,
2585 .irq_unmask = unmask_ioapic_irq,
2586#ifdef CONFIG_INTR_REMAP
2587 .irq_ack = ir_ack_apic_edge,
2588 .irq_eoi = ir_ack_apic_level,
2589#ifdef CONFIG_SMP
2590 .irq_set_affinity = ir_ioapic_set_affinity,
2591#endif
2592#endif
2593 .irq_retrigger = ioapic_retrigger_irq,
2594};
2595
2596static inline void init_IO_APIC_traps(void)
2597{
2598 struct irq_cfg *cfg;
2599 unsigned int irq;
2600
2601 /*
2602 * NOTE! The local APIC isn't very good at handling
2603 * multiple interrupts at the same interrupt level.
2604 * As the interrupt level is determined by taking the
2605 * vector number and shifting that right by 4, we
2606 * want to spread these out a bit so that they don't
2607 * all fall in the same interrupt level.
2608 *
2609 * Also, we've got to be careful not to trash gate
2610 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2611 */
2612 for_each_active_irq(irq) {
2613 cfg = irq_get_chip_data(irq);
2614 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2615 /*
2616 * Hmm.. We don't have an entry for this,
2617 * so default to an old-fashioned 8259
2618 * interrupt if we can..
2619 */
2620 if (irq < legacy_pic->nr_legacy_irqs)
2621 legacy_pic->make_irq(irq);
2622 else
2623 /* Strange. Oh, well.. */
2624 irq_set_chip(irq, &no_irq_chip);
2625 }
2626 }
2627}
2628
2629/*
2630 * The local APIC irq-chip implementation:
2631 */
2632
2633static void mask_lapic_irq(struct irq_data *data)
2634{
2635 unsigned long v;
2636
2637 v = apic_read(APIC_LVT0);
2638 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2639}
2640
2641static void unmask_lapic_irq(struct irq_data *data)
2642{
2643 unsigned long v;
2644
2645 v = apic_read(APIC_LVT0);
2646 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2647}
2648
2649static void ack_lapic_irq(struct irq_data *data)
2650{
2651 ack_APIC_irq();
2652}
2653
2654static struct irq_chip lapic_chip __read_mostly = {
2655 .name = "local-APIC",
2656 .irq_mask = mask_lapic_irq,
2657 .irq_unmask = unmask_lapic_irq,
2658 .irq_ack = ack_lapic_irq,
2659};
2660
2661static void lapic_register_intr(int irq)
2662{
2663 irq_clear_status_flags(irq, IRQ_LEVEL);
2664 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2665 "edge");
2666}
2667
2668/*
2669 * This looks a bit hackish but it's about the only one way of sending
2670 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2671 * not support the ExtINT mode, unfortunately. We need to send these
2672 * cycles as some i82489DX-based boards have glue logic that keeps the
2673 * 8259A interrupt line asserted until INTA. --macro
2674 */
2675static inline void __init unlock_ExtINT_logic(void)
2676{
2677 int apic, pin, i;
2678 struct IO_APIC_route_entry entry0, entry1;
2679 unsigned char save_control, save_freq_select;
2680
2681 pin = find_isa_irq_pin(8, mp_INT);
2682 if (pin == -1) {
2683 WARN_ON_ONCE(1);
2684 return;
2685 }
2686 apic = find_isa_irq_apic(8, mp_INT);
2687 if (apic == -1) {
2688 WARN_ON_ONCE(1);
2689 return;
2690 }
2691
2692 entry0 = ioapic_read_entry(apic, pin);
2693 clear_IO_APIC_pin(apic, pin);
2694
2695 memset(&entry1, 0, sizeof(entry1));
2696
2697 entry1.dest_mode = 0; /* physical delivery */
2698 entry1.mask = 0; /* unmask IRQ now */
2699 entry1.dest = hard_smp_processor_id();
2700 entry1.delivery_mode = dest_ExtINT;
2701 entry1.polarity = entry0.polarity;
2702 entry1.trigger = 0;
2703 entry1.vector = 0;
2704
2705 ioapic_write_entry(apic, pin, entry1);
2706
2707 save_control = CMOS_READ(RTC_CONTROL);
2708 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2709 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2710 RTC_FREQ_SELECT);
2711 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2712
2713 i = 100;
2714 while (i-- > 0) {
2715 mdelay(10);
2716 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2717 i -= 10;
2718 }
2719
2720 CMOS_WRITE(save_control, RTC_CONTROL);
2721 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2722 clear_IO_APIC_pin(apic, pin);
2723
2724 ioapic_write_entry(apic, pin, entry0);
2725}
2726
2727static int disable_timer_pin_1 __initdata;
2728/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2729static int __init disable_timer_pin_setup(char *arg)
2730{
2731 disable_timer_pin_1 = 1;
2732 return 0;
2733}
2734early_param("disable_timer_pin_1", disable_timer_pin_setup);
2735
2736int timer_through_8259 __initdata;
2737
2738/*
2739 * This code may look a bit paranoid, but it's supposed to cooperate with
2740 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2741 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2742 * fanatically on his truly buggy board.
2743 *
2744 * FIXME: really need to revamp this for all platforms.
2745 */
2746static inline void __init check_timer(void)
2747{
2748 struct irq_cfg *cfg = irq_get_chip_data(0);
2749 int node = cpu_to_node(0);
2750 int apic1, pin1, apic2, pin2;
2751 unsigned long flags;
2752 int no_pin1 = 0;
2753
2754 local_irq_save(flags);
2755
2756 /*
2757 * get/set the timer IRQ vector:
2758 */
2759 legacy_pic->mask(0);
2760 assign_irq_vector(0, cfg, apic->target_cpus());
2761
2762 /*
2763 * As IRQ0 is to be enabled in the 8259A, the virtual
2764 * wire has to be disabled in the local APIC. Also
2765 * timer interrupts need to be acknowledged manually in
2766 * the 8259A for the i82489DX when using the NMI
2767 * watchdog as that APIC treats NMIs as level-triggered.
2768 * The AEOI mode will finish them in the 8259A
2769 * automatically.
2770 */
2771 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2772 legacy_pic->init(1);
2773
2774 pin1 = find_isa_irq_pin(0, mp_INT);
2775 apic1 = find_isa_irq_apic(0, mp_INT);
2776 pin2 = ioapic_i8259.pin;
2777 apic2 = ioapic_i8259.apic;
2778
2779 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2780 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2781 cfg->vector, apic1, pin1, apic2, pin2);
2782
2783 /*
2784 * Some BIOS writers are clueless and report the ExtINTA
2785 * I/O APIC input from the cascaded 8259A as the timer
2786 * interrupt input. So just in case, if only one pin
2787 * was found above, try it both directly and through the
2788 * 8259A.
2789 */
2790 if (pin1 == -1) {
2791 if (intr_remapping_enabled)
2792 panic("BIOS bug: timer not connected to IO-APIC");
2793 pin1 = pin2;
2794 apic1 = apic2;
2795 no_pin1 = 1;
2796 } else if (pin2 == -1) {
2797 pin2 = pin1;
2798 apic2 = apic1;
2799 }
2800
2801 if (pin1 != -1) {
2802 /*
2803 * Ok, does IRQ0 through the IOAPIC work?
2804 */
2805 if (no_pin1) {
2806 add_pin_to_irq_node(cfg, node, apic1, pin1);
2807 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2808 } else {
2809 /* for edge trigger, setup_ioapic_irq already
2810 * leave it unmasked.
2811 * so only need to unmask if it is level-trigger
2812 * do we really have level trigger timer?
2813 */
2814 int idx;
2815 idx = find_irq_entry(apic1, pin1, mp_INT);
2816 if (idx != -1 && irq_trigger(idx))
2817 unmask_ioapic(cfg);
2818 }
2819 if (timer_irq_works()) {
2820 if (disable_timer_pin_1 > 0)
2821 clear_IO_APIC_pin(0, pin1);
2822 goto out;
2823 }
2824 if (intr_remapping_enabled)
2825 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2826 local_irq_disable();
2827 clear_IO_APIC_pin(apic1, pin1);
2828 if (!no_pin1)
2829 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2830 "8254 timer not connected to IO-APIC\n");
2831
2832 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2833 "(IRQ0) through the 8259A ...\n");
2834 apic_printk(APIC_QUIET, KERN_INFO
2835 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2836 /*
2837 * legacy devices should be connected to IO APIC #0
2838 */
2839 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2840 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2841 legacy_pic->unmask(0);
2842 if (timer_irq_works()) {
2843 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2844 timer_through_8259 = 1;
2845 goto out;
2846 }
2847 /*
2848 * Cleanup, just in case ...
2849 */
2850 local_irq_disable();
2851 legacy_pic->mask(0);
2852 clear_IO_APIC_pin(apic2, pin2);
2853 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2854 }
2855
2856 apic_printk(APIC_QUIET, KERN_INFO
2857 "...trying to set up timer as Virtual Wire IRQ...\n");
2858
2859 lapic_register_intr(0);
2860 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2861 legacy_pic->unmask(0);
2862
2863 if (timer_irq_works()) {
2864 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2865 goto out;
2866 }
2867 local_irq_disable();
2868 legacy_pic->mask(0);
2869 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2870 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2871
2872 apic_printk(APIC_QUIET, KERN_INFO
2873 "...trying to set up timer as ExtINT IRQ...\n");
2874
2875 legacy_pic->init(0);
2876 legacy_pic->make_irq(0);
2877 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2878
2879 unlock_ExtINT_logic();
2880
2881 if (timer_irq_works()) {
2882 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2883 goto out;
2884 }
2885 local_irq_disable();
2886 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2887 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2888 "report. Then try booting with the 'noapic' option.\n");
2889out:
2890 local_irq_restore(flags);
2891}
2892
2893/*
2894 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2895 * to devices. However there may be an I/O APIC pin available for
2896 * this interrupt regardless. The pin may be left unconnected, but
2897 * typically it will be reused as an ExtINT cascade interrupt for
2898 * the master 8259A. In the MPS case such a pin will normally be
2899 * reported as an ExtINT interrupt in the MP table. With ACPI
2900 * there is no provision for ExtINT interrupts, and in the absence
2901 * of an override it would be treated as an ordinary ISA I/O APIC
2902 * interrupt, that is edge-triggered and unmasked by default. We
2903 * used to do this, but it caused problems on some systems because
2904 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2905 * the same ExtINT cascade interrupt to drive the local APIC of the
2906 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2907 * the I/O APIC in all cases now. No actual device should request
2908 * it anyway. --macro
2909 */
2910#define PIC_IRQS (1UL << PIC_CASCADE_IR)
2911
2912void __init setup_IO_APIC(void)
2913{
2914
2915 /*
2916 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2917 */
2918 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
2919
2920 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2921 /*
2922 * Set up IO-APIC IRQ routing.
2923 */
2924 x86_init.mpparse.setup_ioapic_ids();
2925
2926 sync_Arb_IDs();
2927 setup_IO_APIC_irqs();
2928 init_IO_APIC_traps();
2929 if (legacy_pic->nr_legacy_irqs)
2930 check_timer();
2931}
2932
2933/*
2934 * Called after all the initialization is done. If we didn't find any
2935 * APIC bugs then we can allow the modify fast path
2936 */
2937
2938static int __init io_apic_bug_finalize(void)
2939{
2940 if (sis_apic_bug == -1)
2941 sis_apic_bug = 0;
2942 return 0;
2943}
2944
2945late_initcall(io_apic_bug_finalize);
2946
2947static void resume_ioapic_id(int ioapic_id)
2948{
2949 unsigned long flags;
2950 union IO_APIC_reg_00 reg_00;
2951
2952
2953 raw_spin_lock_irqsave(&ioapic_lock, flags);
2954 reg_00.raw = io_apic_read(ioapic_id, 0);
2955 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_id)) {
2956 reg_00.bits.ID = mpc_ioapic_id(ioapic_id);
2957 io_apic_write(ioapic_id, 0, reg_00.raw);
2958 }
2959 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2960}
2961
2962static void ioapic_resume(void)
2963{
2964 int ioapic_id;
2965
2966 for (ioapic_id = nr_ioapics - 1; ioapic_id >= 0; ioapic_id--)
2967 resume_ioapic_id(ioapic_id);
2968
2969 restore_ioapic_entries();
2970}
2971
2972static struct syscore_ops ioapic_syscore_ops = {
2973 .suspend = save_ioapic_entries,
2974 .resume = ioapic_resume,
2975};
2976
2977static int __init ioapic_init_ops(void)
2978{
2979 register_syscore_ops(&ioapic_syscore_ops);
2980
2981 return 0;
2982}
2983
2984device_initcall(ioapic_init_ops);
2985
2986/*
2987 * Dynamic irq allocate and deallocation
2988 */
2989unsigned int create_irq_nr(unsigned int from, int node)
2990{
2991 struct irq_cfg *cfg;
2992 unsigned long flags;
2993 unsigned int ret = 0;
2994 int irq;
2995
2996 if (from < nr_irqs_gsi)
2997 from = nr_irqs_gsi;
2998
2999 irq = alloc_irq_from(from, node);
3000 if (irq < 0)
3001 return 0;
3002 cfg = alloc_irq_cfg(irq, node);
3003 if (!cfg) {
3004 free_irq_at(irq, NULL);
3005 return 0;
3006 }
3007
3008 raw_spin_lock_irqsave(&vector_lock, flags);
3009 if (!__assign_irq_vector(irq, cfg, apic->target_cpus()))
3010 ret = irq;
3011 raw_spin_unlock_irqrestore(&vector_lock, flags);
3012
3013 if (ret) {
3014 irq_set_chip_data(irq, cfg);
3015 irq_clear_status_flags(irq, IRQ_NOREQUEST);
3016 } else {
3017 free_irq_at(irq, cfg);
3018 }
3019 return ret;
3020}
3021
3022int create_irq(void)
3023{
3024 int node = cpu_to_node(0);
3025 unsigned int irq_want;
3026 int irq;
3027
3028 irq_want = nr_irqs_gsi;
3029 irq = create_irq_nr(irq_want, node);
3030
3031 if (irq == 0)
3032 irq = -1;
3033
3034 return irq;
3035}
3036
3037void destroy_irq(unsigned int irq)
3038{
3039 struct irq_cfg *cfg = irq_get_chip_data(irq);
3040 unsigned long flags;
3041
3042 irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
3043
3044 if (irq_remapped(cfg))
3045 free_irte(irq);
3046 raw_spin_lock_irqsave(&vector_lock, flags);
3047 __clear_irq_vector(irq, cfg);
3048 raw_spin_unlock_irqrestore(&vector_lock, flags);
3049 free_irq_at(irq, cfg);
3050}
3051
3052/*
3053 * MSI message composition
3054 */
3055#ifdef CONFIG_PCI_MSI
3056static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3057 struct msi_msg *msg, u8 hpet_id)
3058{
3059 struct irq_cfg *cfg;
3060 int err;
3061 unsigned dest;
3062
3063 if (disable_apic)
3064 return -ENXIO;
3065
3066 cfg = irq_cfg(irq);
3067 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3068 if (err)
3069 return err;
3070
3071 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3072
3073 if (irq_remapped(cfg)) {
3074 struct irte irte;
3075 int ir_index;
3076 u16 sub_handle;
3077
3078 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3079 BUG_ON(ir_index == -1);
3080
3081 prepare_irte(&irte, cfg->vector, dest);
3082
3083 /* Set source-id of interrupt request */
3084 if (pdev)
3085 set_msi_sid(&irte, pdev);
3086 else
3087 set_hpet_sid(&irte, hpet_id);
3088
3089 modify_irte(irq, &irte);
3090
3091 msg->address_hi = MSI_ADDR_BASE_HI;
3092 msg->data = sub_handle;
3093 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3094 MSI_ADDR_IR_SHV |
3095 MSI_ADDR_IR_INDEX1(ir_index) |
3096 MSI_ADDR_IR_INDEX2(ir_index);
3097 } else {
3098 if (x2apic_enabled())
3099 msg->address_hi = MSI_ADDR_BASE_HI |
3100 MSI_ADDR_EXT_DEST_ID(dest);
3101 else
3102 msg->address_hi = MSI_ADDR_BASE_HI;
3103
3104 msg->address_lo =
3105 MSI_ADDR_BASE_LO |
3106 ((apic->irq_dest_mode == 0) ?
3107 MSI_ADDR_DEST_MODE_PHYSICAL:
3108 MSI_ADDR_DEST_MODE_LOGICAL) |
3109 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3110 MSI_ADDR_REDIRECTION_CPU:
3111 MSI_ADDR_REDIRECTION_LOWPRI) |
3112 MSI_ADDR_DEST_ID(dest);
3113
3114 msg->data =
3115 MSI_DATA_TRIGGER_EDGE |
3116 MSI_DATA_LEVEL_ASSERT |
3117 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3118 MSI_DATA_DELIVERY_FIXED:
3119 MSI_DATA_DELIVERY_LOWPRI) |
3120 MSI_DATA_VECTOR(cfg->vector);
3121 }
3122 return err;
3123}
3124
3125#ifdef CONFIG_SMP
3126static int
3127msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3128{
3129 struct irq_cfg *cfg = data->chip_data;
3130 struct msi_msg msg;
3131 unsigned int dest;
3132
3133 if (__ioapic_set_affinity(data, mask, &dest))
3134 return -1;
3135
3136 __get_cached_msi_msg(data->msi_desc, &msg);
3137
3138 msg.data &= ~MSI_DATA_VECTOR_MASK;
3139 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3140 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3141 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3142
3143 __write_msi_msg(data->msi_desc, &msg);
3144
3145 return 0;
3146}
3147#ifdef CONFIG_INTR_REMAP
3148/*
3149 * Migrate the MSI irq to another cpumask. This migration is
3150 * done in the process context using interrupt-remapping hardware.
3151 */
3152static int
3153ir_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3154 bool force)
3155{
3156 struct irq_cfg *cfg = data->chip_data;
3157 unsigned int dest, irq = data->irq;
3158 struct irte irte;
3159
3160 if (get_irte(irq, &irte))
3161 return -1;
3162
3163 if (__ioapic_set_affinity(data, mask, &dest))
3164 return -1;
3165
3166 irte.vector = cfg->vector;
3167 irte.dest_id = IRTE_DEST(dest);
3168
3169 /*
3170 * atomically update the IRTE with the new destination and vector.
3171 */
3172 modify_irte(irq, &irte);
3173
3174 /*
3175 * After this point, all the interrupts will start arriving
3176 * at the new destination. So, time to cleanup the previous
3177 * vector allocation.
3178 */
3179 if (cfg->move_in_progress)
3180 send_cleanup_vector(cfg);
3181
3182 return 0;
3183}
3184
3185#endif
3186#endif /* CONFIG_SMP */
3187
3188/*
3189 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3190 * which implement the MSI or MSI-X Capability Structure.
3191 */
3192static struct irq_chip msi_chip = {
3193 .name = "PCI-MSI",
3194 .irq_unmask = unmask_msi_irq,
3195 .irq_mask = mask_msi_irq,
3196 .irq_ack = ack_apic_edge,
3197#ifdef CONFIG_SMP
3198 .irq_set_affinity = msi_set_affinity,
3199#endif
3200 .irq_retrigger = ioapic_retrigger_irq,
3201};
3202
3203static struct irq_chip msi_ir_chip = {
3204 .name = "IR-PCI-MSI",
3205 .irq_unmask = unmask_msi_irq,
3206 .irq_mask = mask_msi_irq,
3207#ifdef CONFIG_INTR_REMAP
3208 .irq_ack = ir_ack_apic_edge,
3209#ifdef CONFIG_SMP
3210 .irq_set_affinity = ir_msi_set_affinity,
3211#endif
3212#endif
3213 .irq_retrigger = ioapic_retrigger_irq,
3214};
3215
3216/*
3217 * Map the PCI dev to the corresponding remapping hardware unit
3218 * and allocate 'nvec' consecutive interrupt-remapping table entries
3219 * in it.
3220 */
3221static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3222{
3223 struct intel_iommu *iommu;
3224 int index;
3225
3226 iommu = map_dev_to_ir(dev);
3227 if (!iommu) {
3228 printk(KERN_ERR
3229 "Unable to map PCI %s to iommu\n", pci_name(dev));
3230 return -ENOENT;
3231 }
3232
3233 index = alloc_irte(iommu, irq, nvec);
3234 if (index < 0) {
3235 printk(KERN_ERR
3236 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3237 pci_name(dev));
3238 return -ENOSPC;
3239 }
3240 return index;
3241}
3242
3243static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3244{
3245 struct irq_chip *chip = &msi_chip;
3246 struct msi_msg msg;
3247 int ret;
3248
3249 ret = msi_compose_msg(dev, irq, &msg, -1);
3250 if (ret < 0)
3251 return ret;
3252
3253 irq_set_msi_desc(irq, msidesc);
3254 write_msi_msg(irq, &msg);
3255
3256 if (irq_remapped(irq_get_chip_data(irq))) {
3257 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3258 chip = &msi_ir_chip;
3259 }
3260
3261 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3262
3263 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3264
3265 return 0;
3266}
3267
3268int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3269{
3270 int node, ret, sub_handle, index = 0;
3271 unsigned int irq, irq_want;
3272 struct msi_desc *msidesc;
3273 struct intel_iommu *iommu = NULL;
3274
3275 /* x86 doesn't support multiple MSI yet */
3276 if (type == PCI_CAP_ID_MSI && nvec > 1)
3277 return 1;
3278
3279 node = dev_to_node(&dev->dev);
3280 irq_want = nr_irqs_gsi;
3281 sub_handle = 0;
3282 list_for_each_entry(msidesc, &dev->msi_list, list) {
3283 irq = create_irq_nr(irq_want, node);
3284 if (irq == 0)
3285 return -1;
3286 irq_want = irq + 1;
3287 if (!intr_remapping_enabled)
3288 goto no_ir;
3289
3290 if (!sub_handle) {
3291 /*
3292 * allocate the consecutive block of IRTE's
3293 * for 'nvec'
3294 */
3295 index = msi_alloc_irte(dev, irq, nvec);
3296 if (index < 0) {
3297 ret = index;
3298 goto error;
3299 }
3300 } else {
3301 iommu = map_dev_to_ir(dev);
3302 if (!iommu) {
3303 ret = -ENOENT;
3304 goto error;
3305 }
3306 /*
3307 * setup the mapping between the irq and the IRTE
3308 * base index, the sub_handle pointing to the
3309 * appropriate interrupt remap table entry.
3310 */
3311 set_irte_irq(irq, iommu, index, sub_handle);
3312 }
3313no_ir:
3314 ret = setup_msi_irq(dev, msidesc, irq);
3315 if (ret < 0)
3316 goto error;
3317 sub_handle++;
3318 }
3319 return 0;
3320
3321error:
3322 destroy_irq(irq);
3323 return ret;
3324}
3325
3326void native_teardown_msi_irq(unsigned int irq)
3327{
3328 destroy_irq(irq);
3329}
3330
3331#if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3332#ifdef CONFIG_SMP
3333static int
3334dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3335 bool force)
3336{
3337 struct irq_cfg *cfg = data->chip_data;
3338 unsigned int dest, irq = data->irq;
3339 struct msi_msg msg;
3340
3341 if (__ioapic_set_affinity(data, mask, &dest))
3342 return -1;
3343
3344 dmar_msi_read(irq, &msg);
3345
3346 msg.data &= ~MSI_DATA_VECTOR_MASK;
3347 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3348 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3349 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3350 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
3351
3352 dmar_msi_write(irq, &msg);
3353
3354 return 0;
3355}
3356
3357#endif /* CONFIG_SMP */
3358
3359static struct irq_chip dmar_msi_type = {
3360 .name = "DMAR_MSI",
3361 .irq_unmask = dmar_msi_unmask,
3362 .irq_mask = dmar_msi_mask,
3363 .irq_ack = ack_apic_edge,
3364#ifdef CONFIG_SMP
3365 .irq_set_affinity = dmar_msi_set_affinity,
3366#endif
3367 .irq_retrigger = ioapic_retrigger_irq,
3368};
3369
3370int arch_setup_dmar_msi(unsigned int irq)
3371{
3372 int ret;
3373 struct msi_msg msg;
3374
3375 ret = msi_compose_msg(NULL, irq, &msg, -1);
3376 if (ret < 0)
3377 return ret;
3378 dmar_msi_write(irq, &msg);
3379 irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3380 "edge");
3381 return 0;
3382}
3383#endif
3384
3385#ifdef CONFIG_HPET_TIMER
3386
3387#ifdef CONFIG_SMP
3388static int hpet_msi_set_affinity(struct irq_data *data,
3389 const struct cpumask *mask, bool force)
3390{
3391 struct irq_cfg *cfg = data->chip_data;
3392 struct msi_msg msg;
3393 unsigned int dest;
3394
3395 if (__ioapic_set_affinity(data, mask, &dest))
3396 return -1;
3397
3398 hpet_msi_read(data->handler_data, &msg);
3399
3400 msg.data &= ~MSI_DATA_VECTOR_MASK;
3401 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3402 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3403 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3404
3405 hpet_msi_write(data->handler_data, &msg);
3406
3407 return 0;
3408}
3409
3410#endif /* CONFIG_SMP */
3411
3412static struct irq_chip ir_hpet_msi_type = {
3413 .name = "IR-HPET_MSI",
3414 .irq_unmask = hpet_msi_unmask,
3415 .irq_mask = hpet_msi_mask,
3416#ifdef CONFIG_INTR_REMAP
3417 .irq_ack = ir_ack_apic_edge,
3418#ifdef CONFIG_SMP
3419 .irq_set_affinity = ir_msi_set_affinity,
3420#endif
3421#endif
3422 .irq_retrigger = ioapic_retrigger_irq,
3423};
3424
3425static struct irq_chip hpet_msi_type = {
3426 .name = "HPET_MSI",
3427 .irq_unmask = hpet_msi_unmask,
3428 .irq_mask = hpet_msi_mask,
3429 .irq_ack = ack_apic_edge,
3430#ifdef CONFIG_SMP
3431 .irq_set_affinity = hpet_msi_set_affinity,
3432#endif
3433 .irq_retrigger = ioapic_retrigger_irq,
3434};
3435
3436int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3437{
3438 struct irq_chip *chip = &hpet_msi_type;
3439 struct msi_msg msg;
3440 int ret;
3441
3442 if (intr_remapping_enabled) {
3443 struct intel_iommu *iommu = map_hpet_to_ir(id);
3444 int index;
3445
3446 if (!iommu)
3447 return -1;
3448
3449 index = alloc_irte(iommu, irq, 1);
3450 if (index < 0)
3451 return -1;
3452 }
3453
3454 ret = msi_compose_msg(NULL, irq, &msg, id);
3455 if (ret < 0)
3456 return ret;
3457
3458 hpet_msi_write(irq_get_handler_data(irq), &msg);
3459 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3460 if (irq_remapped(irq_get_chip_data(irq)))
3461 chip = &ir_hpet_msi_type;
3462
3463 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3464 return 0;
3465}
3466#endif
3467
3468#endif /* CONFIG_PCI_MSI */
3469/*
3470 * Hypertransport interrupt support
3471 */
3472#ifdef CONFIG_HT_IRQ
3473
3474#ifdef CONFIG_SMP
3475
3476static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3477{
3478 struct ht_irq_msg msg;
3479 fetch_ht_irq_msg(irq, &msg);
3480
3481 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3482 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3483
3484 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3485 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3486
3487 write_ht_irq_msg(irq, &msg);
3488}
3489
3490static int
3491ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3492{
3493 struct irq_cfg *cfg = data->chip_data;
3494 unsigned int dest;
3495
3496 if (__ioapic_set_affinity(data, mask, &dest))
3497 return -1;
3498
3499 target_ht_irq(data->irq, dest, cfg->vector);
3500 return 0;
3501}
3502
3503#endif
3504
3505static struct irq_chip ht_irq_chip = {
3506 .name = "PCI-HT",
3507 .irq_mask = mask_ht_irq,
3508 .irq_unmask = unmask_ht_irq,
3509 .irq_ack = ack_apic_edge,
3510#ifdef CONFIG_SMP
3511 .irq_set_affinity = ht_set_affinity,
3512#endif
3513 .irq_retrigger = ioapic_retrigger_irq,
3514};
3515
3516int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3517{
3518 struct irq_cfg *cfg;
3519 int err;
3520
3521 if (disable_apic)
3522 return -ENXIO;
3523
3524 cfg = irq_cfg(irq);
3525 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3526 if (!err) {
3527 struct ht_irq_msg msg;
3528 unsigned dest;
3529
3530 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3531 apic->target_cpus());
3532
3533 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3534
3535 msg.address_lo =
3536 HT_IRQ_LOW_BASE |
3537 HT_IRQ_LOW_DEST_ID(dest) |
3538 HT_IRQ_LOW_VECTOR(cfg->vector) |
3539 ((apic->irq_dest_mode == 0) ?
3540 HT_IRQ_LOW_DM_PHYSICAL :
3541 HT_IRQ_LOW_DM_LOGICAL) |
3542 HT_IRQ_LOW_RQEOI_EDGE |
3543 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3544 HT_IRQ_LOW_MT_FIXED :
3545 HT_IRQ_LOW_MT_ARBITRATED) |
3546 HT_IRQ_LOW_IRQ_MASKED;
3547
3548 write_ht_irq_msg(irq, &msg);
3549
3550 irq_set_chip_and_handler_name(irq, &ht_irq_chip,
3551 handle_edge_irq, "edge");
3552
3553 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3554 }
3555 return err;
3556}
3557#endif /* CONFIG_HT_IRQ */
3558
3559static int
3560io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
3561{
3562 struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
3563 int ret;
3564
3565 if (!cfg)
3566 return -EINVAL;
3567 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
3568 if (!ret)
3569 setup_ioapic_irq(attr->ioapic, attr->ioapic_pin, irq, cfg,
3570 attr->trigger, attr->polarity);
3571 return ret;
3572}
3573
3574int io_apic_setup_irq_pin_once(unsigned int irq, int node,
3575 struct io_apic_irq_attr *attr)
3576{
3577 unsigned int id = attr->ioapic, pin = attr->ioapic_pin;
3578 int ret;
3579
3580 /* Avoid redundant programming */
3581 if (test_bit(pin, ioapics[id].pin_programmed)) {
3582 pr_debug("Pin %d-%d already programmed\n",
3583 mpc_ioapic_id(id), pin);
3584 return 0;
3585 }
3586 ret = io_apic_setup_irq_pin(irq, node, attr);
3587 if (!ret)
3588 set_bit(pin, ioapics[id].pin_programmed);
3589 return ret;
3590}
3591
3592static int __init io_apic_get_redir_entries(int ioapic)
3593{
3594 union IO_APIC_reg_01 reg_01;
3595 unsigned long flags;
3596
3597 raw_spin_lock_irqsave(&ioapic_lock, flags);
3598 reg_01.raw = io_apic_read(ioapic, 1);
3599 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3600
3601 /* The register returns the maximum index redir index
3602 * supported, which is one less than the total number of redir
3603 * entries.
3604 */
3605 return reg_01.bits.entries + 1;
3606}
3607
3608static void __init probe_nr_irqs_gsi(void)
3609{
3610 int nr;
3611
3612 nr = gsi_top + NR_IRQS_LEGACY;
3613 if (nr > nr_irqs_gsi)
3614 nr_irqs_gsi = nr;
3615
3616 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3617}
3618
3619int get_nr_irqs_gsi(void)
3620{
3621 return nr_irqs_gsi;
3622}
3623
3624#ifdef CONFIG_SPARSE_IRQ
3625int __init arch_probe_nr_irqs(void)
3626{
3627 int nr;
3628
3629 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3630 nr_irqs = NR_VECTORS * nr_cpu_ids;
3631
3632 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3633#if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3634 /*
3635 * for MSI and HT dyn irq
3636 */
3637 nr += nr_irqs_gsi * 16;
3638#endif
3639 if (nr < nr_irqs)
3640 nr_irqs = nr;
3641
3642 return NR_IRQS_LEGACY;
3643}
3644#endif
3645
3646int io_apic_set_pci_routing(struct device *dev, int irq,
3647 struct io_apic_irq_attr *irq_attr)
3648{
3649 int node;
3650
3651 if (!IO_APIC_IRQ(irq)) {
3652 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3653 irq_attr->ioapic);
3654 return -EINVAL;
3655 }
3656
3657 node = dev ? dev_to_node(dev) : cpu_to_node(0);
3658
3659 return io_apic_setup_irq_pin_once(irq, node, irq_attr);
3660}
3661
3662#ifdef CONFIG_X86_32
3663static int __init io_apic_get_unique_id(int ioapic, int apic_id)
3664{
3665 union IO_APIC_reg_00 reg_00;
3666 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3667 physid_mask_t tmp;
3668 unsigned long flags;
3669 int i = 0;
3670
3671 /*
3672 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3673 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3674 * supports up to 16 on one shared APIC bus.
3675 *
3676 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3677 * advantage of new APIC bus architecture.
3678 */
3679
3680 if (physids_empty(apic_id_map))
3681 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3682
3683 raw_spin_lock_irqsave(&ioapic_lock, flags);
3684 reg_00.raw = io_apic_read(ioapic, 0);
3685 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3686
3687 if (apic_id >= get_physical_broadcast()) {
3688 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3689 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3690 apic_id = reg_00.bits.ID;
3691 }
3692
3693 /*
3694 * Every APIC in a system must have a unique ID or we get lots of nice
3695 * 'stuck on smp_invalidate_needed IPI wait' messages.
3696 */
3697 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3698
3699 for (i = 0; i < get_physical_broadcast(); i++) {
3700 if (!apic->check_apicid_used(&apic_id_map, i))
3701 break;
3702 }
3703
3704 if (i == get_physical_broadcast())
3705 panic("Max apic_id exceeded!\n");
3706
3707 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3708 "trying %d\n", ioapic, apic_id, i);
3709
3710 apic_id = i;
3711 }
3712
3713 apic->apicid_to_cpu_present(apic_id, &tmp);
3714 physids_or(apic_id_map, apic_id_map, tmp);
3715
3716 if (reg_00.bits.ID != apic_id) {
3717 reg_00.bits.ID = apic_id;
3718
3719 raw_spin_lock_irqsave(&ioapic_lock, flags);
3720 io_apic_write(ioapic, 0, reg_00.raw);
3721 reg_00.raw = io_apic_read(ioapic, 0);
3722 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3723
3724 /* Sanity check */
3725 if (reg_00.bits.ID != apic_id) {
3726 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3727 return -1;
3728 }
3729 }
3730
3731 apic_printk(APIC_VERBOSE, KERN_INFO
3732 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3733
3734 return apic_id;
3735}
3736
3737static u8 __init io_apic_unique_id(u8 id)
3738{
3739 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3740 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3741 return io_apic_get_unique_id(nr_ioapics, id);
3742 else
3743 return id;
3744}
3745#else
3746static u8 __init io_apic_unique_id(u8 id)
3747{
3748 int i;
3749 DECLARE_BITMAP(used, 256);
3750
3751 bitmap_zero(used, 256);
3752 for (i = 0; i < nr_ioapics; i++) {
3753 __set_bit(mpc_ioapic_id(i), used);
3754 }
3755 if (!test_bit(id, used))
3756 return id;
3757 return find_first_zero_bit(used, 256);
3758}
3759#endif
3760
3761static int __init io_apic_get_version(int ioapic)
3762{
3763 union IO_APIC_reg_01 reg_01;
3764 unsigned long flags;
3765
3766 raw_spin_lock_irqsave(&ioapic_lock, flags);
3767 reg_01.raw = io_apic_read(ioapic, 1);
3768 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3769
3770 return reg_01.bits.version;
3771}
3772
3773int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3774{
3775 int ioapic, pin, idx;
3776
3777 if (skip_ioapic_setup)
3778 return -1;
3779
3780 ioapic = mp_find_ioapic(gsi);
3781 if (ioapic < 0)
3782 return -1;
3783
3784 pin = mp_find_ioapic_pin(ioapic, gsi);
3785 if (pin < 0)
3786 return -1;
3787
3788 idx = find_irq_entry(ioapic, pin, mp_INT);
3789 if (idx < 0)
3790 return -1;
3791
3792 *trigger = irq_trigger(idx);
3793 *polarity = irq_polarity(idx);
3794 return 0;
3795}
3796
3797/*
3798 * This function currently is only a helper for the i386 smp boot process where
3799 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3800 * so mask in all cases should simply be apic->target_cpus()
3801 */
3802#ifdef CONFIG_SMP
3803void __init setup_ioapic_dest(void)
3804{
3805 int pin, ioapic, irq, irq_entry;
3806 const struct cpumask *mask;
3807 struct irq_data *idata;
3808
3809 if (skip_ioapic_setup == 1)
3810 return;
3811
3812 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
3813 for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) {
3814 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3815 if (irq_entry == -1)
3816 continue;
3817 irq = pin_2_irq(irq_entry, ioapic, pin);
3818
3819 if ((ioapic > 0) && (irq > 16))
3820 continue;
3821
3822 idata = irq_get_irq_data(irq);
3823
3824 /*
3825 * Honour affinities which have been set in early boot
3826 */
3827 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
3828 mask = idata->affinity;
3829 else
3830 mask = apic->target_cpus();
3831
3832 if (intr_remapping_enabled)
3833 ir_ioapic_set_affinity(idata, mask, false);
3834 else
3835 ioapic_set_affinity(idata, mask, false);
3836 }
3837
3838}
3839#endif
3840
3841#define IOAPIC_RESOURCE_NAME_SIZE 11
3842
3843static struct resource *ioapic_resources;
3844
3845static struct resource * __init ioapic_setup_resources(int nr_ioapics)
3846{
3847 unsigned long n;
3848 struct resource *res;
3849 char *mem;
3850 int i;
3851
3852 if (nr_ioapics <= 0)
3853 return NULL;
3854
3855 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3856 n *= nr_ioapics;
3857
3858 mem = alloc_bootmem(n);
3859 res = (void *)mem;
3860
3861 mem += sizeof(struct resource) * nr_ioapics;
3862
3863 for (i = 0; i < nr_ioapics; i++) {
3864 res[i].name = mem;
3865 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3866 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
3867 mem += IOAPIC_RESOURCE_NAME_SIZE;
3868 }
3869
3870 ioapic_resources = res;
3871
3872 return res;
3873}
3874
3875void __init ioapic_and_gsi_init(void)
3876{
3877 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3878 struct resource *ioapic_res;
3879 int i;
3880
3881 ioapic_res = ioapic_setup_resources(nr_ioapics);
3882 for (i = 0; i < nr_ioapics; i++) {
3883 if (smp_found_config) {
3884 ioapic_phys = mpc_ioapic_addr(i);
3885#ifdef CONFIG_X86_32
3886 if (!ioapic_phys) {
3887 printk(KERN_ERR
3888 "WARNING: bogus zero IO-APIC "
3889 "address found in MPTABLE, "
3890 "disabling IO/APIC support!\n");
3891 smp_found_config = 0;
3892 skip_ioapic_setup = 1;
3893 goto fake_ioapic_page;
3894 }
3895#endif
3896 } else {
3897#ifdef CONFIG_X86_32
3898fake_ioapic_page:
3899#endif
3900 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
3901 ioapic_phys = __pa(ioapic_phys);
3902 }
3903 set_fixmap_nocache(idx, ioapic_phys);
3904 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
3905 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
3906 ioapic_phys);
3907 idx++;
3908
3909 ioapic_res->start = ioapic_phys;
3910 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
3911 ioapic_res++;
3912 }
3913
3914 probe_nr_irqs_gsi();
3915}
3916
3917void __init ioapic_insert_resources(void)
3918{
3919 int i;
3920 struct resource *r = ioapic_resources;
3921
3922 if (!r) {
3923 if (nr_ioapics > 0)
3924 printk(KERN_ERR
3925 "IO APIC resources couldn't be allocated.\n");
3926 return;
3927 }
3928
3929 for (i = 0; i < nr_ioapics; i++) {
3930 insert_resource(&iomem_resource, r);
3931 r++;
3932 }
3933}
3934
3935int mp_find_ioapic(u32 gsi)
3936{
3937 int i = 0;
3938
3939 if (nr_ioapics == 0)
3940 return -1;
3941
3942 /* Find the IOAPIC that manages this GSI. */
3943 for (i = 0; i < nr_ioapics; i++) {
3944 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
3945 if ((gsi >= gsi_cfg->gsi_base)
3946 && (gsi <= gsi_cfg->gsi_end))
3947 return i;
3948 }
3949
3950 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
3951 return -1;
3952}
3953
3954int mp_find_ioapic_pin(int ioapic, u32 gsi)
3955{
3956 struct mp_ioapic_gsi *gsi_cfg;
3957
3958 if (WARN_ON(ioapic == -1))
3959 return -1;
3960
3961 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
3962 if (WARN_ON(gsi > gsi_cfg->gsi_end))
3963 return -1;
3964
3965 return gsi - gsi_cfg->gsi_base;
3966}
3967
3968static __init int bad_ioapic(unsigned long address)
3969{
3970 if (nr_ioapics >= MAX_IO_APICS) {
3971 printk(KERN_WARNING "WARNING: Max # of I/O APICs (%d) exceeded "
3972 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
3973 return 1;
3974 }
3975 if (!address) {
3976 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
3977 " found in table, skipping!\n");
3978 return 1;
3979 }
3980 return 0;
3981}
3982
3983void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
3984{
3985 int idx = 0;
3986 int entries;
3987 struct mp_ioapic_gsi *gsi_cfg;
3988
3989 if (bad_ioapic(address))
3990 return;
3991
3992 idx = nr_ioapics;
3993
3994 ioapics[idx].mp_config.type = MP_IOAPIC;
3995 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
3996 ioapics[idx].mp_config.apicaddr = address;
3997
3998 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
3999 ioapics[idx].mp_config.apicid = io_apic_unique_id(id);
4000 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
4001
4002 /*
4003 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4004 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4005 */
4006 entries = io_apic_get_redir_entries(idx);
4007 gsi_cfg = mp_ioapic_gsi_routing(idx);
4008 gsi_cfg->gsi_base = gsi_base;
4009 gsi_cfg->gsi_end = gsi_base + entries - 1;
4010
4011 /*
4012 * The number of IO-APIC IRQ registers (== #pins):
4013 */
4014 ioapics[idx].nr_registers = entries;
4015
4016 if (gsi_cfg->gsi_end >= gsi_top)
4017 gsi_top = gsi_cfg->gsi_end + 1;
4018
4019 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4020 "GSI %d-%d\n", idx, mpc_ioapic_id(idx),
4021 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
4022 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
4023
4024 nr_ioapics++;
4025}
4026
4027/* Enable IOAPIC early just for system timer */
4028void __init pre_init_apic_IRQ0(void)
4029{
4030 struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
4031
4032 printk(KERN_INFO "Early APIC setup for system timer0\n");
4033#ifndef CONFIG_SMP
4034 physid_set_mask_of_physid(boot_cpu_physical_apicid,
4035 &phys_cpu_present_map);
4036#endif
4037 setup_local_APIC();
4038
4039 io_apic_setup_irq_pin(0, 0, &attr);
4040 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
4041 "edge");
4042}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Intel IO-APIC support for multi-Pentium hosts.
4 *
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 *
7 * Many thanks to Stig Venaas for trying out countless experimental
8 * patches and reporting/debugging problems patiently!
9 *
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
12 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
13 * further tested and cleaned up by Zach Brown <zab@redhat.com>
14 * and Ingo Molnar <mingo@redhat.com>
15 *
16 * Fixes
17 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
18 * thanks to Eric Gilmore
19 * and Rolf G. Tews
20 * for testing these extensively
21 * Paul Diefenbaugh : Added full ACPI support
22 *
23 * Historical information which is worth to be preserved:
24 *
25 * - SiS APIC rmw bug:
26 *
27 * We used to have a workaround for a bug in SiS chips which
28 * required to rewrite the index register for a read-modify-write
29 * operation as the chip lost the index information which was
30 * setup for the read already. We cache the data now, so that
31 * workaround has been removed.
32 */
33
34#include <linux/mm.h>
35#include <linux/interrupt.h>
36#include <linux/irq.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/sched.h>
40#include <linux/pci.h>
41#include <linux/mc146818rtc.h>
42#include <linux/compiler.h>
43#include <linux/acpi.h>
44#include <linux/export.h>
45#include <linux/syscore_ops.h>
46#include <linux/freezer.h>
47#include <linux/kthread.h>
48#include <linux/jiffies.h> /* time_after() */
49#include <linux/slab.h>
50#include <linux/memblock.h>
51
52#include <asm/irqdomain.h>
53#include <asm/io.h>
54#include <asm/smp.h>
55#include <asm/cpu.h>
56#include <asm/desc.h>
57#include <asm/proto.h>
58#include <asm/acpi.h>
59#include <asm/dma.h>
60#include <asm/timer.h>
61#include <asm/time.h>
62#include <asm/i8259.h>
63#include <asm/setup.h>
64#include <asm/irq_remapping.h>
65#include <asm/hw_irq.h>
66
67#include <asm/apic.h>
68
69#define for_each_ioapic(idx) \
70 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
71#define for_each_ioapic_reverse(idx) \
72 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
73#define for_each_pin(idx, pin) \
74 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
75#define for_each_ioapic_pin(idx, pin) \
76 for_each_ioapic((idx)) \
77 for_each_pin((idx), (pin))
78#define for_each_irq_pin(entry, head) \
79 list_for_each_entry(entry, &head, list)
80
81static DEFINE_RAW_SPINLOCK(ioapic_lock);
82static DEFINE_MUTEX(ioapic_mutex);
83static unsigned int ioapic_dynirq_base;
84static int ioapic_initialized;
85
86struct irq_pin_list {
87 struct list_head list;
88 int apic, pin;
89};
90
91struct mp_chip_data {
92 struct list_head irq_2_pin;
93 struct IO_APIC_route_entry entry;
94 int trigger;
95 int polarity;
96 u32 count;
97 bool isa_irq;
98};
99
100struct mp_ioapic_gsi {
101 u32 gsi_base;
102 u32 gsi_end;
103};
104
105static struct ioapic {
106 /*
107 * # of IRQ routing registers
108 */
109 int nr_registers;
110 /*
111 * Saved state during suspend/resume, or while enabling intr-remap.
112 */
113 struct IO_APIC_route_entry *saved_registers;
114 /* I/O APIC config */
115 struct mpc_ioapic mp_config;
116 /* IO APIC gsi routing info */
117 struct mp_ioapic_gsi gsi_config;
118 struct ioapic_domain_cfg irqdomain_cfg;
119 struct irq_domain *irqdomain;
120 struct resource *iomem_res;
121} ioapics[MAX_IO_APICS];
122
123#define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
124
125int mpc_ioapic_id(int ioapic_idx)
126{
127 return ioapics[ioapic_idx].mp_config.apicid;
128}
129
130unsigned int mpc_ioapic_addr(int ioapic_idx)
131{
132 return ioapics[ioapic_idx].mp_config.apicaddr;
133}
134
135static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
136{
137 return &ioapics[ioapic_idx].gsi_config;
138}
139
140static inline int mp_ioapic_pin_count(int ioapic)
141{
142 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
143
144 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
145}
146
147static inline u32 mp_pin_to_gsi(int ioapic, int pin)
148{
149 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
150}
151
152static inline bool mp_is_legacy_irq(int irq)
153{
154 return irq >= 0 && irq < nr_legacy_irqs();
155}
156
157static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
158{
159 return ioapics[ioapic].irqdomain;
160}
161
162int nr_ioapics;
163
164/* The one past the highest gsi number used */
165u32 gsi_top;
166
167/* MP IRQ source entries */
168struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
169
170/* # of MP IRQ source entries */
171int mp_irq_entries;
172
173#ifdef CONFIG_EISA
174int mp_bus_id_to_type[MAX_MP_BUSSES];
175#endif
176
177DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
178
179int skip_ioapic_setup;
180
181/**
182 * disable_ioapic_support() - disables ioapic support at runtime
183 */
184void disable_ioapic_support(void)
185{
186#ifdef CONFIG_PCI
187 noioapicquirk = 1;
188 noioapicreroute = -1;
189#endif
190 skip_ioapic_setup = 1;
191}
192
193static int __init parse_noapic(char *str)
194{
195 /* disable IO-APIC */
196 disable_ioapic_support();
197 return 0;
198}
199early_param("noapic", parse_noapic);
200
201/* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
202void mp_save_irq(struct mpc_intsrc *m)
203{
204 int i;
205
206 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
207 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
208 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
209 m->srcbusirq, m->dstapic, m->dstirq);
210
211 for (i = 0; i < mp_irq_entries; i++) {
212 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
213 return;
214 }
215
216 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
217 if (++mp_irq_entries == MAX_IRQ_SOURCES)
218 panic("Max # of irq sources exceeded!!\n");
219}
220
221static void alloc_ioapic_saved_registers(int idx)
222{
223 size_t size;
224
225 if (ioapics[idx].saved_registers)
226 return;
227
228 size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
229 ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
230 if (!ioapics[idx].saved_registers)
231 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
232}
233
234static void free_ioapic_saved_registers(int idx)
235{
236 kfree(ioapics[idx].saved_registers);
237 ioapics[idx].saved_registers = NULL;
238}
239
240int __init arch_early_ioapic_init(void)
241{
242 int i;
243
244 if (!nr_legacy_irqs())
245 io_apic_irqs = ~0UL;
246
247 for_each_ioapic(i)
248 alloc_ioapic_saved_registers(i);
249
250 return 0;
251}
252
253struct io_apic {
254 unsigned int index;
255 unsigned int unused[3];
256 unsigned int data;
257 unsigned int unused2[11];
258 unsigned int eoi;
259};
260
261static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
262{
263 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
264 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
265}
266
267static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
268{
269 struct io_apic __iomem *io_apic = io_apic_base(apic);
270 writel(vector, &io_apic->eoi);
271}
272
273unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
274{
275 struct io_apic __iomem *io_apic = io_apic_base(apic);
276 writel(reg, &io_apic->index);
277 return readl(&io_apic->data);
278}
279
280static void io_apic_write(unsigned int apic, unsigned int reg,
281 unsigned int value)
282{
283 struct io_apic __iomem *io_apic = io_apic_base(apic);
284
285 writel(reg, &io_apic->index);
286 writel(value, &io_apic->data);
287}
288
289union entry_union {
290 struct { u32 w1, w2; };
291 struct IO_APIC_route_entry entry;
292};
293
294static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
295{
296 union entry_union eu;
297
298 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
299 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
300
301 return eu.entry;
302}
303
304static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
305{
306 union entry_union eu;
307 unsigned long flags;
308
309 raw_spin_lock_irqsave(&ioapic_lock, flags);
310 eu.entry = __ioapic_read_entry(apic, pin);
311 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
312
313 return eu.entry;
314}
315
316/*
317 * When we write a new IO APIC routing entry, we need to write the high
318 * word first! If the mask bit in the low word is clear, we will enable
319 * the interrupt, and we need to make sure the entry is fully populated
320 * before that happens.
321 */
322static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
323{
324 union entry_union eu = {{0, 0}};
325
326 eu.entry = e;
327 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
328 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
329}
330
331static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
332{
333 unsigned long flags;
334
335 raw_spin_lock_irqsave(&ioapic_lock, flags);
336 __ioapic_write_entry(apic, pin, e);
337 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
338}
339
340/*
341 * When we mask an IO APIC routing entry, we need to write the low
342 * word first, in order to set the mask bit before we change the
343 * high bits!
344 */
345static void ioapic_mask_entry(int apic, int pin)
346{
347 unsigned long flags;
348 union entry_union eu = { .entry.mask = IOAPIC_MASKED };
349
350 raw_spin_lock_irqsave(&ioapic_lock, flags);
351 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
352 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
353 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
354}
355
356/*
357 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
358 * shared ISA-space IRQs, so we have to support them. We are super
359 * fast in the common case, and fast for shared ISA-space IRQs.
360 */
361static int __add_pin_to_irq_node(struct mp_chip_data *data,
362 int node, int apic, int pin)
363{
364 struct irq_pin_list *entry;
365
366 /* don't allow duplicates */
367 for_each_irq_pin(entry, data->irq_2_pin)
368 if (entry->apic == apic && entry->pin == pin)
369 return 0;
370
371 entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
372 if (!entry) {
373 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
374 node, apic, pin);
375 return -ENOMEM;
376 }
377 entry->apic = apic;
378 entry->pin = pin;
379 list_add_tail(&entry->list, &data->irq_2_pin);
380
381 return 0;
382}
383
384static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
385{
386 struct irq_pin_list *tmp, *entry;
387
388 list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list)
389 if (entry->apic == apic && entry->pin == pin) {
390 list_del(&entry->list);
391 kfree(entry);
392 return;
393 }
394}
395
396static void add_pin_to_irq_node(struct mp_chip_data *data,
397 int node, int apic, int pin)
398{
399 if (__add_pin_to_irq_node(data, node, apic, pin))
400 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
401}
402
403/*
404 * Reroute an IRQ to a different pin.
405 */
406static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
407 int oldapic, int oldpin,
408 int newapic, int newpin)
409{
410 struct irq_pin_list *entry;
411
412 for_each_irq_pin(entry, data->irq_2_pin) {
413 if (entry->apic == oldapic && entry->pin == oldpin) {
414 entry->apic = newapic;
415 entry->pin = newpin;
416 /* every one is different, right? */
417 return;
418 }
419 }
420
421 /* old apic/pin didn't exist, so just add new ones */
422 add_pin_to_irq_node(data, node, newapic, newpin);
423}
424
425static void io_apic_modify_irq(struct mp_chip_data *data,
426 int mask_and, int mask_or,
427 void (*final)(struct irq_pin_list *entry))
428{
429 union entry_union eu;
430 struct irq_pin_list *entry;
431
432 eu.entry = data->entry;
433 eu.w1 &= mask_and;
434 eu.w1 |= mask_or;
435 data->entry = eu.entry;
436
437 for_each_irq_pin(entry, data->irq_2_pin) {
438 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, eu.w1);
439 if (final)
440 final(entry);
441 }
442}
443
444static void io_apic_sync(struct irq_pin_list *entry)
445{
446 /*
447 * Synchronize the IO-APIC and the CPU by doing
448 * a dummy read from the IO-APIC
449 */
450 struct io_apic __iomem *io_apic;
451
452 io_apic = io_apic_base(entry->apic);
453 readl(&io_apic->data);
454}
455
456static void mask_ioapic_irq(struct irq_data *irq_data)
457{
458 struct mp_chip_data *data = irq_data->chip_data;
459 unsigned long flags;
460
461 raw_spin_lock_irqsave(&ioapic_lock, flags);
462 io_apic_modify_irq(data, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
463 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
464}
465
466static void __unmask_ioapic(struct mp_chip_data *data)
467{
468 io_apic_modify_irq(data, ~IO_APIC_REDIR_MASKED, 0, NULL);
469}
470
471static void unmask_ioapic_irq(struct irq_data *irq_data)
472{
473 struct mp_chip_data *data = irq_data->chip_data;
474 unsigned long flags;
475
476 raw_spin_lock_irqsave(&ioapic_lock, flags);
477 __unmask_ioapic(data);
478 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
479}
480
481/*
482 * IO-APIC versions below 0x20 don't support EOI register.
483 * For the record, here is the information about various versions:
484 * 0Xh 82489DX
485 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
486 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
487 * 30h-FFh Reserved
488 *
489 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
490 * version as 0x2. This is an error with documentation and these ICH chips
491 * use io-apic's of version 0x20.
492 *
493 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
494 * Otherwise, we simulate the EOI message manually by changing the trigger
495 * mode to edge and then back to level, with RTE being masked during this.
496 */
497static void __eoi_ioapic_pin(int apic, int pin, int vector)
498{
499 if (mpc_ioapic_ver(apic) >= 0x20) {
500 io_apic_eoi(apic, vector);
501 } else {
502 struct IO_APIC_route_entry entry, entry1;
503
504 entry = entry1 = __ioapic_read_entry(apic, pin);
505
506 /*
507 * Mask the entry and change the trigger mode to edge.
508 */
509 entry1.mask = IOAPIC_MASKED;
510 entry1.trigger = IOAPIC_EDGE;
511
512 __ioapic_write_entry(apic, pin, entry1);
513
514 /*
515 * Restore the previous level triggered entry.
516 */
517 __ioapic_write_entry(apic, pin, entry);
518 }
519}
520
521static void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
522{
523 unsigned long flags;
524 struct irq_pin_list *entry;
525
526 raw_spin_lock_irqsave(&ioapic_lock, flags);
527 for_each_irq_pin(entry, data->irq_2_pin)
528 __eoi_ioapic_pin(entry->apic, entry->pin, vector);
529 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
530}
531
532static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
533{
534 struct IO_APIC_route_entry entry;
535
536 /* Check delivery_mode to be sure we're not clearing an SMI pin */
537 entry = ioapic_read_entry(apic, pin);
538 if (entry.delivery_mode == dest_SMI)
539 return;
540
541 /*
542 * Make sure the entry is masked and re-read the contents to check
543 * if it is a level triggered pin and if the remote-IRR is set.
544 */
545 if (entry.mask == IOAPIC_UNMASKED) {
546 entry.mask = IOAPIC_MASKED;
547 ioapic_write_entry(apic, pin, entry);
548 entry = ioapic_read_entry(apic, pin);
549 }
550
551 if (entry.irr) {
552 unsigned long flags;
553
554 /*
555 * Make sure the trigger mode is set to level. Explicit EOI
556 * doesn't clear the remote-IRR if the trigger mode is not
557 * set to level.
558 */
559 if (entry.trigger == IOAPIC_EDGE) {
560 entry.trigger = IOAPIC_LEVEL;
561 ioapic_write_entry(apic, pin, entry);
562 }
563 raw_spin_lock_irqsave(&ioapic_lock, flags);
564 __eoi_ioapic_pin(apic, pin, entry.vector);
565 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
566 }
567
568 /*
569 * Clear the rest of the bits in the IO-APIC RTE except for the mask
570 * bit.
571 */
572 ioapic_mask_entry(apic, pin);
573 entry = ioapic_read_entry(apic, pin);
574 if (entry.irr)
575 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
576 mpc_ioapic_id(apic), pin);
577}
578
579void clear_IO_APIC (void)
580{
581 int apic, pin;
582
583 for_each_ioapic_pin(apic, pin)
584 clear_IO_APIC_pin(apic, pin);
585}
586
587#ifdef CONFIG_X86_32
588/*
589 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
590 * specific CPU-side IRQs.
591 */
592
593#define MAX_PIRQS 8
594static int pirq_entries[MAX_PIRQS] = {
595 [0 ... MAX_PIRQS - 1] = -1
596};
597
598static int __init ioapic_pirq_setup(char *str)
599{
600 int i, max;
601 int ints[MAX_PIRQS+1];
602
603 get_options(str, ARRAY_SIZE(ints), ints);
604
605 apic_printk(APIC_VERBOSE, KERN_INFO
606 "PIRQ redirection, working around broken MP-BIOS.\n");
607 max = MAX_PIRQS;
608 if (ints[0] < MAX_PIRQS)
609 max = ints[0];
610
611 for (i = 0; i < max; i++) {
612 apic_printk(APIC_VERBOSE, KERN_DEBUG
613 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
614 /*
615 * PIRQs are mapped upside down, usually.
616 */
617 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
618 }
619 return 1;
620}
621
622__setup("pirq=", ioapic_pirq_setup);
623#endif /* CONFIG_X86_32 */
624
625/*
626 * Saves all the IO-APIC RTE's
627 */
628int save_ioapic_entries(void)
629{
630 int apic, pin;
631 int err = 0;
632
633 for_each_ioapic(apic) {
634 if (!ioapics[apic].saved_registers) {
635 err = -ENOMEM;
636 continue;
637 }
638
639 for_each_pin(apic, pin)
640 ioapics[apic].saved_registers[pin] =
641 ioapic_read_entry(apic, pin);
642 }
643
644 return err;
645}
646
647/*
648 * Mask all IO APIC entries.
649 */
650void mask_ioapic_entries(void)
651{
652 int apic, pin;
653
654 for_each_ioapic(apic) {
655 if (!ioapics[apic].saved_registers)
656 continue;
657
658 for_each_pin(apic, pin) {
659 struct IO_APIC_route_entry entry;
660
661 entry = ioapics[apic].saved_registers[pin];
662 if (entry.mask == IOAPIC_UNMASKED) {
663 entry.mask = IOAPIC_MASKED;
664 ioapic_write_entry(apic, pin, entry);
665 }
666 }
667 }
668}
669
670/*
671 * Restore IO APIC entries which was saved in the ioapic structure.
672 */
673int restore_ioapic_entries(void)
674{
675 int apic, pin;
676
677 for_each_ioapic(apic) {
678 if (!ioapics[apic].saved_registers)
679 continue;
680
681 for_each_pin(apic, pin)
682 ioapic_write_entry(apic, pin,
683 ioapics[apic].saved_registers[pin]);
684 }
685 return 0;
686}
687
688/*
689 * Find the IRQ entry number of a certain pin.
690 */
691static int find_irq_entry(int ioapic_idx, int pin, int type)
692{
693 int i;
694
695 for (i = 0; i < mp_irq_entries; i++)
696 if (mp_irqs[i].irqtype == type &&
697 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
698 mp_irqs[i].dstapic == MP_APIC_ALL) &&
699 mp_irqs[i].dstirq == pin)
700 return i;
701
702 return -1;
703}
704
705/*
706 * Find the pin to which IRQ[irq] (ISA) is connected
707 */
708static int __init find_isa_irq_pin(int irq, int type)
709{
710 int i;
711
712 for (i = 0; i < mp_irq_entries; i++) {
713 int lbus = mp_irqs[i].srcbus;
714
715 if (test_bit(lbus, mp_bus_not_pci) &&
716 (mp_irqs[i].irqtype == type) &&
717 (mp_irqs[i].srcbusirq == irq))
718
719 return mp_irqs[i].dstirq;
720 }
721 return -1;
722}
723
724static int __init find_isa_irq_apic(int irq, int type)
725{
726 int i;
727
728 for (i = 0; i < mp_irq_entries; i++) {
729 int lbus = mp_irqs[i].srcbus;
730
731 if (test_bit(lbus, mp_bus_not_pci) &&
732 (mp_irqs[i].irqtype == type) &&
733 (mp_irqs[i].srcbusirq == irq))
734 break;
735 }
736
737 if (i < mp_irq_entries) {
738 int ioapic_idx;
739
740 for_each_ioapic(ioapic_idx)
741 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
742 return ioapic_idx;
743 }
744
745 return -1;
746}
747
748#ifdef CONFIG_EISA
749/*
750 * EISA Edge/Level control register, ELCR
751 */
752static int EISA_ELCR(unsigned int irq)
753{
754 if (irq < nr_legacy_irqs()) {
755 unsigned int port = 0x4d0 + (irq >> 3);
756 return (inb(port) >> (irq & 7)) & 1;
757 }
758 apic_printk(APIC_VERBOSE, KERN_INFO
759 "Broken MPtable reports ISA irq %d\n", irq);
760 return 0;
761}
762
763#endif
764
765/* ISA interrupts are always active high edge triggered,
766 * when listed as conforming in the MP table. */
767
768#define default_ISA_trigger(idx) (IOAPIC_EDGE)
769#define default_ISA_polarity(idx) (IOAPIC_POL_HIGH)
770
771/* EISA interrupts are always polarity zero and can be edge or level
772 * trigger depending on the ELCR value. If an interrupt is listed as
773 * EISA conforming in the MP table, that means its trigger type must
774 * be read in from the ELCR */
775
776#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
777#define default_EISA_polarity(idx) default_ISA_polarity(idx)
778
779/* PCI interrupts are always active low level triggered,
780 * when listed as conforming in the MP table. */
781
782#define default_PCI_trigger(idx) (IOAPIC_LEVEL)
783#define default_PCI_polarity(idx) (IOAPIC_POL_LOW)
784
785static int irq_polarity(int idx)
786{
787 int bus = mp_irqs[idx].srcbus;
788
789 /*
790 * Determine IRQ line polarity (high active or low active):
791 */
792 switch (mp_irqs[idx].irqflag & MP_IRQPOL_MASK) {
793 case MP_IRQPOL_DEFAULT:
794 /* conforms to spec, ie. bus-type dependent polarity */
795 if (test_bit(bus, mp_bus_not_pci))
796 return default_ISA_polarity(idx);
797 else
798 return default_PCI_polarity(idx);
799 case MP_IRQPOL_ACTIVE_HIGH:
800 return IOAPIC_POL_HIGH;
801 case MP_IRQPOL_RESERVED:
802 pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
803 fallthrough;
804 case MP_IRQPOL_ACTIVE_LOW:
805 default: /* Pointless default required due to do gcc stupidity */
806 return IOAPIC_POL_LOW;
807 }
808}
809
810#ifdef CONFIG_EISA
811static int eisa_irq_trigger(int idx, int bus, int trigger)
812{
813 switch (mp_bus_id_to_type[bus]) {
814 case MP_BUS_PCI:
815 case MP_BUS_ISA:
816 return trigger;
817 case MP_BUS_EISA:
818 return default_EISA_trigger(idx);
819 }
820 pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus);
821 return IOAPIC_LEVEL;
822}
823#else
824static inline int eisa_irq_trigger(int idx, int bus, int trigger)
825{
826 return trigger;
827}
828#endif
829
830static int irq_trigger(int idx)
831{
832 int bus = mp_irqs[idx].srcbus;
833 int trigger;
834
835 /*
836 * Determine IRQ trigger mode (edge or level sensitive):
837 */
838 switch (mp_irqs[idx].irqflag & MP_IRQTRIG_MASK) {
839 case MP_IRQTRIG_DEFAULT:
840 /* conforms to spec, ie. bus-type dependent trigger mode */
841 if (test_bit(bus, mp_bus_not_pci))
842 trigger = default_ISA_trigger(idx);
843 else
844 trigger = default_PCI_trigger(idx);
845 /* Take EISA into account */
846 return eisa_irq_trigger(idx, bus, trigger);
847 case MP_IRQTRIG_EDGE:
848 return IOAPIC_EDGE;
849 case MP_IRQTRIG_RESERVED:
850 pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
851 fallthrough;
852 case MP_IRQTRIG_LEVEL:
853 default: /* Pointless default required due to do gcc stupidity */
854 return IOAPIC_LEVEL;
855 }
856}
857
858void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
859 int trigger, int polarity)
860{
861 init_irq_alloc_info(info, NULL);
862 info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
863 info->ioapic_node = node;
864 info->ioapic_trigger = trigger;
865 info->ioapic_polarity = polarity;
866 info->ioapic_valid = 1;
867}
868
869#ifndef CONFIG_ACPI
870int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity);
871#endif
872
873static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
874 struct irq_alloc_info *src,
875 u32 gsi, int ioapic_idx, int pin)
876{
877 int trigger, polarity;
878
879 copy_irq_alloc_info(dst, src);
880 dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
881 dst->ioapic_id = mpc_ioapic_id(ioapic_idx);
882 dst->ioapic_pin = pin;
883 dst->ioapic_valid = 1;
884 if (src && src->ioapic_valid) {
885 dst->ioapic_node = src->ioapic_node;
886 dst->ioapic_trigger = src->ioapic_trigger;
887 dst->ioapic_polarity = src->ioapic_polarity;
888 } else {
889 dst->ioapic_node = NUMA_NO_NODE;
890 if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) {
891 dst->ioapic_trigger = trigger;
892 dst->ioapic_polarity = polarity;
893 } else {
894 /*
895 * PCI interrupts are always active low level
896 * triggered.
897 */
898 dst->ioapic_trigger = IOAPIC_LEVEL;
899 dst->ioapic_polarity = IOAPIC_POL_LOW;
900 }
901 }
902}
903
904static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
905{
906 return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE;
907}
908
909static void mp_register_handler(unsigned int irq, unsigned long trigger)
910{
911 irq_flow_handler_t hdl;
912 bool fasteoi;
913
914 if (trigger) {
915 irq_set_status_flags(irq, IRQ_LEVEL);
916 fasteoi = true;
917 } else {
918 irq_clear_status_flags(irq, IRQ_LEVEL);
919 fasteoi = false;
920 }
921
922 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
923 __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
924}
925
926static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
927{
928 struct mp_chip_data *data = irq_get_chip_data(irq);
929
930 /*
931 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
932 * and polarity attirbutes. So allow the first user to reprogram the
933 * pin with real trigger and polarity attributes.
934 */
935 if (irq < nr_legacy_irqs() && data->count == 1) {
936 if (info->ioapic_trigger != data->trigger)
937 mp_register_handler(irq, info->ioapic_trigger);
938 data->entry.trigger = data->trigger = info->ioapic_trigger;
939 data->entry.polarity = data->polarity = info->ioapic_polarity;
940 }
941
942 return data->trigger == info->ioapic_trigger &&
943 data->polarity == info->ioapic_polarity;
944}
945
946static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
947 struct irq_alloc_info *info)
948{
949 bool legacy = false;
950 int irq = -1;
951 int type = ioapics[ioapic].irqdomain_cfg.type;
952
953 switch (type) {
954 case IOAPIC_DOMAIN_LEGACY:
955 /*
956 * Dynamically allocate IRQ number for non-ISA IRQs in the first
957 * 16 GSIs on some weird platforms.
958 */
959 if (!ioapic_initialized || gsi >= nr_legacy_irqs())
960 irq = gsi;
961 legacy = mp_is_legacy_irq(irq);
962 break;
963 case IOAPIC_DOMAIN_STRICT:
964 irq = gsi;
965 break;
966 case IOAPIC_DOMAIN_DYNAMIC:
967 break;
968 default:
969 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
970 return -1;
971 }
972
973 return __irq_domain_alloc_irqs(domain, irq, 1,
974 ioapic_alloc_attr_node(info),
975 info, legacy, NULL);
976}
977
978/*
979 * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
980 * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
981 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
982 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
983 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
984 * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
985 * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
986 * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
987 */
988static int alloc_isa_irq_from_domain(struct irq_domain *domain,
989 int irq, int ioapic, int pin,
990 struct irq_alloc_info *info)
991{
992 struct mp_chip_data *data;
993 struct irq_data *irq_data = irq_get_irq_data(irq);
994 int node = ioapic_alloc_attr_node(info);
995
996 /*
997 * Legacy ISA IRQ has already been allocated, just add pin to
998 * the pin list assoicated with this IRQ and program the IOAPIC
999 * entry. The IOAPIC entry
1000 */
1001 if (irq_data && irq_data->parent_data) {
1002 if (!mp_check_pin_attr(irq, info))
1003 return -EBUSY;
1004 if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic,
1005 info->ioapic_pin))
1006 return -ENOMEM;
1007 } else {
1008 info->flags |= X86_IRQ_ALLOC_LEGACY;
1009 irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true,
1010 NULL);
1011 if (irq >= 0) {
1012 irq_data = irq_domain_get_irq_data(domain, irq);
1013 data = irq_data->chip_data;
1014 data->isa_irq = true;
1015 }
1016 }
1017
1018 return irq;
1019}
1020
1021static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1022 unsigned int flags, struct irq_alloc_info *info)
1023{
1024 int irq;
1025 bool legacy = false;
1026 struct irq_alloc_info tmp;
1027 struct mp_chip_data *data;
1028 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
1029
1030 if (!domain)
1031 return -ENOSYS;
1032
1033 if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
1034 irq = mp_irqs[idx].srcbusirq;
1035 legacy = mp_is_legacy_irq(irq);
1036 }
1037
1038 mutex_lock(&ioapic_mutex);
1039 if (!(flags & IOAPIC_MAP_ALLOC)) {
1040 if (!legacy) {
1041 irq = irq_find_mapping(domain, pin);
1042 if (irq == 0)
1043 irq = -ENOENT;
1044 }
1045 } else {
1046 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
1047 if (legacy)
1048 irq = alloc_isa_irq_from_domain(domain, irq,
1049 ioapic, pin, &tmp);
1050 else if ((irq = irq_find_mapping(domain, pin)) == 0)
1051 irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
1052 else if (!mp_check_pin_attr(irq, &tmp))
1053 irq = -EBUSY;
1054 if (irq >= 0) {
1055 data = irq_get_chip_data(irq);
1056 data->count++;
1057 }
1058 }
1059 mutex_unlock(&ioapic_mutex);
1060
1061 return irq;
1062}
1063
1064static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1065{
1066 u32 gsi = mp_pin_to_gsi(ioapic, pin);
1067
1068 /*
1069 * Debugging check, we are in big trouble if this message pops up!
1070 */
1071 if (mp_irqs[idx].dstirq != pin)
1072 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1073
1074#ifdef CONFIG_X86_32
1075 /*
1076 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1077 */
1078 if ((pin >= 16) && (pin <= 23)) {
1079 if (pirq_entries[pin-16] != -1) {
1080 if (!pirq_entries[pin-16]) {
1081 apic_printk(APIC_VERBOSE, KERN_DEBUG
1082 "disabling PIRQ%d\n", pin-16);
1083 } else {
1084 int irq = pirq_entries[pin-16];
1085 apic_printk(APIC_VERBOSE, KERN_DEBUG
1086 "using PIRQ%d -> IRQ %d\n",
1087 pin-16, irq);
1088 return irq;
1089 }
1090 }
1091 }
1092#endif
1093
1094 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1095}
1096
1097int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
1098{
1099 int ioapic, pin, idx;
1100
1101 ioapic = mp_find_ioapic(gsi);
1102 if (ioapic < 0)
1103 return -ENODEV;
1104
1105 pin = mp_find_ioapic_pin(ioapic, gsi);
1106 idx = find_irq_entry(ioapic, pin, mp_INT);
1107 if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1108 return -ENODEV;
1109
1110 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1111}
1112
1113void mp_unmap_irq(int irq)
1114{
1115 struct irq_data *irq_data = irq_get_irq_data(irq);
1116 struct mp_chip_data *data;
1117
1118 if (!irq_data || !irq_data->domain)
1119 return;
1120
1121 data = irq_data->chip_data;
1122 if (!data || data->isa_irq)
1123 return;
1124
1125 mutex_lock(&ioapic_mutex);
1126 if (--data->count == 0)
1127 irq_domain_free_irqs(irq, 1);
1128 mutex_unlock(&ioapic_mutex);
1129}
1130
1131/*
1132 * Find a specific PCI IRQ entry.
1133 * Not an __init, possibly needed by modules
1134 */
1135int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1136{
1137 int irq, i, best_ioapic = -1, best_idx = -1;
1138
1139 apic_printk(APIC_DEBUG,
1140 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1141 bus, slot, pin);
1142 if (test_bit(bus, mp_bus_not_pci)) {
1143 apic_printk(APIC_VERBOSE,
1144 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1145 return -1;
1146 }
1147
1148 for (i = 0; i < mp_irq_entries; i++) {
1149 int lbus = mp_irqs[i].srcbus;
1150 int ioapic_idx, found = 0;
1151
1152 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1153 slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1154 continue;
1155
1156 for_each_ioapic(ioapic_idx)
1157 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1158 mp_irqs[i].dstapic == MP_APIC_ALL) {
1159 found = 1;
1160 break;
1161 }
1162 if (!found)
1163 continue;
1164
1165 /* Skip ISA IRQs */
1166 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1167 if (irq > 0 && !IO_APIC_IRQ(irq))
1168 continue;
1169
1170 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1171 best_idx = i;
1172 best_ioapic = ioapic_idx;
1173 goto out;
1174 }
1175
1176 /*
1177 * Use the first all-but-pin matching entry as a
1178 * best-guess fuzzy result for broken mptables.
1179 */
1180 if (best_idx < 0) {
1181 best_idx = i;
1182 best_ioapic = ioapic_idx;
1183 }
1184 }
1185 if (best_idx < 0)
1186 return -1;
1187
1188out:
1189 return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1190 IOAPIC_MAP_ALLOC);
1191}
1192EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1193
1194static struct irq_chip ioapic_chip, ioapic_ir_chip;
1195
1196static void __init setup_IO_APIC_irqs(void)
1197{
1198 unsigned int ioapic, pin;
1199 int idx;
1200
1201 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1202
1203 for_each_ioapic_pin(ioapic, pin) {
1204 idx = find_irq_entry(ioapic, pin, mp_INT);
1205 if (idx < 0)
1206 apic_printk(APIC_VERBOSE,
1207 KERN_DEBUG " apic %d pin %d not connected\n",
1208 mpc_ioapic_id(ioapic), pin);
1209 else
1210 pin_2_irq(idx, ioapic, pin,
1211 ioapic ? 0 : IOAPIC_MAP_ALLOC);
1212 }
1213}
1214
1215void ioapic_zap_locks(void)
1216{
1217 raw_spin_lock_init(&ioapic_lock);
1218}
1219
1220static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1221{
1222 int i;
1223 char buf[256];
1224 struct IO_APIC_route_entry entry;
1225 struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry;
1226
1227 printk(KERN_DEBUG "IOAPIC %d:\n", apic);
1228 for (i = 0; i <= nr_entries; i++) {
1229 entry = ioapic_read_entry(apic, i);
1230 snprintf(buf, sizeof(buf),
1231 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1232 i,
1233 entry.mask == IOAPIC_MASKED ? "disabled" : "enabled ",
1234 entry.trigger == IOAPIC_LEVEL ? "level" : "edge ",
1235 entry.polarity == IOAPIC_POL_LOW ? "low " : "high",
1236 entry.vector, entry.irr, entry.delivery_status);
1237 if (ir_entry->format)
1238 printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n",
1239 buf, (ir_entry->index2 << 15) | ir_entry->index,
1240 ir_entry->zero);
1241 else
1242 printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n",
1243 buf,
1244 entry.dest_mode == IOAPIC_DEST_MODE_LOGICAL ?
1245 "logical " : "physical",
1246 entry.dest, entry.delivery_mode);
1247 }
1248}
1249
1250static void __init print_IO_APIC(int ioapic_idx)
1251{
1252 union IO_APIC_reg_00 reg_00;
1253 union IO_APIC_reg_01 reg_01;
1254 union IO_APIC_reg_02 reg_02;
1255 union IO_APIC_reg_03 reg_03;
1256 unsigned long flags;
1257
1258 raw_spin_lock_irqsave(&ioapic_lock, flags);
1259 reg_00.raw = io_apic_read(ioapic_idx, 0);
1260 reg_01.raw = io_apic_read(ioapic_idx, 1);
1261 if (reg_01.bits.version >= 0x10)
1262 reg_02.raw = io_apic_read(ioapic_idx, 2);
1263 if (reg_01.bits.version >= 0x20)
1264 reg_03.raw = io_apic_read(ioapic_idx, 3);
1265 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1266
1267 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1268 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1269 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1270 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1271 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1272
1273 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1274 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1275 reg_01.bits.entries);
1276
1277 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1278 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1279 reg_01.bits.version);
1280
1281 /*
1282 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1283 * but the value of reg_02 is read as the previous read register
1284 * value, so ignore it if reg_02 == reg_01.
1285 */
1286 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1287 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1288 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1289 }
1290
1291 /*
1292 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1293 * or reg_03, but the value of reg_0[23] is read as the previous read
1294 * register value, so ignore it if reg_03 == reg_0[12].
1295 */
1296 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1297 reg_03.raw != reg_01.raw) {
1298 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1299 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1300 }
1301
1302 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1303 io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1304}
1305
1306void __init print_IO_APICs(void)
1307{
1308 int ioapic_idx;
1309 unsigned int irq;
1310
1311 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1312 for_each_ioapic(ioapic_idx)
1313 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1314 mpc_ioapic_id(ioapic_idx),
1315 ioapics[ioapic_idx].nr_registers);
1316
1317 /*
1318 * We are a bit conservative about what we expect. We have to
1319 * know about every hardware change ASAP.
1320 */
1321 printk(KERN_INFO "testing the IO APIC.......................\n");
1322
1323 for_each_ioapic(ioapic_idx)
1324 print_IO_APIC(ioapic_idx);
1325
1326 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1327 for_each_active_irq(irq) {
1328 struct irq_pin_list *entry;
1329 struct irq_chip *chip;
1330 struct mp_chip_data *data;
1331
1332 chip = irq_get_chip(irq);
1333 if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1334 continue;
1335 data = irq_get_chip_data(irq);
1336 if (!data)
1337 continue;
1338 if (list_empty(&data->irq_2_pin))
1339 continue;
1340
1341 printk(KERN_DEBUG "IRQ%d ", irq);
1342 for_each_irq_pin(entry, data->irq_2_pin)
1343 pr_cont("-> %d:%d", entry->apic, entry->pin);
1344 pr_cont("\n");
1345 }
1346
1347 printk(KERN_INFO ".................................... done.\n");
1348}
1349
1350/* Where if anywhere is the i8259 connect in external int mode */
1351static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1352
1353void __init enable_IO_APIC(void)
1354{
1355 int i8259_apic, i8259_pin;
1356 int apic, pin;
1357
1358 if (skip_ioapic_setup)
1359 nr_ioapics = 0;
1360
1361 if (!nr_legacy_irqs() || !nr_ioapics)
1362 return;
1363
1364 for_each_ioapic_pin(apic, pin) {
1365 /* See if any of the pins is in ExtINT mode */
1366 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1367
1368 /* If the interrupt line is enabled and in ExtInt mode
1369 * I have found the pin where the i8259 is connected.
1370 */
1371 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1372 ioapic_i8259.apic = apic;
1373 ioapic_i8259.pin = pin;
1374 goto found_i8259;
1375 }
1376 }
1377 found_i8259:
1378 /* Look to see what if the MP table has reported the ExtINT */
1379 /* If we could not find the appropriate pin by looking at the ioapic
1380 * the i8259 probably is not connected the ioapic but give the
1381 * mptable a chance anyway.
1382 */
1383 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1384 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1385 /* Trust the MP table if nothing is setup in the hardware */
1386 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1387 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1388 ioapic_i8259.pin = i8259_pin;
1389 ioapic_i8259.apic = i8259_apic;
1390 }
1391 /* Complain if the MP table and the hardware disagree */
1392 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1393 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1394 {
1395 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1396 }
1397
1398 /*
1399 * Do not trust the IO-APIC being empty at bootup
1400 */
1401 clear_IO_APIC();
1402}
1403
1404void native_restore_boot_irq_mode(void)
1405{
1406 /*
1407 * If the i8259 is routed through an IOAPIC
1408 * Put that IOAPIC in virtual wire mode
1409 * so legacy interrupts can be delivered.
1410 */
1411 if (ioapic_i8259.pin != -1) {
1412 struct IO_APIC_route_entry entry;
1413
1414 memset(&entry, 0, sizeof(entry));
1415 entry.mask = IOAPIC_UNMASKED;
1416 entry.trigger = IOAPIC_EDGE;
1417 entry.polarity = IOAPIC_POL_HIGH;
1418 entry.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
1419 entry.delivery_mode = dest_ExtINT;
1420 entry.dest = read_apic_id();
1421
1422 /*
1423 * Add it to the IO-APIC irq-routing table:
1424 */
1425 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1426 }
1427
1428 if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config())
1429 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1430}
1431
1432void restore_boot_irq_mode(void)
1433{
1434 if (!nr_legacy_irqs())
1435 return;
1436
1437 x86_apic_ops.restore();
1438}
1439
1440#ifdef CONFIG_X86_32
1441/*
1442 * function to set the IO-APIC physical IDs based on the
1443 * values stored in the MPC table.
1444 *
1445 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1446 */
1447void __init setup_ioapic_ids_from_mpc_nocheck(void)
1448{
1449 union IO_APIC_reg_00 reg_00;
1450 physid_mask_t phys_id_present_map;
1451 int ioapic_idx;
1452 int i;
1453 unsigned char old_id;
1454 unsigned long flags;
1455
1456 /*
1457 * This is broken; anything with a real cpu count has to
1458 * circumvent this idiocy regardless.
1459 */
1460 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1461
1462 /*
1463 * Set the IOAPIC ID to the value stored in the MPC table.
1464 */
1465 for_each_ioapic(ioapic_idx) {
1466 /* Read the register 0 value */
1467 raw_spin_lock_irqsave(&ioapic_lock, flags);
1468 reg_00.raw = io_apic_read(ioapic_idx, 0);
1469 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1470
1471 old_id = mpc_ioapic_id(ioapic_idx);
1472
1473 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1474 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1475 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1476 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1477 reg_00.bits.ID);
1478 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1479 }
1480
1481 /*
1482 * Sanity check, is the ID really free? Every APIC in a
1483 * system must have a unique ID or we get lots of nice
1484 * 'stuck on smp_invalidate_needed IPI wait' messages.
1485 */
1486 if (apic->check_apicid_used(&phys_id_present_map,
1487 mpc_ioapic_id(ioapic_idx))) {
1488 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1489 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1490 for (i = 0; i < get_physical_broadcast(); i++)
1491 if (!physid_isset(i, phys_id_present_map))
1492 break;
1493 if (i >= get_physical_broadcast())
1494 panic("Max APIC ID exceeded!\n");
1495 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1496 i);
1497 physid_set(i, phys_id_present_map);
1498 ioapics[ioapic_idx].mp_config.apicid = i;
1499 } else {
1500 physid_mask_t tmp;
1501 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1502 &tmp);
1503 apic_printk(APIC_VERBOSE, "Setting %d in the "
1504 "phys_id_present_map\n",
1505 mpc_ioapic_id(ioapic_idx));
1506 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1507 }
1508
1509 /*
1510 * We need to adjust the IRQ routing table
1511 * if the ID changed.
1512 */
1513 if (old_id != mpc_ioapic_id(ioapic_idx))
1514 for (i = 0; i < mp_irq_entries; i++)
1515 if (mp_irqs[i].dstapic == old_id)
1516 mp_irqs[i].dstapic
1517 = mpc_ioapic_id(ioapic_idx);
1518
1519 /*
1520 * Update the ID register according to the right value
1521 * from the MPC table if they are different.
1522 */
1523 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1524 continue;
1525
1526 apic_printk(APIC_VERBOSE, KERN_INFO
1527 "...changing IO-APIC physical APIC ID to %d ...",
1528 mpc_ioapic_id(ioapic_idx));
1529
1530 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1531 raw_spin_lock_irqsave(&ioapic_lock, flags);
1532 io_apic_write(ioapic_idx, 0, reg_00.raw);
1533 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1534
1535 /*
1536 * Sanity check
1537 */
1538 raw_spin_lock_irqsave(&ioapic_lock, flags);
1539 reg_00.raw = io_apic_read(ioapic_idx, 0);
1540 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1541 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1542 pr_cont("could not set ID!\n");
1543 else
1544 apic_printk(APIC_VERBOSE, " ok.\n");
1545 }
1546}
1547
1548void __init setup_ioapic_ids_from_mpc(void)
1549{
1550
1551 if (acpi_ioapic)
1552 return;
1553 /*
1554 * Don't check I/O APIC IDs for xAPIC systems. They have
1555 * no meaning without the serial APIC bus.
1556 */
1557 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1558 || APIC_XAPIC(boot_cpu_apic_version))
1559 return;
1560 setup_ioapic_ids_from_mpc_nocheck();
1561}
1562#endif
1563
1564int no_timer_check __initdata;
1565
1566static int __init notimercheck(char *s)
1567{
1568 no_timer_check = 1;
1569 return 1;
1570}
1571__setup("no_timer_check", notimercheck);
1572
1573static void __init delay_with_tsc(void)
1574{
1575 unsigned long long start, now;
1576 unsigned long end = jiffies + 4;
1577
1578 start = rdtsc();
1579
1580 /*
1581 * We don't know the TSC frequency yet, but waiting for
1582 * 40000000000/HZ TSC cycles is safe:
1583 * 4 GHz == 10 jiffies
1584 * 1 GHz == 40 jiffies
1585 */
1586 do {
1587 rep_nop();
1588 now = rdtsc();
1589 } while ((now - start) < 40000000000ULL / HZ &&
1590 time_before_eq(jiffies, end));
1591}
1592
1593static void __init delay_without_tsc(void)
1594{
1595 unsigned long end = jiffies + 4;
1596 int band = 1;
1597
1598 /*
1599 * We don't know any frequency yet, but waiting for
1600 * 40940000000/HZ cycles is safe:
1601 * 4 GHz == 10 jiffies
1602 * 1 GHz == 40 jiffies
1603 * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094
1604 */
1605 do {
1606 __delay(((1U << band++) * 10000000UL) / HZ);
1607 } while (band < 12 && time_before_eq(jiffies, end));
1608}
1609
1610/*
1611 * There is a nasty bug in some older SMP boards, their mptable lies
1612 * about the timer IRQ. We do the following to work around the situation:
1613 *
1614 * - timer IRQ defaults to IO-APIC IRQ
1615 * - if this function detects that timer IRQs are defunct, then we fall
1616 * back to ISA timer IRQs
1617 */
1618static int __init timer_irq_works(void)
1619{
1620 unsigned long t1 = jiffies;
1621 unsigned long flags;
1622
1623 if (no_timer_check)
1624 return 1;
1625
1626 local_save_flags(flags);
1627 local_irq_enable();
1628
1629 if (boot_cpu_has(X86_FEATURE_TSC))
1630 delay_with_tsc();
1631 else
1632 delay_without_tsc();
1633
1634 local_irq_restore(flags);
1635
1636 /*
1637 * Expect a few ticks at least, to be sure some possible
1638 * glue logic does not lock up after one or two first
1639 * ticks in a non-ExtINT mode. Also the local APIC
1640 * might have cached one ExtINT interrupt. Finally, at
1641 * least one tick may be lost due to delays.
1642 */
1643
1644 /* jiffies wrap? */
1645 if (time_after(jiffies, t1 + 4))
1646 return 1;
1647 return 0;
1648}
1649
1650/*
1651 * In the SMP+IOAPIC case it might happen that there are an unspecified
1652 * number of pending IRQ events unhandled. These cases are very rare,
1653 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1654 * better to do it this way as thus we do not have to be aware of
1655 * 'pending' interrupts in the IRQ path, except at this point.
1656 */
1657/*
1658 * Edge triggered needs to resend any interrupt
1659 * that was delayed but this is now handled in the device
1660 * independent code.
1661 */
1662
1663/*
1664 * Starting up a edge-triggered IO-APIC interrupt is
1665 * nasty - we need to make sure that we get the edge.
1666 * If it is already asserted for some reason, we need
1667 * return 1 to indicate that is was pending.
1668 *
1669 * This is not complete - we should be able to fake
1670 * an edge even if it isn't on the 8259A...
1671 */
1672static unsigned int startup_ioapic_irq(struct irq_data *data)
1673{
1674 int was_pending = 0, irq = data->irq;
1675 unsigned long flags;
1676
1677 raw_spin_lock_irqsave(&ioapic_lock, flags);
1678 if (irq < nr_legacy_irqs()) {
1679 legacy_pic->mask(irq);
1680 if (legacy_pic->irq_pending(irq))
1681 was_pending = 1;
1682 }
1683 __unmask_ioapic(data->chip_data);
1684 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1685
1686 return was_pending;
1687}
1688
1689atomic_t irq_mis_count;
1690
1691#ifdef CONFIG_GENERIC_PENDING_IRQ
1692static bool io_apic_level_ack_pending(struct mp_chip_data *data)
1693{
1694 struct irq_pin_list *entry;
1695 unsigned long flags;
1696
1697 raw_spin_lock_irqsave(&ioapic_lock, flags);
1698 for_each_irq_pin(entry, data->irq_2_pin) {
1699 unsigned int reg;
1700 int pin;
1701
1702 pin = entry->pin;
1703 reg = io_apic_read(entry->apic, 0x10 + pin*2);
1704 /* Is the remote IRR bit set? */
1705 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
1706 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1707 return true;
1708 }
1709 }
1710 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1711
1712 return false;
1713}
1714
1715static inline bool ioapic_prepare_move(struct irq_data *data)
1716{
1717 /* If we are moving the IRQ we need to mask it */
1718 if (unlikely(irqd_is_setaffinity_pending(data))) {
1719 if (!irqd_irq_masked(data))
1720 mask_ioapic_irq(data);
1721 return true;
1722 }
1723 return false;
1724}
1725
1726static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
1727{
1728 if (unlikely(moveit)) {
1729 /* Only migrate the irq if the ack has been received.
1730 *
1731 * On rare occasions the broadcast level triggered ack gets
1732 * delayed going to ioapics, and if we reprogram the
1733 * vector while Remote IRR is still set the irq will never
1734 * fire again.
1735 *
1736 * To prevent this scenario we read the Remote IRR bit
1737 * of the ioapic. This has two effects.
1738 * - On any sane system the read of the ioapic will
1739 * flush writes (and acks) going to the ioapic from
1740 * this cpu.
1741 * - We get to see if the ACK has actually been delivered.
1742 *
1743 * Based on failed experiments of reprogramming the
1744 * ioapic entry from outside of irq context starting
1745 * with masking the ioapic entry and then polling until
1746 * Remote IRR was clear before reprogramming the
1747 * ioapic I don't trust the Remote IRR bit to be
1748 * completey accurate.
1749 *
1750 * However there appears to be no other way to plug
1751 * this race, so if the Remote IRR bit is not
1752 * accurate and is causing problems then it is a hardware bug
1753 * and you can go talk to the chipset vendor about it.
1754 */
1755 if (!io_apic_level_ack_pending(data->chip_data))
1756 irq_move_masked_irq(data);
1757 /* If the IRQ is masked in the core, leave it: */
1758 if (!irqd_irq_masked(data))
1759 unmask_ioapic_irq(data);
1760 }
1761}
1762#else
1763static inline bool ioapic_prepare_move(struct irq_data *data)
1764{
1765 return false;
1766}
1767static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
1768{
1769}
1770#endif
1771
1772static void ioapic_ack_level(struct irq_data *irq_data)
1773{
1774 struct irq_cfg *cfg = irqd_cfg(irq_data);
1775 unsigned long v;
1776 bool moveit;
1777 int i;
1778
1779 irq_complete_move(cfg);
1780 moveit = ioapic_prepare_move(irq_data);
1781
1782 /*
1783 * It appears there is an erratum which affects at least version 0x11
1784 * of I/O APIC (that's the 82093AA and cores integrated into various
1785 * chipsets). Under certain conditions a level-triggered interrupt is
1786 * erroneously delivered as edge-triggered one but the respective IRR
1787 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1788 * message but it will never arrive and further interrupts are blocked
1789 * from the source. The exact reason is so far unknown, but the
1790 * phenomenon was observed when two consecutive interrupt requests
1791 * from a given source get delivered to the same CPU and the source is
1792 * temporarily disabled in between.
1793 *
1794 * A workaround is to simulate an EOI message manually. We achieve it
1795 * by setting the trigger mode to edge and then to level when the edge
1796 * trigger mode gets detected in the TMR of a local APIC for a
1797 * level-triggered interrupt. We mask the source for the time of the
1798 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1799 * The idea is from Manfred Spraul. --macro
1800 *
1801 * Also in the case when cpu goes offline, fixup_irqs() will forward
1802 * any unhandled interrupt on the offlined cpu to the new cpu
1803 * destination that is handling the corresponding interrupt. This
1804 * interrupt forwarding is done via IPI's. Hence, in this case also
1805 * level-triggered io-apic interrupt will be seen as an edge
1806 * interrupt in the IRR. And we can't rely on the cpu's EOI
1807 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1808 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1809 * supporting EOI register, we do an explicit EOI to clear the
1810 * remote IRR and on IO-APIC's which don't have an EOI register,
1811 * we use the above logic (mask+edge followed by unmask+level) from
1812 * Manfred Spraul to clear the remote IRR.
1813 */
1814 i = cfg->vector;
1815 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1816
1817 /*
1818 * We must acknowledge the irq before we move it or the acknowledge will
1819 * not propagate properly.
1820 */
1821 ack_APIC_irq();
1822
1823 /*
1824 * Tail end of clearing remote IRR bit (either by delivering the EOI
1825 * message via io-apic EOI register write or simulating it using
1826 * mask+edge followed by unnask+level logic) manually when the
1827 * level triggered interrupt is seen as the edge triggered interrupt
1828 * at the cpu.
1829 */
1830 if (!(v & (1 << (i & 0x1f)))) {
1831 atomic_inc(&irq_mis_count);
1832 eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
1833 }
1834
1835 ioapic_finish_move(irq_data, moveit);
1836}
1837
1838static void ioapic_ir_ack_level(struct irq_data *irq_data)
1839{
1840 struct mp_chip_data *data = irq_data->chip_data;
1841
1842 /*
1843 * Intr-remapping uses pin number as the virtual vector
1844 * in the RTE. Actual vector is programmed in
1845 * intr-remapping table entry. Hence for the io-apic
1846 * EOI we use the pin number.
1847 */
1848 apic_ack_irq(irq_data);
1849 eoi_ioapic_pin(data->entry.vector, data);
1850}
1851
1852static void ioapic_configure_entry(struct irq_data *irqd)
1853{
1854 struct mp_chip_data *mpd = irqd->chip_data;
1855 struct irq_cfg *cfg = irqd_cfg(irqd);
1856 struct irq_pin_list *entry;
1857
1858 /*
1859 * Only update when the parent is the vector domain, don't touch it
1860 * if the parent is the remapping domain. Check the installed
1861 * ioapic chip to verify that.
1862 */
1863 if (irqd->chip == &ioapic_chip) {
1864 mpd->entry.dest = cfg->dest_apicid;
1865 mpd->entry.vector = cfg->vector;
1866 }
1867 for_each_irq_pin(entry, mpd->irq_2_pin)
1868 __ioapic_write_entry(entry->apic, entry->pin, mpd->entry);
1869}
1870
1871static int ioapic_set_affinity(struct irq_data *irq_data,
1872 const struct cpumask *mask, bool force)
1873{
1874 struct irq_data *parent = irq_data->parent_data;
1875 unsigned long flags;
1876 int ret;
1877
1878 ret = parent->chip->irq_set_affinity(parent, mask, force);
1879 raw_spin_lock_irqsave(&ioapic_lock, flags);
1880 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE)
1881 ioapic_configure_entry(irq_data);
1882 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1883
1884 return ret;
1885}
1886
1887/*
1888 * Interrupt shutdown masks the ioapic pin, but the interrupt might already
1889 * be in flight, but not yet serviced by the target CPU. That means
1890 * __synchronize_hardirq() would return and claim that everything is calmed
1891 * down. So free_irq() would proceed and deactivate the interrupt and free
1892 * resources.
1893 *
1894 * Once the target CPU comes around to service it it will find a cleared
1895 * vector and complain. While the spurious interrupt is harmless, the full
1896 * release of resources might prevent the interrupt from being acknowledged
1897 * which keeps the hardware in a weird state.
1898 *
1899 * Verify that the corresponding Remote-IRR bits are clear.
1900 */
1901static int ioapic_irq_get_chip_state(struct irq_data *irqd,
1902 enum irqchip_irq_state which,
1903 bool *state)
1904{
1905 struct mp_chip_data *mcd = irqd->chip_data;
1906 struct IO_APIC_route_entry rentry;
1907 struct irq_pin_list *p;
1908
1909 if (which != IRQCHIP_STATE_ACTIVE)
1910 return -EINVAL;
1911
1912 *state = false;
1913 raw_spin_lock(&ioapic_lock);
1914 for_each_irq_pin(p, mcd->irq_2_pin) {
1915 rentry = __ioapic_read_entry(p->apic, p->pin);
1916 /*
1917 * The remote IRR is only valid in level trigger mode. It's
1918 * meaning is undefined for edge triggered interrupts and
1919 * irrelevant because the IO-APIC treats them as fire and
1920 * forget.
1921 */
1922 if (rentry.irr && rentry.trigger) {
1923 *state = true;
1924 break;
1925 }
1926 }
1927 raw_spin_unlock(&ioapic_lock);
1928 return 0;
1929}
1930
1931static struct irq_chip ioapic_chip __read_mostly = {
1932 .name = "IO-APIC",
1933 .irq_startup = startup_ioapic_irq,
1934 .irq_mask = mask_ioapic_irq,
1935 .irq_unmask = unmask_ioapic_irq,
1936 .irq_ack = irq_chip_ack_parent,
1937 .irq_eoi = ioapic_ack_level,
1938 .irq_set_affinity = ioapic_set_affinity,
1939 .irq_retrigger = irq_chip_retrigger_hierarchy,
1940 .irq_get_irqchip_state = ioapic_irq_get_chip_state,
1941 .flags = IRQCHIP_SKIP_SET_WAKE,
1942};
1943
1944static struct irq_chip ioapic_ir_chip __read_mostly = {
1945 .name = "IR-IO-APIC",
1946 .irq_startup = startup_ioapic_irq,
1947 .irq_mask = mask_ioapic_irq,
1948 .irq_unmask = unmask_ioapic_irq,
1949 .irq_ack = irq_chip_ack_parent,
1950 .irq_eoi = ioapic_ir_ack_level,
1951 .irq_set_affinity = ioapic_set_affinity,
1952 .irq_retrigger = irq_chip_retrigger_hierarchy,
1953 .irq_get_irqchip_state = ioapic_irq_get_chip_state,
1954 .flags = IRQCHIP_SKIP_SET_WAKE,
1955};
1956
1957static inline void init_IO_APIC_traps(void)
1958{
1959 struct irq_cfg *cfg;
1960 unsigned int irq;
1961
1962 for_each_active_irq(irq) {
1963 cfg = irq_cfg(irq);
1964 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
1965 /*
1966 * Hmm.. We don't have an entry for this,
1967 * so default to an old-fashioned 8259
1968 * interrupt if we can..
1969 */
1970 if (irq < nr_legacy_irqs())
1971 legacy_pic->make_irq(irq);
1972 else
1973 /* Strange. Oh, well.. */
1974 irq_set_chip(irq, &no_irq_chip);
1975 }
1976 }
1977}
1978
1979/*
1980 * The local APIC irq-chip implementation:
1981 */
1982
1983static void mask_lapic_irq(struct irq_data *data)
1984{
1985 unsigned long v;
1986
1987 v = apic_read(APIC_LVT0);
1988 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1989}
1990
1991static void unmask_lapic_irq(struct irq_data *data)
1992{
1993 unsigned long v;
1994
1995 v = apic_read(APIC_LVT0);
1996 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1997}
1998
1999static void ack_lapic_irq(struct irq_data *data)
2000{
2001 ack_APIC_irq();
2002}
2003
2004static struct irq_chip lapic_chip __read_mostly = {
2005 .name = "local-APIC",
2006 .irq_mask = mask_lapic_irq,
2007 .irq_unmask = unmask_lapic_irq,
2008 .irq_ack = ack_lapic_irq,
2009};
2010
2011static void lapic_register_intr(int irq)
2012{
2013 irq_clear_status_flags(irq, IRQ_LEVEL);
2014 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2015 "edge");
2016}
2017
2018/*
2019 * This looks a bit hackish but it's about the only one way of sending
2020 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2021 * not support the ExtINT mode, unfortunately. We need to send these
2022 * cycles as some i82489DX-based boards have glue logic that keeps the
2023 * 8259A interrupt line asserted until INTA. --macro
2024 */
2025static inline void __init unlock_ExtINT_logic(void)
2026{
2027 int apic, pin, i;
2028 struct IO_APIC_route_entry entry0, entry1;
2029 unsigned char save_control, save_freq_select;
2030
2031 pin = find_isa_irq_pin(8, mp_INT);
2032 if (pin == -1) {
2033 WARN_ON_ONCE(1);
2034 return;
2035 }
2036 apic = find_isa_irq_apic(8, mp_INT);
2037 if (apic == -1) {
2038 WARN_ON_ONCE(1);
2039 return;
2040 }
2041
2042 entry0 = ioapic_read_entry(apic, pin);
2043 clear_IO_APIC_pin(apic, pin);
2044
2045 memset(&entry1, 0, sizeof(entry1));
2046
2047 entry1.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
2048 entry1.mask = IOAPIC_UNMASKED;
2049 entry1.dest = hard_smp_processor_id();
2050 entry1.delivery_mode = dest_ExtINT;
2051 entry1.polarity = entry0.polarity;
2052 entry1.trigger = IOAPIC_EDGE;
2053 entry1.vector = 0;
2054
2055 ioapic_write_entry(apic, pin, entry1);
2056
2057 save_control = CMOS_READ(RTC_CONTROL);
2058 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2059 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2060 RTC_FREQ_SELECT);
2061 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2062
2063 i = 100;
2064 while (i-- > 0) {
2065 mdelay(10);
2066 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2067 i -= 10;
2068 }
2069
2070 CMOS_WRITE(save_control, RTC_CONTROL);
2071 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2072 clear_IO_APIC_pin(apic, pin);
2073
2074 ioapic_write_entry(apic, pin, entry0);
2075}
2076
2077static int disable_timer_pin_1 __initdata;
2078/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2079static int __init disable_timer_pin_setup(char *arg)
2080{
2081 disable_timer_pin_1 = 1;
2082 return 0;
2083}
2084early_param("disable_timer_pin_1", disable_timer_pin_setup);
2085
2086static int mp_alloc_timer_irq(int ioapic, int pin)
2087{
2088 int irq = -1;
2089 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2090
2091 if (domain) {
2092 struct irq_alloc_info info;
2093
2094 ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2095 info.ioapic_id = mpc_ioapic_id(ioapic);
2096 info.ioapic_pin = pin;
2097 mutex_lock(&ioapic_mutex);
2098 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2099 mutex_unlock(&ioapic_mutex);
2100 }
2101
2102 return irq;
2103}
2104
2105/*
2106 * This code may look a bit paranoid, but it's supposed to cooperate with
2107 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2108 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2109 * fanatically on his truly buggy board.
2110 *
2111 * FIXME: really need to revamp this for all platforms.
2112 */
2113static inline void __init check_timer(void)
2114{
2115 struct irq_data *irq_data = irq_get_irq_data(0);
2116 struct mp_chip_data *data = irq_data->chip_data;
2117 struct irq_cfg *cfg = irqd_cfg(irq_data);
2118 int node = cpu_to_node(0);
2119 int apic1, pin1, apic2, pin2;
2120 unsigned long flags;
2121 int no_pin1 = 0;
2122
2123 if (!global_clock_event)
2124 return;
2125
2126 local_irq_save(flags);
2127
2128 /*
2129 * get/set the timer IRQ vector:
2130 */
2131 legacy_pic->mask(0);
2132
2133 /*
2134 * As IRQ0 is to be enabled in the 8259A, the virtual
2135 * wire has to be disabled in the local APIC. Also
2136 * timer interrupts need to be acknowledged manually in
2137 * the 8259A for the i82489DX when using the NMI
2138 * watchdog as that APIC treats NMIs as level-triggered.
2139 * The AEOI mode will finish them in the 8259A
2140 * automatically.
2141 */
2142 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2143 legacy_pic->init(1);
2144
2145 pin1 = find_isa_irq_pin(0, mp_INT);
2146 apic1 = find_isa_irq_apic(0, mp_INT);
2147 pin2 = ioapic_i8259.pin;
2148 apic2 = ioapic_i8259.apic;
2149
2150 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2151 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2152 cfg->vector, apic1, pin1, apic2, pin2);
2153
2154 /*
2155 * Some BIOS writers are clueless and report the ExtINTA
2156 * I/O APIC input from the cascaded 8259A as the timer
2157 * interrupt input. So just in case, if only one pin
2158 * was found above, try it both directly and through the
2159 * 8259A.
2160 */
2161 if (pin1 == -1) {
2162 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2163 pin1 = pin2;
2164 apic1 = apic2;
2165 no_pin1 = 1;
2166 } else if (pin2 == -1) {
2167 pin2 = pin1;
2168 apic2 = apic1;
2169 }
2170
2171 if (pin1 != -1) {
2172 /* Ok, does IRQ0 through the IOAPIC work? */
2173 if (no_pin1) {
2174 mp_alloc_timer_irq(apic1, pin1);
2175 } else {
2176 /*
2177 * for edge trigger, it's already unmasked,
2178 * so only need to unmask if it is level-trigger
2179 * do we really have level trigger timer?
2180 */
2181 int idx;
2182 idx = find_irq_entry(apic1, pin1, mp_INT);
2183 if (idx != -1 && irq_trigger(idx))
2184 unmask_ioapic_irq(irq_get_irq_data(0));
2185 }
2186 irq_domain_deactivate_irq(irq_data);
2187 irq_domain_activate_irq(irq_data, false);
2188 if (timer_irq_works()) {
2189 if (disable_timer_pin_1 > 0)
2190 clear_IO_APIC_pin(0, pin1);
2191 goto out;
2192 }
2193 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2194 local_irq_disable();
2195 clear_IO_APIC_pin(apic1, pin1);
2196 if (!no_pin1)
2197 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2198 "8254 timer not connected to IO-APIC\n");
2199
2200 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2201 "(IRQ0) through the 8259A ...\n");
2202 apic_printk(APIC_QUIET, KERN_INFO
2203 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2204 /*
2205 * legacy devices should be connected to IO APIC #0
2206 */
2207 replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
2208 irq_domain_deactivate_irq(irq_data);
2209 irq_domain_activate_irq(irq_data, false);
2210 legacy_pic->unmask(0);
2211 if (timer_irq_works()) {
2212 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2213 goto out;
2214 }
2215 /*
2216 * Cleanup, just in case ...
2217 */
2218 local_irq_disable();
2219 legacy_pic->mask(0);
2220 clear_IO_APIC_pin(apic2, pin2);
2221 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2222 }
2223
2224 apic_printk(APIC_QUIET, KERN_INFO
2225 "...trying to set up timer as Virtual Wire IRQ...\n");
2226
2227 lapic_register_intr(0);
2228 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2229 legacy_pic->unmask(0);
2230
2231 if (timer_irq_works()) {
2232 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2233 goto out;
2234 }
2235 local_irq_disable();
2236 legacy_pic->mask(0);
2237 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2238 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2239
2240 apic_printk(APIC_QUIET, KERN_INFO
2241 "...trying to set up timer as ExtINT IRQ...\n");
2242
2243 legacy_pic->init(0);
2244 legacy_pic->make_irq(0);
2245 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2246 legacy_pic->unmask(0);
2247
2248 unlock_ExtINT_logic();
2249
2250 if (timer_irq_works()) {
2251 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2252 goto out;
2253 }
2254 local_irq_disable();
2255 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2256 if (apic_is_x2apic_enabled())
2257 apic_printk(APIC_QUIET, KERN_INFO
2258 "Perhaps problem with the pre-enabled x2apic mode\n"
2259 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2260 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2261 "report. Then try booting with the 'noapic' option.\n");
2262out:
2263 local_irq_restore(flags);
2264}
2265
2266/*
2267 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2268 * to devices. However there may be an I/O APIC pin available for
2269 * this interrupt regardless. The pin may be left unconnected, but
2270 * typically it will be reused as an ExtINT cascade interrupt for
2271 * the master 8259A. In the MPS case such a pin will normally be
2272 * reported as an ExtINT interrupt in the MP table. With ACPI
2273 * there is no provision for ExtINT interrupts, and in the absence
2274 * of an override it would be treated as an ordinary ISA I/O APIC
2275 * interrupt, that is edge-triggered and unmasked by default. We
2276 * used to do this, but it caused problems on some systems because
2277 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2278 * the same ExtINT cascade interrupt to drive the local APIC of the
2279 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2280 * the I/O APIC in all cases now. No actual device should request
2281 * it anyway. --macro
2282 */
2283#define PIC_IRQS (1UL << PIC_CASCADE_IR)
2284
2285static int mp_irqdomain_create(int ioapic)
2286{
2287 struct irq_alloc_info info;
2288 struct irq_domain *parent;
2289 int hwirqs = mp_ioapic_pin_count(ioapic);
2290 struct ioapic *ip = &ioapics[ioapic];
2291 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2292 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2293 struct fwnode_handle *fn;
2294 char *name = "IO-APIC";
2295
2296 if (cfg->type == IOAPIC_DOMAIN_INVALID)
2297 return 0;
2298
2299 init_irq_alloc_info(&info, NULL);
2300 info.type = X86_IRQ_ALLOC_TYPE_IOAPIC;
2301 info.ioapic_id = mpc_ioapic_id(ioapic);
2302 parent = irq_remapping_get_ir_irq_domain(&info);
2303 if (!parent)
2304 parent = x86_vector_domain;
2305 else
2306 name = "IO-APIC-IR";
2307
2308 /* Handle device tree enumerated APICs proper */
2309 if (cfg->dev) {
2310 fn = of_node_to_fwnode(cfg->dev);
2311 } else {
2312 fn = irq_domain_alloc_named_id_fwnode(name, ioapic);
2313 if (!fn)
2314 return -ENOMEM;
2315 }
2316
2317 ip->irqdomain = irq_domain_create_linear(fn, hwirqs, cfg->ops,
2318 (void *)(long)ioapic);
2319
2320 if (!ip->irqdomain) {
2321 /* Release fw handle if it was allocated above */
2322 if (!cfg->dev)
2323 irq_domain_free_fwnode(fn);
2324 return -ENOMEM;
2325 }
2326
2327 ip->irqdomain->parent = parent;
2328
2329 if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2330 cfg->type == IOAPIC_DOMAIN_STRICT)
2331 ioapic_dynirq_base = max(ioapic_dynirq_base,
2332 gsi_cfg->gsi_end + 1);
2333
2334 return 0;
2335}
2336
2337static void ioapic_destroy_irqdomain(int idx)
2338{
2339 struct ioapic_domain_cfg *cfg = &ioapics[idx].irqdomain_cfg;
2340 struct fwnode_handle *fn = ioapics[idx].irqdomain->fwnode;
2341
2342 if (ioapics[idx].irqdomain) {
2343 irq_domain_remove(ioapics[idx].irqdomain);
2344 if (!cfg->dev)
2345 irq_domain_free_fwnode(fn);
2346 ioapics[idx].irqdomain = NULL;
2347 }
2348}
2349
2350void __init setup_IO_APIC(void)
2351{
2352 int ioapic;
2353
2354 if (skip_ioapic_setup || !nr_ioapics)
2355 return;
2356
2357 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2358
2359 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2360 for_each_ioapic(ioapic)
2361 BUG_ON(mp_irqdomain_create(ioapic));
2362
2363 /*
2364 * Set up IO-APIC IRQ routing.
2365 */
2366 x86_init.mpparse.setup_ioapic_ids();
2367
2368 sync_Arb_IDs();
2369 setup_IO_APIC_irqs();
2370 init_IO_APIC_traps();
2371 if (nr_legacy_irqs())
2372 check_timer();
2373
2374 ioapic_initialized = 1;
2375}
2376
2377static void resume_ioapic_id(int ioapic_idx)
2378{
2379 unsigned long flags;
2380 union IO_APIC_reg_00 reg_00;
2381
2382 raw_spin_lock_irqsave(&ioapic_lock, flags);
2383 reg_00.raw = io_apic_read(ioapic_idx, 0);
2384 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2385 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2386 io_apic_write(ioapic_idx, 0, reg_00.raw);
2387 }
2388 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2389}
2390
2391static void ioapic_resume(void)
2392{
2393 int ioapic_idx;
2394
2395 for_each_ioapic_reverse(ioapic_idx)
2396 resume_ioapic_id(ioapic_idx);
2397
2398 restore_ioapic_entries();
2399}
2400
2401static struct syscore_ops ioapic_syscore_ops = {
2402 .suspend = save_ioapic_entries,
2403 .resume = ioapic_resume,
2404};
2405
2406static int __init ioapic_init_ops(void)
2407{
2408 register_syscore_ops(&ioapic_syscore_ops);
2409
2410 return 0;
2411}
2412
2413device_initcall(ioapic_init_ops);
2414
2415static int io_apic_get_redir_entries(int ioapic)
2416{
2417 union IO_APIC_reg_01 reg_01;
2418 unsigned long flags;
2419
2420 raw_spin_lock_irqsave(&ioapic_lock, flags);
2421 reg_01.raw = io_apic_read(ioapic, 1);
2422 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2423
2424 /* The register returns the maximum index redir index
2425 * supported, which is one less than the total number of redir
2426 * entries.
2427 */
2428 return reg_01.bits.entries + 1;
2429}
2430
2431unsigned int arch_dynirq_lower_bound(unsigned int from)
2432{
2433 /*
2434 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2435 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2436 */
2437 if (!ioapic_initialized)
2438 return gsi_top;
2439 /*
2440 * For DT enabled machines ioapic_dynirq_base is irrelevant and not
2441 * updated. So simply return @from if ioapic_dynirq_base == 0.
2442 */
2443 return ioapic_dynirq_base ? : from;
2444}
2445
2446#ifdef CONFIG_X86_32
2447static int io_apic_get_unique_id(int ioapic, int apic_id)
2448{
2449 union IO_APIC_reg_00 reg_00;
2450 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2451 physid_mask_t tmp;
2452 unsigned long flags;
2453 int i = 0;
2454
2455 /*
2456 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2457 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2458 * supports up to 16 on one shared APIC bus.
2459 *
2460 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2461 * advantage of new APIC bus architecture.
2462 */
2463
2464 if (physids_empty(apic_id_map))
2465 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
2466
2467 raw_spin_lock_irqsave(&ioapic_lock, flags);
2468 reg_00.raw = io_apic_read(ioapic, 0);
2469 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2470
2471 if (apic_id >= get_physical_broadcast()) {
2472 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2473 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2474 apic_id = reg_00.bits.ID;
2475 }
2476
2477 /*
2478 * Every APIC in a system must have a unique ID or we get lots of nice
2479 * 'stuck on smp_invalidate_needed IPI wait' messages.
2480 */
2481 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
2482
2483 for (i = 0; i < get_physical_broadcast(); i++) {
2484 if (!apic->check_apicid_used(&apic_id_map, i))
2485 break;
2486 }
2487
2488 if (i == get_physical_broadcast())
2489 panic("Max apic_id exceeded!\n");
2490
2491 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2492 "trying %d\n", ioapic, apic_id, i);
2493
2494 apic_id = i;
2495 }
2496
2497 apic->apicid_to_cpu_present(apic_id, &tmp);
2498 physids_or(apic_id_map, apic_id_map, tmp);
2499
2500 if (reg_00.bits.ID != apic_id) {
2501 reg_00.bits.ID = apic_id;
2502
2503 raw_spin_lock_irqsave(&ioapic_lock, flags);
2504 io_apic_write(ioapic, 0, reg_00.raw);
2505 reg_00.raw = io_apic_read(ioapic, 0);
2506 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2507
2508 /* Sanity check */
2509 if (reg_00.bits.ID != apic_id) {
2510 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2511 ioapic);
2512 return -1;
2513 }
2514 }
2515
2516 apic_printk(APIC_VERBOSE, KERN_INFO
2517 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2518
2519 return apic_id;
2520}
2521
2522static u8 io_apic_unique_id(int idx, u8 id)
2523{
2524 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
2525 !APIC_XAPIC(boot_cpu_apic_version))
2526 return io_apic_get_unique_id(idx, id);
2527 else
2528 return id;
2529}
2530#else
2531static u8 io_apic_unique_id(int idx, u8 id)
2532{
2533 union IO_APIC_reg_00 reg_00;
2534 DECLARE_BITMAP(used, 256);
2535 unsigned long flags;
2536 u8 new_id;
2537 int i;
2538
2539 bitmap_zero(used, 256);
2540 for_each_ioapic(i)
2541 __set_bit(mpc_ioapic_id(i), used);
2542
2543 /* Hand out the requested id if available */
2544 if (!test_bit(id, used))
2545 return id;
2546
2547 /*
2548 * Read the current id from the ioapic and keep it if
2549 * available.
2550 */
2551 raw_spin_lock_irqsave(&ioapic_lock, flags);
2552 reg_00.raw = io_apic_read(idx, 0);
2553 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2554 new_id = reg_00.bits.ID;
2555 if (!test_bit(new_id, used)) {
2556 apic_printk(APIC_VERBOSE, KERN_INFO
2557 "IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2558 idx, new_id, id);
2559 return new_id;
2560 }
2561
2562 /*
2563 * Get the next free id and write it to the ioapic.
2564 */
2565 new_id = find_first_zero_bit(used, 256);
2566 reg_00.bits.ID = new_id;
2567 raw_spin_lock_irqsave(&ioapic_lock, flags);
2568 io_apic_write(idx, 0, reg_00.raw);
2569 reg_00.raw = io_apic_read(idx, 0);
2570 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2571 /* Sanity check */
2572 BUG_ON(reg_00.bits.ID != new_id);
2573
2574 return new_id;
2575}
2576#endif
2577
2578static int io_apic_get_version(int ioapic)
2579{
2580 union IO_APIC_reg_01 reg_01;
2581 unsigned long flags;
2582
2583 raw_spin_lock_irqsave(&ioapic_lock, flags);
2584 reg_01.raw = io_apic_read(ioapic, 1);
2585 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2586
2587 return reg_01.bits.version;
2588}
2589
2590int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
2591{
2592 int ioapic, pin, idx;
2593
2594 if (skip_ioapic_setup)
2595 return -1;
2596
2597 ioapic = mp_find_ioapic(gsi);
2598 if (ioapic < 0)
2599 return -1;
2600
2601 pin = mp_find_ioapic_pin(ioapic, gsi);
2602 if (pin < 0)
2603 return -1;
2604
2605 idx = find_irq_entry(ioapic, pin, mp_INT);
2606 if (idx < 0)
2607 return -1;
2608
2609 *trigger = irq_trigger(idx);
2610 *polarity = irq_polarity(idx);
2611 return 0;
2612}
2613
2614/*
2615 * This function updates target affinity of IOAPIC interrupts to include
2616 * the CPUs which came online during SMP bringup.
2617 */
2618#define IOAPIC_RESOURCE_NAME_SIZE 11
2619
2620static struct resource *ioapic_resources;
2621
2622static struct resource * __init ioapic_setup_resources(void)
2623{
2624 unsigned long n;
2625 struct resource *res;
2626 char *mem;
2627 int i;
2628
2629 if (nr_ioapics == 0)
2630 return NULL;
2631
2632 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2633 n *= nr_ioapics;
2634
2635 mem = memblock_alloc(n, SMP_CACHE_BYTES);
2636 if (!mem)
2637 panic("%s: Failed to allocate %lu bytes\n", __func__, n);
2638 res = (void *)mem;
2639
2640 mem += sizeof(struct resource) * nr_ioapics;
2641
2642 for_each_ioapic(i) {
2643 res[i].name = mem;
2644 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2645 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2646 mem += IOAPIC_RESOURCE_NAME_SIZE;
2647 ioapics[i].iomem_res = &res[i];
2648 }
2649
2650 ioapic_resources = res;
2651
2652 return res;
2653}
2654
2655void __init io_apic_init_mappings(void)
2656{
2657 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2658 struct resource *ioapic_res;
2659 int i;
2660
2661 ioapic_res = ioapic_setup_resources();
2662 for_each_ioapic(i) {
2663 if (smp_found_config) {
2664 ioapic_phys = mpc_ioapic_addr(i);
2665#ifdef CONFIG_X86_32
2666 if (!ioapic_phys) {
2667 printk(KERN_ERR
2668 "WARNING: bogus zero IO-APIC "
2669 "address found in MPTABLE, "
2670 "disabling IO/APIC support!\n");
2671 smp_found_config = 0;
2672 skip_ioapic_setup = 1;
2673 goto fake_ioapic_page;
2674 }
2675#endif
2676 } else {
2677#ifdef CONFIG_X86_32
2678fake_ioapic_page:
2679#endif
2680 ioapic_phys = (unsigned long)memblock_alloc(PAGE_SIZE,
2681 PAGE_SIZE);
2682 if (!ioapic_phys)
2683 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
2684 __func__, PAGE_SIZE, PAGE_SIZE);
2685 ioapic_phys = __pa(ioapic_phys);
2686 }
2687 set_fixmap_nocache(idx, ioapic_phys);
2688 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
2689 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
2690 ioapic_phys);
2691 idx++;
2692
2693 ioapic_res->start = ioapic_phys;
2694 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2695 ioapic_res++;
2696 }
2697}
2698
2699void __init ioapic_insert_resources(void)
2700{
2701 int i;
2702 struct resource *r = ioapic_resources;
2703
2704 if (!r) {
2705 if (nr_ioapics > 0)
2706 printk(KERN_ERR
2707 "IO APIC resources couldn't be allocated.\n");
2708 return;
2709 }
2710
2711 for_each_ioapic(i) {
2712 insert_resource(&iomem_resource, r);
2713 r++;
2714 }
2715}
2716
2717int mp_find_ioapic(u32 gsi)
2718{
2719 int i;
2720
2721 if (nr_ioapics == 0)
2722 return -1;
2723
2724 /* Find the IOAPIC that manages this GSI. */
2725 for_each_ioapic(i) {
2726 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2727 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2728 return i;
2729 }
2730
2731 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
2732 return -1;
2733}
2734
2735int mp_find_ioapic_pin(int ioapic, u32 gsi)
2736{
2737 struct mp_ioapic_gsi *gsi_cfg;
2738
2739 if (WARN_ON(ioapic < 0))
2740 return -1;
2741
2742 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2743 if (WARN_ON(gsi > gsi_cfg->gsi_end))
2744 return -1;
2745
2746 return gsi - gsi_cfg->gsi_base;
2747}
2748
2749static int bad_ioapic_register(int idx)
2750{
2751 union IO_APIC_reg_00 reg_00;
2752 union IO_APIC_reg_01 reg_01;
2753 union IO_APIC_reg_02 reg_02;
2754
2755 reg_00.raw = io_apic_read(idx, 0);
2756 reg_01.raw = io_apic_read(idx, 1);
2757 reg_02.raw = io_apic_read(idx, 2);
2758
2759 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
2760 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2761 mpc_ioapic_addr(idx));
2762 return 1;
2763 }
2764
2765 return 0;
2766}
2767
2768static int find_free_ioapic_entry(void)
2769{
2770 int idx;
2771
2772 for (idx = 0; idx < MAX_IO_APICS; idx++)
2773 if (ioapics[idx].nr_registers == 0)
2774 return idx;
2775
2776 return MAX_IO_APICS;
2777}
2778
2779/**
2780 * mp_register_ioapic - Register an IOAPIC device
2781 * @id: hardware IOAPIC ID
2782 * @address: physical address of IOAPIC register area
2783 * @gsi_base: base of GSI associated with the IOAPIC
2784 * @cfg: configuration information for the IOAPIC
2785 */
2786int mp_register_ioapic(int id, u32 address, u32 gsi_base,
2787 struct ioapic_domain_cfg *cfg)
2788{
2789 bool hotplug = !!ioapic_initialized;
2790 struct mp_ioapic_gsi *gsi_cfg;
2791 int idx, ioapic, entries;
2792 u32 gsi_end;
2793
2794 if (!address) {
2795 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2796 return -EINVAL;
2797 }
2798 for_each_ioapic(ioapic)
2799 if (ioapics[ioapic].mp_config.apicaddr == address) {
2800 pr_warn("address 0x%x conflicts with IOAPIC%d\n",
2801 address, ioapic);
2802 return -EEXIST;
2803 }
2804
2805 idx = find_free_ioapic_entry();
2806 if (idx >= MAX_IO_APICS) {
2807 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2808 MAX_IO_APICS, idx);
2809 return -ENOSPC;
2810 }
2811
2812 ioapics[idx].mp_config.type = MP_IOAPIC;
2813 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
2814 ioapics[idx].mp_config.apicaddr = address;
2815
2816 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
2817 if (bad_ioapic_register(idx)) {
2818 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2819 return -ENODEV;
2820 }
2821
2822 ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2823 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2824
2825 /*
2826 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2827 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2828 */
2829 entries = io_apic_get_redir_entries(idx);
2830 gsi_end = gsi_base + entries - 1;
2831 for_each_ioapic(ioapic) {
2832 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2833 if ((gsi_base >= gsi_cfg->gsi_base &&
2834 gsi_base <= gsi_cfg->gsi_end) ||
2835 (gsi_end >= gsi_cfg->gsi_base &&
2836 gsi_end <= gsi_cfg->gsi_end)) {
2837 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2838 gsi_base, gsi_end,
2839 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2840 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2841 return -ENOSPC;
2842 }
2843 }
2844 gsi_cfg = mp_ioapic_gsi_routing(idx);
2845 gsi_cfg->gsi_base = gsi_base;
2846 gsi_cfg->gsi_end = gsi_end;
2847
2848 ioapics[idx].irqdomain = NULL;
2849 ioapics[idx].irqdomain_cfg = *cfg;
2850
2851 /*
2852 * If mp_register_ioapic() is called during early boot stage when
2853 * walking ACPI/SFI/DT tables, it's too early to create irqdomain,
2854 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2855 */
2856 if (hotplug) {
2857 if (mp_irqdomain_create(idx)) {
2858 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2859 return -ENOMEM;
2860 }
2861 alloc_ioapic_saved_registers(idx);
2862 }
2863
2864 if (gsi_cfg->gsi_end >= gsi_top)
2865 gsi_top = gsi_cfg->gsi_end + 1;
2866 if (nr_ioapics <= idx)
2867 nr_ioapics = idx + 1;
2868
2869 /* Set nr_registers to mark entry present */
2870 ioapics[idx].nr_registers = entries;
2871
2872 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2873 idx, mpc_ioapic_id(idx),
2874 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
2875 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2876
2877 return 0;
2878}
2879
2880int mp_unregister_ioapic(u32 gsi_base)
2881{
2882 int ioapic, pin;
2883 int found = 0;
2884
2885 for_each_ioapic(ioapic)
2886 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
2887 found = 1;
2888 break;
2889 }
2890 if (!found) {
2891 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
2892 return -ENODEV;
2893 }
2894
2895 for_each_pin(ioapic, pin) {
2896 u32 gsi = mp_pin_to_gsi(ioapic, pin);
2897 int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
2898 struct mp_chip_data *data;
2899
2900 if (irq >= 0) {
2901 data = irq_get_chip_data(irq);
2902 if (data && data->count) {
2903 pr_warn("pin%d on IOAPIC%d is still in use.\n",
2904 pin, ioapic);
2905 return -EBUSY;
2906 }
2907 }
2908 }
2909
2910 /* Mark entry not present */
2911 ioapics[ioapic].nr_registers = 0;
2912 ioapic_destroy_irqdomain(ioapic);
2913 free_ioapic_saved_registers(ioapic);
2914 if (ioapics[ioapic].iomem_res)
2915 release_resource(ioapics[ioapic].iomem_res);
2916 clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
2917 memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
2918
2919 return 0;
2920}
2921
2922int mp_ioapic_registered(u32 gsi_base)
2923{
2924 int ioapic;
2925
2926 for_each_ioapic(ioapic)
2927 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
2928 return 1;
2929
2930 return 0;
2931}
2932
2933static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
2934 struct irq_alloc_info *info)
2935{
2936 if (info && info->ioapic_valid) {
2937 data->trigger = info->ioapic_trigger;
2938 data->polarity = info->ioapic_polarity;
2939 } else if (acpi_get_override_irq(gsi, &data->trigger,
2940 &data->polarity) < 0) {
2941 /* PCI interrupts are always active low level triggered. */
2942 data->trigger = IOAPIC_LEVEL;
2943 data->polarity = IOAPIC_POL_LOW;
2944 }
2945}
2946
2947static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data,
2948 struct IO_APIC_route_entry *entry)
2949{
2950 memset(entry, 0, sizeof(*entry));
2951 entry->delivery_mode = apic->irq_delivery_mode;
2952 entry->dest_mode = apic->irq_dest_mode;
2953 entry->dest = cfg->dest_apicid;
2954 entry->vector = cfg->vector;
2955 entry->trigger = data->trigger;
2956 entry->polarity = data->polarity;
2957 /*
2958 * Mask level triggered irqs. Edge triggered irqs are masked
2959 * by the irq core code in case they fire.
2960 */
2961 if (data->trigger == IOAPIC_LEVEL)
2962 entry->mask = IOAPIC_MASKED;
2963 else
2964 entry->mask = IOAPIC_UNMASKED;
2965}
2966
2967int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
2968 unsigned int nr_irqs, void *arg)
2969{
2970 int ret, ioapic, pin;
2971 struct irq_cfg *cfg;
2972 struct irq_data *irq_data;
2973 struct mp_chip_data *data;
2974 struct irq_alloc_info *info = arg;
2975 unsigned long flags;
2976
2977 if (!info || nr_irqs > 1)
2978 return -EINVAL;
2979 irq_data = irq_domain_get_irq_data(domain, virq);
2980 if (!irq_data)
2981 return -EINVAL;
2982
2983 ioapic = mp_irqdomain_ioapic_idx(domain);
2984 pin = info->ioapic_pin;
2985 if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
2986 return -EEXIST;
2987
2988 data = kzalloc(sizeof(*data), GFP_KERNEL);
2989 if (!data)
2990 return -ENOMEM;
2991
2992 info->ioapic_entry = &data->entry;
2993 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
2994 if (ret < 0) {
2995 kfree(data);
2996 return ret;
2997 }
2998
2999 INIT_LIST_HEAD(&data->irq_2_pin);
3000 irq_data->hwirq = info->ioapic_pin;
3001 irq_data->chip = (domain->parent == x86_vector_domain) ?
3002 &ioapic_chip : &ioapic_ir_chip;
3003 irq_data->chip_data = data;
3004 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
3005
3006 cfg = irqd_cfg(irq_data);
3007 add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin);
3008
3009 local_irq_save(flags);
3010 if (info->ioapic_entry)
3011 mp_setup_entry(cfg, data, info->ioapic_entry);
3012 mp_register_handler(virq, data->trigger);
3013 if (virq < nr_legacy_irqs())
3014 legacy_pic->mask(virq);
3015 local_irq_restore(flags);
3016
3017 apic_printk(APIC_VERBOSE, KERN_DEBUG
3018 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n",
3019 ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector,
3020 virq, data->trigger, data->polarity, cfg->dest_apicid);
3021
3022 return 0;
3023}
3024
3025void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
3026 unsigned int nr_irqs)
3027{
3028 struct irq_data *irq_data;
3029 struct mp_chip_data *data;
3030
3031 BUG_ON(nr_irqs != 1);
3032 irq_data = irq_domain_get_irq_data(domain, virq);
3033 if (irq_data && irq_data->chip_data) {
3034 data = irq_data->chip_data;
3035 __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain),
3036 (int)irq_data->hwirq);
3037 WARN_ON(!list_empty(&data->irq_2_pin));
3038 kfree(irq_data->chip_data);
3039 }
3040 irq_domain_free_irqs_top(domain, virq, nr_irqs);
3041}
3042
3043int mp_irqdomain_activate(struct irq_domain *domain,
3044 struct irq_data *irq_data, bool reserve)
3045{
3046 unsigned long flags;
3047
3048 raw_spin_lock_irqsave(&ioapic_lock, flags);
3049 ioapic_configure_entry(irq_data);
3050 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3051 return 0;
3052}
3053
3054void mp_irqdomain_deactivate(struct irq_domain *domain,
3055 struct irq_data *irq_data)
3056{
3057 /* It won't be called for IRQ with multiple IOAPIC pins associated */
3058 ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain),
3059 (int)irq_data->hwirq);
3060}
3061
3062int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
3063{
3064 return (int)(long)domain->host_data;
3065}
3066
3067const struct irq_domain_ops mp_ioapic_irqdomain_ops = {
3068 .alloc = mp_irqdomain_alloc,
3069 .free = mp_irqdomain_free,
3070 .activate = mp_irqdomain_activate,
3071 .deactivate = mp_irqdomain_deactivate,
3072};