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1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004 MIPS Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
17#include <linux/smp.h>
18#include <linux/stddef.h>
19#include <linux/module.h>
20
21#include <asm/bugs.h>
22#include <asm/cpu.h>
23#include <asm/fpu.h>
24#include <asm/mipsregs.h>
25#include <asm/system.h>
26#include <asm/watch.h>
27#include <asm/spram.h>
28#include <asm/uaccess.h>
29
30/*
31 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
32 * the implementation of the "wait" feature differs between CPU families. This
33 * points to the function that implements CPU specific wait.
34 * The wait instruction stops the pipeline and reduces the power consumption of
35 * the CPU very much.
36 */
37void (*cpu_wait)(void);
38EXPORT_SYMBOL(cpu_wait);
39
40static void r3081_wait(void)
41{
42 unsigned long cfg = read_c0_conf();
43 write_c0_conf(cfg | R30XX_CONF_HALT);
44}
45
46static void r39xx_wait(void)
47{
48 local_irq_disable();
49 if (!need_resched())
50 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
51 local_irq_enable();
52}
53
54extern void r4k_wait(void);
55
56/*
57 * This variant is preferable as it allows testing need_resched and going to
58 * sleep depending on the outcome atomically. Unfortunately the "It is
59 * implementation-dependent whether the pipeline restarts when a non-enabled
60 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
61 * using this version a gamble.
62 */
63void r4k_wait_irqoff(void)
64{
65 local_irq_disable();
66 if (!need_resched())
67 __asm__(" .set push \n"
68 " .set mips3 \n"
69 " wait \n"
70 " .set pop \n");
71 local_irq_enable();
72 __asm__(" .globl __pastwait \n"
73 "__pastwait: \n");
74}
75
76/*
77 * The RM7000 variant has to handle erratum 38. The workaround is to not
78 * have any pending stores when the WAIT instruction is executed.
79 */
80static void rm7k_wait_irqoff(void)
81{
82 local_irq_disable();
83 if (!need_resched())
84 __asm__(
85 " .set push \n"
86 " .set mips3 \n"
87 " .set noat \n"
88 " mfc0 $1, $12 \n"
89 " sync \n"
90 " mtc0 $1, $12 # stalls until W stage \n"
91 " wait \n"
92 " mtc0 $1, $12 # stalls until W stage \n"
93 " .set pop \n");
94 local_irq_enable();
95}
96
97/*
98 * The Au1xxx wait is available only if using 32khz counter or
99 * external timer source, but specifically not CP0 Counter.
100 * alchemy/common/time.c may override cpu_wait!
101 */
102static void au1k_wait(void)
103{
104 __asm__(" .set mips3 \n"
105 " cache 0x14, 0(%0) \n"
106 " cache 0x14, 32(%0) \n"
107 " sync \n"
108 " nop \n"
109 " wait \n"
110 " nop \n"
111 " nop \n"
112 " nop \n"
113 " nop \n"
114 " .set mips0 \n"
115 : : "r" (au1k_wait));
116}
117
118static int __initdata nowait;
119
120static int __init wait_disable(char *s)
121{
122 nowait = 1;
123
124 return 1;
125}
126
127__setup("nowait", wait_disable);
128
129static int __cpuinitdata mips_fpu_disabled;
130
131static int __init fpu_disable(char *s)
132{
133 cpu_data[0].options &= ~MIPS_CPU_FPU;
134 mips_fpu_disabled = 1;
135
136 return 1;
137}
138
139__setup("nofpu", fpu_disable);
140
141int __cpuinitdata mips_dsp_disabled;
142
143static int __init dsp_disable(char *s)
144{
145 cpu_data[0].ases &= ~MIPS_ASE_DSP;
146 mips_dsp_disabled = 1;
147
148 return 1;
149}
150
151__setup("nodsp", dsp_disable);
152
153void __init check_wait(void)
154{
155 struct cpuinfo_mips *c = ¤t_cpu_data;
156
157 if (nowait) {
158 printk("Wait instruction disabled.\n");
159 return;
160 }
161
162 switch (c->cputype) {
163 case CPU_R3081:
164 case CPU_R3081E:
165 cpu_wait = r3081_wait;
166 break;
167 case CPU_TX3927:
168 cpu_wait = r39xx_wait;
169 break;
170 case CPU_R4200:
171/* case CPU_R4300: */
172 case CPU_R4600:
173 case CPU_R4640:
174 case CPU_R4650:
175 case CPU_R4700:
176 case CPU_R5000:
177 case CPU_R5500:
178 case CPU_NEVADA:
179 case CPU_4KC:
180 case CPU_4KEC:
181 case CPU_4KSC:
182 case CPU_5KC:
183 case CPU_25KF:
184 case CPU_PR4450:
185 case CPU_BMIPS3300:
186 case CPU_BMIPS4350:
187 case CPU_BMIPS4380:
188 case CPU_BMIPS5000:
189 case CPU_CAVIUM_OCTEON:
190 case CPU_CAVIUM_OCTEON_PLUS:
191 case CPU_CAVIUM_OCTEON2:
192 case CPU_JZRISC:
193 cpu_wait = r4k_wait;
194 break;
195
196 case CPU_RM7000:
197 cpu_wait = rm7k_wait_irqoff;
198 break;
199
200 case CPU_24K:
201 case CPU_34K:
202 case CPU_1004K:
203 cpu_wait = r4k_wait;
204 if (read_c0_config7() & MIPS_CONF7_WII)
205 cpu_wait = r4k_wait_irqoff;
206 break;
207
208 case CPU_74K:
209 cpu_wait = r4k_wait;
210 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
211 cpu_wait = r4k_wait_irqoff;
212 break;
213
214 case CPU_TX49XX:
215 cpu_wait = r4k_wait_irqoff;
216 break;
217 case CPU_ALCHEMY:
218 cpu_wait = au1k_wait;
219 break;
220 case CPU_20KC:
221 /*
222 * WAIT on Rev1.0 has E1, E2, E3 and E16.
223 * WAIT on Rev2.0 and Rev3.0 has E16.
224 * Rev3.1 WAIT is nop, why bother
225 */
226 if ((c->processor_id & 0xff) <= 0x64)
227 break;
228
229 /*
230 * Another rev is incremeting c0_count at a reduced clock
231 * rate while in WAIT mode. So we basically have the choice
232 * between using the cp0 timer as clocksource or avoiding
233 * the WAIT instruction. Until more details are known,
234 * disable the use of WAIT for 20Kc entirely.
235 cpu_wait = r4k_wait;
236 */
237 break;
238 case CPU_RM9000:
239 if ((c->processor_id & 0x00ff) >= 0x40)
240 cpu_wait = r4k_wait;
241 break;
242 default:
243 break;
244 }
245}
246
247static inline void check_errata(void)
248{
249 struct cpuinfo_mips *c = ¤t_cpu_data;
250
251 switch (c->cputype) {
252 case CPU_34K:
253 /*
254 * Erratum "RPS May Cause Incorrect Instruction Execution"
255 * This code only handles VPE0, any SMP/SMTC/RTOS code
256 * making use of VPE1 will be responsable for that VPE.
257 */
258 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
259 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
260 break;
261 default:
262 break;
263 }
264}
265
266void __init check_bugs32(void)
267{
268 check_errata();
269}
270
271/*
272 * Probe whether cpu has config register by trying to play with
273 * alternate cache bit and see whether it matters.
274 * It's used by cpu_probe to distinguish between R3000A and R3081.
275 */
276static inline int cpu_has_confreg(void)
277{
278#ifdef CONFIG_CPU_R3000
279 extern unsigned long r3k_cache_size(unsigned long);
280 unsigned long size1, size2;
281 unsigned long cfg = read_c0_conf();
282
283 size1 = r3k_cache_size(ST0_ISC);
284 write_c0_conf(cfg ^ R30XX_CONF_AC);
285 size2 = r3k_cache_size(ST0_ISC);
286 write_c0_conf(cfg);
287 return size1 != size2;
288#else
289 return 0;
290#endif
291}
292
293static inline void set_elf_platform(int cpu, const char *plat)
294{
295 if (cpu == 0)
296 __elf_platform = plat;
297}
298
299/*
300 * Get the FPU Implementation/Revision.
301 */
302static inline unsigned long cpu_get_fpu_id(void)
303{
304 unsigned long tmp, fpu_id;
305
306 tmp = read_c0_status();
307 __enable_fpu();
308 fpu_id = read_32bit_cp1_register(CP1_REVISION);
309 write_c0_status(tmp);
310 return fpu_id;
311}
312
313/*
314 * Check the CPU has an FPU the official way.
315 */
316static inline int __cpu_has_fpu(void)
317{
318 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
319}
320
321static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
322{
323#ifdef __NEED_VMBITS_PROBE
324 write_c0_entryhi(0x3fffffffffffe000ULL);
325 back_to_back_c0_hazard();
326 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
327#endif
328}
329
330#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
331 | MIPS_CPU_COUNTER)
332
333static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
334{
335 switch (c->processor_id & 0xff00) {
336 case PRID_IMP_R2000:
337 c->cputype = CPU_R2000;
338 __cpu_name[cpu] = "R2000";
339 c->isa_level = MIPS_CPU_ISA_I;
340 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
341 MIPS_CPU_NOFPUEX;
342 if (__cpu_has_fpu())
343 c->options |= MIPS_CPU_FPU;
344 c->tlbsize = 64;
345 break;
346 case PRID_IMP_R3000:
347 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
348 if (cpu_has_confreg()) {
349 c->cputype = CPU_R3081E;
350 __cpu_name[cpu] = "R3081";
351 } else {
352 c->cputype = CPU_R3000A;
353 __cpu_name[cpu] = "R3000A";
354 }
355 break;
356 } else {
357 c->cputype = CPU_R3000;
358 __cpu_name[cpu] = "R3000";
359 }
360 c->isa_level = MIPS_CPU_ISA_I;
361 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
362 MIPS_CPU_NOFPUEX;
363 if (__cpu_has_fpu())
364 c->options |= MIPS_CPU_FPU;
365 c->tlbsize = 64;
366 break;
367 case PRID_IMP_R4000:
368 if (read_c0_config() & CONF_SC) {
369 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
370 c->cputype = CPU_R4400PC;
371 __cpu_name[cpu] = "R4400PC";
372 } else {
373 c->cputype = CPU_R4000PC;
374 __cpu_name[cpu] = "R4000PC";
375 }
376 } else {
377 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
378 c->cputype = CPU_R4400SC;
379 __cpu_name[cpu] = "R4400SC";
380 } else {
381 c->cputype = CPU_R4000SC;
382 __cpu_name[cpu] = "R4000SC";
383 }
384 }
385
386 c->isa_level = MIPS_CPU_ISA_III;
387 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
388 MIPS_CPU_WATCH | MIPS_CPU_VCE |
389 MIPS_CPU_LLSC;
390 c->tlbsize = 48;
391 break;
392 case PRID_IMP_VR41XX:
393 switch (c->processor_id & 0xf0) {
394 case PRID_REV_VR4111:
395 c->cputype = CPU_VR4111;
396 __cpu_name[cpu] = "NEC VR4111";
397 break;
398 case PRID_REV_VR4121:
399 c->cputype = CPU_VR4121;
400 __cpu_name[cpu] = "NEC VR4121";
401 break;
402 case PRID_REV_VR4122:
403 if ((c->processor_id & 0xf) < 0x3) {
404 c->cputype = CPU_VR4122;
405 __cpu_name[cpu] = "NEC VR4122";
406 } else {
407 c->cputype = CPU_VR4181A;
408 __cpu_name[cpu] = "NEC VR4181A";
409 }
410 break;
411 case PRID_REV_VR4130:
412 if ((c->processor_id & 0xf) < 0x4) {
413 c->cputype = CPU_VR4131;
414 __cpu_name[cpu] = "NEC VR4131";
415 } else {
416 c->cputype = CPU_VR4133;
417 __cpu_name[cpu] = "NEC VR4133";
418 }
419 break;
420 default:
421 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
422 c->cputype = CPU_VR41XX;
423 __cpu_name[cpu] = "NEC Vr41xx";
424 break;
425 }
426 c->isa_level = MIPS_CPU_ISA_III;
427 c->options = R4K_OPTS;
428 c->tlbsize = 32;
429 break;
430 case PRID_IMP_R4300:
431 c->cputype = CPU_R4300;
432 __cpu_name[cpu] = "R4300";
433 c->isa_level = MIPS_CPU_ISA_III;
434 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
435 MIPS_CPU_LLSC;
436 c->tlbsize = 32;
437 break;
438 case PRID_IMP_R4600:
439 c->cputype = CPU_R4600;
440 __cpu_name[cpu] = "R4600";
441 c->isa_level = MIPS_CPU_ISA_III;
442 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
443 MIPS_CPU_LLSC;
444 c->tlbsize = 48;
445 break;
446 #if 0
447 case PRID_IMP_R4650:
448 /*
449 * This processor doesn't have an MMU, so it's not
450 * "real easy" to run Linux on it. It is left purely
451 * for documentation. Commented out because it shares
452 * it's c0_prid id number with the TX3900.
453 */
454 c->cputype = CPU_R4650;
455 __cpu_name[cpu] = "R4650";
456 c->isa_level = MIPS_CPU_ISA_III;
457 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
458 c->tlbsize = 48;
459 break;
460 #endif
461 case PRID_IMP_TX39:
462 c->isa_level = MIPS_CPU_ISA_I;
463 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
464
465 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
466 c->cputype = CPU_TX3927;
467 __cpu_name[cpu] = "TX3927";
468 c->tlbsize = 64;
469 } else {
470 switch (c->processor_id & 0xff) {
471 case PRID_REV_TX3912:
472 c->cputype = CPU_TX3912;
473 __cpu_name[cpu] = "TX3912";
474 c->tlbsize = 32;
475 break;
476 case PRID_REV_TX3922:
477 c->cputype = CPU_TX3922;
478 __cpu_name[cpu] = "TX3922";
479 c->tlbsize = 64;
480 break;
481 }
482 }
483 break;
484 case PRID_IMP_R4700:
485 c->cputype = CPU_R4700;
486 __cpu_name[cpu] = "R4700";
487 c->isa_level = MIPS_CPU_ISA_III;
488 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
489 MIPS_CPU_LLSC;
490 c->tlbsize = 48;
491 break;
492 case PRID_IMP_TX49:
493 c->cputype = CPU_TX49XX;
494 __cpu_name[cpu] = "R49XX";
495 c->isa_level = MIPS_CPU_ISA_III;
496 c->options = R4K_OPTS | MIPS_CPU_LLSC;
497 if (!(c->processor_id & 0x08))
498 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
499 c->tlbsize = 48;
500 break;
501 case PRID_IMP_R5000:
502 c->cputype = CPU_R5000;
503 __cpu_name[cpu] = "R5000";
504 c->isa_level = MIPS_CPU_ISA_IV;
505 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
506 MIPS_CPU_LLSC;
507 c->tlbsize = 48;
508 break;
509 case PRID_IMP_R5432:
510 c->cputype = CPU_R5432;
511 __cpu_name[cpu] = "R5432";
512 c->isa_level = MIPS_CPU_ISA_IV;
513 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
514 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
515 c->tlbsize = 48;
516 break;
517 case PRID_IMP_R5500:
518 c->cputype = CPU_R5500;
519 __cpu_name[cpu] = "R5500";
520 c->isa_level = MIPS_CPU_ISA_IV;
521 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
522 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
523 c->tlbsize = 48;
524 break;
525 case PRID_IMP_NEVADA:
526 c->cputype = CPU_NEVADA;
527 __cpu_name[cpu] = "Nevada";
528 c->isa_level = MIPS_CPU_ISA_IV;
529 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
530 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
531 c->tlbsize = 48;
532 break;
533 case PRID_IMP_R6000:
534 c->cputype = CPU_R6000;
535 __cpu_name[cpu] = "R6000";
536 c->isa_level = MIPS_CPU_ISA_II;
537 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
538 MIPS_CPU_LLSC;
539 c->tlbsize = 32;
540 break;
541 case PRID_IMP_R6000A:
542 c->cputype = CPU_R6000A;
543 __cpu_name[cpu] = "R6000A";
544 c->isa_level = MIPS_CPU_ISA_II;
545 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
546 MIPS_CPU_LLSC;
547 c->tlbsize = 32;
548 break;
549 case PRID_IMP_RM7000:
550 c->cputype = CPU_RM7000;
551 __cpu_name[cpu] = "RM7000";
552 c->isa_level = MIPS_CPU_ISA_IV;
553 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
554 MIPS_CPU_LLSC;
555 /*
556 * Undocumented RM7000: Bit 29 in the info register of
557 * the RM7000 v2.0 indicates if the TLB has 48 or 64
558 * entries.
559 *
560 * 29 1 => 64 entry JTLB
561 * 0 => 48 entry JTLB
562 */
563 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
564 break;
565 case PRID_IMP_RM9000:
566 c->cputype = CPU_RM9000;
567 __cpu_name[cpu] = "RM9000";
568 c->isa_level = MIPS_CPU_ISA_IV;
569 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
570 MIPS_CPU_LLSC;
571 /*
572 * Bit 29 in the info register of the RM9000
573 * indicates if the TLB has 48 or 64 entries.
574 *
575 * 29 1 => 64 entry JTLB
576 * 0 => 48 entry JTLB
577 */
578 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
579 break;
580 case PRID_IMP_R8000:
581 c->cputype = CPU_R8000;
582 __cpu_name[cpu] = "RM8000";
583 c->isa_level = MIPS_CPU_ISA_IV;
584 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
585 MIPS_CPU_FPU | MIPS_CPU_32FPR |
586 MIPS_CPU_LLSC;
587 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
588 break;
589 case PRID_IMP_R10000:
590 c->cputype = CPU_R10000;
591 __cpu_name[cpu] = "R10000";
592 c->isa_level = MIPS_CPU_ISA_IV;
593 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
594 MIPS_CPU_FPU | MIPS_CPU_32FPR |
595 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
596 MIPS_CPU_LLSC;
597 c->tlbsize = 64;
598 break;
599 case PRID_IMP_R12000:
600 c->cputype = CPU_R12000;
601 __cpu_name[cpu] = "R12000";
602 c->isa_level = MIPS_CPU_ISA_IV;
603 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
604 MIPS_CPU_FPU | MIPS_CPU_32FPR |
605 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
606 MIPS_CPU_LLSC;
607 c->tlbsize = 64;
608 break;
609 case PRID_IMP_R14000:
610 c->cputype = CPU_R14000;
611 __cpu_name[cpu] = "R14000";
612 c->isa_level = MIPS_CPU_ISA_IV;
613 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
614 MIPS_CPU_FPU | MIPS_CPU_32FPR |
615 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
616 MIPS_CPU_LLSC;
617 c->tlbsize = 64;
618 break;
619 case PRID_IMP_LOONGSON2:
620 c->cputype = CPU_LOONGSON2;
621 __cpu_name[cpu] = "ICT Loongson-2";
622
623 switch (c->processor_id & PRID_REV_MASK) {
624 case PRID_REV_LOONGSON2E:
625 set_elf_platform(cpu, "loongson2e");
626 break;
627 case PRID_REV_LOONGSON2F:
628 set_elf_platform(cpu, "loongson2f");
629 break;
630 }
631
632 c->isa_level = MIPS_CPU_ISA_III;
633 c->options = R4K_OPTS |
634 MIPS_CPU_FPU | MIPS_CPU_LLSC |
635 MIPS_CPU_32FPR;
636 c->tlbsize = 64;
637 break;
638 }
639}
640
641static char unknown_isa[] __cpuinitdata = KERN_ERR \
642 "Unsupported ISA type, c0.config0: %d.";
643
644static inline unsigned int decode_config0(struct cpuinfo_mips *c)
645{
646 unsigned int config0;
647 int isa;
648
649 config0 = read_c0_config();
650
651 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
652 c->options |= MIPS_CPU_TLB;
653 isa = (config0 & MIPS_CONF_AT) >> 13;
654 switch (isa) {
655 case 0:
656 switch ((config0 & MIPS_CONF_AR) >> 10) {
657 case 0:
658 c->isa_level = MIPS_CPU_ISA_M32R1;
659 break;
660 case 1:
661 c->isa_level = MIPS_CPU_ISA_M32R2;
662 break;
663 default:
664 goto unknown;
665 }
666 break;
667 case 2:
668 switch ((config0 & MIPS_CONF_AR) >> 10) {
669 case 0:
670 c->isa_level = MIPS_CPU_ISA_M64R1;
671 break;
672 case 1:
673 c->isa_level = MIPS_CPU_ISA_M64R2;
674 break;
675 default:
676 goto unknown;
677 }
678 break;
679 default:
680 goto unknown;
681 }
682
683 return config0 & MIPS_CONF_M;
684
685unknown:
686 panic(unknown_isa, config0);
687}
688
689static inline unsigned int decode_config1(struct cpuinfo_mips *c)
690{
691 unsigned int config1;
692
693 config1 = read_c0_config1();
694
695 if (config1 & MIPS_CONF1_MD)
696 c->ases |= MIPS_ASE_MDMX;
697 if (config1 & MIPS_CONF1_WR)
698 c->options |= MIPS_CPU_WATCH;
699 if (config1 & MIPS_CONF1_CA)
700 c->ases |= MIPS_ASE_MIPS16;
701 if (config1 & MIPS_CONF1_EP)
702 c->options |= MIPS_CPU_EJTAG;
703 if (config1 & MIPS_CONF1_FP) {
704 c->options |= MIPS_CPU_FPU;
705 c->options |= MIPS_CPU_32FPR;
706 }
707 if (cpu_has_tlb)
708 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
709
710 return config1 & MIPS_CONF_M;
711}
712
713static inline unsigned int decode_config2(struct cpuinfo_mips *c)
714{
715 unsigned int config2;
716
717 config2 = read_c0_config2();
718
719 if (config2 & MIPS_CONF2_SL)
720 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
721
722 return config2 & MIPS_CONF_M;
723}
724
725static inline unsigned int decode_config3(struct cpuinfo_mips *c)
726{
727 unsigned int config3;
728
729 config3 = read_c0_config3();
730
731 if (config3 & MIPS_CONF3_SM)
732 c->ases |= MIPS_ASE_SMARTMIPS;
733 if (config3 & MIPS_CONF3_DSP)
734 c->ases |= MIPS_ASE_DSP;
735 if (config3 & MIPS_CONF3_VINT)
736 c->options |= MIPS_CPU_VINT;
737 if (config3 & MIPS_CONF3_VEIC)
738 c->options |= MIPS_CPU_VEIC;
739 if (config3 & MIPS_CONF3_MT)
740 c->ases |= MIPS_ASE_MIPSMT;
741 if (config3 & MIPS_CONF3_ULRI)
742 c->options |= MIPS_CPU_ULRI;
743
744 return config3 & MIPS_CONF_M;
745}
746
747static inline unsigned int decode_config4(struct cpuinfo_mips *c)
748{
749 unsigned int config4;
750
751 config4 = read_c0_config4();
752
753 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
754 && cpu_has_tlb)
755 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
756
757 c->kscratch_mask = (config4 >> 16) & 0xff;
758
759 return config4 & MIPS_CONF_M;
760}
761
762static void __cpuinit decode_configs(struct cpuinfo_mips *c)
763{
764 int ok;
765
766 /* MIPS32 or MIPS64 compliant CPU. */
767 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
768 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
769
770 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
771
772 ok = decode_config0(c); /* Read Config registers. */
773 BUG_ON(!ok); /* Arch spec violation! */
774 if (ok)
775 ok = decode_config1(c);
776 if (ok)
777 ok = decode_config2(c);
778 if (ok)
779 ok = decode_config3(c);
780 if (ok)
781 ok = decode_config4(c);
782
783 mips_probe_watch_registers(c);
784
785 if (cpu_has_mips_r2)
786 c->core = read_c0_ebase() & 0x3ff;
787}
788
789static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
790{
791 decode_configs(c);
792 switch (c->processor_id & 0xff00) {
793 case PRID_IMP_4KC:
794 c->cputype = CPU_4KC;
795 __cpu_name[cpu] = "MIPS 4Kc";
796 break;
797 case PRID_IMP_4KEC:
798 case PRID_IMP_4KECR2:
799 c->cputype = CPU_4KEC;
800 __cpu_name[cpu] = "MIPS 4KEc";
801 break;
802 case PRID_IMP_4KSC:
803 case PRID_IMP_4KSD:
804 c->cputype = CPU_4KSC;
805 __cpu_name[cpu] = "MIPS 4KSc";
806 break;
807 case PRID_IMP_5KC:
808 c->cputype = CPU_5KC;
809 __cpu_name[cpu] = "MIPS 5Kc";
810 break;
811 case PRID_IMP_20KC:
812 c->cputype = CPU_20KC;
813 __cpu_name[cpu] = "MIPS 20Kc";
814 break;
815 case PRID_IMP_24K:
816 case PRID_IMP_24KE:
817 c->cputype = CPU_24K;
818 __cpu_name[cpu] = "MIPS 24Kc";
819 break;
820 case PRID_IMP_25KF:
821 c->cputype = CPU_25KF;
822 __cpu_name[cpu] = "MIPS 25Kc";
823 break;
824 case PRID_IMP_34K:
825 c->cputype = CPU_34K;
826 __cpu_name[cpu] = "MIPS 34Kc";
827 break;
828 case PRID_IMP_74K:
829 c->cputype = CPU_74K;
830 __cpu_name[cpu] = "MIPS 74Kc";
831 break;
832 case PRID_IMP_1004K:
833 c->cputype = CPU_1004K;
834 __cpu_name[cpu] = "MIPS 1004Kc";
835 break;
836 }
837
838 spram_config();
839}
840
841static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
842{
843 decode_configs(c);
844 switch (c->processor_id & 0xff00) {
845 case PRID_IMP_AU1_REV1:
846 case PRID_IMP_AU1_REV2:
847 c->cputype = CPU_ALCHEMY;
848 switch ((c->processor_id >> 24) & 0xff) {
849 case 0:
850 __cpu_name[cpu] = "Au1000";
851 break;
852 case 1:
853 __cpu_name[cpu] = "Au1500";
854 break;
855 case 2:
856 __cpu_name[cpu] = "Au1100";
857 break;
858 case 3:
859 __cpu_name[cpu] = "Au1550";
860 break;
861 case 4:
862 __cpu_name[cpu] = "Au1200";
863 if ((c->processor_id & 0xff) == 2)
864 __cpu_name[cpu] = "Au1250";
865 break;
866 case 5:
867 __cpu_name[cpu] = "Au1210";
868 break;
869 default:
870 __cpu_name[cpu] = "Au1xxx";
871 break;
872 }
873 break;
874 }
875}
876
877static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
878{
879 decode_configs(c);
880
881 switch (c->processor_id & 0xff00) {
882 case PRID_IMP_SB1:
883 c->cputype = CPU_SB1;
884 __cpu_name[cpu] = "SiByte SB1";
885 /* FPU in pass1 is known to have issues. */
886 if ((c->processor_id & 0xff) < 0x02)
887 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
888 break;
889 case PRID_IMP_SB1A:
890 c->cputype = CPU_SB1A;
891 __cpu_name[cpu] = "SiByte SB1A";
892 break;
893 }
894}
895
896static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
897{
898 decode_configs(c);
899 switch (c->processor_id & 0xff00) {
900 case PRID_IMP_SR71000:
901 c->cputype = CPU_SR71000;
902 __cpu_name[cpu] = "Sandcraft SR71000";
903 c->scache.ways = 8;
904 c->tlbsize = 64;
905 break;
906 }
907}
908
909static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
910{
911 decode_configs(c);
912 switch (c->processor_id & 0xff00) {
913 case PRID_IMP_PR4450:
914 c->cputype = CPU_PR4450;
915 __cpu_name[cpu] = "Philips PR4450";
916 c->isa_level = MIPS_CPU_ISA_M32R1;
917 break;
918 }
919}
920
921static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
922{
923 decode_configs(c);
924 switch (c->processor_id & 0xff00) {
925 case PRID_IMP_BMIPS32_REV4:
926 case PRID_IMP_BMIPS32_REV8:
927 c->cputype = CPU_BMIPS32;
928 __cpu_name[cpu] = "Broadcom BMIPS32";
929 set_elf_platform(cpu, "bmips32");
930 break;
931 case PRID_IMP_BMIPS3300:
932 case PRID_IMP_BMIPS3300_ALT:
933 case PRID_IMP_BMIPS3300_BUG:
934 c->cputype = CPU_BMIPS3300;
935 __cpu_name[cpu] = "Broadcom BMIPS3300";
936 set_elf_platform(cpu, "bmips3300");
937 break;
938 case PRID_IMP_BMIPS43XX: {
939 int rev = c->processor_id & 0xff;
940
941 if (rev >= PRID_REV_BMIPS4380_LO &&
942 rev <= PRID_REV_BMIPS4380_HI) {
943 c->cputype = CPU_BMIPS4380;
944 __cpu_name[cpu] = "Broadcom BMIPS4380";
945 set_elf_platform(cpu, "bmips4380");
946 } else {
947 c->cputype = CPU_BMIPS4350;
948 __cpu_name[cpu] = "Broadcom BMIPS4350";
949 set_elf_platform(cpu, "bmips4350");
950 }
951 break;
952 }
953 case PRID_IMP_BMIPS5000:
954 c->cputype = CPU_BMIPS5000;
955 __cpu_name[cpu] = "Broadcom BMIPS5000";
956 set_elf_platform(cpu, "bmips5000");
957 c->options |= MIPS_CPU_ULRI;
958 break;
959 }
960}
961
962static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
963{
964 decode_configs(c);
965 switch (c->processor_id & 0xff00) {
966 case PRID_IMP_CAVIUM_CN38XX:
967 case PRID_IMP_CAVIUM_CN31XX:
968 case PRID_IMP_CAVIUM_CN30XX:
969 c->cputype = CPU_CAVIUM_OCTEON;
970 __cpu_name[cpu] = "Cavium Octeon";
971 goto platform;
972 case PRID_IMP_CAVIUM_CN58XX:
973 case PRID_IMP_CAVIUM_CN56XX:
974 case PRID_IMP_CAVIUM_CN50XX:
975 case PRID_IMP_CAVIUM_CN52XX:
976 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
977 __cpu_name[cpu] = "Cavium Octeon+";
978platform:
979 set_elf_platform(cpu, "octeon");
980 break;
981 case PRID_IMP_CAVIUM_CN63XX:
982 c->cputype = CPU_CAVIUM_OCTEON2;
983 __cpu_name[cpu] = "Cavium Octeon II";
984 set_elf_platform(cpu, "octeon2");
985 break;
986 default:
987 printk(KERN_INFO "Unknown Octeon chip!\n");
988 c->cputype = CPU_UNKNOWN;
989 break;
990 }
991}
992
993static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
994{
995 decode_configs(c);
996 /* JZRISC does not implement the CP0 counter. */
997 c->options &= ~MIPS_CPU_COUNTER;
998 switch (c->processor_id & 0xff00) {
999 case PRID_IMP_JZRISC:
1000 c->cputype = CPU_JZRISC;
1001 __cpu_name[cpu] = "Ingenic JZRISC";
1002 break;
1003 default:
1004 panic("Unknown Ingenic Processor ID!");
1005 break;
1006 }
1007}
1008
1009static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1010{
1011 decode_configs(c);
1012
1013 c->options = (MIPS_CPU_TLB |
1014 MIPS_CPU_4KEX |
1015 MIPS_CPU_COUNTER |
1016 MIPS_CPU_DIVEC |
1017 MIPS_CPU_WATCH |
1018 MIPS_CPU_EJTAG |
1019 MIPS_CPU_LLSC);
1020
1021 switch (c->processor_id & 0xff00) {
1022 case PRID_IMP_NETLOGIC_XLR732:
1023 case PRID_IMP_NETLOGIC_XLR716:
1024 case PRID_IMP_NETLOGIC_XLR532:
1025 case PRID_IMP_NETLOGIC_XLR308:
1026 case PRID_IMP_NETLOGIC_XLR532C:
1027 case PRID_IMP_NETLOGIC_XLR516C:
1028 case PRID_IMP_NETLOGIC_XLR508C:
1029 case PRID_IMP_NETLOGIC_XLR308C:
1030 c->cputype = CPU_XLR;
1031 __cpu_name[cpu] = "Netlogic XLR";
1032 break;
1033
1034 case PRID_IMP_NETLOGIC_XLS608:
1035 case PRID_IMP_NETLOGIC_XLS408:
1036 case PRID_IMP_NETLOGIC_XLS404:
1037 case PRID_IMP_NETLOGIC_XLS208:
1038 case PRID_IMP_NETLOGIC_XLS204:
1039 case PRID_IMP_NETLOGIC_XLS108:
1040 case PRID_IMP_NETLOGIC_XLS104:
1041 case PRID_IMP_NETLOGIC_XLS616B:
1042 case PRID_IMP_NETLOGIC_XLS608B:
1043 case PRID_IMP_NETLOGIC_XLS416B:
1044 case PRID_IMP_NETLOGIC_XLS412B:
1045 case PRID_IMP_NETLOGIC_XLS408B:
1046 case PRID_IMP_NETLOGIC_XLS404B:
1047 c->cputype = CPU_XLR;
1048 __cpu_name[cpu] = "Netlogic XLS";
1049 break;
1050
1051 default:
1052 printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n",
1053 c->processor_id);
1054 c->cputype = CPU_XLR;
1055 break;
1056 }
1057
1058 c->isa_level = MIPS_CPU_ISA_M64R1;
1059 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1060}
1061
1062#ifdef CONFIG_64BIT
1063/* For use by uaccess.h */
1064u64 __ua_limit;
1065EXPORT_SYMBOL(__ua_limit);
1066#endif
1067
1068const char *__cpu_name[NR_CPUS];
1069const char *__elf_platform;
1070
1071__cpuinit void cpu_probe(void)
1072{
1073 struct cpuinfo_mips *c = ¤t_cpu_data;
1074 unsigned int cpu = smp_processor_id();
1075
1076 c->processor_id = PRID_IMP_UNKNOWN;
1077 c->fpu_id = FPIR_IMP_NONE;
1078 c->cputype = CPU_UNKNOWN;
1079
1080 c->processor_id = read_c0_prid();
1081 switch (c->processor_id & 0xff0000) {
1082 case PRID_COMP_LEGACY:
1083 cpu_probe_legacy(c, cpu);
1084 break;
1085 case PRID_COMP_MIPS:
1086 cpu_probe_mips(c, cpu);
1087 break;
1088 case PRID_COMP_ALCHEMY:
1089 cpu_probe_alchemy(c, cpu);
1090 break;
1091 case PRID_COMP_SIBYTE:
1092 cpu_probe_sibyte(c, cpu);
1093 break;
1094 case PRID_COMP_BROADCOM:
1095 cpu_probe_broadcom(c, cpu);
1096 break;
1097 case PRID_COMP_SANDCRAFT:
1098 cpu_probe_sandcraft(c, cpu);
1099 break;
1100 case PRID_COMP_NXP:
1101 cpu_probe_nxp(c, cpu);
1102 break;
1103 case PRID_COMP_CAVIUM:
1104 cpu_probe_cavium(c, cpu);
1105 break;
1106 case PRID_COMP_INGENIC:
1107 cpu_probe_ingenic(c, cpu);
1108 break;
1109 case PRID_COMP_NETLOGIC:
1110 cpu_probe_netlogic(c, cpu);
1111 break;
1112 }
1113
1114 BUG_ON(!__cpu_name[cpu]);
1115 BUG_ON(c->cputype == CPU_UNKNOWN);
1116
1117 /*
1118 * Platform code can force the cpu type to optimize code
1119 * generation. In that case be sure the cpu type is correctly
1120 * manually setup otherwise it could trigger some nasty bugs.
1121 */
1122 BUG_ON(current_cpu_type() != c->cputype);
1123
1124 if (mips_fpu_disabled)
1125 c->options &= ~MIPS_CPU_FPU;
1126
1127 if (mips_dsp_disabled)
1128 c->ases &= ~MIPS_ASE_DSP;
1129
1130 if (c->options & MIPS_CPU_FPU) {
1131 c->fpu_id = cpu_get_fpu_id();
1132
1133 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1134 c->isa_level == MIPS_CPU_ISA_M32R2 ||
1135 c->isa_level == MIPS_CPU_ISA_M64R1 ||
1136 c->isa_level == MIPS_CPU_ISA_M64R2) {
1137 if (c->fpu_id & MIPS_FPIR_3D)
1138 c->ases |= MIPS_ASE_MIPS3D;
1139 }
1140 }
1141
1142 if (cpu_has_mips_r2)
1143 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1144 else
1145 c->srsets = 1;
1146
1147 cpu_probe_vmbits(c);
1148
1149#ifdef CONFIG_64BIT
1150 if (cpu == 0)
1151 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1152#endif
1153}
1154
1155__cpuinit void cpu_report(void)
1156{
1157 struct cpuinfo_mips *c = ¤t_cpu_data;
1158
1159 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1160 c->processor_id, cpu_name_string());
1161 if (c->options & MIPS_CPU_FPU)
1162 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1163}
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Processor capabilities determination functions.
4 *
5 * Copyright (C) xxxx the Anonymous
6 * Copyright (C) 1994 - 2006 Ralf Baechle
7 * Copyright (C) 2003, 2004 Maciej W. Rozycki
8 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 */
10#include <linux/init.h>
11#include <linux/kernel.h>
12#include <linux/ptrace.h>
13#include <linux/smp.h>
14#include <linux/stddef.h>
15#include <linux/export.h>
16
17#include <asm/bugs.h>
18#include <asm/cpu.h>
19#include <asm/cpu-features.h>
20#include <asm/cpu-type.h>
21#include <asm/fpu.h>
22#include <asm/mipsregs.h>
23#include <asm/mipsmtregs.h>
24#include <asm/msa.h>
25#include <asm/watch.h>
26#include <asm/elf.h>
27#include <asm/pgtable-bits.h>
28#include <asm/spram.h>
29#include <linux/uaccess.h>
30
31#include <asm/mach-loongson64/cpucfg-emul.h>
32
33/* Hardware capabilities */
34unsigned int elf_hwcap __read_mostly;
35EXPORT_SYMBOL_GPL(elf_hwcap);
36
37#ifdef CONFIG_MIPS_FP_SUPPORT
38
39/*
40 * Get the FPU Implementation/Revision.
41 */
42static inline unsigned long cpu_get_fpu_id(void)
43{
44 unsigned long tmp, fpu_id;
45
46 tmp = read_c0_status();
47 __enable_fpu(FPU_AS_IS);
48 fpu_id = read_32bit_cp1_register(CP1_REVISION);
49 write_c0_status(tmp);
50 return fpu_id;
51}
52
53/*
54 * Check if the CPU has an external FPU.
55 */
56static inline int __cpu_has_fpu(void)
57{
58 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
59}
60
61/*
62 * Determine the FCSR mask for FPU hardware.
63 */
64static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
65{
66 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
67
68 fcsr = c->fpu_csr31;
69 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
70
71 sr = read_c0_status();
72 __enable_fpu(FPU_AS_IS);
73
74 fcsr0 = fcsr & mask;
75 write_32bit_cp1_register(CP1_STATUS, fcsr0);
76 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
77
78 fcsr1 = fcsr | ~mask;
79 write_32bit_cp1_register(CP1_STATUS, fcsr1);
80 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
81
82 write_32bit_cp1_register(CP1_STATUS, fcsr);
83
84 write_c0_status(sr);
85
86 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
87}
88
89/*
90 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
91 * supported by FPU hardware.
92 */
93static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
94{
95 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
96 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
97 MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
98 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
99 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
100
101 sr = read_c0_status();
102 __enable_fpu(FPU_AS_IS);
103
104 fir = read_32bit_cp1_register(CP1_REVISION);
105 if (fir & MIPS_FPIR_HAS2008) {
106 fcsr = read_32bit_cp1_register(CP1_STATUS);
107
108 /*
109 * MAC2008 toolchain never landed in real world, so we're only
110 * testing wether it can be disabled and don't try to enabled
111 * it.
112 */
113 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008 | FPU_CSR_MAC2008);
114 write_32bit_cp1_register(CP1_STATUS, fcsr0);
115 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
116
117 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
118 write_32bit_cp1_register(CP1_STATUS, fcsr1);
119 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
120
121 write_32bit_cp1_register(CP1_STATUS, fcsr);
122
123 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2)) {
124 /*
125 * The bit for MAC2008 might be reused by R6 in future,
126 * so we only test for R2-R5.
127 */
128 if (fcsr0 & FPU_CSR_MAC2008)
129 c->options |= MIPS_CPU_MAC_2008_ONLY;
130 }
131
132 if (!(fcsr0 & FPU_CSR_NAN2008))
133 c->options |= MIPS_CPU_NAN_LEGACY;
134 if (fcsr1 & FPU_CSR_NAN2008)
135 c->options |= MIPS_CPU_NAN_2008;
136
137 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
138 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
139 else
140 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
141
142 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
143 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
144 else
145 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
146 } else {
147 c->options |= MIPS_CPU_NAN_LEGACY;
148 }
149
150 write_c0_status(sr);
151 } else {
152 c->options |= MIPS_CPU_NAN_LEGACY;
153 }
154}
155
156/*
157 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
158 * ABS.fmt/NEG.fmt execution mode.
159 */
160static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
161
162/*
163 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
164 * to support by the FPU emulator according to the IEEE 754 conformance
165 * mode selected. Note that "relaxed" straps the emulator so that it
166 * allows 2008-NaN binaries even for legacy processors.
167 */
168static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
169{
170 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
171 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
172 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
173
174 switch (ieee754) {
175 case STRICT:
176 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
177 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
178 MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
179 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
180 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
181 } else {
182 c->options |= MIPS_CPU_NAN_LEGACY;
183 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
184 }
185 break;
186 case LEGACY:
187 c->options |= MIPS_CPU_NAN_LEGACY;
188 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
189 break;
190 case STD2008:
191 c->options |= MIPS_CPU_NAN_2008;
192 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
193 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
194 break;
195 case RELAXED:
196 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
197 break;
198 }
199}
200
201/*
202 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
203 * according to the "ieee754=" parameter.
204 */
205static void cpu_set_nan_2008(struct cpuinfo_mips *c)
206{
207 switch (ieee754) {
208 case STRICT:
209 mips_use_nan_legacy = !!cpu_has_nan_legacy;
210 mips_use_nan_2008 = !!cpu_has_nan_2008;
211 break;
212 case LEGACY:
213 mips_use_nan_legacy = !!cpu_has_nan_legacy;
214 mips_use_nan_2008 = !cpu_has_nan_legacy;
215 break;
216 case STD2008:
217 mips_use_nan_legacy = !cpu_has_nan_2008;
218 mips_use_nan_2008 = !!cpu_has_nan_2008;
219 break;
220 case RELAXED:
221 mips_use_nan_legacy = true;
222 mips_use_nan_2008 = true;
223 break;
224 }
225}
226
227/*
228 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
229 * settings:
230 *
231 * strict: accept binaries that request a NaN encoding supported by the FPU
232 * legacy: only accept legacy-NaN binaries
233 * 2008: only accept 2008-NaN binaries
234 * relaxed: accept any binaries regardless of whether supported by the FPU
235 */
236static int __init ieee754_setup(char *s)
237{
238 if (!s)
239 return -1;
240 else if (!strcmp(s, "strict"))
241 ieee754 = STRICT;
242 else if (!strcmp(s, "legacy"))
243 ieee754 = LEGACY;
244 else if (!strcmp(s, "2008"))
245 ieee754 = STD2008;
246 else if (!strcmp(s, "relaxed"))
247 ieee754 = RELAXED;
248 else
249 return -1;
250
251 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
252 cpu_set_nofpu_2008(&boot_cpu_data);
253 cpu_set_nan_2008(&boot_cpu_data);
254
255 return 0;
256}
257
258early_param("ieee754", ieee754_setup);
259
260/*
261 * Set the FIR feature flags for the FPU emulator.
262 */
263static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
264{
265 u32 value;
266
267 value = 0;
268 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
269 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
270 MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
271 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
272 value |= MIPS_FPIR_D | MIPS_FPIR_S;
273 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
274 MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
275 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
276 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
277 if (c->options & MIPS_CPU_NAN_2008)
278 value |= MIPS_FPIR_HAS2008;
279 c->fpu_id = value;
280}
281
282/* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
283static unsigned int mips_nofpu_msk31;
284
285/*
286 * Set options for FPU hardware.
287 */
288static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
289{
290 c->fpu_id = cpu_get_fpu_id();
291 mips_nofpu_msk31 = c->fpu_msk31;
292
293 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
294 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
295 MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
296 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
297 if (c->fpu_id & MIPS_FPIR_3D)
298 c->ases |= MIPS_ASE_MIPS3D;
299 if (c->fpu_id & MIPS_FPIR_UFRP)
300 c->options |= MIPS_CPU_UFR;
301 if (c->fpu_id & MIPS_FPIR_FREP)
302 c->options |= MIPS_CPU_FRE;
303 }
304
305 cpu_set_fpu_fcsr_mask(c);
306 cpu_set_fpu_2008(c);
307 cpu_set_nan_2008(c);
308}
309
310/*
311 * Set options for the FPU emulator.
312 */
313static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
314{
315 c->options &= ~MIPS_CPU_FPU;
316 c->fpu_msk31 = mips_nofpu_msk31;
317
318 cpu_set_nofpu_2008(c);
319 cpu_set_nan_2008(c);
320 cpu_set_nofpu_id(c);
321}
322
323static int mips_fpu_disabled;
324
325static int __init fpu_disable(char *s)
326{
327 cpu_set_nofpu_opts(&boot_cpu_data);
328 mips_fpu_disabled = 1;
329
330 return 1;
331}
332
333__setup("nofpu", fpu_disable);
334
335#else /* !CONFIG_MIPS_FP_SUPPORT */
336
337#define mips_fpu_disabled 1
338
339static inline unsigned long cpu_get_fpu_id(void)
340{
341 return FPIR_IMP_NONE;
342}
343
344static inline int __cpu_has_fpu(void)
345{
346 return 0;
347}
348
349static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
350{
351 /* no-op */
352}
353
354static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
355{
356 /* no-op */
357}
358
359#endif /* CONFIG_MIPS_FP_SUPPORT */
360
361static inline unsigned long cpu_get_msa_id(void)
362{
363 unsigned long status, msa_id;
364
365 status = read_c0_status();
366 __enable_fpu(FPU_64BIT);
367 enable_msa();
368 msa_id = read_msa_ir();
369 disable_msa();
370 write_c0_status(status);
371 return msa_id;
372}
373
374static int mips_dsp_disabled;
375
376static int __init dsp_disable(char *s)
377{
378 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
379 mips_dsp_disabled = 1;
380
381 return 1;
382}
383
384__setup("nodsp", dsp_disable);
385
386static int mips_htw_disabled;
387
388static int __init htw_disable(char *s)
389{
390 mips_htw_disabled = 1;
391 cpu_data[0].options &= ~MIPS_CPU_HTW;
392 write_c0_pwctl(read_c0_pwctl() &
393 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
394
395 return 1;
396}
397
398__setup("nohtw", htw_disable);
399
400static int mips_ftlb_disabled;
401static int mips_has_ftlb_configured;
402
403enum ftlb_flags {
404 FTLB_EN = 1 << 0,
405 FTLB_SET_PROB = 1 << 1,
406};
407
408static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
409
410static int __init ftlb_disable(char *s)
411{
412 unsigned int config4, mmuextdef;
413
414 /*
415 * If the core hasn't done any FTLB configuration, there is nothing
416 * for us to do here.
417 */
418 if (!mips_has_ftlb_configured)
419 return 1;
420
421 /* Disable it in the boot cpu */
422 if (set_ftlb_enable(&cpu_data[0], 0)) {
423 pr_warn("Can't turn FTLB off\n");
424 return 1;
425 }
426
427 config4 = read_c0_config4();
428
429 /* Check that FTLB has been disabled */
430 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
431 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
432 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
433 /* This should never happen */
434 pr_warn("FTLB could not be disabled!\n");
435 return 1;
436 }
437
438 mips_ftlb_disabled = 1;
439 mips_has_ftlb_configured = 0;
440
441 /*
442 * noftlb is mainly used for debug purposes so print
443 * an informative message instead of using pr_debug()
444 */
445 pr_info("FTLB has been disabled\n");
446
447 /*
448 * Some of these bits are duplicated in the decode_config4.
449 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
450 * once FTLB has been disabled so undo what decode_config4 did.
451 */
452 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
453 cpu_data[0].tlbsizeftlbsets;
454 cpu_data[0].tlbsizeftlbsets = 0;
455 cpu_data[0].tlbsizeftlbways = 0;
456
457 return 1;
458}
459
460__setup("noftlb", ftlb_disable);
461
462/*
463 * Check if the CPU has per tc perf counters
464 */
465static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c)
466{
467 if (read_c0_config7() & MTI_CONF7_PTC)
468 c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS;
469}
470
471static inline void check_errata(void)
472{
473 struct cpuinfo_mips *c = ¤t_cpu_data;
474
475 switch (current_cpu_type()) {
476 case CPU_34K:
477 /*
478 * Erratum "RPS May Cause Incorrect Instruction Execution"
479 * This code only handles VPE0, any SMP/RTOS code
480 * making use of VPE1 will be responsable for that VPE.
481 */
482 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
483 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
484 break;
485 default:
486 break;
487 }
488}
489
490void __init check_bugs32(void)
491{
492 check_errata();
493}
494
495/*
496 * Probe whether cpu has config register by trying to play with
497 * alternate cache bit and see whether it matters.
498 * It's used by cpu_probe to distinguish between R3000A and R3081.
499 */
500static inline int cpu_has_confreg(void)
501{
502#ifdef CONFIG_CPU_R3000
503 extern unsigned long r3k_cache_size(unsigned long);
504 unsigned long size1, size2;
505 unsigned long cfg = read_c0_conf();
506
507 size1 = r3k_cache_size(ST0_ISC);
508 write_c0_conf(cfg ^ R30XX_CONF_AC);
509 size2 = r3k_cache_size(ST0_ISC);
510 write_c0_conf(cfg);
511 return size1 != size2;
512#else
513 return 0;
514#endif
515}
516
517static inline void set_elf_platform(int cpu, const char *plat)
518{
519 if (cpu == 0)
520 __elf_platform = plat;
521}
522
523static inline void set_elf_base_platform(const char *plat)
524{
525 if (__elf_base_platform == NULL) {
526 __elf_base_platform = plat;
527 }
528}
529
530static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
531{
532#ifdef __NEED_VMBITS_PROBE
533 write_c0_entryhi(0x3fffffffffffe000ULL);
534 back_to_back_c0_hazard();
535 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
536#endif
537}
538
539static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
540{
541 switch (isa) {
542 case MIPS_CPU_ISA_M64R5:
543 c->isa_level |= MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5;
544 set_elf_base_platform("mips64r5");
545 fallthrough;
546 case MIPS_CPU_ISA_M64R2:
547 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
548 set_elf_base_platform("mips64r2");
549 fallthrough;
550 case MIPS_CPU_ISA_M64R1:
551 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
552 set_elf_base_platform("mips64");
553 fallthrough;
554 case MIPS_CPU_ISA_V:
555 c->isa_level |= MIPS_CPU_ISA_V;
556 set_elf_base_platform("mips5");
557 fallthrough;
558 case MIPS_CPU_ISA_IV:
559 c->isa_level |= MIPS_CPU_ISA_IV;
560 set_elf_base_platform("mips4");
561 fallthrough;
562 case MIPS_CPU_ISA_III:
563 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
564 set_elf_base_platform("mips3");
565 break;
566
567 /* R6 incompatible with everything else */
568 case MIPS_CPU_ISA_M64R6:
569 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
570 set_elf_base_platform("mips64r6");
571 fallthrough;
572 case MIPS_CPU_ISA_M32R6:
573 c->isa_level |= MIPS_CPU_ISA_M32R6;
574 set_elf_base_platform("mips32r6");
575 /* Break here so we don't add incompatible ISAs */
576 break;
577 case MIPS_CPU_ISA_M32R5:
578 c->isa_level |= MIPS_CPU_ISA_M32R5;
579 set_elf_base_platform("mips32r5");
580 fallthrough;
581 case MIPS_CPU_ISA_M32R2:
582 c->isa_level |= MIPS_CPU_ISA_M32R2;
583 set_elf_base_platform("mips32r2");
584 fallthrough;
585 case MIPS_CPU_ISA_M32R1:
586 c->isa_level |= MIPS_CPU_ISA_M32R1;
587 set_elf_base_platform("mips32");
588 fallthrough;
589 case MIPS_CPU_ISA_II:
590 c->isa_level |= MIPS_CPU_ISA_II;
591 set_elf_base_platform("mips2");
592 break;
593 }
594}
595
596static char unknown_isa[] = KERN_ERR \
597 "Unsupported ISA type, c0.config0: %d.";
598
599static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
600{
601
602 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
603
604 /*
605 * 0 = All TLBWR instructions go to FTLB
606 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
607 * FTLB and 1 goes to the VTLB.
608 * 2 = 7:1: As above with 7:1 ratio.
609 * 3 = 3:1: As above with 3:1 ratio.
610 *
611 * Use the linear midpoint as the probability threshold.
612 */
613 if (probability >= 12)
614 return 1;
615 else if (probability >= 6)
616 return 2;
617 else
618 /*
619 * So FTLB is less than 4 times bigger than VTLB.
620 * A 3:1 ratio can still be useful though.
621 */
622 return 3;
623}
624
625static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
626{
627 unsigned int config;
628
629 /* It's implementation dependent how the FTLB can be enabled */
630 switch (c->cputype) {
631 case CPU_PROAPTIV:
632 case CPU_P5600:
633 case CPU_P6600:
634 /* proAptiv & related cores use Config6 to enable the FTLB */
635 config = read_c0_config6();
636
637 if (flags & FTLB_EN)
638 config |= MTI_CONF6_FTLBEN;
639 else
640 config &= ~MTI_CONF6_FTLBEN;
641
642 if (flags & FTLB_SET_PROB) {
643 config &= ~(3 << MTI_CONF6_FTLBP_SHIFT);
644 config |= calculate_ftlb_probability(c)
645 << MTI_CONF6_FTLBP_SHIFT;
646 }
647
648 write_c0_config6(config);
649 back_to_back_c0_hazard();
650 break;
651 case CPU_I6400:
652 case CPU_I6500:
653 /* There's no way to disable the FTLB */
654 if (!(flags & FTLB_EN))
655 return 1;
656 return 0;
657 case CPU_LOONGSON64:
658 /* Flush ITLB, DTLB, VTLB and FTLB */
659 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
660 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
661 /* Loongson-3 cores use Config6 to enable the FTLB */
662 config = read_c0_config6();
663 if (flags & FTLB_EN)
664 /* Enable FTLB */
665 write_c0_config6(config & ~LOONGSON_CONF6_FTLBDIS);
666 else
667 /* Disable FTLB */
668 write_c0_config6(config | LOONGSON_CONF6_FTLBDIS);
669 break;
670 default:
671 return 1;
672 }
673
674 return 0;
675}
676
677static int mm_config(struct cpuinfo_mips *c)
678{
679 unsigned int config0, update, mm;
680
681 config0 = read_c0_config();
682 mm = config0 & MIPS_CONF_MM;
683
684 /*
685 * It's implementation dependent what type of write-merge is supported
686 * and whether it can be enabled/disabled. If it is settable lets make
687 * the merging allowed by default. Some platforms might have
688 * write-through caching unsupported. In this case just ignore the
689 * CP0.Config.MM bit field value.
690 */
691 switch (c->cputype) {
692 case CPU_24K:
693 case CPU_34K:
694 case CPU_74K:
695 case CPU_P5600:
696 case CPU_P6600:
697 c->options |= MIPS_CPU_MM_FULL;
698 update = MIPS_CONF_MM_FULL;
699 break;
700 case CPU_1004K:
701 case CPU_1074K:
702 case CPU_INTERAPTIV:
703 case CPU_PROAPTIV:
704 mm = 0;
705 fallthrough;
706 default:
707 update = 0;
708 break;
709 }
710
711 if (update) {
712 config0 = (config0 & ~MIPS_CONF_MM) | update;
713 write_c0_config(config0);
714 } else if (mm == MIPS_CONF_MM_SYSAD) {
715 c->options |= MIPS_CPU_MM_SYSAD;
716 } else if (mm == MIPS_CONF_MM_FULL) {
717 c->options |= MIPS_CPU_MM_FULL;
718 }
719
720 return 0;
721}
722
723static inline unsigned int decode_config0(struct cpuinfo_mips *c)
724{
725 unsigned int config0;
726 int isa, mt;
727
728 config0 = read_c0_config();
729
730 /*
731 * Look for Standard TLB or Dual VTLB and FTLB
732 */
733 mt = config0 & MIPS_CONF_MT;
734 if (mt == MIPS_CONF_MT_TLB)
735 c->options |= MIPS_CPU_TLB;
736 else if (mt == MIPS_CONF_MT_FTLB)
737 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
738
739 isa = (config0 & MIPS_CONF_AT) >> 13;
740 switch (isa) {
741 case 0:
742 switch ((config0 & MIPS_CONF_AR) >> 10) {
743 case 0:
744 set_isa(c, MIPS_CPU_ISA_M32R1);
745 break;
746 case 1:
747 set_isa(c, MIPS_CPU_ISA_M32R2);
748 break;
749 case 2:
750 set_isa(c, MIPS_CPU_ISA_M32R6);
751 break;
752 default:
753 goto unknown;
754 }
755 break;
756 case 2:
757 switch ((config0 & MIPS_CONF_AR) >> 10) {
758 case 0:
759 set_isa(c, MIPS_CPU_ISA_M64R1);
760 break;
761 case 1:
762 set_isa(c, MIPS_CPU_ISA_M64R2);
763 break;
764 case 2:
765 set_isa(c, MIPS_CPU_ISA_M64R6);
766 break;
767 default:
768 goto unknown;
769 }
770 break;
771 default:
772 goto unknown;
773 }
774
775 return config0 & MIPS_CONF_M;
776
777unknown:
778 panic(unknown_isa, config0);
779}
780
781static inline unsigned int decode_config1(struct cpuinfo_mips *c)
782{
783 unsigned int config1;
784
785 config1 = read_c0_config1();
786
787 if (config1 & MIPS_CONF1_MD)
788 c->ases |= MIPS_ASE_MDMX;
789 if (config1 & MIPS_CONF1_PC)
790 c->options |= MIPS_CPU_PERF;
791 if (config1 & MIPS_CONF1_WR)
792 c->options |= MIPS_CPU_WATCH;
793 if (config1 & MIPS_CONF1_CA)
794 c->ases |= MIPS_ASE_MIPS16;
795 if (config1 & MIPS_CONF1_EP)
796 c->options |= MIPS_CPU_EJTAG;
797 if (config1 & MIPS_CONF1_FP) {
798 c->options |= MIPS_CPU_FPU;
799 c->options |= MIPS_CPU_32FPR;
800 }
801 if (cpu_has_tlb) {
802 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
803 c->tlbsizevtlb = c->tlbsize;
804 c->tlbsizeftlbsets = 0;
805 }
806
807 return config1 & MIPS_CONF_M;
808}
809
810static inline unsigned int decode_config2(struct cpuinfo_mips *c)
811{
812 unsigned int config2;
813
814 config2 = read_c0_config2();
815
816 if (config2 & MIPS_CONF2_SL)
817 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
818
819 return config2 & MIPS_CONF_M;
820}
821
822static inline unsigned int decode_config3(struct cpuinfo_mips *c)
823{
824 unsigned int config3;
825
826 config3 = read_c0_config3();
827
828 if (config3 & MIPS_CONF3_SM) {
829 c->ases |= MIPS_ASE_SMARTMIPS;
830 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
831 }
832 if (config3 & MIPS_CONF3_RXI)
833 c->options |= MIPS_CPU_RIXI;
834 if (config3 & MIPS_CONF3_CTXTC)
835 c->options |= MIPS_CPU_CTXTC;
836 if (config3 & MIPS_CONF3_DSP)
837 c->ases |= MIPS_ASE_DSP;
838 if (config3 & MIPS_CONF3_DSP2P) {
839 c->ases |= MIPS_ASE_DSP2P;
840 if (cpu_has_mips_r6)
841 c->ases |= MIPS_ASE_DSP3;
842 }
843 if (config3 & MIPS_CONF3_VINT)
844 c->options |= MIPS_CPU_VINT;
845 if (config3 & MIPS_CONF3_VEIC)
846 c->options |= MIPS_CPU_VEIC;
847 if (config3 & MIPS_CONF3_LPA)
848 c->options |= MIPS_CPU_LPA;
849 if (config3 & MIPS_CONF3_MT)
850 c->ases |= MIPS_ASE_MIPSMT;
851 if (config3 & MIPS_CONF3_ULRI)
852 c->options |= MIPS_CPU_ULRI;
853 if (config3 & MIPS_CONF3_ISA)
854 c->options |= MIPS_CPU_MICROMIPS;
855 if (config3 & MIPS_CONF3_VZ)
856 c->ases |= MIPS_ASE_VZ;
857 if (config3 & MIPS_CONF3_SC)
858 c->options |= MIPS_CPU_SEGMENTS;
859 if (config3 & MIPS_CONF3_BI)
860 c->options |= MIPS_CPU_BADINSTR;
861 if (config3 & MIPS_CONF3_BP)
862 c->options |= MIPS_CPU_BADINSTRP;
863 if (config3 & MIPS_CONF3_MSA)
864 c->ases |= MIPS_ASE_MSA;
865 if (config3 & MIPS_CONF3_PW) {
866 c->htw_seq = 0;
867 c->options |= MIPS_CPU_HTW;
868 }
869 if (config3 & MIPS_CONF3_CDMM)
870 c->options |= MIPS_CPU_CDMM;
871 if (config3 & MIPS_CONF3_SP)
872 c->options |= MIPS_CPU_SP;
873
874 return config3 & MIPS_CONF_M;
875}
876
877static inline unsigned int decode_config4(struct cpuinfo_mips *c)
878{
879 unsigned int config4;
880 unsigned int newcf4;
881 unsigned int mmuextdef;
882 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
883 unsigned long asid_mask;
884
885 config4 = read_c0_config4();
886
887 if (cpu_has_tlb) {
888 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
889 c->options |= MIPS_CPU_TLBINV;
890
891 /*
892 * R6 has dropped the MMUExtDef field from config4.
893 * On R6 the fields always describe the FTLB, and only if it is
894 * present according to Config.MT.
895 */
896 if (!cpu_has_mips_r6)
897 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
898 else if (cpu_has_ftlb)
899 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
900 else
901 mmuextdef = 0;
902
903 switch (mmuextdef) {
904 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
905 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
906 c->tlbsizevtlb = c->tlbsize;
907 break;
908 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
909 c->tlbsizevtlb +=
910 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
911 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
912 c->tlbsize = c->tlbsizevtlb;
913 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
914 fallthrough;
915 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
916 if (mips_ftlb_disabled)
917 break;
918 newcf4 = (config4 & ~ftlb_page) |
919 (page_size_ftlb(mmuextdef) <<
920 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
921 write_c0_config4(newcf4);
922 back_to_back_c0_hazard();
923 config4 = read_c0_config4();
924 if (config4 != newcf4) {
925 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
926 PAGE_SIZE, config4);
927 /* Switch FTLB off */
928 set_ftlb_enable(c, 0);
929 mips_ftlb_disabled = 1;
930 break;
931 }
932 c->tlbsizeftlbsets = 1 <<
933 ((config4 & MIPS_CONF4_FTLBSETS) >>
934 MIPS_CONF4_FTLBSETS_SHIFT);
935 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
936 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
937 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
938 mips_has_ftlb_configured = 1;
939 break;
940 }
941 }
942
943 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
944 >> MIPS_CONF4_KSCREXIST_SHIFT;
945
946 asid_mask = MIPS_ENTRYHI_ASID;
947 if (config4 & MIPS_CONF4_AE)
948 asid_mask |= MIPS_ENTRYHI_ASIDX;
949 set_cpu_asid_mask(c, asid_mask);
950
951 /*
952 * Warn if the computed ASID mask doesn't match the mask the kernel
953 * is built for. This may indicate either a serious problem or an
954 * easy optimisation opportunity, but either way should be addressed.
955 */
956 WARN_ON(asid_mask != cpu_asid_mask(c));
957
958 return config4 & MIPS_CONF_M;
959}
960
961static inline unsigned int decode_config5(struct cpuinfo_mips *c)
962{
963 unsigned int config5, max_mmid_width;
964 unsigned long asid_mask;
965
966 config5 = read_c0_config5();
967 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
968
969 if (cpu_has_mips_r6) {
970 if (!__builtin_constant_p(cpu_has_mmid) || cpu_has_mmid)
971 config5 |= MIPS_CONF5_MI;
972 else
973 config5 &= ~MIPS_CONF5_MI;
974 }
975
976 write_c0_config5(config5);
977
978 if (config5 & MIPS_CONF5_EVA)
979 c->options |= MIPS_CPU_EVA;
980 if (config5 & MIPS_CONF5_MRP)
981 c->options |= MIPS_CPU_MAAR;
982 if (config5 & MIPS_CONF5_LLB)
983 c->options |= MIPS_CPU_RW_LLB;
984 if (config5 & MIPS_CONF5_MVH)
985 c->options |= MIPS_CPU_MVH;
986 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
987 c->options |= MIPS_CPU_VP;
988 if (config5 & MIPS_CONF5_CA2)
989 c->ases |= MIPS_ASE_MIPS16E2;
990
991 if (config5 & MIPS_CONF5_CRCP)
992 elf_hwcap |= HWCAP_MIPS_CRC32;
993
994 if (cpu_has_mips_r6) {
995 /* Ensure the write to config5 above takes effect */
996 back_to_back_c0_hazard();
997
998 /* Check whether we successfully enabled MMID support */
999 config5 = read_c0_config5();
1000 if (config5 & MIPS_CONF5_MI)
1001 c->options |= MIPS_CPU_MMID;
1002
1003 /*
1004 * Warn if we've hardcoded cpu_has_mmid to a value unsuitable
1005 * for the CPU we're running on, or if CPUs in an SMP system
1006 * have inconsistent MMID support.
1007 */
1008 WARN_ON(!!cpu_has_mmid != !!(config5 & MIPS_CONF5_MI));
1009
1010 if (cpu_has_mmid) {
1011 write_c0_memorymapid(~0ul);
1012 back_to_back_c0_hazard();
1013 asid_mask = read_c0_memorymapid();
1014
1015 /*
1016 * We maintain a bitmap to track MMID allocation, and
1017 * need a sensible upper bound on the size of that
1018 * bitmap. The initial CPU with MMID support (I6500)
1019 * supports 16 bit MMIDs, which gives us an 8KiB
1020 * bitmap. The architecture recommends that hardware
1021 * support 32 bit MMIDs, which would give us a 512MiB
1022 * bitmap - that's too big in most cases.
1023 *
1024 * Cap MMID width at 16 bits for now & we can revisit
1025 * this if & when hardware supports anything wider.
1026 */
1027 max_mmid_width = 16;
1028 if (asid_mask > GENMASK(max_mmid_width - 1, 0)) {
1029 pr_info("Capping MMID width at %d bits",
1030 max_mmid_width);
1031 asid_mask = GENMASK(max_mmid_width - 1, 0);
1032 }
1033
1034 set_cpu_asid_mask(c, asid_mask);
1035 }
1036 }
1037
1038 return config5 & MIPS_CONF_M;
1039}
1040
1041static void decode_configs(struct cpuinfo_mips *c)
1042{
1043 int ok;
1044
1045 /* MIPS32 or MIPS64 compliant CPU. */
1046 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
1047 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
1048
1049 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
1050
1051 /* Enable FTLB if present and not disabled */
1052 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
1053
1054 ok = decode_config0(c); /* Read Config registers. */
1055 BUG_ON(!ok); /* Arch spec violation! */
1056 if (ok)
1057 ok = decode_config1(c);
1058 if (ok)
1059 ok = decode_config2(c);
1060 if (ok)
1061 ok = decode_config3(c);
1062 if (ok)
1063 ok = decode_config4(c);
1064 if (ok)
1065 ok = decode_config5(c);
1066
1067 /* Probe the EBase.WG bit */
1068 if (cpu_has_mips_r2_r6) {
1069 u64 ebase;
1070 unsigned int status;
1071
1072 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
1073 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
1074 : (s32)read_c0_ebase();
1075 if (ebase & MIPS_EBASE_WG) {
1076 /* WG bit already set, we can avoid the clumsy probe */
1077 c->options |= MIPS_CPU_EBASE_WG;
1078 } else {
1079 /* Its UNDEFINED to change EBase while BEV=0 */
1080 status = read_c0_status();
1081 write_c0_status(status | ST0_BEV);
1082 irq_enable_hazard();
1083 /*
1084 * On pre-r6 cores, this may well clobber the upper bits
1085 * of EBase. This is hard to avoid without potentially
1086 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
1087 */
1088 if (cpu_has_mips64r6)
1089 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
1090 else
1091 write_c0_ebase(ebase | MIPS_EBASE_WG);
1092 back_to_back_c0_hazard();
1093 /* Restore BEV */
1094 write_c0_status(status);
1095 if (read_c0_ebase() & MIPS_EBASE_WG) {
1096 c->options |= MIPS_CPU_EBASE_WG;
1097 write_c0_ebase(ebase);
1098 }
1099 }
1100 }
1101
1102 /* configure the FTLB write probability */
1103 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
1104
1105 mips_probe_watch_registers(c);
1106
1107#ifndef CONFIG_MIPS_CPS
1108 if (cpu_has_mips_r2_r6) {
1109 unsigned int core;
1110
1111 core = get_ebase_cpunum();
1112 if (cpu_has_mipsmt)
1113 core >>= fls(core_nvpes()) - 1;
1114 cpu_set_core(c, core);
1115 }
1116#endif
1117}
1118
1119/*
1120 * Probe for certain guest capabilities by writing config bits and reading back.
1121 * Finally write back the original value.
1122 */
1123#define probe_gc0_config(name, maxconf, bits) \
1124do { \
1125 unsigned int tmp; \
1126 tmp = read_gc0_##name(); \
1127 write_gc0_##name(tmp | (bits)); \
1128 back_to_back_c0_hazard(); \
1129 maxconf = read_gc0_##name(); \
1130 write_gc0_##name(tmp); \
1131} while (0)
1132
1133/*
1134 * Probe for dynamic guest capabilities by changing certain config bits and
1135 * reading back to see if they change. Finally write back the original value.
1136 */
1137#define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \
1138do { \
1139 maxconf = read_gc0_##name(); \
1140 write_gc0_##name(maxconf ^ (bits)); \
1141 back_to_back_c0_hazard(); \
1142 dynconf = maxconf ^ read_gc0_##name(); \
1143 write_gc0_##name(maxconf); \
1144 maxconf |= dynconf; \
1145} while (0)
1146
1147static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
1148{
1149 unsigned int config0;
1150
1151 probe_gc0_config(config, config0, MIPS_CONF_M);
1152
1153 if (config0 & MIPS_CONF_M)
1154 c->guest.conf |= BIT(1);
1155 return config0 & MIPS_CONF_M;
1156}
1157
1158static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
1159{
1160 unsigned int config1, config1_dyn;
1161
1162 probe_gc0_config_dyn(config1, config1, config1_dyn,
1163 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
1164 MIPS_CONF1_FP);
1165
1166 if (config1 & MIPS_CONF1_FP)
1167 c->guest.options |= MIPS_CPU_FPU;
1168 if (config1_dyn & MIPS_CONF1_FP)
1169 c->guest.options_dyn |= MIPS_CPU_FPU;
1170
1171 if (config1 & MIPS_CONF1_WR)
1172 c->guest.options |= MIPS_CPU_WATCH;
1173 if (config1_dyn & MIPS_CONF1_WR)
1174 c->guest.options_dyn |= MIPS_CPU_WATCH;
1175
1176 if (config1 & MIPS_CONF1_PC)
1177 c->guest.options |= MIPS_CPU_PERF;
1178 if (config1_dyn & MIPS_CONF1_PC)
1179 c->guest.options_dyn |= MIPS_CPU_PERF;
1180
1181 if (config1 & MIPS_CONF_M)
1182 c->guest.conf |= BIT(2);
1183 return config1 & MIPS_CONF_M;
1184}
1185
1186static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
1187{
1188 unsigned int config2;
1189
1190 probe_gc0_config(config2, config2, MIPS_CONF_M);
1191
1192 if (config2 & MIPS_CONF_M)
1193 c->guest.conf |= BIT(3);
1194 return config2 & MIPS_CONF_M;
1195}
1196
1197static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
1198{
1199 unsigned int config3, config3_dyn;
1200
1201 probe_gc0_config_dyn(config3, config3, config3_dyn,
1202 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI |
1203 MIPS_CONF3_CTXTC);
1204
1205 if (config3 & MIPS_CONF3_CTXTC)
1206 c->guest.options |= MIPS_CPU_CTXTC;
1207 if (config3_dyn & MIPS_CONF3_CTXTC)
1208 c->guest.options_dyn |= MIPS_CPU_CTXTC;
1209
1210 if (config3 & MIPS_CONF3_PW)
1211 c->guest.options |= MIPS_CPU_HTW;
1212
1213 if (config3 & MIPS_CONF3_ULRI)
1214 c->guest.options |= MIPS_CPU_ULRI;
1215
1216 if (config3 & MIPS_CONF3_SC)
1217 c->guest.options |= MIPS_CPU_SEGMENTS;
1218
1219 if (config3 & MIPS_CONF3_BI)
1220 c->guest.options |= MIPS_CPU_BADINSTR;
1221 if (config3 & MIPS_CONF3_BP)
1222 c->guest.options |= MIPS_CPU_BADINSTRP;
1223
1224 if (config3 & MIPS_CONF3_MSA)
1225 c->guest.ases |= MIPS_ASE_MSA;
1226 if (config3_dyn & MIPS_CONF3_MSA)
1227 c->guest.ases_dyn |= MIPS_ASE_MSA;
1228
1229 if (config3 & MIPS_CONF_M)
1230 c->guest.conf |= BIT(4);
1231 return config3 & MIPS_CONF_M;
1232}
1233
1234static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
1235{
1236 unsigned int config4;
1237
1238 probe_gc0_config(config4, config4,
1239 MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
1240
1241 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
1242 >> MIPS_CONF4_KSCREXIST_SHIFT;
1243
1244 if (config4 & MIPS_CONF_M)
1245 c->guest.conf |= BIT(5);
1246 return config4 & MIPS_CONF_M;
1247}
1248
1249static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
1250{
1251 unsigned int config5, config5_dyn;
1252
1253 probe_gc0_config_dyn(config5, config5, config5_dyn,
1254 MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP);
1255
1256 if (config5 & MIPS_CONF5_MRP)
1257 c->guest.options |= MIPS_CPU_MAAR;
1258 if (config5_dyn & MIPS_CONF5_MRP)
1259 c->guest.options_dyn |= MIPS_CPU_MAAR;
1260
1261 if (config5 & MIPS_CONF5_LLB)
1262 c->guest.options |= MIPS_CPU_RW_LLB;
1263
1264 if (config5 & MIPS_CONF5_MVH)
1265 c->guest.options |= MIPS_CPU_MVH;
1266
1267 if (config5 & MIPS_CONF_M)
1268 c->guest.conf |= BIT(6);
1269 return config5 & MIPS_CONF_M;
1270}
1271
1272static inline void decode_guest_configs(struct cpuinfo_mips *c)
1273{
1274 unsigned int ok;
1275
1276 ok = decode_guest_config0(c);
1277 if (ok)
1278 ok = decode_guest_config1(c);
1279 if (ok)
1280 ok = decode_guest_config2(c);
1281 if (ok)
1282 ok = decode_guest_config3(c);
1283 if (ok)
1284 ok = decode_guest_config4(c);
1285 if (ok)
1286 decode_guest_config5(c);
1287}
1288
1289static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
1290{
1291 unsigned int guestctl0, temp;
1292
1293 guestctl0 = read_c0_guestctl0();
1294
1295 if (guestctl0 & MIPS_GCTL0_G0E)
1296 c->options |= MIPS_CPU_GUESTCTL0EXT;
1297 if (guestctl0 & MIPS_GCTL0_G1)
1298 c->options |= MIPS_CPU_GUESTCTL1;
1299 if (guestctl0 & MIPS_GCTL0_G2)
1300 c->options |= MIPS_CPU_GUESTCTL2;
1301 if (!(guestctl0 & MIPS_GCTL0_RAD)) {
1302 c->options |= MIPS_CPU_GUESTID;
1303
1304 /*
1305 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
1306 * first, otherwise all data accesses will be fully virtualised
1307 * as if they were performed by guest mode.
1308 */
1309 write_c0_guestctl1(0);
1310 tlbw_use_hazard();
1311
1312 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
1313 back_to_back_c0_hazard();
1314 temp = read_c0_guestctl0();
1315
1316 if (temp & MIPS_GCTL0_DRG) {
1317 write_c0_guestctl0(guestctl0);
1318 c->options |= MIPS_CPU_DRG;
1319 }
1320 }
1321}
1322
1323static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1324{
1325 if (cpu_has_guestid) {
1326 /* determine the number of bits of GuestID available */
1327 write_c0_guestctl1(MIPS_GCTL1_ID);
1328 back_to_back_c0_hazard();
1329 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1330 >> MIPS_GCTL1_ID_SHIFT;
1331 write_c0_guestctl1(0);
1332 }
1333}
1334
1335static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1336{
1337 /* determine the number of bits of GTOffset available */
1338 write_c0_gtoffset(0xffffffff);
1339 back_to_back_c0_hazard();
1340 c->gtoffset_mask = read_c0_gtoffset();
1341 write_c0_gtoffset(0);
1342}
1343
1344static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1345{
1346 cpu_probe_guestctl0(c);
1347 if (cpu_has_guestctl1)
1348 cpu_probe_guestctl1(c);
1349
1350 cpu_probe_gtoffset(c);
1351
1352 decode_guest_configs(c);
1353}
1354
1355#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1356 | MIPS_CPU_COUNTER)
1357
1358static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1359{
1360 switch (c->processor_id & PRID_IMP_MASK) {
1361 case PRID_IMP_R2000:
1362 c->cputype = CPU_R2000;
1363 __cpu_name[cpu] = "R2000";
1364 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1365 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1366 MIPS_CPU_NOFPUEX;
1367 if (__cpu_has_fpu())
1368 c->options |= MIPS_CPU_FPU;
1369 c->tlbsize = 64;
1370 break;
1371 case PRID_IMP_R3000:
1372 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
1373 if (cpu_has_confreg()) {
1374 c->cputype = CPU_R3081E;
1375 __cpu_name[cpu] = "R3081";
1376 } else {
1377 c->cputype = CPU_R3000A;
1378 __cpu_name[cpu] = "R3000A";
1379 }
1380 } else {
1381 c->cputype = CPU_R3000;
1382 __cpu_name[cpu] = "R3000";
1383 }
1384 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1385 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1386 MIPS_CPU_NOFPUEX;
1387 if (__cpu_has_fpu())
1388 c->options |= MIPS_CPU_FPU;
1389 c->tlbsize = 64;
1390 break;
1391 case PRID_IMP_R4000:
1392 if (read_c0_config() & CONF_SC) {
1393 if ((c->processor_id & PRID_REV_MASK) >=
1394 PRID_REV_R4400) {
1395 c->cputype = CPU_R4400PC;
1396 __cpu_name[cpu] = "R4400PC";
1397 } else {
1398 c->cputype = CPU_R4000PC;
1399 __cpu_name[cpu] = "R4000PC";
1400 }
1401 } else {
1402 int cca = read_c0_config() & CONF_CM_CMASK;
1403 int mc;
1404
1405 /*
1406 * SC and MC versions can't be reliably told apart,
1407 * but only the latter support coherent caching
1408 * modes so assume the firmware has set the KSEG0
1409 * coherency attribute reasonably (if uncached, we
1410 * assume SC).
1411 */
1412 switch (cca) {
1413 case CONF_CM_CACHABLE_CE:
1414 case CONF_CM_CACHABLE_COW:
1415 case CONF_CM_CACHABLE_CUW:
1416 mc = 1;
1417 break;
1418 default:
1419 mc = 0;
1420 break;
1421 }
1422 if ((c->processor_id & PRID_REV_MASK) >=
1423 PRID_REV_R4400) {
1424 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1425 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
1426 } else {
1427 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1428 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
1429 }
1430 }
1431
1432 set_isa(c, MIPS_CPU_ISA_III);
1433 c->fpu_msk31 |= FPU_CSR_CONDX;
1434 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1435 MIPS_CPU_WATCH | MIPS_CPU_VCE |
1436 MIPS_CPU_LLSC;
1437 c->tlbsize = 48;
1438 break;
1439 case PRID_IMP_VR41XX:
1440 set_isa(c, MIPS_CPU_ISA_III);
1441 c->fpu_msk31 |= FPU_CSR_CONDX;
1442 c->options = R4K_OPTS;
1443 c->tlbsize = 32;
1444 switch (c->processor_id & 0xf0) {
1445 case PRID_REV_VR4111:
1446 c->cputype = CPU_VR4111;
1447 __cpu_name[cpu] = "NEC VR4111";
1448 break;
1449 case PRID_REV_VR4121:
1450 c->cputype = CPU_VR4121;
1451 __cpu_name[cpu] = "NEC VR4121";
1452 break;
1453 case PRID_REV_VR4122:
1454 if ((c->processor_id & 0xf) < 0x3) {
1455 c->cputype = CPU_VR4122;
1456 __cpu_name[cpu] = "NEC VR4122";
1457 } else {
1458 c->cputype = CPU_VR4181A;
1459 __cpu_name[cpu] = "NEC VR4181A";
1460 }
1461 break;
1462 case PRID_REV_VR4130:
1463 if ((c->processor_id & 0xf) < 0x4) {
1464 c->cputype = CPU_VR4131;
1465 __cpu_name[cpu] = "NEC VR4131";
1466 } else {
1467 c->cputype = CPU_VR4133;
1468 c->options |= MIPS_CPU_LLSC;
1469 __cpu_name[cpu] = "NEC VR4133";
1470 }
1471 break;
1472 default:
1473 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
1474 c->cputype = CPU_VR41XX;
1475 __cpu_name[cpu] = "NEC Vr41xx";
1476 break;
1477 }
1478 break;
1479 case PRID_IMP_R4600:
1480 c->cputype = CPU_R4600;
1481 __cpu_name[cpu] = "R4600";
1482 set_isa(c, MIPS_CPU_ISA_III);
1483 c->fpu_msk31 |= FPU_CSR_CONDX;
1484 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1485 MIPS_CPU_LLSC;
1486 c->tlbsize = 48;
1487 break;
1488 #if 0
1489 case PRID_IMP_R4650:
1490 /*
1491 * This processor doesn't have an MMU, so it's not
1492 * "real easy" to run Linux on it. It is left purely
1493 * for documentation. Commented out because it shares
1494 * it's c0_prid id number with the TX3900.
1495 */
1496 c->cputype = CPU_R4650;
1497 __cpu_name[cpu] = "R4650";
1498 set_isa(c, MIPS_CPU_ISA_III);
1499 c->fpu_msk31 |= FPU_CSR_CONDX;
1500 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1501 c->tlbsize = 48;
1502 break;
1503 #endif
1504 case PRID_IMP_TX39:
1505 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1506 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1507
1508 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1509 c->cputype = CPU_TX3927;
1510 __cpu_name[cpu] = "TX3927";
1511 c->tlbsize = 64;
1512 } else {
1513 switch (c->processor_id & PRID_REV_MASK) {
1514 case PRID_REV_TX3912:
1515 c->cputype = CPU_TX3912;
1516 __cpu_name[cpu] = "TX3912";
1517 c->tlbsize = 32;
1518 break;
1519 case PRID_REV_TX3922:
1520 c->cputype = CPU_TX3922;
1521 __cpu_name[cpu] = "TX3922";
1522 c->tlbsize = 64;
1523 break;
1524 }
1525 }
1526 break;
1527 case PRID_IMP_R4700:
1528 c->cputype = CPU_R4700;
1529 __cpu_name[cpu] = "R4700";
1530 set_isa(c, MIPS_CPU_ISA_III);
1531 c->fpu_msk31 |= FPU_CSR_CONDX;
1532 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1533 MIPS_CPU_LLSC;
1534 c->tlbsize = 48;
1535 break;
1536 case PRID_IMP_TX49:
1537 c->cputype = CPU_TX49XX;
1538 __cpu_name[cpu] = "R49XX";
1539 set_isa(c, MIPS_CPU_ISA_III);
1540 c->fpu_msk31 |= FPU_CSR_CONDX;
1541 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1542 if (!(c->processor_id & 0x08))
1543 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1544 c->tlbsize = 48;
1545 break;
1546 case PRID_IMP_R5000:
1547 c->cputype = CPU_R5000;
1548 __cpu_name[cpu] = "R5000";
1549 set_isa(c, MIPS_CPU_ISA_IV);
1550 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1551 MIPS_CPU_LLSC;
1552 c->tlbsize = 48;
1553 break;
1554 case PRID_IMP_R5500:
1555 c->cputype = CPU_R5500;
1556 __cpu_name[cpu] = "R5500";
1557 set_isa(c, MIPS_CPU_ISA_IV);
1558 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1559 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1560 c->tlbsize = 48;
1561 break;
1562 case PRID_IMP_NEVADA:
1563 c->cputype = CPU_NEVADA;
1564 __cpu_name[cpu] = "Nevada";
1565 set_isa(c, MIPS_CPU_ISA_IV);
1566 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1567 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1568 c->tlbsize = 48;
1569 break;
1570 case PRID_IMP_RM7000:
1571 c->cputype = CPU_RM7000;
1572 __cpu_name[cpu] = "RM7000";
1573 set_isa(c, MIPS_CPU_ISA_IV);
1574 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1575 MIPS_CPU_LLSC;
1576 /*
1577 * Undocumented RM7000: Bit 29 in the info register of
1578 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1579 * entries.
1580 *
1581 * 29 1 => 64 entry JTLB
1582 * 0 => 48 entry JTLB
1583 */
1584 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1585 break;
1586 case PRID_IMP_R10000:
1587 c->cputype = CPU_R10000;
1588 __cpu_name[cpu] = "R10000";
1589 set_isa(c, MIPS_CPU_ISA_IV);
1590 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1591 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1592 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1593 MIPS_CPU_LLSC;
1594 c->tlbsize = 64;
1595 break;
1596 case PRID_IMP_R12000:
1597 c->cputype = CPU_R12000;
1598 __cpu_name[cpu] = "R12000";
1599 set_isa(c, MIPS_CPU_ISA_IV);
1600 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1601 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1602 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1603 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1604 c->tlbsize = 64;
1605 break;
1606 case PRID_IMP_R14000:
1607 if (((c->processor_id >> 4) & 0x0f) > 2) {
1608 c->cputype = CPU_R16000;
1609 __cpu_name[cpu] = "R16000";
1610 } else {
1611 c->cputype = CPU_R14000;
1612 __cpu_name[cpu] = "R14000";
1613 }
1614 set_isa(c, MIPS_CPU_ISA_IV);
1615 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1616 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1617 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1618 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1619 c->tlbsize = 64;
1620 break;
1621 case PRID_IMP_LOONGSON_64C: /* Loongson-2/3 */
1622 switch (c->processor_id & PRID_REV_MASK) {
1623 case PRID_REV_LOONGSON2E:
1624 c->cputype = CPU_LOONGSON2EF;
1625 __cpu_name[cpu] = "ICT Loongson-2";
1626 set_elf_platform(cpu, "loongson2e");
1627 set_isa(c, MIPS_CPU_ISA_III);
1628 c->fpu_msk31 |= FPU_CSR_CONDX;
1629 break;
1630 case PRID_REV_LOONGSON2F:
1631 c->cputype = CPU_LOONGSON2EF;
1632 __cpu_name[cpu] = "ICT Loongson-2";
1633 set_elf_platform(cpu, "loongson2f");
1634 set_isa(c, MIPS_CPU_ISA_III);
1635 c->fpu_msk31 |= FPU_CSR_CONDX;
1636 break;
1637 case PRID_REV_LOONGSON3A_R1:
1638 c->cputype = CPU_LOONGSON64;
1639 __cpu_name[cpu] = "ICT Loongson-3";
1640 set_elf_platform(cpu, "loongson3a");
1641 set_isa(c, MIPS_CPU_ISA_M64R1);
1642 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1643 MIPS_ASE_LOONGSON_EXT);
1644 break;
1645 case PRID_REV_LOONGSON3B_R1:
1646 case PRID_REV_LOONGSON3B_R2:
1647 c->cputype = CPU_LOONGSON64;
1648 __cpu_name[cpu] = "ICT Loongson-3";
1649 set_elf_platform(cpu, "loongson3b");
1650 set_isa(c, MIPS_CPU_ISA_M64R1);
1651 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1652 MIPS_ASE_LOONGSON_EXT);
1653 break;
1654 }
1655
1656 c->options = R4K_OPTS |
1657 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1658 MIPS_CPU_32FPR;
1659 c->tlbsize = 64;
1660 set_cpu_asid_mask(c, MIPS_ENTRYHI_ASID);
1661 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1662 break;
1663 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1664 decode_configs(c);
1665
1666 c->cputype = CPU_LOONGSON32;
1667
1668 switch (c->processor_id & PRID_REV_MASK) {
1669 case PRID_REV_LOONGSON1B:
1670 __cpu_name[cpu] = "Loongson 1B";
1671 break;
1672 }
1673
1674 break;
1675 }
1676}
1677
1678static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1679{
1680 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1681 switch (c->processor_id & PRID_IMP_MASK) {
1682 case PRID_IMP_QEMU_GENERIC:
1683 c->writecombine = _CACHE_UNCACHED;
1684 c->cputype = CPU_QEMU_GENERIC;
1685 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1686 break;
1687 case PRID_IMP_4KC:
1688 c->cputype = CPU_4KC;
1689 c->writecombine = _CACHE_UNCACHED;
1690 __cpu_name[cpu] = "MIPS 4Kc";
1691 break;
1692 case PRID_IMP_4KEC:
1693 case PRID_IMP_4KECR2:
1694 c->cputype = CPU_4KEC;
1695 c->writecombine = _CACHE_UNCACHED;
1696 __cpu_name[cpu] = "MIPS 4KEc";
1697 break;
1698 case PRID_IMP_4KSC:
1699 case PRID_IMP_4KSD:
1700 c->cputype = CPU_4KSC;
1701 c->writecombine = _CACHE_UNCACHED;
1702 __cpu_name[cpu] = "MIPS 4KSc";
1703 break;
1704 case PRID_IMP_5KC:
1705 c->cputype = CPU_5KC;
1706 c->writecombine = _CACHE_UNCACHED;
1707 __cpu_name[cpu] = "MIPS 5Kc";
1708 break;
1709 case PRID_IMP_5KE:
1710 c->cputype = CPU_5KE;
1711 c->writecombine = _CACHE_UNCACHED;
1712 __cpu_name[cpu] = "MIPS 5KE";
1713 break;
1714 case PRID_IMP_20KC:
1715 c->cputype = CPU_20KC;
1716 c->writecombine = _CACHE_UNCACHED;
1717 __cpu_name[cpu] = "MIPS 20Kc";
1718 break;
1719 case PRID_IMP_24K:
1720 c->cputype = CPU_24K;
1721 c->writecombine = _CACHE_UNCACHED;
1722 __cpu_name[cpu] = "MIPS 24Kc";
1723 break;
1724 case PRID_IMP_24KE:
1725 c->cputype = CPU_24K;
1726 c->writecombine = _CACHE_UNCACHED;
1727 __cpu_name[cpu] = "MIPS 24KEc";
1728 break;
1729 case PRID_IMP_25KF:
1730 c->cputype = CPU_25KF;
1731 c->writecombine = _CACHE_UNCACHED;
1732 __cpu_name[cpu] = "MIPS 25Kc";
1733 break;
1734 case PRID_IMP_34K:
1735 c->cputype = CPU_34K;
1736 c->writecombine = _CACHE_UNCACHED;
1737 __cpu_name[cpu] = "MIPS 34Kc";
1738 cpu_set_mt_per_tc_perf(c);
1739 break;
1740 case PRID_IMP_74K:
1741 c->cputype = CPU_74K;
1742 c->writecombine = _CACHE_UNCACHED;
1743 __cpu_name[cpu] = "MIPS 74Kc";
1744 break;
1745 case PRID_IMP_M14KC:
1746 c->cputype = CPU_M14KC;
1747 c->writecombine = _CACHE_UNCACHED;
1748 __cpu_name[cpu] = "MIPS M14Kc";
1749 break;
1750 case PRID_IMP_M14KEC:
1751 c->cputype = CPU_M14KEC;
1752 c->writecombine = _CACHE_UNCACHED;
1753 __cpu_name[cpu] = "MIPS M14KEc";
1754 break;
1755 case PRID_IMP_1004K:
1756 c->cputype = CPU_1004K;
1757 c->writecombine = _CACHE_UNCACHED;
1758 __cpu_name[cpu] = "MIPS 1004Kc";
1759 cpu_set_mt_per_tc_perf(c);
1760 break;
1761 case PRID_IMP_1074K:
1762 c->cputype = CPU_1074K;
1763 c->writecombine = _CACHE_UNCACHED;
1764 __cpu_name[cpu] = "MIPS 1074Kc";
1765 break;
1766 case PRID_IMP_INTERAPTIV_UP:
1767 c->cputype = CPU_INTERAPTIV;
1768 __cpu_name[cpu] = "MIPS interAptiv";
1769 cpu_set_mt_per_tc_perf(c);
1770 break;
1771 case PRID_IMP_INTERAPTIV_MP:
1772 c->cputype = CPU_INTERAPTIV;
1773 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1774 cpu_set_mt_per_tc_perf(c);
1775 break;
1776 case PRID_IMP_PROAPTIV_UP:
1777 c->cputype = CPU_PROAPTIV;
1778 __cpu_name[cpu] = "MIPS proAptiv";
1779 break;
1780 case PRID_IMP_PROAPTIV_MP:
1781 c->cputype = CPU_PROAPTIV;
1782 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1783 break;
1784 case PRID_IMP_P5600:
1785 c->cputype = CPU_P5600;
1786 __cpu_name[cpu] = "MIPS P5600";
1787 break;
1788 case PRID_IMP_P6600:
1789 c->cputype = CPU_P6600;
1790 __cpu_name[cpu] = "MIPS P6600";
1791 break;
1792 case PRID_IMP_I6400:
1793 c->cputype = CPU_I6400;
1794 __cpu_name[cpu] = "MIPS I6400";
1795 break;
1796 case PRID_IMP_I6500:
1797 c->cputype = CPU_I6500;
1798 __cpu_name[cpu] = "MIPS I6500";
1799 break;
1800 case PRID_IMP_M5150:
1801 c->cputype = CPU_M5150;
1802 __cpu_name[cpu] = "MIPS M5150";
1803 break;
1804 case PRID_IMP_M6250:
1805 c->cputype = CPU_M6250;
1806 __cpu_name[cpu] = "MIPS M6250";
1807 break;
1808 }
1809
1810 decode_configs(c);
1811
1812 spram_config();
1813
1814 mm_config(c);
1815
1816 switch (__get_cpu_type(c->cputype)) {
1817 case CPU_M5150:
1818 case CPU_P5600:
1819 set_isa(c, MIPS_CPU_ISA_M32R5);
1820 break;
1821 case CPU_I6500:
1822 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES;
1823 fallthrough;
1824 case CPU_I6400:
1825 c->options |= MIPS_CPU_SHARED_FTLB_RAM;
1826 fallthrough;
1827 default:
1828 break;
1829 }
1830
1831 /* Recent MIPS cores use the implementation-dependent ExcCode 16 for
1832 * cache/FTLB parity exceptions.
1833 */
1834 switch (__get_cpu_type(c->cputype)) {
1835 case CPU_PROAPTIV:
1836 case CPU_P5600:
1837 case CPU_P6600:
1838 case CPU_I6400:
1839 case CPU_I6500:
1840 c->options |= MIPS_CPU_FTLBPAREX;
1841 break;
1842 }
1843}
1844
1845static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1846{
1847 decode_configs(c);
1848 switch (c->processor_id & PRID_IMP_MASK) {
1849 case PRID_IMP_AU1_REV1:
1850 case PRID_IMP_AU1_REV2:
1851 c->cputype = CPU_ALCHEMY;
1852 switch ((c->processor_id >> 24) & 0xff) {
1853 case 0:
1854 __cpu_name[cpu] = "Au1000";
1855 break;
1856 case 1:
1857 __cpu_name[cpu] = "Au1500";
1858 break;
1859 case 2:
1860 __cpu_name[cpu] = "Au1100";
1861 break;
1862 case 3:
1863 __cpu_name[cpu] = "Au1550";
1864 break;
1865 case 4:
1866 __cpu_name[cpu] = "Au1200";
1867 if ((c->processor_id & PRID_REV_MASK) == 2)
1868 __cpu_name[cpu] = "Au1250";
1869 break;
1870 case 5:
1871 __cpu_name[cpu] = "Au1210";
1872 break;
1873 default:
1874 __cpu_name[cpu] = "Au1xxx";
1875 break;
1876 }
1877 break;
1878 }
1879}
1880
1881static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1882{
1883 decode_configs(c);
1884
1885 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1886 switch (c->processor_id & PRID_IMP_MASK) {
1887 case PRID_IMP_SB1:
1888 c->cputype = CPU_SB1;
1889 __cpu_name[cpu] = "SiByte SB1";
1890 /* FPU in pass1 is known to have issues. */
1891 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1892 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1893 break;
1894 case PRID_IMP_SB1A:
1895 c->cputype = CPU_SB1A;
1896 __cpu_name[cpu] = "SiByte SB1A";
1897 break;
1898 }
1899}
1900
1901static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1902{
1903 decode_configs(c);
1904 switch (c->processor_id & PRID_IMP_MASK) {
1905 case PRID_IMP_SR71000:
1906 c->cputype = CPU_SR71000;
1907 __cpu_name[cpu] = "Sandcraft SR71000";
1908 c->scache.ways = 8;
1909 c->tlbsize = 64;
1910 break;
1911 }
1912}
1913
1914static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1915{
1916 decode_configs(c);
1917 switch (c->processor_id & PRID_IMP_MASK) {
1918 case PRID_IMP_PR4450:
1919 c->cputype = CPU_PR4450;
1920 __cpu_name[cpu] = "Philips PR4450";
1921 set_isa(c, MIPS_CPU_ISA_M32R1);
1922 break;
1923 }
1924}
1925
1926static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1927{
1928 decode_configs(c);
1929 switch (c->processor_id & PRID_IMP_MASK) {
1930 case PRID_IMP_BMIPS32_REV4:
1931 case PRID_IMP_BMIPS32_REV8:
1932 c->cputype = CPU_BMIPS32;
1933 __cpu_name[cpu] = "Broadcom BMIPS32";
1934 set_elf_platform(cpu, "bmips32");
1935 break;
1936 case PRID_IMP_BMIPS3300:
1937 case PRID_IMP_BMIPS3300_ALT:
1938 case PRID_IMP_BMIPS3300_BUG:
1939 c->cputype = CPU_BMIPS3300;
1940 __cpu_name[cpu] = "Broadcom BMIPS3300";
1941 set_elf_platform(cpu, "bmips3300");
1942 break;
1943 case PRID_IMP_BMIPS43XX: {
1944 int rev = c->processor_id & PRID_REV_MASK;
1945
1946 if (rev >= PRID_REV_BMIPS4380_LO &&
1947 rev <= PRID_REV_BMIPS4380_HI) {
1948 c->cputype = CPU_BMIPS4380;
1949 __cpu_name[cpu] = "Broadcom BMIPS4380";
1950 set_elf_platform(cpu, "bmips4380");
1951 c->options |= MIPS_CPU_RIXI;
1952 } else {
1953 c->cputype = CPU_BMIPS4350;
1954 __cpu_name[cpu] = "Broadcom BMIPS4350";
1955 set_elf_platform(cpu, "bmips4350");
1956 }
1957 break;
1958 }
1959 case PRID_IMP_BMIPS5000:
1960 case PRID_IMP_BMIPS5200:
1961 c->cputype = CPU_BMIPS5000;
1962 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1963 __cpu_name[cpu] = "Broadcom BMIPS5200";
1964 else
1965 __cpu_name[cpu] = "Broadcom BMIPS5000";
1966 set_elf_platform(cpu, "bmips5000");
1967 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
1968 break;
1969 }
1970}
1971
1972static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1973{
1974 decode_configs(c);
1975 switch (c->processor_id & PRID_IMP_MASK) {
1976 case PRID_IMP_CAVIUM_CN38XX:
1977 case PRID_IMP_CAVIUM_CN31XX:
1978 case PRID_IMP_CAVIUM_CN30XX:
1979 c->cputype = CPU_CAVIUM_OCTEON;
1980 __cpu_name[cpu] = "Cavium Octeon";
1981 goto platform;
1982 case PRID_IMP_CAVIUM_CN58XX:
1983 case PRID_IMP_CAVIUM_CN56XX:
1984 case PRID_IMP_CAVIUM_CN50XX:
1985 case PRID_IMP_CAVIUM_CN52XX:
1986 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1987 __cpu_name[cpu] = "Cavium Octeon+";
1988platform:
1989 set_elf_platform(cpu, "octeon");
1990 break;
1991 case PRID_IMP_CAVIUM_CN61XX:
1992 case PRID_IMP_CAVIUM_CN63XX:
1993 case PRID_IMP_CAVIUM_CN66XX:
1994 case PRID_IMP_CAVIUM_CN68XX:
1995 case PRID_IMP_CAVIUM_CNF71XX:
1996 c->cputype = CPU_CAVIUM_OCTEON2;
1997 __cpu_name[cpu] = "Cavium Octeon II";
1998 set_elf_platform(cpu, "octeon2");
1999 break;
2000 case PRID_IMP_CAVIUM_CN70XX:
2001 case PRID_IMP_CAVIUM_CN73XX:
2002 case PRID_IMP_CAVIUM_CNF75XX:
2003 case PRID_IMP_CAVIUM_CN78XX:
2004 c->cputype = CPU_CAVIUM_OCTEON3;
2005 __cpu_name[cpu] = "Cavium Octeon III";
2006 set_elf_platform(cpu, "octeon3");
2007 break;
2008 default:
2009 printk(KERN_INFO "Unknown Octeon chip!\n");
2010 c->cputype = CPU_UNKNOWN;
2011 break;
2012 }
2013}
2014
2015#ifdef CONFIG_CPU_LOONGSON64
2016#include <loongson_regs.h>
2017
2018static inline void decode_cpucfg(struct cpuinfo_mips *c)
2019{
2020 u32 cfg1 = read_cpucfg(LOONGSON_CFG1);
2021 u32 cfg2 = read_cpucfg(LOONGSON_CFG2);
2022 u32 cfg3 = read_cpucfg(LOONGSON_CFG3);
2023
2024 if (cfg1 & LOONGSON_CFG1_MMI)
2025 c->ases |= MIPS_ASE_LOONGSON_MMI;
2026
2027 if (cfg2 & LOONGSON_CFG2_LEXT1)
2028 c->ases |= MIPS_ASE_LOONGSON_EXT;
2029
2030 if (cfg2 & LOONGSON_CFG2_LEXT2)
2031 c->ases |= MIPS_ASE_LOONGSON_EXT2;
2032
2033 if (cfg2 & LOONGSON_CFG2_LSPW) {
2034 c->options |= MIPS_CPU_LDPTE;
2035 c->guest.options |= MIPS_CPU_LDPTE;
2036 }
2037
2038 if (cfg3 & LOONGSON_CFG3_LCAMP)
2039 c->ases |= MIPS_ASE_LOONGSON_CAM;
2040}
2041
2042static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
2043{
2044 decode_configs(c);
2045
2046 /* All Loongson processors covered here define ExcCode 16 as GSExc. */
2047 c->options |= MIPS_CPU_GSEXCEX;
2048
2049 switch (c->processor_id & PRID_IMP_MASK) {
2050 case PRID_IMP_LOONGSON_64R: /* Loongson-64 Reduced */
2051 switch (c->processor_id & PRID_REV_MASK) {
2052 case PRID_REV_LOONGSON2K_R1_0:
2053 case PRID_REV_LOONGSON2K_R1_1:
2054 case PRID_REV_LOONGSON2K_R1_2:
2055 case PRID_REV_LOONGSON2K_R1_3:
2056 c->cputype = CPU_LOONGSON64;
2057 __cpu_name[cpu] = "Loongson-2K";
2058 set_elf_platform(cpu, "gs264e");
2059 set_isa(c, MIPS_CPU_ISA_M64R2);
2060 break;
2061 }
2062 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2063 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_EXT |
2064 MIPS_ASE_LOONGSON_EXT2);
2065 break;
2066 case PRID_IMP_LOONGSON_64C: /* Loongson-3 Classic */
2067 switch (c->processor_id & PRID_REV_MASK) {
2068 case PRID_REV_LOONGSON3A_R2_0:
2069 case PRID_REV_LOONGSON3A_R2_1:
2070 c->cputype = CPU_LOONGSON64;
2071 __cpu_name[cpu] = "ICT Loongson-3";
2072 set_elf_platform(cpu, "loongson3a");
2073 set_isa(c, MIPS_CPU_ISA_M64R2);
2074 break;
2075 case PRID_REV_LOONGSON3A_R3_0:
2076 case PRID_REV_LOONGSON3A_R3_1:
2077 c->cputype = CPU_LOONGSON64;
2078 __cpu_name[cpu] = "ICT Loongson-3";
2079 set_elf_platform(cpu, "loongson3a");
2080 set_isa(c, MIPS_CPU_ISA_M64R2);
2081 break;
2082 }
2083 /*
2084 * Loongson-3 Classic did not implement MIPS standard TLBINV
2085 * but implemented TLBINVF and EHINV. As currently we're only
2086 * using these two features, enable MIPS_CPU_TLBINV as well.
2087 *
2088 * Also some early Loongson-3A2000 had wrong TLB type in Config
2089 * register, we correct it here.
2090 */
2091 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
2092 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2093 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
2094 MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
2095 c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */
2096 break;
2097 case PRID_IMP_LOONGSON_64G:
2098 c->cputype = CPU_LOONGSON64;
2099 __cpu_name[cpu] = "ICT Loongson-3";
2100 set_elf_platform(cpu, "loongson3a");
2101 set_isa(c, MIPS_CPU_ISA_M64R2);
2102 decode_cpucfg(c);
2103 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2104 break;
2105 default:
2106 panic("Unknown Loongson Processor ID!");
2107 break;
2108 }
2109}
2110#else
2111static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { }
2112#endif
2113
2114static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
2115{
2116 decode_configs(c);
2117
2118 /*
2119 * XBurst misses a config2 register, so config3 decode was skipped in
2120 * decode_configs().
2121 */
2122 decode_config3(c);
2123
2124 /* XBurst does not implement the CP0 counter. */
2125 c->options &= ~MIPS_CPU_COUNTER;
2126 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
2127
2128 switch (c->processor_id & PRID_IMP_MASK) {
2129
2130 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
2131 case PRID_IMP_XBURST_REV1:
2132
2133 /*
2134 * The XBurst core by default attempts to avoid branch target
2135 * buffer lookups by detecting & special casing loops. This
2136 * feature will cause BogoMIPS and lpj calculate in error.
2137 * Set cp0 config7 bit 4 to disable this feature.
2138 */
2139 set_c0_config7(MIPS_CONF7_BTB_LOOP_EN);
2140
2141 switch (c->processor_id & PRID_COMP_MASK) {
2142
2143 /*
2144 * The config0 register in the XBurst CPUs with a processor ID of
2145 * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
2146 * but they don't actually support this ISA.
2147 */
2148 case PRID_COMP_INGENIC_D0:
2149 c->isa_level &= ~MIPS_CPU_ISA_M32R2;
2150 break;
2151
2152 /*
2153 * The config0 register in the XBurst CPUs with a processor ID of
2154 * PRID_COMP_INGENIC_D1 has an abandoned huge page tlb mode, this
2155 * mode is not compatible with the MIPS standard, it will cause
2156 * tlbmiss and into an infinite loop (line 21 in the tlb-funcs.S)
2157 * when starting the init process. After chip reset, the default
2158 * is HPTLB mode, Write 0xa9000000 to cp0 register 5 sel 4 to
2159 * switch back to VTLB mode to prevent getting stuck.
2160 */
2161 case PRID_COMP_INGENIC_D1:
2162 write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS);
2163 break;
2164
2165 default:
2166 break;
2167 }
2168 fallthrough;
2169
2170 /* XBurst®1 with MXU2.0 SIMD ISA */
2171 case PRID_IMP_XBURST_REV2:
2172 c->cputype = CPU_XBURST;
2173 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2174 __cpu_name[cpu] = "Ingenic XBurst";
2175 break;
2176
2177 /* XBurst®2 with MXU2.1 SIMD ISA */
2178 case PRID_IMP_XBURST2:
2179 c->cputype = CPU_XBURST;
2180 __cpu_name[cpu] = "Ingenic XBurst II";
2181 break;
2182
2183 default:
2184 panic("Unknown Ingenic Processor ID!");
2185 break;
2186 }
2187}
2188
2189static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
2190{
2191 decode_configs(c);
2192
2193 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
2194 c->cputype = CPU_ALCHEMY;
2195 __cpu_name[cpu] = "Au1300";
2196 /* following stuff is not for Alchemy */
2197 return;
2198 }
2199
2200 c->options = (MIPS_CPU_TLB |
2201 MIPS_CPU_4KEX |
2202 MIPS_CPU_COUNTER |
2203 MIPS_CPU_DIVEC |
2204 MIPS_CPU_WATCH |
2205 MIPS_CPU_EJTAG |
2206 MIPS_CPU_LLSC);
2207
2208 switch (c->processor_id & PRID_IMP_MASK) {
2209 case PRID_IMP_NETLOGIC_XLP2XX:
2210 case PRID_IMP_NETLOGIC_XLP9XX:
2211 case PRID_IMP_NETLOGIC_XLP5XX:
2212 c->cputype = CPU_XLP;
2213 __cpu_name[cpu] = "Broadcom XLPII";
2214 break;
2215
2216 case PRID_IMP_NETLOGIC_XLP8XX:
2217 case PRID_IMP_NETLOGIC_XLP3XX:
2218 c->cputype = CPU_XLP;
2219 __cpu_name[cpu] = "Netlogic XLP";
2220 break;
2221
2222 case PRID_IMP_NETLOGIC_XLR732:
2223 case PRID_IMP_NETLOGIC_XLR716:
2224 case PRID_IMP_NETLOGIC_XLR532:
2225 case PRID_IMP_NETLOGIC_XLR308:
2226 case PRID_IMP_NETLOGIC_XLR532C:
2227 case PRID_IMP_NETLOGIC_XLR516C:
2228 case PRID_IMP_NETLOGIC_XLR508C:
2229 case PRID_IMP_NETLOGIC_XLR308C:
2230 c->cputype = CPU_XLR;
2231 __cpu_name[cpu] = "Netlogic XLR";
2232 break;
2233
2234 case PRID_IMP_NETLOGIC_XLS608:
2235 case PRID_IMP_NETLOGIC_XLS408:
2236 case PRID_IMP_NETLOGIC_XLS404:
2237 case PRID_IMP_NETLOGIC_XLS208:
2238 case PRID_IMP_NETLOGIC_XLS204:
2239 case PRID_IMP_NETLOGIC_XLS108:
2240 case PRID_IMP_NETLOGIC_XLS104:
2241 case PRID_IMP_NETLOGIC_XLS616B:
2242 case PRID_IMP_NETLOGIC_XLS608B:
2243 case PRID_IMP_NETLOGIC_XLS416B:
2244 case PRID_IMP_NETLOGIC_XLS412B:
2245 case PRID_IMP_NETLOGIC_XLS408B:
2246 case PRID_IMP_NETLOGIC_XLS404B:
2247 c->cputype = CPU_XLR;
2248 __cpu_name[cpu] = "Netlogic XLS";
2249 break;
2250
2251 default:
2252 pr_info("Unknown Netlogic chip id [%02x]!\n",
2253 c->processor_id);
2254 c->cputype = CPU_XLR;
2255 break;
2256 }
2257
2258 if (c->cputype == CPU_XLP) {
2259 set_isa(c, MIPS_CPU_ISA_M64R2);
2260 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
2261 /* This will be updated again after all threads are woken up */
2262 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
2263 } else {
2264 set_isa(c, MIPS_CPU_ISA_M64R1);
2265 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
2266 }
2267 c->kscratch_mask = 0xf;
2268}
2269
2270#ifdef CONFIG_64BIT
2271/* For use by uaccess.h */
2272u64 __ua_limit;
2273EXPORT_SYMBOL(__ua_limit);
2274#endif
2275
2276const char *__cpu_name[NR_CPUS];
2277const char *__elf_platform;
2278const char *__elf_base_platform;
2279
2280void cpu_probe(void)
2281{
2282 struct cpuinfo_mips *c = ¤t_cpu_data;
2283 unsigned int cpu = smp_processor_id();
2284
2285 /*
2286 * Set a default elf platform, cpu probe may later
2287 * overwrite it with a more precise value
2288 */
2289 set_elf_platform(cpu, "mips");
2290
2291 c->processor_id = PRID_IMP_UNKNOWN;
2292 c->fpu_id = FPIR_IMP_NONE;
2293 c->cputype = CPU_UNKNOWN;
2294 c->writecombine = _CACHE_UNCACHED;
2295
2296 c->fpu_csr31 = FPU_CSR_RN;
2297 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
2298
2299 c->processor_id = read_c0_prid();
2300 switch (c->processor_id & PRID_COMP_MASK) {
2301 case PRID_COMP_LEGACY:
2302 cpu_probe_legacy(c, cpu);
2303 break;
2304 case PRID_COMP_MIPS:
2305 cpu_probe_mips(c, cpu);
2306 break;
2307 case PRID_COMP_ALCHEMY:
2308 cpu_probe_alchemy(c, cpu);
2309 break;
2310 case PRID_COMP_SIBYTE:
2311 cpu_probe_sibyte(c, cpu);
2312 break;
2313 case PRID_COMP_BROADCOM:
2314 cpu_probe_broadcom(c, cpu);
2315 break;
2316 case PRID_COMP_SANDCRAFT:
2317 cpu_probe_sandcraft(c, cpu);
2318 break;
2319 case PRID_COMP_NXP:
2320 cpu_probe_nxp(c, cpu);
2321 break;
2322 case PRID_COMP_CAVIUM:
2323 cpu_probe_cavium(c, cpu);
2324 break;
2325 case PRID_COMP_LOONGSON:
2326 cpu_probe_loongson(c, cpu);
2327 break;
2328 case PRID_COMP_INGENIC_13:
2329 case PRID_COMP_INGENIC_D0:
2330 case PRID_COMP_INGENIC_D1:
2331 case PRID_COMP_INGENIC_E1:
2332 cpu_probe_ingenic(c, cpu);
2333 break;
2334 case PRID_COMP_NETLOGIC:
2335 cpu_probe_netlogic(c, cpu);
2336 break;
2337 }
2338
2339 BUG_ON(!__cpu_name[cpu]);
2340 BUG_ON(c->cputype == CPU_UNKNOWN);
2341
2342 /*
2343 * Platform code can force the cpu type to optimize code
2344 * generation. In that case be sure the cpu type is correctly
2345 * manually setup otherwise it could trigger some nasty bugs.
2346 */
2347 BUG_ON(current_cpu_type() != c->cputype);
2348
2349 if (cpu_has_rixi) {
2350 /* Enable the RIXI exceptions */
2351 set_c0_pagegrain(PG_IEC);
2352 back_to_back_c0_hazard();
2353 /* Verify the IEC bit is set */
2354 if (read_c0_pagegrain() & PG_IEC)
2355 c->options |= MIPS_CPU_RIXIEX;
2356 }
2357
2358 if (mips_fpu_disabled)
2359 c->options &= ~MIPS_CPU_FPU;
2360
2361 if (mips_dsp_disabled)
2362 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
2363
2364 if (mips_htw_disabled) {
2365 c->options &= ~MIPS_CPU_HTW;
2366 write_c0_pwctl(read_c0_pwctl() &
2367 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
2368 }
2369
2370 if (c->options & MIPS_CPU_FPU)
2371 cpu_set_fpu_opts(c);
2372 else
2373 cpu_set_nofpu_opts(c);
2374
2375 if (cpu_has_bp_ghist)
2376 write_c0_r10k_diag(read_c0_r10k_diag() |
2377 R10K_DIAG_E_GHIST);
2378
2379 if (cpu_has_mips_r2_r6) {
2380 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
2381 /* R2 has Performance Counter Interrupt indicator */
2382 c->options |= MIPS_CPU_PCI;
2383 }
2384 else
2385 c->srsets = 1;
2386
2387 if (cpu_has_mips_r6)
2388 elf_hwcap |= HWCAP_MIPS_R6;
2389
2390 if (cpu_has_msa) {
2391 c->msa_id = cpu_get_msa_id();
2392 WARN(c->msa_id & MSA_IR_WRPF,
2393 "Vector register partitioning unimplemented!");
2394 elf_hwcap |= HWCAP_MIPS_MSA;
2395 }
2396
2397 if (cpu_has_mips16)
2398 elf_hwcap |= HWCAP_MIPS_MIPS16;
2399
2400 if (cpu_has_mdmx)
2401 elf_hwcap |= HWCAP_MIPS_MDMX;
2402
2403 if (cpu_has_mips3d)
2404 elf_hwcap |= HWCAP_MIPS_MIPS3D;
2405
2406 if (cpu_has_smartmips)
2407 elf_hwcap |= HWCAP_MIPS_SMARTMIPS;
2408
2409 if (cpu_has_dsp)
2410 elf_hwcap |= HWCAP_MIPS_DSP;
2411
2412 if (cpu_has_dsp2)
2413 elf_hwcap |= HWCAP_MIPS_DSP2;
2414
2415 if (cpu_has_dsp3)
2416 elf_hwcap |= HWCAP_MIPS_DSP3;
2417
2418 if (cpu_has_mips16e2)
2419 elf_hwcap |= HWCAP_MIPS_MIPS16E2;
2420
2421 if (cpu_has_loongson_mmi)
2422 elf_hwcap |= HWCAP_LOONGSON_MMI;
2423
2424 if (cpu_has_loongson_ext)
2425 elf_hwcap |= HWCAP_LOONGSON_EXT;
2426
2427 if (cpu_has_loongson_ext2)
2428 elf_hwcap |= HWCAP_LOONGSON_EXT2;
2429
2430 if (cpu_has_vz)
2431 cpu_probe_vz(c);
2432
2433 cpu_probe_vmbits(c);
2434
2435 /* Synthesize CPUCFG data if running on Loongson processors;
2436 * no-op otherwise.
2437 *
2438 * This looks at previously probed features, so keep this at bottom.
2439 */
2440 loongson3_cpucfg_synthesize_data(c);
2441
2442#ifdef CONFIG_64BIT
2443 if (cpu == 0)
2444 __ua_limit = ~((1ull << cpu_vmbits) - 1);
2445#endif
2446}
2447
2448void cpu_report(void)
2449{
2450 struct cpuinfo_mips *c = ¤t_cpu_data;
2451
2452 pr_info("CPU%d revision is: %08x (%s)\n",
2453 smp_processor_id(), c->processor_id, cpu_name_string());
2454 if (c->options & MIPS_CPU_FPU)
2455 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
2456 if (cpu_has_msa)
2457 pr_info("MSA revision is: %08x\n", c->msa_id);
2458}
2459
2460void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster)
2461{
2462 /* Ensure the core number fits in the field */
2463 WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >>
2464 MIPS_GLOBALNUMBER_CLUSTER_SHF));
2465
2466 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER;
2467 cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF;
2468}
2469
2470void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core)
2471{
2472 /* Ensure the core number fits in the field */
2473 WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF));
2474
2475 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE;
2476 cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF;
2477}
2478
2479void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe)
2480{
2481 /* Ensure the VP(E) ID fits in the field */
2482 WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF));
2483
2484 /* Ensure we're not using VP(E)s without support */
2485 WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) &&
2486 !IS_ENABLED(CONFIG_CPU_MIPSR6));
2487
2488 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP;
2489 cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF;
2490}