1// SPDX-License-Identifier: GPL-2.0
 2/*
 3 * Renesas USB driver RZ/A initialization and power control
 4 *
 5 * Copyright (C) 2018 Chris Brandt
 6 * Copyright (C) 2018-2019 Renesas Electronics Corporation
 7 */
 8
 9#include <linux/delay.h>
10#include <linux/io.h>
11#include <linux/of_device.h>
12#include "common.h"
13#include "rza.h"
14
15static int usbhs_rza1_hardware_init(struct platform_device *pdev)
16{
17	struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
18	struct device_node *usb_x1_clk, *extal_clk;
19	u32 freq_usb = 0, freq_extal = 0;
20
21	/* Input Clock Selection (NOTE: ch0 controls both ch0 and ch1) */
22	usb_x1_clk = of_find_node_by_name(NULL, "usb_x1");
23	extal_clk = of_find_node_by_name(NULL, "extal");
24	of_property_read_u32(usb_x1_clk, "clock-frequency", &freq_usb);
25	of_property_read_u32(extal_clk, "clock-frequency", &freq_extal);
26	if (freq_usb == 0) {
27		if (freq_extal == 12000000) {
28			/* Select 12MHz XTAL */
29			usbhs_bset(priv, SYSCFG, UCKSEL, UCKSEL);
30		} else {
31			dev_err(usbhs_priv_to_dev(priv), "A 48MHz USB clock or 12MHz main clock is required.\n");
32			return -EIO;
33		}
34	}
35
36	/* Enable USB PLL (NOTE: ch0 controls both ch0 and ch1) */
37	usbhs_bset(priv, SYSCFG, UPLLE, UPLLE);
38	usleep_range(1000, 2000);
39	usbhs_bset(priv, SUSPMODE, SUSPM, SUSPM);
40
41	return 0;
42}
43
44const struct renesas_usbhs_platform_info usbhs_rza1_plat_info = {
45	.platform_callback = {
46		.hardware_init = usbhs_rza1_hardware_init,
47		.get_id = usbhs_get_id_as_gadget,
48	},
49	.driver_param = {
50		.has_new_pipe_configs = 1,
51	},
52};