Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * mtu3_core.c - hardware access layer and gadget init/exit of
4 * MediaTek usb3 Dual-Role Controller Driver
5 *
6 * Copyright (C) 2016 MediaTek Inc.
7 *
8 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
9 */
10
11#include <linux/dma-mapping.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of_address.h>
15#include <linux/of_irq.h>
16#include <linux/platform_device.h>
17
18#include "mtu3.h"
19#include "mtu3_dr.h"
20#include "mtu3_debug.h"
21#include "mtu3_trace.h"
22
23static int ep_fifo_alloc(struct mtu3_ep *mep, u32 seg_size)
24{
25 struct mtu3_fifo_info *fifo = mep->fifo;
26 u32 num_bits = DIV_ROUND_UP(seg_size, MTU3_EP_FIFO_UNIT);
27 u32 start_bit;
28
29 /* ensure that @mep->fifo_seg_size is power of two */
30 num_bits = roundup_pow_of_two(num_bits);
31 if (num_bits > fifo->limit)
32 return -EINVAL;
33
34 mep->fifo_seg_size = num_bits * MTU3_EP_FIFO_UNIT;
35 num_bits = num_bits * (mep->slot + 1);
36 start_bit = bitmap_find_next_zero_area(fifo->bitmap,
37 fifo->limit, 0, num_bits, 0);
38 if (start_bit >= fifo->limit)
39 return -EOVERFLOW;
40
41 bitmap_set(fifo->bitmap, start_bit, num_bits);
42 mep->fifo_size = num_bits * MTU3_EP_FIFO_UNIT;
43 mep->fifo_addr = fifo->base + MTU3_EP_FIFO_UNIT * start_bit;
44
45 dev_dbg(mep->mtu->dev, "%s fifo:%#x/%#x, start_bit: %d\n",
46 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
47
48 return mep->fifo_addr;
49}
50
51static void ep_fifo_free(struct mtu3_ep *mep)
52{
53 struct mtu3_fifo_info *fifo = mep->fifo;
54 u32 addr = mep->fifo_addr;
55 u32 bits = mep->fifo_size / MTU3_EP_FIFO_UNIT;
56 u32 start_bit;
57
58 if (unlikely(addr < fifo->base || bits > fifo->limit))
59 return;
60
61 start_bit = (addr - fifo->base) / MTU3_EP_FIFO_UNIT;
62 bitmap_clear(fifo->bitmap, start_bit, bits);
63 mep->fifo_size = 0;
64 mep->fifo_seg_size = 0;
65
66 dev_dbg(mep->mtu->dev, "%s size:%#x/%#x, start_bit: %d\n",
67 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
68}
69
70/* enable/disable U3D SS function */
71static inline void mtu3_ss_func_set(struct mtu3 *mtu, bool enable)
72{
73 /* If usb3_en==0, LTSSM will go to SS.Disable state */
74 if (enable)
75 mtu3_setbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
76 else
77 mtu3_clrbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
78
79 dev_dbg(mtu->dev, "USB3_EN = %d\n", !!enable);
80}
81
82/* set/clear U3D HS device soft connect */
83static inline void mtu3_hs_softconn_set(struct mtu3 *mtu, bool enable)
84{
85 if (enable) {
86 mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
87 SOFT_CONN | SUSPENDM_ENABLE);
88 } else {
89 mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
90 SOFT_CONN | SUSPENDM_ENABLE);
91 }
92 dev_dbg(mtu->dev, "SOFTCONN = %d\n", !!enable);
93}
94
95/* only port0 of U2/U3 supports device mode */
96static int mtu3_device_enable(struct mtu3 *mtu)
97{
98 void __iomem *ibase = mtu->ippc_base;
99 u32 check_clk = 0;
100
101 mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
102
103 if (mtu->is_u3_ip) {
104 check_clk = SSUSB_U3_MAC_RST_B_STS;
105 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
106 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN |
107 SSUSB_U3_PORT_HOST_SEL));
108 }
109 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0),
110 (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN |
111 SSUSB_U2_PORT_HOST_SEL));
112
113 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) {
114 mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
115 if (mtu->is_u3_ip)
116 mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
117 SSUSB_U3_PORT_DUAL_MODE);
118 }
119
120 return ssusb_check_clocks(mtu->ssusb, check_clk);
121}
122
123static void mtu3_device_disable(struct mtu3 *mtu)
124{
125 void __iomem *ibase = mtu->ippc_base;
126
127 if (mtu->is_u3_ip)
128 mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
129 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN));
130
131 mtu3_setbits(ibase, SSUSB_U2_CTRL(0),
132 SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN);
133
134 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) {
135 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
136 if (mtu->is_u3_ip)
137 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
138 SSUSB_U3_PORT_DUAL_MODE);
139 }
140
141 mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
142}
143
144/* reset U3D's device module. */
145static void mtu3_device_reset(struct mtu3 *mtu)
146{
147 void __iomem *ibase = mtu->ippc_base;
148
149 mtu3_setbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
150 udelay(1);
151 mtu3_clrbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
152}
153
154static void mtu3_intr_status_clear(struct mtu3 *mtu)
155{
156 void __iomem *mbase = mtu->mac_base;
157
158 /* Clear EP0 and Tx/Rx EPn interrupts status */
159 mtu3_writel(mbase, U3D_EPISR, ~0x0);
160 /* Clear U2 USB common interrupts status */
161 mtu3_writel(mbase, U3D_COMMON_USB_INTR, ~0x0);
162 /* Clear U3 LTSSM interrupts status */
163 mtu3_writel(mbase, U3D_LTSSM_INTR, ~0x0);
164 /* Clear speed change interrupt status */
165 mtu3_writel(mbase, U3D_DEV_LINK_INTR, ~0x0);
166 /* Clear QMU interrupt status */
167 mtu3_writel(mbase, U3D_QISAR0, ~0x0);
168}
169
170/* disable all interrupts */
171static void mtu3_intr_disable(struct mtu3 *mtu)
172{
173 /* Disable level 1 interrupts */
174 mtu3_writel(mtu->mac_base, U3D_LV1IECR, ~0x0);
175 /* Disable endpoint interrupts */
176 mtu3_writel(mtu->mac_base, U3D_EPIECR, ~0x0);
177 mtu3_intr_status_clear(mtu);
178}
179
180/* enable system global interrupt */
181static void mtu3_intr_enable(struct mtu3 *mtu)
182{
183 void __iomem *mbase = mtu->mac_base;
184 u32 value;
185
186 /*Enable level 1 interrupts (BMU, QMU, MAC3, DMA, MAC2, EPCTL) */
187 value = BMU_INTR | QMU_INTR | MAC3_INTR | MAC2_INTR | EP_CTRL_INTR;
188 mtu3_writel(mbase, U3D_LV1IESR, value);
189
190 /* Enable U2 common USB interrupts */
191 value = SUSPEND_INTR | RESUME_INTR | RESET_INTR;
192 mtu3_writel(mbase, U3D_COMMON_USB_INTR_ENABLE, value);
193
194 if (mtu->is_u3_ip) {
195 /* Enable U3 LTSSM interrupts */
196 value = HOT_RST_INTR | WARM_RST_INTR |
197 ENTER_U3_INTR | EXIT_U3_INTR;
198 mtu3_writel(mbase, U3D_LTSSM_INTR_ENABLE, value);
199 }
200
201 /* Enable QMU interrupts. */
202 value = TXQ_CSERR_INT | TXQ_LENERR_INT | RXQ_CSERR_INT |
203 RXQ_LENERR_INT | RXQ_ZLPERR_INT;
204 mtu3_writel(mbase, U3D_QIESR1, value);
205
206 /* Enable speed change interrupt */
207 mtu3_writel(mbase, U3D_DEV_LINK_INTR_ENABLE, SSUSB_DEV_SPEED_CHG_INTR);
208}
209
210void mtu3_set_speed(struct mtu3 *mtu, enum usb_device_speed speed)
211{
212 void __iomem *mbase = mtu->mac_base;
213
214 if (speed > mtu->max_speed)
215 speed = mtu->max_speed;
216
217 switch (speed) {
218 case USB_SPEED_FULL:
219 /* disable U3 SS function */
220 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
221 /* disable HS function */
222 mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
223 break;
224 case USB_SPEED_HIGH:
225 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
226 /* HS/FS detected by HW */
227 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
228 break;
229 case USB_SPEED_SUPER:
230 mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
231 SSUSB_U3_PORT_SSP_SPEED);
232 break;
233 case USB_SPEED_SUPER_PLUS:
234 mtu3_setbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
235 SSUSB_U3_PORT_SSP_SPEED);
236 break;
237 default:
238 dev_err(mtu->dev, "invalid speed: %s\n",
239 usb_speed_string(speed));
240 return;
241 }
242
243 mtu->speed = speed;
244 dev_dbg(mtu->dev, "set speed: %s\n", usb_speed_string(speed));
245}
246
247/* CSR registers will be reset to default value if port is disabled */
248static void mtu3_csr_init(struct mtu3 *mtu)
249{
250 void __iomem *mbase = mtu->mac_base;
251
252 if (mtu->is_u3_ip) {
253 /* disable LGO_U1/U2 by default */
254 mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL,
255 SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE);
256 /* enable accept LGO_U1/U2 link command from host */
257 mtu3_setbits(mbase, U3D_LINK_POWER_CONTROL,
258 SW_U1_ACCEPT_ENABLE | SW_U2_ACCEPT_ENABLE);
259 /* device responses to u3_exit from host automatically */
260 mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN);
261 /* automatically build U2 link when U3 detect fail */
262 mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH);
263 /* auto clear SOFT_CONN when clear USB3_EN if work as HS */
264 mtu3_setbits(mbase, U3D_U3U2_SWITCH_CTRL, SOFTCON_CLR_AUTO_EN);
265 }
266
267 /* delay about 0.1us from detecting reset to send chirp-K */
268 mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK);
269 /* enable automatical HWRW from L1 */
270 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, LPM_HRWE);
271}
272
273/* reset: u2 - data toggle, u3 - SeqN, flow control status etc */
274static void mtu3_ep_reset(struct mtu3_ep *mep)
275{
276 struct mtu3 *mtu = mep->mtu;
277 u32 rst_bit = EP_RST(mep->is_in, mep->epnum);
278
279 mtu3_setbits(mtu->mac_base, U3D_EP_RST, rst_bit);
280 mtu3_clrbits(mtu->mac_base, U3D_EP_RST, rst_bit);
281}
282
283/* set/clear the stall and toggle bits for non-ep0 */
284void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set)
285{
286 struct mtu3 *mtu = mep->mtu;
287 void __iomem *mbase = mtu->mac_base;
288 u8 epnum = mep->epnum;
289 u32 csr;
290
291 if (mep->is_in) { /* TX */
292 csr = mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)) & TX_W1C_BITS;
293 if (set)
294 csr |= TX_SENDSTALL;
295 else
296 csr = (csr & (~TX_SENDSTALL)) | TX_SENTSTALL;
297 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr);
298 } else { /* RX */
299 csr = mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)) & RX_W1C_BITS;
300 if (set)
301 csr |= RX_SENDSTALL;
302 else
303 csr = (csr & (~RX_SENDSTALL)) | RX_SENTSTALL;
304 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr);
305 }
306
307 if (!set) {
308 mtu3_ep_reset(mep);
309 mep->flags &= ~MTU3_EP_STALL;
310 } else {
311 mep->flags |= MTU3_EP_STALL;
312 }
313
314 dev_dbg(mtu->dev, "%s: %s\n", mep->name,
315 set ? "SEND STALL" : "CLEAR STALL, with EP RESET");
316}
317
318void mtu3_dev_on_off(struct mtu3 *mtu, int is_on)
319{
320 if (mtu->is_u3_ip && mtu->speed >= USB_SPEED_SUPER)
321 mtu3_ss_func_set(mtu, is_on);
322 else
323 mtu3_hs_softconn_set(mtu, is_on);
324
325 dev_info(mtu->dev, "gadget (%s) pullup D%s\n",
326 usb_speed_string(mtu->speed), is_on ? "+" : "-");
327}
328
329void mtu3_start(struct mtu3 *mtu)
330{
331 void __iomem *mbase = mtu->mac_base;
332
333 dev_dbg(mtu->dev, "%s devctl 0x%x\n", __func__,
334 mtu3_readl(mbase, U3D_DEVICE_CONTROL));
335
336 mtu3_clrbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
337
338 mtu3_csr_init(mtu);
339 mtu3_set_speed(mtu, mtu->speed);
340
341 /* Initialize the default interrupts */
342 mtu3_intr_enable(mtu);
343 mtu->is_active = 1;
344
345 if (mtu->softconnect)
346 mtu3_dev_on_off(mtu, 1);
347}
348
349void mtu3_stop(struct mtu3 *mtu)
350{
351 dev_dbg(mtu->dev, "%s\n", __func__);
352
353 mtu3_intr_disable(mtu);
354
355 if (mtu->softconnect)
356 mtu3_dev_on_off(mtu, 0);
357
358 mtu->is_active = 0;
359 mtu3_setbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
360}
361
362/* for non-ep0 */
363int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
364 int interval, int burst, int mult)
365{
366 void __iomem *mbase = mtu->mac_base;
367 bool gen2cp = mtu->gen2cp;
368 int epnum = mep->epnum;
369 u32 csr0, csr1, csr2;
370 int fifo_sgsz, fifo_addr;
371 int num_pkts;
372
373 fifo_addr = ep_fifo_alloc(mep, mep->maxp);
374 if (fifo_addr < 0) {
375 dev_err(mtu->dev, "alloc ep fifo failed(%d)\n", mep->maxp);
376 return -ENOMEM;
377 }
378 fifo_sgsz = ilog2(mep->fifo_seg_size);
379 dev_dbg(mtu->dev, "%s fifosz: %x(%x/%x)\n", __func__, fifo_sgsz,
380 mep->fifo_seg_size, mep->fifo_size);
381
382 if (mep->is_in) {
383 csr0 = TX_TXMAXPKTSZ(mep->maxp);
384 csr0 |= TX_DMAREQEN;
385
386 num_pkts = (burst + 1) * (mult + 1) - 1;
387 csr1 = TX_SS_BURST(burst) | TX_SLOT(mep->slot);
388 csr1 |= TX_MAX_PKT(gen2cp, num_pkts) | TX_MULT(gen2cp, mult);
389
390 csr2 = TX_FIFOADDR(fifo_addr >> 4);
391 csr2 |= TX_FIFOSEGSIZE(fifo_sgsz);
392
393 switch (mep->type) {
394 case USB_ENDPOINT_XFER_BULK:
395 csr1 |= TX_TYPE(TYPE_BULK);
396 break;
397 case USB_ENDPOINT_XFER_ISOC:
398 csr1 |= TX_TYPE(TYPE_ISO);
399 csr2 |= TX_BINTERVAL(interval);
400 break;
401 case USB_ENDPOINT_XFER_INT:
402 csr1 |= TX_TYPE(TYPE_INT);
403 csr2 |= TX_BINTERVAL(interval);
404 break;
405 }
406
407 /* Enable QMU Done interrupt */
408 mtu3_setbits(mbase, U3D_QIESR0, QMU_TX_DONE_INT(epnum));
409
410 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr0);
411 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), csr1);
412 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), csr2);
413
414 dev_dbg(mtu->dev, "U3D_TX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
415 epnum, mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)),
416 mtu3_readl(mbase, MU3D_EP_TXCR1(epnum)),
417 mtu3_readl(mbase, MU3D_EP_TXCR2(epnum)));
418 } else {
419 csr0 = RX_RXMAXPKTSZ(mep->maxp);
420 csr0 |= RX_DMAREQEN;
421
422 num_pkts = (burst + 1) * (mult + 1) - 1;
423 csr1 = RX_SS_BURST(burst) | RX_SLOT(mep->slot);
424 csr1 |= RX_MAX_PKT(gen2cp, num_pkts) | RX_MULT(gen2cp, mult);
425
426 csr2 = RX_FIFOADDR(fifo_addr >> 4);
427 csr2 |= RX_FIFOSEGSIZE(fifo_sgsz);
428
429 switch (mep->type) {
430 case USB_ENDPOINT_XFER_BULK:
431 csr1 |= RX_TYPE(TYPE_BULK);
432 break;
433 case USB_ENDPOINT_XFER_ISOC:
434 csr1 |= RX_TYPE(TYPE_ISO);
435 csr2 |= RX_BINTERVAL(interval);
436 break;
437 case USB_ENDPOINT_XFER_INT:
438 csr1 |= RX_TYPE(TYPE_INT);
439 csr2 |= RX_BINTERVAL(interval);
440 break;
441 }
442
443 /*Enable QMU Done interrupt */
444 mtu3_setbits(mbase, U3D_QIESR0, QMU_RX_DONE_INT(epnum));
445
446 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr0);
447 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), csr1);
448 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), csr2);
449
450 dev_dbg(mtu->dev, "U3D_RX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
451 epnum, mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)),
452 mtu3_readl(mbase, MU3D_EP_RXCR1(epnum)),
453 mtu3_readl(mbase, MU3D_EP_RXCR2(epnum)));
454 }
455
456 dev_dbg(mtu->dev, "csr0:%#x, csr1:%#x, csr2:%#x\n", csr0, csr1, csr2);
457 dev_dbg(mtu->dev, "%s: %s, fifo-addr:%#x, fifo-size:%#x(%#x/%#x)\n",
458 __func__, mep->name, mep->fifo_addr, mep->fifo_size,
459 fifo_sgsz, mep->fifo_seg_size);
460
461 return 0;
462}
463
464/* for non-ep0 */
465void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep)
466{
467 void __iomem *mbase = mtu->mac_base;
468 int epnum = mep->epnum;
469
470 if (mep->is_in) {
471 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), 0);
472 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), 0);
473 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), 0);
474 mtu3_setbits(mbase, U3D_QIECR0, QMU_TX_DONE_INT(epnum));
475 } else {
476 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), 0);
477 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), 0);
478 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), 0);
479 mtu3_setbits(mbase, U3D_QIECR0, QMU_RX_DONE_INT(epnum));
480 }
481
482 mtu3_ep_reset(mep);
483 ep_fifo_free(mep);
484
485 dev_dbg(mtu->dev, "%s: %s\n", __func__, mep->name);
486}
487
488/*
489 * Two scenarios:
490 * 1. when device IP supports SS, the fifo of EP0, TX EPs, RX EPs
491 * are separated;
492 * 2. when supports only HS, the fifo is shared for all EPs, and
493 * the capability registers of @EPNTXFFSZ or @EPNRXFFSZ indicate
494 * the total fifo size of non-ep0, and ep0's is fixed to 64B,
495 * so the total fifo size is 64B + @EPNTXFFSZ;
496 * Due to the first 64B should be reserved for EP0, non-ep0's fifo
497 * starts from offset 64 and are divided into two equal parts for
498 * TX or RX EPs for simplification.
499 */
500static void get_ep_fifo_config(struct mtu3 *mtu)
501{
502 struct mtu3_fifo_info *tx_fifo;
503 struct mtu3_fifo_info *rx_fifo;
504 u32 fifosize;
505
506 if (mtu->is_u3_ip) {
507 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
508 tx_fifo = &mtu->tx_fifo;
509 tx_fifo->base = 0;
510 tx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
511 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
512
513 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNRXFFSZ);
514 rx_fifo = &mtu->rx_fifo;
515 rx_fifo->base = 0;
516 rx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
517 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
518 mtu->slot = MTU3_U3_IP_SLOT_DEFAULT;
519 } else {
520 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
521 tx_fifo = &mtu->tx_fifo;
522 tx_fifo->base = MTU3_U2_IP_EP0_FIFO_SIZE;
523 tx_fifo->limit = (fifosize / MTU3_EP_FIFO_UNIT) >> 1;
524 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
525
526 rx_fifo = &mtu->rx_fifo;
527 rx_fifo->base =
528 tx_fifo->base + tx_fifo->limit * MTU3_EP_FIFO_UNIT;
529 rx_fifo->limit = tx_fifo->limit;
530 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
531 mtu->slot = MTU3_U2_IP_SLOT_DEFAULT;
532 }
533
534 dev_dbg(mtu->dev, "%s, TX: base-%d, limit-%d; RX: base-%d, limit-%d\n",
535 __func__, tx_fifo->base, tx_fifo->limit,
536 rx_fifo->base, rx_fifo->limit);
537}
538
539void mtu3_ep0_setup(struct mtu3 *mtu)
540{
541 u32 maxpacket = mtu->g.ep0->maxpacket;
542 u32 csr;
543
544 dev_dbg(mtu->dev, "%s maxpacket: %d\n", __func__, maxpacket);
545
546 csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR);
547 csr &= ~EP0_MAXPKTSZ_MSK;
548 csr |= EP0_MAXPKTSZ(maxpacket);
549 csr &= EP0_W1C_BITS;
550 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);
551
552 /* Enable EP0 interrupt */
553 mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR | SETUPENDISR);
554}
555
556static int mtu3_mem_alloc(struct mtu3 *mtu)
557{
558 void __iomem *mbase = mtu->mac_base;
559 struct mtu3_ep *ep_array;
560 int in_ep_num, out_ep_num;
561 u32 cap_epinfo;
562 int ret;
563 int i;
564
565 cap_epinfo = mtu3_readl(mbase, U3D_CAP_EPINFO);
566 in_ep_num = CAP_TX_EP_NUM(cap_epinfo);
567 out_ep_num = CAP_RX_EP_NUM(cap_epinfo);
568
569 dev_info(mtu->dev, "fifosz/epnum: Tx=%#x/%d, Rx=%#x/%d\n",
570 mtu3_readl(mbase, U3D_CAP_EPNTXFFSZ), in_ep_num,
571 mtu3_readl(mbase, U3D_CAP_EPNRXFFSZ), out_ep_num);
572
573 /* one for ep0, another is reserved */
574 mtu->num_eps = min(in_ep_num, out_ep_num) + 1;
575 ep_array = kcalloc(mtu->num_eps * 2, sizeof(*ep_array), GFP_KERNEL);
576 if (ep_array == NULL)
577 return -ENOMEM;
578
579 mtu->ep_array = ep_array;
580 mtu->in_eps = ep_array;
581 mtu->out_eps = &ep_array[mtu->num_eps];
582 /* ep0 uses in_eps[0], out_eps[0] is reserved */
583 mtu->ep0 = mtu->in_eps;
584 mtu->ep0->mtu = mtu;
585 mtu->ep0->epnum = 0;
586
587 for (i = 1; i < mtu->num_eps; i++) {
588 struct mtu3_ep *mep = mtu->in_eps + i;
589
590 mep->fifo = &mtu->tx_fifo;
591 mep = mtu->out_eps + i;
592 mep->fifo = &mtu->rx_fifo;
593 }
594
595 get_ep_fifo_config(mtu);
596
597 ret = mtu3_qmu_init(mtu);
598 if (ret)
599 kfree(mtu->ep_array);
600
601 return ret;
602}
603
604static void mtu3_mem_free(struct mtu3 *mtu)
605{
606 mtu3_qmu_exit(mtu);
607 kfree(mtu->ep_array);
608}
609
610static void mtu3_regs_init(struct mtu3 *mtu)
611{
612 void __iomem *mbase = mtu->mac_base;
613
614 /* be sure interrupts are disabled before registration of ISR */
615 mtu3_intr_disable(mtu);
616
617 mtu3_csr_init(mtu);
618
619 /* U2/U3 detected by HW */
620 mtu3_writel(mbase, U3D_DEVICE_CONF, 0);
621 /* vbus detected by HW */
622 mtu3_clrbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN | VBUS_ON);
623 /* use new QMU format when HW version >= 0x1003 */
624 if (mtu->gen2cp)
625 mtu3_writel(mbase, U3D_QFCR, ~0x0);
626}
627
628static irqreturn_t mtu3_link_isr(struct mtu3 *mtu)
629{
630 void __iomem *mbase = mtu->mac_base;
631 enum usb_device_speed udev_speed;
632 u32 maxpkt = 64;
633 u32 link;
634 u32 speed;
635
636 link = mtu3_readl(mbase, U3D_DEV_LINK_INTR);
637 link &= mtu3_readl(mbase, U3D_DEV_LINK_INTR_ENABLE);
638 mtu3_writel(mbase, U3D_DEV_LINK_INTR, link); /* W1C */
639 dev_dbg(mtu->dev, "=== LINK[%x] ===\n", link);
640
641 if (!(link & SSUSB_DEV_SPEED_CHG_INTR))
642 return IRQ_NONE;
643
644 speed = SSUSB_DEV_SPEED(mtu3_readl(mbase, U3D_DEVICE_CONF));
645
646 switch (speed) {
647 case MTU3_SPEED_FULL:
648 udev_speed = USB_SPEED_FULL;
649 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
650 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
651 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
652 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
653 LPM_BESL_STALL | LPM_BESLD_STALL);
654 break;
655 case MTU3_SPEED_HIGH:
656 udev_speed = USB_SPEED_HIGH;
657 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
658 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
659 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
660 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
661 LPM_BESL_STALL | LPM_BESLD_STALL);
662 break;
663 case MTU3_SPEED_SUPER:
664 udev_speed = USB_SPEED_SUPER;
665 maxpkt = 512;
666 break;
667 case MTU3_SPEED_SUPER_PLUS:
668 udev_speed = USB_SPEED_SUPER_PLUS;
669 maxpkt = 512;
670 break;
671 default:
672 udev_speed = USB_SPEED_UNKNOWN;
673 break;
674 }
675 dev_dbg(mtu->dev, "%s: %s\n", __func__, usb_speed_string(udev_speed));
676 mtu3_dbg_trace(mtu->dev, "link speed %s",
677 usb_speed_string(udev_speed));
678
679 mtu->g.speed = udev_speed;
680 mtu->g.ep0->maxpacket = maxpkt;
681 mtu->ep0_state = MU3D_EP0_STATE_SETUP;
682
683 if (udev_speed == USB_SPEED_UNKNOWN)
684 mtu3_gadget_disconnect(mtu);
685 else
686 mtu3_ep0_setup(mtu);
687
688 return IRQ_HANDLED;
689}
690
691static irqreturn_t mtu3_u3_ltssm_isr(struct mtu3 *mtu)
692{
693 void __iomem *mbase = mtu->mac_base;
694 u32 ltssm;
695
696 ltssm = mtu3_readl(mbase, U3D_LTSSM_INTR);
697 ltssm &= mtu3_readl(mbase, U3D_LTSSM_INTR_ENABLE);
698 mtu3_writel(mbase, U3D_LTSSM_INTR, ltssm); /* W1C */
699 dev_dbg(mtu->dev, "=== LTSSM[%x] ===\n", ltssm);
700 trace_mtu3_u3_ltssm_isr(ltssm);
701
702 if (ltssm & (HOT_RST_INTR | WARM_RST_INTR))
703 mtu3_gadget_reset(mtu);
704
705 if (ltssm & VBUS_FALL_INTR) {
706 mtu3_ss_func_set(mtu, false);
707 mtu3_gadget_reset(mtu);
708 }
709
710 if (ltssm & VBUS_RISE_INTR)
711 mtu3_ss_func_set(mtu, true);
712
713 if (ltssm & EXIT_U3_INTR)
714 mtu3_gadget_resume(mtu);
715
716 if (ltssm & ENTER_U3_INTR)
717 mtu3_gadget_suspend(mtu);
718
719 return IRQ_HANDLED;
720}
721
722static irqreturn_t mtu3_u2_common_isr(struct mtu3 *mtu)
723{
724 void __iomem *mbase = mtu->mac_base;
725 u32 u2comm;
726
727 u2comm = mtu3_readl(mbase, U3D_COMMON_USB_INTR);
728 u2comm &= mtu3_readl(mbase, U3D_COMMON_USB_INTR_ENABLE);
729 mtu3_writel(mbase, U3D_COMMON_USB_INTR, u2comm); /* W1C */
730 dev_dbg(mtu->dev, "=== U2COMM[%x] ===\n", u2comm);
731 trace_mtu3_u2_common_isr(u2comm);
732
733 if (u2comm & SUSPEND_INTR)
734 mtu3_gadget_suspend(mtu);
735
736 if (u2comm & RESUME_INTR)
737 mtu3_gadget_resume(mtu);
738
739 if (u2comm & RESET_INTR)
740 mtu3_gadget_reset(mtu);
741
742 return IRQ_HANDLED;
743}
744
745static irqreturn_t mtu3_irq(int irq, void *data)
746{
747 struct mtu3 *mtu = (struct mtu3 *)data;
748 unsigned long flags;
749 u32 level1;
750
751 spin_lock_irqsave(&mtu->lock, flags);
752
753 /* U3D_LV1ISR is RU */
754 level1 = mtu3_readl(mtu->mac_base, U3D_LV1ISR);
755 level1 &= mtu3_readl(mtu->mac_base, U3D_LV1IER);
756
757 if (level1 & EP_CTRL_INTR)
758 mtu3_link_isr(mtu);
759
760 if (level1 & MAC2_INTR)
761 mtu3_u2_common_isr(mtu);
762
763 if (level1 & MAC3_INTR)
764 mtu3_u3_ltssm_isr(mtu);
765
766 if (level1 & BMU_INTR)
767 mtu3_ep0_isr(mtu);
768
769 if (level1 & QMU_INTR)
770 mtu3_qmu_isr(mtu);
771
772 spin_unlock_irqrestore(&mtu->lock, flags);
773
774 return IRQ_HANDLED;
775}
776
777static void mtu3_check_params(struct mtu3 *mtu)
778{
779 /* check the max_speed parameter */
780 switch (mtu->max_speed) {
781 case USB_SPEED_FULL:
782 case USB_SPEED_HIGH:
783 case USB_SPEED_SUPER:
784 case USB_SPEED_SUPER_PLUS:
785 break;
786 default:
787 dev_err(mtu->dev, "invalid max_speed: %s\n",
788 usb_speed_string(mtu->max_speed));
789 fallthrough;
790 case USB_SPEED_UNKNOWN:
791 /* default as SSP */
792 mtu->max_speed = USB_SPEED_SUPER_PLUS;
793 break;
794 }
795
796 if (!mtu->is_u3_ip && (mtu->max_speed > USB_SPEED_HIGH))
797 mtu->max_speed = USB_SPEED_HIGH;
798
799 mtu->speed = mtu->max_speed;
800
801 dev_info(mtu->dev, "max_speed: %s\n",
802 usb_speed_string(mtu->max_speed));
803}
804
805static int mtu3_hw_init(struct mtu3 *mtu)
806{
807 u32 value;
808 int ret;
809
810 value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_TRUNK_VERS);
811 mtu->hw_version = IP_TRUNK_VERS(value);
812 mtu->gen2cp = !!(mtu->hw_version >= MTU3_TRUNK_VERS_1003);
813
814 value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_DEV_CAP);
815 mtu->is_u3_ip = !!SSUSB_IP_DEV_U3_PORT_NUM(value);
816
817 dev_info(mtu->dev, "IP version 0x%x(%s IP)\n", mtu->hw_version,
818 mtu->is_u3_ip ? "U3" : "U2");
819
820 mtu3_check_params(mtu);
821
822 mtu3_device_reset(mtu);
823
824 ret = mtu3_device_enable(mtu);
825 if (ret) {
826 dev_err(mtu->dev, "device enable failed %d\n", ret);
827 return ret;
828 }
829
830 ret = mtu3_mem_alloc(mtu);
831 if (ret)
832 return -ENOMEM;
833
834 mtu3_regs_init(mtu);
835
836 return 0;
837}
838
839static void mtu3_hw_exit(struct mtu3 *mtu)
840{
841 mtu3_device_disable(mtu);
842 mtu3_mem_free(mtu);
843}
844
845/*
846 * we set 32-bit DMA mask by default, here check whether the controller
847 * supports 36-bit DMA or not, if it does, set 36-bit DMA mask.
848 */
849static int mtu3_set_dma_mask(struct mtu3 *mtu)
850{
851 struct device *dev = mtu->dev;
852 bool is_36bit = false;
853 int ret = 0;
854 u32 value;
855
856 value = mtu3_readl(mtu->mac_base, U3D_MISC_CTRL);
857 if (value & DMA_ADDR_36BIT) {
858 is_36bit = true;
859 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
860 /* If set 36-bit DMA mask fails, fall back to 32-bit DMA mask */
861 if (ret) {
862 is_36bit = false;
863 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
864 }
865 }
866 dev_info(dev, "dma mask: %s bits\n", is_36bit ? "36" : "32");
867
868 return ret;
869}
870
871int ssusb_gadget_init(struct ssusb_mtk *ssusb)
872{
873 struct device *dev = ssusb->dev;
874 struct platform_device *pdev = to_platform_device(dev);
875 struct mtu3 *mtu = NULL;
876 int ret = -ENOMEM;
877
878 mtu = devm_kzalloc(dev, sizeof(struct mtu3), GFP_KERNEL);
879 if (mtu == NULL)
880 return -ENOMEM;
881
882 mtu->irq = platform_get_irq(pdev, 0);
883 if (mtu->irq < 0)
884 return mtu->irq;
885 dev_info(dev, "irq %d\n", mtu->irq);
886
887 mtu->mac_base = devm_platform_ioremap_resource_byname(pdev, "mac");
888 if (IS_ERR(mtu->mac_base)) {
889 dev_err(dev, "error mapping memory for dev mac\n");
890 return PTR_ERR(mtu->mac_base);
891 }
892
893 spin_lock_init(&mtu->lock);
894 mtu->dev = dev;
895 mtu->ippc_base = ssusb->ippc_base;
896 ssusb->mac_base = mtu->mac_base;
897 ssusb->u3d = mtu;
898 mtu->ssusb = ssusb;
899 mtu->max_speed = usb_get_maximum_speed(dev);
900
901 dev_dbg(dev, "mac_base=0x%p, ippc_base=0x%p\n",
902 mtu->mac_base, mtu->ippc_base);
903
904 ret = mtu3_hw_init(mtu);
905 if (ret) {
906 dev_err(dev, "mtu3 hw init failed:%d\n", ret);
907 return ret;
908 }
909
910 ret = mtu3_set_dma_mask(mtu);
911 if (ret) {
912 dev_err(dev, "mtu3 set dma_mask failed:%d\n", ret);
913 goto dma_mask_err;
914 }
915
916 ret = devm_request_irq(dev, mtu->irq, mtu3_irq, 0, dev_name(dev), mtu);
917 if (ret) {
918 dev_err(dev, "request irq %d failed!\n", mtu->irq);
919 goto irq_err;
920 }
921
922 device_init_wakeup(dev, true);
923
924 ret = mtu3_gadget_setup(mtu);
925 if (ret) {
926 dev_err(dev, "mtu3 gadget init failed:%d\n", ret);
927 goto gadget_err;
928 }
929
930 /* init as host mode, power down device IP for power saving */
931 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
932 mtu3_stop(mtu);
933
934 ssusb_dev_debugfs_init(ssusb);
935
936 dev_dbg(dev, " %s() done...\n", __func__);
937
938 return 0;
939
940gadget_err:
941 device_init_wakeup(dev, false);
942
943dma_mask_err:
944irq_err:
945 mtu3_hw_exit(mtu);
946 ssusb->u3d = NULL;
947 dev_err(dev, " %s() fail...\n", __func__);
948
949 return ret;
950}
951
952void ssusb_gadget_exit(struct ssusb_mtk *ssusb)
953{
954 struct mtu3 *mtu = ssusb->u3d;
955
956 mtu3_gadget_cleanup(mtu);
957 device_init_wakeup(ssusb->dev, false);
958 mtu3_hw_exit(mtu);
959}