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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Qualcomm self-authenticating modem subsystem remoteproc driver
4 *
5 * Copyright (C) 2016 Linaro Ltd.
6 * Copyright (C) 2014 Sony Mobile Communications AB
7 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/devcoredump.h>
13#include <linux/dma-mapping.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/mfd/syscon.h>
17#include <linux/module.h>
18#include <linux/of_address.h>
19#include <linux/of_device.h>
20#include <linux/platform_device.h>
21#include <linux/pm_domain.h>
22#include <linux/pm_runtime.h>
23#include <linux/regmap.h>
24#include <linux/regulator/consumer.h>
25#include <linux/remoteproc.h>
26#include <linux/reset.h>
27#include <linux/soc/qcom/mdt_loader.h>
28#include <linux/iopoll.h>
29#include <linux/slab.h>
30
31#include "remoteproc_internal.h"
32#include "qcom_common.h"
33#include "qcom_pil_info.h"
34#include "qcom_q6v5.h"
35
36#include <linux/qcom_scm.h>
37
38#define MPSS_CRASH_REASON_SMEM 421
39
40#define MBA_LOG_SIZE SZ_4K
41
42/* RMB Status Register Values */
43#define RMB_PBL_SUCCESS 0x1
44
45#define RMB_MBA_XPU_UNLOCKED 0x1
46#define RMB_MBA_XPU_UNLOCKED_SCRIBBLED 0x2
47#define RMB_MBA_META_DATA_AUTH_SUCCESS 0x3
48#define RMB_MBA_AUTH_COMPLETE 0x4
49
50/* PBL/MBA interface registers */
51#define RMB_MBA_IMAGE_REG 0x00
52#define RMB_PBL_STATUS_REG 0x04
53#define RMB_MBA_COMMAND_REG 0x08
54#define RMB_MBA_STATUS_REG 0x0C
55#define RMB_PMI_META_DATA_REG 0x10
56#define RMB_PMI_CODE_START_REG 0x14
57#define RMB_PMI_CODE_LENGTH_REG 0x18
58#define RMB_MBA_MSS_STATUS 0x40
59#define RMB_MBA_ALT_RESET 0x44
60
61#define RMB_CMD_META_DATA_READY 0x1
62#define RMB_CMD_LOAD_READY 0x2
63
64/* QDSP6SS Register Offsets */
65#define QDSP6SS_RESET_REG 0x014
66#define QDSP6SS_GFMUX_CTL_REG 0x020
67#define QDSP6SS_PWR_CTL_REG 0x030
68#define QDSP6SS_MEM_PWR_CTL 0x0B0
69#define QDSP6V6SS_MEM_PWR_CTL 0x034
70#define QDSP6SS_STRAP_ACC 0x110
71
72/* AXI Halt Register Offsets */
73#define AXI_HALTREQ_REG 0x0
74#define AXI_HALTACK_REG 0x4
75#define AXI_IDLE_REG 0x8
76#define AXI_GATING_VALID_OVERRIDE BIT(0)
77
78#define HALT_ACK_TIMEOUT_US 100000
79
80/* QDSP6SS_RESET */
81#define Q6SS_STOP_CORE BIT(0)
82#define Q6SS_CORE_ARES BIT(1)
83#define Q6SS_BUS_ARES_ENABLE BIT(2)
84
85/* QDSP6SS CBCR */
86#define Q6SS_CBCR_CLKEN BIT(0)
87#define Q6SS_CBCR_CLKOFF BIT(31)
88#define Q6SS_CBCR_TIMEOUT_US 200
89
90/* QDSP6SS_GFMUX_CTL */
91#define Q6SS_CLK_ENABLE BIT(1)
92
93/* QDSP6SS_PWR_CTL */
94#define Q6SS_L2DATA_SLP_NRET_N_0 BIT(0)
95#define Q6SS_L2DATA_SLP_NRET_N_1 BIT(1)
96#define Q6SS_L2DATA_SLP_NRET_N_2 BIT(2)
97#define Q6SS_L2TAG_SLP_NRET_N BIT(16)
98#define Q6SS_ETB_SLP_NRET_N BIT(17)
99#define Q6SS_L2DATA_STBY_N BIT(18)
100#define Q6SS_SLP_RET_N BIT(19)
101#define Q6SS_CLAMP_IO BIT(20)
102#define QDSS_BHS_ON BIT(21)
103#define QDSS_LDO_BYP BIT(22)
104
105/* QDSP6v56 parameters */
106#define QDSP6v56_LDO_BYP BIT(25)
107#define QDSP6v56_BHS_ON BIT(24)
108#define QDSP6v56_CLAMP_WL BIT(21)
109#define QDSP6v56_CLAMP_QMC_MEM BIT(22)
110#define QDSP6SS_XO_CBCR 0x0038
111#define QDSP6SS_ACC_OVERRIDE_VAL 0x20
112
113/* QDSP6v65 parameters */
114#define QDSP6SS_CORE_CBCR 0x20
115#define QDSP6SS_SLEEP 0x3C
116#define QDSP6SS_BOOT_CORE_START 0x400
117#define QDSP6SS_BOOT_CMD 0x404
118#define BOOT_FSM_TIMEOUT 10000
119
120struct reg_info {
121 struct regulator *reg;
122 int uV;
123 int uA;
124};
125
126struct qcom_mss_reg_res {
127 const char *supply;
128 int uV;
129 int uA;
130};
131
132struct rproc_hexagon_res {
133 const char *hexagon_mba_image;
134 struct qcom_mss_reg_res *proxy_supply;
135 struct qcom_mss_reg_res *active_supply;
136 char **proxy_clk_names;
137 char **reset_clk_names;
138 char **active_clk_names;
139 char **active_pd_names;
140 char **proxy_pd_names;
141 int version;
142 bool need_mem_protection;
143 bool has_alt_reset;
144 bool has_mba_logs;
145 bool has_spare_reg;
146};
147
148struct q6v5 {
149 struct device *dev;
150 struct rproc *rproc;
151
152 void __iomem *reg_base;
153 void __iomem *rmb_base;
154
155 struct regmap *halt_map;
156 struct regmap *conn_map;
157
158 u32 halt_q6;
159 u32 halt_modem;
160 u32 halt_nc;
161 u32 conn_box;
162
163 struct reset_control *mss_restart;
164 struct reset_control *pdc_reset;
165
166 struct qcom_q6v5 q6v5;
167
168 struct clk *active_clks[8];
169 struct clk *reset_clks[4];
170 struct clk *proxy_clks[4];
171 struct device *active_pds[1];
172 struct device *proxy_pds[3];
173 int active_clk_count;
174 int reset_clk_count;
175 int proxy_clk_count;
176 int active_pd_count;
177 int proxy_pd_count;
178
179 struct reg_info active_regs[1];
180 struct reg_info proxy_regs[3];
181 int active_reg_count;
182 int proxy_reg_count;
183
184 bool dump_mba_loaded;
185 size_t current_dump_size;
186 size_t total_dump_size;
187
188 phys_addr_t mba_phys;
189 void *mba_region;
190 size_t mba_size;
191 size_t dp_size;
192
193 phys_addr_t mpss_phys;
194 phys_addr_t mpss_reloc;
195 size_t mpss_size;
196
197 struct qcom_rproc_glink glink_subdev;
198 struct qcom_rproc_subdev smd_subdev;
199 struct qcom_rproc_ssr ssr_subdev;
200 struct qcom_sysmon *sysmon;
201 bool need_mem_protection;
202 bool has_alt_reset;
203 bool has_mba_logs;
204 bool has_spare_reg;
205 int mpss_perm;
206 int mba_perm;
207 const char *hexagon_mdt_image;
208 int version;
209};
210
211enum {
212 MSS_MSM8916,
213 MSS_MSM8974,
214 MSS_MSM8996,
215 MSS_MSM8998,
216 MSS_SC7180,
217 MSS_SDM845,
218};
219
220static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
221 const struct qcom_mss_reg_res *reg_res)
222{
223 int rc;
224 int i;
225
226 if (!reg_res)
227 return 0;
228
229 for (i = 0; reg_res[i].supply; i++) {
230 regs[i].reg = devm_regulator_get(dev, reg_res[i].supply);
231 if (IS_ERR(regs[i].reg)) {
232 rc = PTR_ERR(regs[i].reg);
233 if (rc != -EPROBE_DEFER)
234 dev_err(dev, "Failed to get %s\n regulator",
235 reg_res[i].supply);
236 return rc;
237 }
238
239 regs[i].uV = reg_res[i].uV;
240 regs[i].uA = reg_res[i].uA;
241 }
242
243 return i;
244}
245
246static int q6v5_regulator_enable(struct q6v5 *qproc,
247 struct reg_info *regs, int count)
248{
249 int ret;
250 int i;
251
252 for (i = 0; i < count; i++) {
253 if (regs[i].uV > 0) {
254 ret = regulator_set_voltage(regs[i].reg,
255 regs[i].uV, INT_MAX);
256 if (ret) {
257 dev_err(qproc->dev,
258 "Failed to request voltage for %d.\n",
259 i);
260 goto err;
261 }
262 }
263
264 if (regs[i].uA > 0) {
265 ret = regulator_set_load(regs[i].reg,
266 regs[i].uA);
267 if (ret < 0) {
268 dev_err(qproc->dev,
269 "Failed to set regulator mode\n");
270 goto err;
271 }
272 }
273
274 ret = regulator_enable(regs[i].reg);
275 if (ret) {
276 dev_err(qproc->dev, "Regulator enable failed\n");
277 goto err;
278 }
279 }
280
281 return 0;
282err:
283 for (; i >= 0; i--) {
284 if (regs[i].uV > 0)
285 regulator_set_voltage(regs[i].reg, 0, INT_MAX);
286
287 if (regs[i].uA > 0)
288 regulator_set_load(regs[i].reg, 0);
289
290 regulator_disable(regs[i].reg);
291 }
292
293 return ret;
294}
295
296static void q6v5_regulator_disable(struct q6v5 *qproc,
297 struct reg_info *regs, int count)
298{
299 int i;
300
301 for (i = 0; i < count; i++) {
302 if (regs[i].uV > 0)
303 regulator_set_voltage(regs[i].reg, 0, INT_MAX);
304
305 if (regs[i].uA > 0)
306 regulator_set_load(regs[i].reg, 0);
307
308 regulator_disable(regs[i].reg);
309 }
310}
311
312static int q6v5_clk_enable(struct device *dev,
313 struct clk **clks, int count)
314{
315 int rc;
316 int i;
317
318 for (i = 0; i < count; i++) {
319 rc = clk_prepare_enable(clks[i]);
320 if (rc) {
321 dev_err(dev, "Clock enable failed\n");
322 goto err;
323 }
324 }
325
326 return 0;
327err:
328 for (i--; i >= 0; i--)
329 clk_disable_unprepare(clks[i]);
330
331 return rc;
332}
333
334static void q6v5_clk_disable(struct device *dev,
335 struct clk **clks, int count)
336{
337 int i;
338
339 for (i = 0; i < count; i++)
340 clk_disable_unprepare(clks[i]);
341}
342
343static int q6v5_pds_enable(struct q6v5 *qproc, struct device **pds,
344 size_t pd_count)
345{
346 int ret;
347 int i;
348
349 for (i = 0; i < pd_count; i++) {
350 dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
351 ret = pm_runtime_get_sync(pds[i]);
352 if (ret < 0)
353 goto unroll_pd_votes;
354 }
355
356 return 0;
357
358unroll_pd_votes:
359 for (i--; i >= 0; i--) {
360 dev_pm_genpd_set_performance_state(pds[i], 0);
361 pm_runtime_put(pds[i]);
362 }
363
364 return ret;
365}
366
367static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds,
368 size_t pd_count)
369{
370 int i;
371
372 for (i = 0; i < pd_count; i++) {
373 dev_pm_genpd_set_performance_state(pds[i], 0);
374 pm_runtime_put(pds[i]);
375 }
376}
377
378static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm,
379 bool local, bool remote, phys_addr_t addr,
380 size_t size)
381{
382 struct qcom_scm_vmperm next[2];
383 int perms = 0;
384
385 if (!qproc->need_mem_protection)
386 return 0;
387
388 if (local == !!(*current_perm & BIT(QCOM_SCM_VMID_HLOS)) &&
389 remote == !!(*current_perm & BIT(QCOM_SCM_VMID_MSS_MSA)))
390 return 0;
391
392 if (local) {
393 next[perms].vmid = QCOM_SCM_VMID_HLOS;
394 next[perms].perm = QCOM_SCM_PERM_RWX;
395 perms++;
396 }
397
398 if (remote) {
399 next[perms].vmid = QCOM_SCM_VMID_MSS_MSA;
400 next[perms].perm = QCOM_SCM_PERM_RW;
401 perms++;
402 }
403
404 return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K),
405 current_perm, next, perms);
406}
407
408static void q6v5_debug_policy_load(struct q6v5 *qproc)
409{
410 const struct firmware *dp_fw;
411
412 if (request_firmware_direct(&dp_fw, "msadp", qproc->dev))
413 return;
414
415 if (SZ_1M + dp_fw->size <= qproc->mba_size) {
416 memcpy(qproc->mba_region + SZ_1M, dp_fw->data, dp_fw->size);
417 qproc->dp_size = dp_fw->size;
418 }
419
420 release_firmware(dp_fw);
421}
422
423static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
424{
425 struct q6v5 *qproc = rproc->priv;
426
427 /* MBA is restricted to a maximum size of 1M */
428 if (fw->size > qproc->mba_size || fw->size > SZ_1M) {
429 dev_err(qproc->dev, "MBA firmware load failed\n");
430 return -EINVAL;
431 }
432
433 memcpy(qproc->mba_region, fw->data, fw->size);
434 q6v5_debug_policy_load(qproc);
435
436 return 0;
437}
438
439static int q6v5_reset_assert(struct q6v5 *qproc)
440{
441 int ret;
442
443 if (qproc->has_alt_reset) {
444 reset_control_assert(qproc->pdc_reset);
445 ret = reset_control_reset(qproc->mss_restart);
446 reset_control_deassert(qproc->pdc_reset);
447 } else if (qproc->has_spare_reg) {
448 /*
449 * When the AXI pipeline is being reset with the Q6 modem partly
450 * operational there is possibility of AXI valid signal to
451 * glitch, leading to spurious transactions and Q6 hangs. A work
452 * around is employed by asserting the AXI_GATING_VALID_OVERRIDE
453 * BIT before triggering Q6 MSS reset. AXI_GATING_VALID_OVERRIDE
454 * is withdrawn post MSS assert followed by a MSS deassert,
455 * while holding the PDC reset.
456 */
457 reset_control_assert(qproc->pdc_reset);
458 regmap_update_bits(qproc->conn_map, qproc->conn_box,
459 AXI_GATING_VALID_OVERRIDE, 1);
460 reset_control_assert(qproc->mss_restart);
461 reset_control_deassert(qproc->pdc_reset);
462 regmap_update_bits(qproc->conn_map, qproc->conn_box,
463 AXI_GATING_VALID_OVERRIDE, 0);
464 ret = reset_control_deassert(qproc->mss_restart);
465 } else {
466 ret = reset_control_assert(qproc->mss_restart);
467 }
468
469 return ret;
470}
471
472static int q6v5_reset_deassert(struct q6v5 *qproc)
473{
474 int ret;
475
476 if (qproc->has_alt_reset) {
477 reset_control_assert(qproc->pdc_reset);
478 writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
479 ret = reset_control_reset(qproc->mss_restart);
480 writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
481 reset_control_deassert(qproc->pdc_reset);
482 } else if (qproc->has_spare_reg) {
483 ret = reset_control_reset(qproc->mss_restart);
484 } else {
485 ret = reset_control_deassert(qproc->mss_restart);
486 }
487
488 return ret;
489}
490
491static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
492{
493 unsigned long timeout;
494 s32 val;
495
496 timeout = jiffies + msecs_to_jiffies(ms);
497 for (;;) {
498 val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
499 if (val)
500 break;
501
502 if (time_after(jiffies, timeout))
503 return -ETIMEDOUT;
504
505 msleep(1);
506 }
507
508 return val;
509}
510
511static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
512{
513
514 unsigned long timeout;
515 s32 val;
516
517 timeout = jiffies + msecs_to_jiffies(ms);
518 for (;;) {
519 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
520 if (val < 0)
521 break;
522
523 if (!status && val)
524 break;
525 else if (status && val == status)
526 break;
527
528 if (time_after(jiffies, timeout))
529 return -ETIMEDOUT;
530
531 msleep(1);
532 }
533
534 return val;
535}
536
537static void q6v5_dump_mba_logs(struct q6v5 *qproc)
538{
539 struct rproc *rproc = qproc->rproc;
540 void *data;
541
542 if (!qproc->has_mba_logs)
543 return;
544
545 if (q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false, qproc->mba_phys,
546 qproc->mba_size))
547 return;
548
549 data = vmalloc(MBA_LOG_SIZE);
550 if (!data)
551 return;
552
553 memcpy(data, qproc->mba_region, MBA_LOG_SIZE);
554 dev_coredumpv(&rproc->dev, data, MBA_LOG_SIZE, GFP_KERNEL);
555}
556
557static int q6v5proc_reset(struct q6v5 *qproc)
558{
559 u32 val;
560 int ret;
561 int i;
562
563 if (qproc->version == MSS_SDM845) {
564 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
565 val |= Q6SS_CBCR_CLKEN;
566 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
567
568 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
569 val, !(val & Q6SS_CBCR_CLKOFF), 1,
570 Q6SS_CBCR_TIMEOUT_US);
571 if (ret) {
572 dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
573 return -ETIMEDOUT;
574 }
575
576 /* De-assert QDSP6 stop core */
577 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
578 /* Trigger boot FSM */
579 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
580
581 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
582 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
583 if (ret) {
584 dev_err(qproc->dev, "Boot FSM failed to complete.\n");
585 /* Reset the modem so that boot FSM is in reset state */
586 q6v5_reset_deassert(qproc);
587 return ret;
588 }
589
590 goto pbl_wait;
591 } else if (qproc->version == MSS_SC7180) {
592 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
593 val |= Q6SS_CBCR_CLKEN;
594 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
595
596 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
597 val, !(val & Q6SS_CBCR_CLKOFF), 1,
598 Q6SS_CBCR_TIMEOUT_US);
599 if (ret) {
600 dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
601 return -ETIMEDOUT;
602 }
603
604 /* Turn on the XO clock needed for PLL setup */
605 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
606 val |= Q6SS_CBCR_CLKEN;
607 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
608
609 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
610 val, !(val & Q6SS_CBCR_CLKOFF), 1,
611 Q6SS_CBCR_TIMEOUT_US);
612 if (ret) {
613 dev_err(qproc->dev, "QDSP6SS XO clock timed out\n");
614 return -ETIMEDOUT;
615 }
616
617 /* Configure Q6 core CBCR to auto-enable after reset sequence */
618 val = readl(qproc->reg_base + QDSP6SS_CORE_CBCR);
619 val |= Q6SS_CBCR_CLKEN;
620 writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR);
621
622 /* De-assert the Q6 stop core signal */
623 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
624
625 /* Wait for 10 us for any staggering logic to settle */
626 usleep_range(10, 20);
627
628 /* Trigger the boot FSM to start the Q6 out-of-reset sequence */
629 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
630
631 /* Poll the MSS_STATUS for FSM completion */
632 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
633 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
634 if (ret) {
635 dev_err(qproc->dev, "Boot FSM failed to complete.\n");
636 /* Reset the modem so that boot FSM is in reset state */
637 q6v5_reset_deassert(qproc);
638 return ret;
639 }
640 goto pbl_wait;
641 } else if (qproc->version == MSS_MSM8996 ||
642 qproc->version == MSS_MSM8998) {
643 int mem_pwr_ctl;
644
645 /* Override the ACC value if required */
646 writel(QDSP6SS_ACC_OVERRIDE_VAL,
647 qproc->reg_base + QDSP6SS_STRAP_ACC);
648
649 /* Assert resets, stop core */
650 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
651 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
652 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
653
654 /* BHS require xo cbcr to be enabled */
655 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
656 val |= Q6SS_CBCR_CLKEN;
657 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
658
659 /* Read CLKOFF bit to go low indicating CLK is enabled */
660 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
661 val, !(val & Q6SS_CBCR_CLKOFF), 1,
662 Q6SS_CBCR_TIMEOUT_US);
663 if (ret) {
664 dev_err(qproc->dev,
665 "xo cbcr enabling timed out (rc:%d)\n", ret);
666 return ret;
667 }
668 /* Enable power block headswitch and wait for it to stabilize */
669 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
670 val |= QDSP6v56_BHS_ON;
671 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
672 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
673 udelay(1);
674
675 /* Put LDO in bypass mode */
676 val |= QDSP6v56_LDO_BYP;
677 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
678
679 /* Deassert QDSP6 compiler memory clamp */
680 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
681 val &= ~QDSP6v56_CLAMP_QMC_MEM;
682 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
683
684 /* Deassert memory peripheral sleep and L2 memory standby */
685 val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
686 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
687
688 /* Turn on L1, L2, ETB and JU memories 1 at a time */
689 if (qproc->version == MSS_MSM8996) {
690 mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL;
691 i = 19;
692 } else {
693 /* MSS_MSM8998 */
694 mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL;
695 i = 28;
696 }
697 val = readl(qproc->reg_base + mem_pwr_ctl);
698 for (; i >= 0; i--) {
699 val |= BIT(i);
700 writel(val, qproc->reg_base + mem_pwr_ctl);
701 /*
702 * Read back value to ensure the write is done then
703 * wait for 1us for both memory peripheral and data
704 * array to turn on.
705 */
706 val |= readl(qproc->reg_base + mem_pwr_ctl);
707 udelay(1);
708 }
709 /* Remove word line clamp */
710 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
711 val &= ~QDSP6v56_CLAMP_WL;
712 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
713 } else {
714 /* Assert resets, stop core */
715 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
716 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
717 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
718
719 /* Enable power block headswitch and wait for it to stabilize */
720 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
721 val |= QDSS_BHS_ON | QDSS_LDO_BYP;
722 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
723 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
724 udelay(1);
725 /*
726 * Turn on memories. L2 banks should be done individually
727 * to minimize inrush current.
728 */
729 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
730 val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
731 Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
732 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
733 val |= Q6SS_L2DATA_SLP_NRET_N_2;
734 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
735 val |= Q6SS_L2DATA_SLP_NRET_N_1;
736 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
737 val |= Q6SS_L2DATA_SLP_NRET_N_0;
738 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
739 }
740 /* Remove IO clamp */
741 val &= ~Q6SS_CLAMP_IO;
742 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
743
744 /* Bring core out of reset */
745 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
746 val &= ~Q6SS_CORE_ARES;
747 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
748
749 /* Turn on core clock */
750 val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
751 val |= Q6SS_CLK_ENABLE;
752 writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
753
754 /* Start core execution */
755 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
756 val &= ~Q6SS_STOP_CORE;
757 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
758
759pbl_wait:
760 /* Wait for PBL status */
761 ret = q6v5_rmb_pbl_wait(qproc, 1000);
762 if (ret == -ETIMEDOUT) {
763 dev_err(qproc->dev, "PBL boot timed out\n");
764 } else if (ret != RMB_PBL_SUCCESS) {
765 dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
766 ret = -EINVAL;
767 } else {
768 ret = 0;
769 }
770
771 return ret;
772}
773
774static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
775 struct regmap *halt_map,
776 u32 offset)
777{
778 unsigned int val;
779 int ret;
780
781 /* Check if we're already idle */
782 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
783 if (!ret && val)
784 return;
785
786 /* Assert halt request */
787 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
788
789 /* Wait for halt */
790 regmap_read_poll_timeout(halt_map, offset + AXI_HALTACK_REG, val,
791 val, 1000, HALT_ACK_TIMEOUT_US);
792
793 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
794 if (ret || !val)
795 dev_err(qproc->dev, "port failed halt\n");
796
797 /* Clear halt request (port will remain halted until reset) */
798 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
799}
800
801static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw)
802{
803 unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
804 dma_addr_t phys;
805 void *metadata;
806 int mdata_perm;
807 int xferop_ret;
808 size_t size;
809 void *ptr;
810 int ret;
811
812 metadata = qcom_mdt_read_metadata(fw, &size);
813 if (IS_ERR(metadata))
814 return PTR_ERR(metadata);
815
816 ptr = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs);
817 if (!ptr) {
818 kfree(metadata);
819 dev_err(qproc->dev, "failed to allocate mdt buffer\n");
820 return -ENOMEM;
821 }
822
823 memcpy(ptr, metadata, size);
824
825 /* Hypervisor mapping to access metadata by modem */
826 mdata_perm = BIT(QCOM_SCM_VMID_HLOS);
827 ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, false, true,
828 phys, size);
829 if (ret) {
830 dev_err(qproc->dev,
831 "assigning Q6 access to metadata failed: %d\n", ret);
832 ret = -EAGAIN;
833 goto free_dma_attrs;
834 }
835
836 writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
837 writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
838
839 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000);
840 if (ret == -ETIMEDOUT)
841 dev_err(qproc->dev, "MPSS header authentication timed out\n");
842 else if (ret < 0)
843 dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret);
844
845 /* Metadata authentication done, remove modem access */
846 xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, true, false,
847 phys, size);
848 if (xferop_ret)
849 dev_warn(qproc->dev,
850 "mdt buffer not reclaimed system may become unstable\n");
851
852free_dma_attrs:
853 dma_free_attrs(qproc->dev, size, ptr, phys, dma_attrs);
854 kfree(metadata);
855
856 return ret < 0 ? ret : 0;
857}
858
859static bool q6v5_phdr_valid(const struct elf32_phdr *phdr)
860{
861 if (phdr->p_type != PT_LOAD)
862 return false;
863
864 if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
865 return false;
866
867 if (!phdr->p_memsz)
868 return false;
869
870 return true;
871}
872
873static int q6v5_mba_load(struct q6v5 *qproc)
874{
875 int ret;
876 int xfermemop_ret;
877 bool mba_load_err = false;
878
879 qcom_q6v5_prepare(&qproc->q6v5);
880
881 ret = q6v5_pds_enable(qproc, qproc->active_pds, qproc->active_pd_count);
882 if (ret < 0) {
883 dev_err(qproc->dev, "failed to enable active power domains\n");
884 goto disable_irqs;
885 }
886
887 ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
888 if (ret < 0) {
889 dev_err(qproc->dev, "failed to enable proxy power domains\n");
890 goto disable_active_pds;
891 }
892
893 ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
894 qproc->proxy_reg_count);
895 if (ret) {
896 dev_err(qproc->dev, "failed to enable proxy supplies\n");
897 goto disable_proxy_pds;
898 }
899
900 ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
901 qproc->proxy_clk_count);
902 if (ret) {
903 dev_err(qproc->dev, "failed to enable proxy clocks\n");
904 goto disable_proxy_reg;
905 }
906
907 ret = q6v5_regulator_enable(qproc, qproc->active_regs,
908 qproc->active_reg_count);
909 if (ret) {
910 dev_err(qproc->dev, "failed to enable supplies\n");
911 goto disable_proxy_clk;
912 }
913
914 ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
915 qproc->reset_clk_count);
916 if (ret) {
917 dev_err(qproc->dev, "failed to enable reset clocks\n");
918 goto disable_vdd;
919 }
920
921 ret = q6v5_reset_deassert(qproc);
922 if (ret) {
923 dev_err(qproc->dev, "failed to deassert mss restart\n");
924 goto disable_reset_clks;
925 }
926
927 ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
928 qproc->active_clk_count);
929 if (ret) {
930 dev_err(qproc->dev, "failed to enable clocks\n");
931 goto assert_reset;
932 }
933
934 /* Assign MBA image access in DDR to q6 */
935 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, true,
936 qproc->mba_phys, qproc->mba_size);
937 if (ret) {
938 dev_err(qproc->dev,
939 "assigning Q6 access to mba memory failed: %d\n", ret);
940 goto disable_active_clks;
941 }
942
943 writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
944 if (qproc->dp_size) {
945 writel(qproc->mba_phys + SZ_1M, qproc->rmb_base + RMB_PMI_CODE_START_REG);
946 writel(qproc->dp_size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
947 }
948
949 ret = q6v5proc_reset(qproc);
950 if (ret)
951 goto reclaim_mba;
952
953 ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
954 if (ret == -ETIMEDOUT) {
955 dev_err(qproc->dev, "MBA boot timed out\n");
956 goto halt_axi_ports;
957 } else if (ret != RMB_MBA_XPU_UNLOCKED &&
958 ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
959 dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
960 ret = -EINVAL;
961 goto halt_axi_ports;
962 }
963
964 qproc->dump_mba_loaded = true;
965 return 0;
966
967halt_axi_ports:
968 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
969 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
970 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
971 mba_load_err = true;
972reclaim_mba:
973 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
974 false, qproc->mba_phys,
975 qproc->mba_size);
976 if (xfermemop_ret) {
977 dev_err(qproc->dev,
978 "Failed to reclaim mba buffer, system may become unstable\n");
979 } else if (mba_load_err) {
980 q6v5_dump_mba_logs(qproc);
981 }
982
983disable_active_clks:
984 q6v5_clk_disable(qproc->dev, qproc->active_clks,
985 qproc->active_clk_count);
986assert_reset:
987 q6v5_reset_assert(qproc);
988disable_reset_clks:
989 q6v5_clk_disable(qproc->dev, qproc->reset_clks,
990 qproc->reset_clk_count);
991disable_vdd:
992 q6v5_regulator_disable(qproc, qproc->active_regs,
993 qproc->active_reg_count);
994disable_proxy_clk:
995 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
996 qproc->proxy_clk_count);
997disable_proxy_reg:
998 q6v5_regulator_disable(qproc, qproc->proxy_regs,
999 qproc->proxy_reg_count);
1000disable_proxy_pds:
1001 q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1002disable_active_pds:
1003 q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
1004disable_irqs:
1005 qcom_q6v5_unprepare(&qproc->q6v5);
1006
1007 return ret;
1008}
1009
1010static void q6v5_mba_reclaim(struct q6v5 *qproc)
1011{
1012 int ret;
1013 u32 val;
1014
1015 qproc->dump_mba_loaded = false;
1016 qproc->dp_size = 0;
1017
1018 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
1019 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
1020 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
1021 if (qproc->version == MSS_MSM8996) {
1022 /*
1023 * To avoid high MX current during LPASS/MSS restart.
1024 */
1025 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1026 val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL |
1027 QDSP6v56_CLAMP_QMC_MEM;
1028 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1029 }
1030
1031 q6v5_reset_assert(qproc);
1032
1033 q6v5_clk_disable(qproc->dev, qproc->reset_clks,
1034 qproc->reset_clk_count);
1035 q6v5_clk_disable(qproc->dev, qproc->active_clks,
1036 qproc->active_clk_count);
1037 q6v5_regulator_disable(qproc, qproc->active_regs,
1038 qproc->active_reg_count);
1039 q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
1040
1041 /* In case of failure or coredump scenario where reclaiming MBA memory
1042 * could not happen reclaim it here.
1043 */
1044 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false,
1045 qproc->mba_phys,
1046 qproc->mba_size);
1047 WARN_ON(ret);
1048
1049 ret = qcom_q6v5_unprepare(&qproc->q6v5);
1050 if (ret) {
1051 q6v5_pds_disable(qproc, qproc->proxy_pds,
1052 qproc->proxy_pd_count);
1053 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1054 qproc->proxy_clk_count);
1055 q6v5_regulator_disable(qproc, qproc->proxy_regs,
1056 qproc->proxy_reg_count);
1057 }
1058}
1059
1060static int q6v5_reload_mba(struct rproc *rproc)
1061{
1062 struct q6v5 *qproc = rproc->priv;
1063 const struct firmware *fw;
1064 int ret;
1065
1066 ret = request_firmware(&fw, rproc->firmware, qproc->dev);
1067 if (ret < 0)
1068 return ret;
1069
1070 q6v5_load(rproc, fw);
1071 ret = q6v5_mba_load(qproc);
1072 release_firmware(fw);
1073
1074 return ret;
1075}
1076
1077static int q6v5_mpss_load(struct q6v5 *qproc)
1078{
1079 const struct elf32_phdr *phdrs;
1080 const struct elf32_phdr *phdr;
1081 const struct firmware *seg_fw;
1082 const struct firmware *fw;
1083 struct elf32_hdr *ehdr;
1084 phys_addr_t mpss_reloc;
1085 phys_addr_t boot_addr;
1086 phys_addr_t min_addr = PHYS_ADDR_MAX;
1087 phys_addr_t max_addr = 0;
1088 u32 code_length;
1089 bool relocate = false;
1090 char *fw_name;
1091 size_t fw_name_len;
1092 ssize_t offset;
1093 size_t size = 0;
1094 void *ptr;
1095 int ret;
1096 int i;
1097
1098 fw_name_len = strlen(qproc->hexagon_mdt_image);
1099 if (fw_name_len <= 4)
1100 return -EINVAL;
1101
1102 fw_name = kstrdup(qproc->hexagon_mdt_image, GFP_KERNEL);
1103 if (!fw_name)
1104 return -ENOMEM;
1105
1106 ret = request_firmware(&fw, fw_name, qproc->dev);
1107 if (ret < 0) {
1108 dev_err(qproc->dev, "unable to load %s\n", fw_name);
1109 goto out;
1110 }
1111
1112 /* Initialize the RMB validator */
1113 writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1114
1115 ret = q6v5_mpss_init_image(qproc, fw);
1116 if (ret)
1117 goto release_firmware;
1118
1119 ehdr = (struct elf32_hdr *)fw->data;
1120 phdrs = (struct elf32_phdr *)(ehdr + 1);
1121
1122 for (i = 0; i < ehdr->e_phnum; i++) {
1123 phdr = &phdrs[i];
1124
1125 if (!q6v5_phdr_valid(phdr))
1126 continue;
1127
1128 if (phdr->p_flags & QCOM_MDT_RELOCATABLE)
1129 relocate = true;
1130
1131 if (phdr->p_paddr < min_addr)
1132 min_addr = phdr->p_paddr;
1133
1134 if (phdr->p_paddr + phdr->p_memsz > max_addr)
1135 max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
1136 }
1137
1138 /**
1139 * In case of a modem subsystem restart on secure devices, the modem
1140 * memory can be reclaimed only after MBA is loaded. For modem cold
1141 * boot this will be a nop
1142 */
1143 q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, false,
1144 qproc->mpss_phys, qproc->mpss_size);
1145
1146 /* Share ownership between Linux and MSS, during segment loading */
1147 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, true,
1148 qproc->mpss_phys, qproc->mpss_size);
1149 if (ret) {
1150 dev_err(qproc->dev,
1151 "assigning Q6 access to mpss memory failed: %d\n", ret);
1152 ret = -EAGAIN;
1153 goto release_firmware;
1154 }
1155
1156 mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
1157 qproc->mpss_reloc = mpss_reloc;
1158 /* Load firmware segments */
1159 for (i = 0; i < ehdr->e_phnum; i++) {
1160 phdr = &phdrs[i];
1161
1162 if (!q6v5_phdr_valid(phdr))
1163 continue;
1164
1165 offset = phdr->p_paddr - mpss_reloc;
1166 if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) {
1167 dev_err(qproc->dev, "segment outside memory range\n");
1168 ret = -EINVAL;
1169 goto release_firmware;
1170 }
1171
1172 ptr = ioremap_wc(qproc->mpss_phys + offset, phdr->p_memsz);
1173 if (!ptr) {
1174 dev_err(qproc->dev,
1175 "unable to map memory region: %pa+%zx-%x\n",
1176 &qproc->mpss_phys, offset, phdr->p_memsz);
1177 goto release_firmware;
1178 }
1179
1180 if (phdr->p_filesz && phdr->p_offset < fw->size) {
1181 /* Firmware is large enough to be non-split */
1182 if (phdr->p_offset + phdr->p_filesz > fw->size) {
1183 dev_err(qproc->dev,
1184 "failed to load segment %d from truncated file %s\n",
1185 i, fw_name);
1186 ret = -EINVAL;
1187 iounmap(ptr);
1188 goto release_firmware;
1189 }
1190
1191 memcpy(ptr, fw->data + phdr->p_offset, phdr->p_filesz);
1192 } else if (phdr->p_filesz) {
1193 /* Replace "xxx.xxx" with "xxx.bxx" */
1194 sprintf(fw_name + fw_name_len - 3, "b%02d", i);
1195 ret = request_firmware_into_buf(&seg_fw, fw_name, qproc->dev,
1196 ptr, phdr->p_filesz);
1197 if (ret) {
1198 dev_err(qproc->dev, "failed to load %s\n", fw_name);
1199 iounmap(ptr);
1200 goto release_firmware;
1201 }
1202
1203 release_firmware(seg_fw);
1204 }
1205
1206 if (phdr->p_memsz > phdr->p_filesz) {
1207 memset(ptr + phdr->p_filesz, 0,
1208 phdr->p_memsz - phdr->p_filesz);
1209 }
1210 iounmap(ptr);
1211 size += phdr->p_memsz;
1212
1213 code_length = readl(qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1214 if (!code_length) {
1215 boot_addr = relocate ? qproc->mpss_phys : min_addr;
1216 writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
1217 writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
1218 }
1219 writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1220
1221 ret = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
1222 if (ret < 0) {
1223 dev_err(qproc->dev, "MPSS authentication failed: %d\n",
1224 ret);
1225 goto release_firmware;
1226 }
1227 }
1228
1229 /* Transfer ownership of modem ddr region to q6 */
1230 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
1231 qproc->mpss_phys, qproc->mpss_size);
1232 if (ret) {
1233 dev_err(qproc->dev,
1234 "assigning Q6 access to mpss memory failed: %d\n", ret);
1235 ret = -EAGAIN;
1236 goto release_firmware;
1237 }
1238
1239 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000);
1240 if (ret == -ETIMEDOUT)
1241 dev_err(qproc->dev, "MPSS authentication timed out\n");
1242 else if (ret < 0)
1243 dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
1244
1245 qcom_pil_info_store("modem", qproc->mpss_phys, qproc->mpss_size);
1246
1247release_firmware:
1248 release_firmware(fw);
1249out:
1250 kfree(fw_name);
1251
1252 return ret < 0 ? ret : 0;
1253}
1254
1255static void qcom_q6v5_dump_segment(struct rproc *rproc,
1256 struct rproc_dump_segment *segment,
1257 void *dest, size_t cp_offset, size_t size)
1258{
1259 int ret = 0;
1260 struct q6v5 *qproc = rproc->priv;
1261 int offset = segment->da - qproc->mpss_reloc;
1262 void *ptr = NULL;
1263
1264 /* Unlock mba before copying segments */
1265 if (!qproc->dump_mba_loaded) {
1266 ret = q6v5_reload_mba(rproc);
1267 if (!ret) {
1268 /* Reset ownership back to Linux to copy segments */
1269 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1270 true, false,
1271 qproc->mpss_phys,
1272 qproc->mpss_size);
1273 }
1274 }
1275
1276 if (!ret)
1277 ptr = ioremap_wc(qproc->mpss_phys + offset + cp_offset, size);
1278
1279 if (ptr) {
1280 memcpy(dest, ptr, size);
1281 iounmap(ptr);
1282 } else {
1283 memset(dest, 0xff, size);
1284 }
1285
1286 qproc->current_dump_size += size;
1287
1288 /* Reclaim mba after copying segments */
1289 if (qproc->current_dump_size == qproc->total_dump_size) {
1290 if (qproc->dump_mba_loaded) {
1291 /* Try to reset ownership back to Q6 */
1292 q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1293 false, true,
1294 qproc->mpss_phys,
1295 qproc->mpss_size);
1296 q6v5_mba_reclaim(qproc);
1297 }
1298 }
1299}
1300
1301static int q6v5_start(struct rproc *rproc)
1302{
1303 struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1304 int xfermemop_ret;
1305 int ret;
1306
1307 ret = q6v5_mba_load(qproc);
1308 if (ret)
1309 return ret;
1310
1311 dev_info(qproc->dev, "MBA booted with%s debug policy, loading mpss\n",
1312 qproc->dp_size ? "" : "out");
1313
1314 ret = q6v5_mpss_load(qproc);
1315 if (ret)
1316 goto reclaim_mpss;
1317
1318 ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000));
1319 if (ret == -ETIMEDOUT) {
1320 dev_err(qproc->dev, "start timed out\n");
1321 goto reclaim_mpss;
1322 }
1323
1324 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
1325 false, qproc->mba_phys,
1326 qproc->mba_size);
1327 if (xfermemop_ret)
1328 dev_err(qproc->dev,
1329 "Failed to reclaim mba buffer system may become unstable\n");
1330
1331 /* Reset Dump Segment Mask */
1332 qproc->current_dump_size = 0;
1333
1334 return 0;
1335
1336reclaim_mpss:
1337 q6v5_mba_reclaim(qproc);
1338 q6v5_dump_mba_logs(qproc);
1339
1340 return ret;
1341}
1342
1343static int q6v5_stop(struct rproc *rproc)
1344{
1345 struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1346 int ret;
1347
1348 ret = qcom_q6v5_request_stop(&qproc->q6v5);
1349 if (ret == -ETIMEDOUT)
1350 dev_err(qproc->dev, "timed out on wait\n");
1351
1352 q6v5_mba_reclaim(qproc);
1353
1354 return 0;
1355}
1356
1357static int qcom_q6v5_register_dump_segments(struct rproc *rproc,
1358 const struct firmware *mba_fw)
1359{
1360 const struct firmware *fw;
1361 const struct elf32_phdr *phdrs;
1362 const struct elf32_phdr *phdr;
1363 const struct elf32_hdr *ehdr;
1364 struct q6v5 *qproc = rproc->priv;
1365 unsigned long i;
1366 int ret;
1367
1368 ret = request_firmware(&fw, qproc->hexagon_mdt_image, qproc->dev);
1369 if (ret < 0) {
1370 dev_err(qproc->dev, "unable to load %s\n",
1371 qproc->hexagon_mdt_image);
1372 return ret;
1373 }
1374
1375 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
1376
1377 ehdr = (struct elf32_hdr *)fw->data;
1378 phdrs = (struct elf32_phdr *)(ehdr + 1);
1379 qproc->total_dump_size = 0;
1380
1381 for (i = 0; i < ehdr->e_phnum; i++) {
1382 phdr = &phdrs[i];
1383
1384 if (!q6v5_phdr_valid(phdr))
1385 continue;
1386
1387 ret = rproc_coredump_add_custom_segment(rproc, phdr->p_paddr,
1388 phdr->p_memsz,
1389 qcom_q6v5_dump_segment,
1390 NULL);
1391 if (ret)
1392 break;
1393
1394 qproc->total_dump_size += phdr->p_memsz;
1395 }
1396
1397 release_firmware(fw);
1398 return ret;
1399}
1400
1401static const struct rproc_ops q6v5_ops = {
1402 .start = q6v5_start,
1403 .stop = q6v5_stop,
1404 .parse_fw = qcom_q6v5_register_dump_segments,
1405 .load = q6v5_load,
1406};
1407
1408static void qcom_msa_handover(struct qcom_q6v5 *q6v5)
1409{
1410 struct q6v5 *qproc = container_of(q6v5, struct q6v5, q6v5);
1411
1412 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1413 qproc->proxy_clk_count);
1414 q6v5_regulator_disable(qproc, qproc->proxy_regs,
1415 qproc->proxy_reg_count);
1416 q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1417}
1418
1419static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
1420{
1421 struct of_phandle_args args;
1422 struct resource *res;
1423 int ret;
1424
1425 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
1426 qproc->reg_base = devm_ioremap_resource(&pdev->dev, res);
1427 if (IS_ERR(qproc->reg_base))
1428 return PTR_ERR(qproc->reg_base);
1429
1430 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
1431 qproc->rmb_base = devm_ioremap_resource(&pdev->dev, res);
1432 if (IS_ERR(qproc->rmb_base))
1433 return PTR_ERR(qproc->rmb_base);
1434
1435 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1436 "qcom,halt-regs", 3, 0, &args);
1437 if (ret < 0) {
1438 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
1439 return -EINVAL;
1440 }
1441
1442 qproc->halt_map = syscon_node_to_regmap(args.np);
1443 of_node_put(args.np);
1444 if (IS_ERR(qproc->halt_map))
1445 return PTR_ERR(qproc->halt_map);
1446
1447 qproc->halt_q6 = args.args[0];
1448 qproc->halt_modem = args.args[1];
1449 qproc->halt_nc = args.args[2];
1450
1451 if (qproc->has_spare_reg) {
1452 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1453 "qcom,spare-regs",
1454 1, 0, &args);
1455 if (ret < 0) {
1456 dev_err(&pdev->dev, "failed to parse spare-regs\n");
1457 return -EINVAL;
1458 }
1459
1460 qproc->conn_map = syscon_node_to_regmap(args.np);
1461 of_node_put(args.np);
1462 if (IS_ERR(qproc->conn_map))
1463 return PTR_ERR(qproc->conn_map);
1464
1465 qproc->conn_box = args.args[0];
1466 }
1467
1468 return 0;
1469}
1470
1471static int q6v5_init_clocks(struct device *dev, struct clk **clks,
1472 char **clk_names)
1473{
1474 int i;
1475
1476 if (!clk_names)
1477 return 0;
1478
1479 for (i = 0; clk_names[i]; i++) {
1480 clks[i] = devm_clk_get(dev, clk_names[i]);
1481 if (IS_ERR(clks[i])) {
1482 int rc = PTR_ERR(clks[i]);
1483
1484 if (rc != -EPROBE_DEFER)
1485 dev_err(dev, "Failed to get %s clock\n",
1486 clk_names[i]);
1487 return rc;
1488 }
1489 }
1490
1491 return i;
1492}
1493
1494static int q6v5_pds_attach(struct device *dev, struct device **devs,
1495 char **pd_names)
1496{
1497 size_t num_pds = 0;
1498 int ret;
1499 int i;
1500
1501 if (!pd_names)
1502 return 0;
1503
1504 while (pd_names[num_pds])
1505 num_pds++;
1506
1507 for (i = 0; i < num_pds; i++) {
1508 devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
1509 if (IS_ERR_OR_NULL(devs[i])) {
1510 ret = PTR_ERR(devs[i]) ? : -ENODATA;
1511 goto unroll_attach;
1512 }
1513 }
1514
1515 return num_pds;
1516
1517unroll_attach:
1518 for (i--; i >= 0; i--)
1519 dev_pm_domain_detach(devs[i], false);
1520
1521 return ret;
1522}
1523
1524static void q6v5_pds_detach(struct q6v5 *qproc, struct device **pds,
1525 size_t pd_count)
1526{
1527 int i;
1528
1529 for (i = 0; i < pd_count; i++)
1530 dev_pm_domain_detach(pds[i], false);
1531}
1532
1533static int q6v5_init_reset(struct q6v5 *qproc)
1534{
1535 qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
1536 "mss_restart");
1537 if (IS_ERR(qproc->mss_restart)) {
1538 dev_err(qproc->dev, "failed to acquire mss restart\n");
1539 return PTR_ERR(qproc->mss_restart);
1540 }
1541
1542 if (qproc->has_alt_reset || qproc->has_spare_reg) {
1543 qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
1544 "pdc_reset");
1545 if (IS_ERR(qproc->pdc_reset)) {
1546 dev_err(qproc->dev, "failed to acquire pdc reset\n");
1547 return PTR_ERR(qproc->pdc_reset);
1548 }
1549 }
1550
1551 return 0;
1552}
1553
1554static int q6v5_alloc_memory_region(struct q6v5 *qproc)
1555{
1556 struct device_node *child;
1557 struct device_node *node;
1558 struct resource r;
1559 int ret;
1560
1561 /*
1562 * In the absence of mba/mpss sub-child, extract the mba and mpss
1563 * reserved memory regions from device's memory-region property.
1564 */
1565 child = of_get_child_by_name(qproc->dev->of_node, "mba");
1566 if (!child)
1567 node = of_parse_phandle(qproc->dev->of_node,
1568 "memory-region", 0);
1569 else
1570 node = of_parse_phandle(child, "memory-region", 0);
1571
1572 ret = of_address_to_resource(node, 0, &r);
1573 if (ret) {
1574 dev_err(qproc->dev, "unable to resolve mba region\n");
1575 return ret;
1576 }
1577 of_node_put(node);
1578
1579 qproc->mba_phys = r.start;
1580 qproc->mba_size = resource_size(&r);
1581 qproc->mba_region = devm_ioremap_wc(qproc->dev, qproc->mba_phys, qproc->mba_size);
1582 if (!qproc->mba_region) {
1583 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
1584 &r.start, qproc->mba_size);
1585 return -EBUSY;
1586 }
1587
1588 if (!child) {
1589 node = of_parse_phandle(qproc->dev->of_node,
1590 "memory-region", 1);
1591 } else {
1592 child = of_get_child_by_name(qproc->dev->of_node, "mpss");
1593 node = of_parse_phandle(child, "memory-region", 0);
1594 }
1595
1596 ret = of_address_to_resource(node, 0, &r);
1597 if (ret) {
1598 dev_err(qproc->dev, "unable to resolve mpss region\n");
1599 return ret;
1600 }
1601 of_node_put(node);
1602
1603 qproc->mpss_phys = qproc->mpss_reloc = r.start;
1604 qproc->mpss_size = resource_size(&r);
1605
1606 return 0;
1607}
1608
1609static int q6v5_probe(struct platform_device *pdev)
1610{
1611 const struct rproc_hexagon_res *desc;
1612 struct q6v5 *qproc;
1613 struct rproc *rproc;
1614 const char *mba_image;
1615 int ret;
1616
1617 desc = of_device_get_match_data(&pdev->dev);
1618 if (!desc)
1619 return -EINVAL;
1620
1621 if (desc->need_mem_protection && !qcom_scm_is_available())
1622 return -EPROBE_DEFER;
1623
1624 mba_image = desc->hexagon_mba_image;
1625 ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1626 0, &mba_image);
1627 if (ret < 0 && ret != -EINVAL)
1628 return ret;
1629
1630 rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
1631 mba_image, sizeof(*qproc));
1632 if (!rproc) {
1633 dev_err(&pdev->dev, "failed to allocate rproc\n");
1634 return -ENOMEM;
1635 }
1636
1637 rproc->auto_boot = false;
1638 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
1639
1640 qproc = (struct q6v5 *)rproc->priv;
1641 qproc->dev = &pdev->dev;
1642 qproc->rproc = rproc;
1643 qproc->hexagon_mdt_image = "modem.mdt";
1644 ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1645 1, &qproc->hexagon_mdt_image);
1646 if (ret < 0 && ret != -EINVAL)
1647 goto free_rproc;
1648
1649 platform_set_drvdata(pdev, qproc);
1650
1651 qproc->has_spare_reg = desc->has_spare_reg;
1652 ret = q6v5_init_mem(qproc, pdev);
1653 if (ret)
1654 goto free_rproc;
1655
1656 ret = q6v5_alloc_memory_region(qproc);
1657 if (ret)
1658 goto free_rproc;
1659
1660 ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks,
1661 desc->proxy_clk_names);
1662 if (ret < 0) {
1663 dev_err(&pdev->dev, "Failed to get proxy clocks.\n");
1664 goto free_rproc;
1665 }
1666 qproc->proxy_clk_count = ret;
1667
1668 ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
1669 desc->reset_clk_names);
1670 if (ret < 0) {
1671 dev_err(&pdev->dev, "Failed to get reset clocks.\n");
1672 goto free_rproc;
1673 }
1674 qproc->reset_clk_count = ret;
1675
1676 ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
1677 desc->active_clk_names);
1678 if (ret < 0) {
1679 dev_err(&pdev->dev, "Failed to get active clocks.\n");
1680 goto free_rproc;
1681 }
1682 qproc->active_clk_count = ret;
1683
1684 ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs,
1685 desc->proxy_supply);
1686 if (ret < 0) {
1687 dev_err(&pdev->dev, "Failed to get proxy regulators.\n");
1688 goto free_rproc;
1689 }
1690 qproc->proxy_reg_count = ret;
1691
1692 ret = q6v5_regulator_init(&pdev->dev, qproc->active_regs,
1693 desc->active_supply);
1694 if (ret < 0) {
1695 dev_err(&pdev->dev, "Failed to get active regulators.\n");
1696 goto free_rproc;
1697 }
1698 qproc->active_reg_count = ret;
1699
1700 ret = q6v5_pds_attach(&pdev->dev, qproc->active_pds,
1701 desc->active_pd_names);
1702 if (ret < 0) {
1703 dev_err(&pdev->dev, "Failed to attach active power domains\n");
1704 goto free_rproc;
1705 }
1706 qproc->active_pd_count = ret;
1707
1708 ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds,
1709 desc->proxy_pd_names);
1710 if (ret < 0) {
1711 dev_err(&pdev->dev, "Failed to init power domains\n");
1712 goto detach_active_pds;
1713 }
1714 qproc->proxy_pd_count = ret;
1715
1716 qproc->has_alt_reset = desc->has_alt_reset;
1717 ret = q6v5_init_reset(qproc);
1718 if (ret)
1719 goto detach_proxy_pds;
1720
1721 qproc->version = desc->version;
1722 qproc->need_mem_protection = desc->need_mem_protection;
1723 qproc->has_mba_logs = desc->has_mba_logs;
1724
1725 ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM,
1726 qcom_msa_handover);
1727 if (ret)
1728 goto detach_proxy_pds;
1729
1730 qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
1731 qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
1732 qcom_add_glink_subdev(rproc, &qproc->glink_subdev, "mpss");
1733 qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
1734 qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
1735 qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
1736 if (IS_ERR(qproc->sysmon)) {
1737 ret = PTR_ERR(qproc->sysmon);
1738 goto remove_subdevs;
1739 }
1740
1741 ret = rproc_add(rproc);
1742 if (ret)
1743 goto remove_sysmon_subdev;
1744
1745 return 0;
1746
1747remove_sysmon_subdev:
1748 qcom_remove_sysmon_subdev(qproc->sysmon);
1749remove_subdevs:
1750 qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
1751 qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
1752 qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
1753detach_proxy_pds:
1754 q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1755detach_active_pds:
1756 q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
1757free_rproc:
1758 rproc_free(rproc);
1759
1760 return ret;
1761}
1762
1763static int q6v5_remove(struct platform_device *pdev)
1764{
1765 struct q6v5 *qproc = platform_get_drvdata(pdev);
1766 struct rproc *rproc = qproc->rproc;
1767
1768 rproc_del(rproc);
1769
1770 qcom_remove_sysmon_subdev(qproc->sysmon);
1771 qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
1772 qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
1773 qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
1774
1775 q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1776 q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
1777
1778 rproc_free(rproc);
1779
1780 return 0;
1781}
1782
1783static const struct rproc_hexagon_res sc7180_mss = {
1784 .hexagon_mba_image = "mba.mbn",
1785 .proxy_clk_names = (char*[]){
1786 "xo",
1787 NULL
1788 },
1789 .reset_clk_names = (char*[]){
1790 "iface",
1791 "bus",
1792 "snoc_axi",
1793 NULL
1794 },
1795 .active_clk_names = (char*[]){
1796 "mnoc_axi",
1797 "nav",
1798 NULL
1799 },
1800 .active_pd_names = (char*[]){
1801 "load_state",
1802 NULL
1803 },
1804 .proxy_pd_names = (char*[]){
1805 "cx",
1806 "mx",
1807 "mss",
1808 NULL
1809 },
1810 .need_mem_protection = true,
1811 .has_alt_reset = false,
1812 .has_mba_logs = true,
1813 .has_spare_reg = true,
1814 .version = MSS_SC7180,
1815};
1816
1817static const struct rproc_hexagon_res sdm845_mss = {
1818 .hexagon_mba_image = "mba.mbn",
1819 .proxy_clk_names = (char*[]){
1820 "xo",
1821 "prng",
1822 NULL
1823 },
1824 .reset_clk_names = (char*[]){
1825 "iface",
1826 "snoc_axi",
1827 NULL
1828 },
1829 .active_clk_names = (char*[]){
1830 "bus",
1831 "mem",
1832 "gpll0_mss",
1833 "mnoc_axi",
1834 NULL
1835 },
1836 .active_pd_names = (char*[]){
1837 "load_state",
1838 NULL
1839 },
1840 .proxy_pd_names = (char*[]){
1841 "cx",
1842 "mx",
1843 "mss",
1844 NULL
1845 },
1846 .need_mem_protection = true,
1847 .has_alt_reset = true,
1848 .has_mba_logs = false,
1849 .has_spare_reg = false,
1850 .version = MSS_SDM845,
1851};
1852
1853static const struct rproc_hexagon_res msm8998_mss = {
1854 .hexagon_mba_image = "mba.mbn",
1855 .proxy_clk_names = (char*[]){
1856 "xo",
1857 "qdss",
1858 "mem",
1859 NULL
1860 },
1861 .active_clk_names = (char*[]){
1862 "iface",
1863 "bus",
1864 "gpll0_mss",
1865 "mnoc_axi",
1866 "snoc_axi",
1867 NULL
1868 },
1869 .proxy_pd_names = (char*[]){
1870 "cx",
1871 "mx",
1872 NULL
1873 },
1874 .need_mem_protection = true,
1875 .has_alt_reset = false,
1876 .has_mba_logs = false,
1877 .has_spare_reg = false,
1878 .version = MSS_MSM8998,
1879};
1880
1881static const struct rproc_hexagon_res msm8996_mss = {
1882 .hexagon_mba_image = "mba.mbn",
1883 .proxy_supply = (struct qcom_mss_reg_res[]) {
1884 {
1885 .supply = "pll",
1886 .uA = 100000,
1887 },
1888 {}
1889 },
1890 .proxy_clk_names = (char*[]){
1891 "xo",
1892 "pnoc",
1893 "qdss",
1894 NULL
1895 },
1896 .active_clk_names = (char*[]){
1897 "iface",
1898 "bus",
1899 "mem",
1900 "gpll0_mss",
1901 "snoc_axi",
1902 "mnoc_axi",
1903 NULL
1904 },
1905 .need_mem_protection = true,
1906 .has_alt_reset = false,
1907 .has_mba_logs = false,
1908 .has_spare_reg = false,
1909 .version = MSS_MSM8996,
1910};
1911
1912static const struct rproc_hexagon_res msm8916_mss = {
1913 .hexagon_mba_image = "mba.mbn",
1914 .proxy_supply = (struct qcom_mss_reg_res[]) {
1915 {
1916 .supply = "mx",
1917 .uV = 1050000,
1918 },
1919 {
1920 .supply = "cx",
1921 .uA = 100000,
1922 },
1923 {
1924 .supply = "pll",
1925 .uA = 100000,
1926 },
1927 {}
1928 },
1929 .proxy_clk_names = (char*[]){
1930 "xo",
1931 NULL
1932 },
1933 .active_clk_names = (char*[]){
1934 "iface",
1935 "bus",
1936 "mem",
1937 NULL
1938 },
1939 .need_mem_protection = false,
1940 .has_alt_reset = false,
1941 .has_mba_logs = false,
1942 .has_spare_reg = false,
1943 .version = MSS_MSM8916,
1944};
1945
1946static const struct rproc_hexagon_res msm8974_mss = {
1947 .hexagon_mba_image = "mba.b00",
1948 .proxy_supply = (struct qcom_mss_reg_res[]) {
1949 {
1950 .supply = "mx",
1951 .uV = 1050000,
1952 },
1953 {
1954 .supply = "cx",
1955 .uA = 100000,
1956 },
1957 {
1958 .supply = "pll",
1959 .uA = 100000,
1960 },
1961 {}
1962 },
1963 .active_supply = (struct qcom_mss_reg_res[]) {
1964 {
1965 .supply = "mss",
1966 .uV = 1050000,
1967 .uA = 100000,
1968 },
1969 {}
1970 },
1971 .proxy_clk_names = (char*[]){
1972 "xo",
1973 NULL
1974 },
1975 .active_clk_names = (char*[]){
1976 "iface",
1977 "bus",
1978 "mem",
1979 NULL
1980 },
1981 .need_mem_protection = false,
1982 .has_alt_reset = false,
1983 .has_mba_logs = false,
1984 .has_spare_reg = false,
1985 .version = MSS_MSM8974,
1986};
1987
1988static const struct of_device_id q6v5_of_match[] = {
1989 { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
1990 { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
1991 { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
1992 { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
1993 { .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
1994 { .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss},
1995 { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
1996 { },
1997};
1998MODULE_DEVICE_TABLE(of, q6v5_of_match);
1999
2000static struct platform_driver q6v5_driver = {
2001 .probe = q6v5_probe,
2002 .remove = q6v5_remove,
2003 .driver = {
2004 .name = "qcom-q6v5-mss",
2005 .of_match_table = q6v5_of_match,
2006 },
2007};
2008module_platform_driver(q6v5_driver);
2009
2010MODULE_DESCRIPTION("Qualcomm Self-authenticating modem remoteproc driver");
2011MODULE_LICENSE("GPL v2");