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1// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2/*
3 * Mellanox platform driver
4 *
5 * Copyright (C) 2016-2018 Mellanox Technologies
6 * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com>
7 */
8
9#include <linux/device.h>
10#include <linux/dmi.h>
11#include <linux/i2c.h>
12#include <linux/i2c-mux.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/platform_data/i2c-mux-reg.h>
17#include <linux/platform_data/mlxreg.h>
18#include <linux/regmap.h>
19
20#define MLX_PLAT_DEVICE_NAME "mlxplat"
21
22/* LPC bus IO offsets */
23#define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000
24#define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500
25#define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00
26#define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01
27#define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02
28#define MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET 0x03
29#define MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET 0x04
30#define MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET 0x06
31#define MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET 0x08
32#define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET 0x0a
33#define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d
34#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e
35#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f
36#define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20
37#define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21
38#define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22
39#define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23
40#define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24
41#define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a
42#define MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET 0x2b
43#define MLXPLAT_CPLD_LPC_REG_GP0_OFFSET 0x2e
44#define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30
45#define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31
46#define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32
47#define MLXPLAT_CPLD_LPC_REG_WP2_OFFSET 0x33
48#define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37
49#define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a
50#define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b
51#define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40
52#define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41
53#define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42
54#define MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET 0x43
55#define MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET 0x44
56#define MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET 0x45
57#define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50
58#define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51
59#define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52
60#define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58
61#define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0x59
62#define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0x5a
63#define MLXPLAT_CPLD_LPC_REG_PWR_OFFSET 0x64
64#define MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET 0x65
65#define MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET 0x66
66#define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88
67#define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89
68#define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a
69#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7
70#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0xc8
71#define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0xc9
72#define MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET 0xcb
73#define MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET 0xcd
74#define MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET 0xce
75#define MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET 0xcf
76#define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET 0xd1
77#define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2
78#define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3
79#define MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET 0xde
80#define MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET 0xdf
81#define MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET 0xe0
82#define MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET 0xe1
83#define MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET 0xe2
84#define MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET 0xe3
85#define MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET 0xe4
86#define MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET 0xe5
87#define MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET 0xe6
88#define MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET 0xe7
89#define MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET 0xe8
90#define MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET 0xe9
91#define MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET 0xeb
92#define MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET 0xec
93#define MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET 0xed
94#define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xee
95#define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xef
96#define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xf0
97#define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET 0xf5
98#define MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET 0xf6
99#define MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET 0xf7
100#define MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET 0xf8
101#define MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET 0xf9
102#define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0xfb
103#define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc
104#define MLXPLAT_CPLD_LPC_IO_RANGE 0x100
105#define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb
106#define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda
107#define MLXPLAT_CPLD_LPC_I2C_CH3_OFF 0xdc
108
109#define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL
110#define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
111 MLXPLAT_CPLD_LPC_I2C_CH1_OFF) | \
112 MLXPLAT_CPLD_LPC_PIO_OFFSET)
113#define MLXPLAT_CPLD_LPC_REG2 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
114 MLXPLAT_CPLD_LPC_I2C_CH2_OFF) | \
115 MLXPLAT_CPLD_LPC_PIO_OFFSET)
116#define MLXPLAT_CPLD_LPC_REG3 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
117 MLXPLAT_CPLD_LPC_I2C_CH3_OFF) | \
118 MLXPLAT_CPLD_LPC_PIO_OFFSET)
119
120/* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */
121#define MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF 0x04
122#define MLXPLAT_CPLD_AGGR_PSU_MASK_DEF 0x08
123#define MLXPLAT_CPLD_AGGR_PWR_MASK_DEF 0x08
124#define MLXPLAT_CPLD_AGGR_FAN_MASK_DEF 0x40
125#define MLXPLAT_CPLD_AGGR_MASK_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \
126 MLXPLAT_CPLD_AGGR_PSU_MASK_DEF | \
127 MLXPLAT_CPLD_AGGR_FAN_MASK_DEF)
128#define MLXPLAT_CPLD_AGGR_ASIC_MASK_NG 0x01
129#define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04
130#define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0)
131#define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1
132#define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6)
133#define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0)
134#define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0)
135#define MLXPLAT_CPLD_PSU_EXT_MASK GENMASK(3, 0)
136#define MLXPLAT_CPLD_PWR_EXT_MASK GENMASK(3, 0)
137#define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0)
138#define MLXPLAT_CPLD_ASIC_MASK GENMASK(1, 0)
139#define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(5, 0)
140#define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4)
141#define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0)
142#define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4)
143#define MLXPLAT_CPLD_I2C_CAP_BIT 0x04
144#define MLXPLAT_CPLD_I2C_CAP_MASK GENMASK(5, MLXPLAT_CPLD_I2C_CAP_BIT)
145
146/* Masks for aggregation for comex carriers */
147#define MLXPLAT_CPLD_AGGR_MASK_CARRIER BIT(1)
148#define MLXPLAT_CPLD_AGGR_MASK_CARR_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \
149 MLXPLAT_CPLD_AGGR_MASK_CARRIER)
150#define MLXPLAT_CPLD_LOW_AGGRCX_MASK 0xc1
151
152/* Default I2C parent bus number */
153#define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1
154
155/* Maximum number of possible physical buses equipped on system */
156#define MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM 16
157#define MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM 24
158
159/* Number of channels in group */
160#define MLXPLAT_CPLD_GRP_CHNL_NUM 8
161
162/* Start channel numbers */
163#define MLXPLAT_CPLD_CH1 2
164#define MLXPLAT_CPLD_CH2 10
165#define MLXPLAT_CPLD_CH3 18
166
167/* Number of LPC attached MUX platform devices */
168#define MLXPLAT_CPLD_LPC_MUX_DEVS 3
169
170/* Hotplug devices adapter numbers */
171#define MLXPLAT_CPLD_NR_NONE -1
172#define MLXPLAT_CPLD_PSU_DEFAULT_NR 10
173#define MLXPLAT_CPLD_PSU_MSNXXXX_NR 4
174#define MLXPLAT_CPLD_FAN1_DEFAULT_NR 11
175#define MLXPLAT_CPLD_FAN2_DEFAULT_NR 12
176#define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13
177#define MLXPLAT_CPLD_FAN4_DEFAULT_NR 14
178
179/* Masks and default values for watchdogs */
180#define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1)
181#define MLXPLAT_CPLD_WD2_CLEAR_MASK (GENMASK(7, 0) & ~BIT(1))
182
183#define MLXPLAT_CPLD_WD_TYPE1_TO_MASK GENMASK(7, 4)
184#define MLXPLAT_CPLD_WD_TYPE2_TO_MASK 0
185#define MLXPLAT_CPLD_WD_RESET_ACT_MASK GENMASK(7, 1)
186#define MLXPLAT_CPLD_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4))
187#define MLXPLAT_CPLD_WD_COUNT_ACT_MASK (GENMASK(7, 0) & ~BIT(7))
188#define MLXPLAT_CPLD_WD_CPBLTY_MASK (GENMASK(7, 0) & ~BIT(6))
189#define MLXPLAT_CPLD_WD_DFLT_TIMEOUT 30
190#define MLXPLAT_CPLD_WD3_DFLT_TIMEOUT 600
191#define MLXPLAT_CPLD_WD_MAX_DEVS 2
192
193/* mlxplat_priv - platform private data
194 * @pdev_i2c - i2c controller platform device
195 * @pdev_mux - array of mux platform devices
196 * @pdev_hotplug - hotplug platform devices
197 * @pdev_led - led platform devices
198 * @pdev_io_regs - register access platform devices
199 * @pdev_fan - FAN platform devices
200 * @pdev_wd - array of watchdog platform devices
201 * @regmap: device register map
202 */
203struct mlxplat_priv {
204 struct platform_device *pdev_i2c;
205 struct platform_device *pdev_mux[MLXPLAT_CPLD_LPC_MUX_DEVS];
206 struct platform_device *pdev_hotplug;
207 struct platform_device *pdev_led;
208 struct platform_device *pdev_io_regs;
209 struct platform_device *pdev_fan;
210 struct platform_device *pdev_wd[MLXPLAT_CPLD_WD_MAX_DEVS];
211 void *regmap;
212};
213
214/* Regions for LPC I2C controller and LPC base register space */
215static const struct resource mlxplat_lpc_resources[] = {
216 [0] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_I2C_BASE_ADRR,
217 MLXPLAT_CPLD_LPC_IO_RANGE,
218 "mlxplat_cpld_lpc_i2c_ctrl", IORESOURCE_IO),
219 [1] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_REG_BASE_ADRR,
220 MLXPLAT_CPLD_LPC_IO_RANGE,
221 "mlxplat_cpld_lpc_regs",
222 IORESOURCE_IO),
223};
224
225/* Platform i2c next generation systems data */
226static struct mlxreg_core_data mlxplat_mlxcpld_i2c_ng_items_data[] = {
227 {
228 .reg = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
229 .mask = MLXPLAT_CPLD_I2C_CAP_MASK,
230 .bit = MLXPLAT_CPLD_I2C_CAP_BIT,
231 },
232};
233
234static struct mlxreg_core_item mlxplat_mlxcpld_i2c_ng_items[] = {
235 {
236 .data = mlxplat_mlxcpld_i2c_ng_items_data,
237 },
238};
239
240/* Platform next generation systems i2c data */
241static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_ng_data = {
242 .items = mlxplat_mlxcpld_i2c_ng_items,
243 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
244 .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX,
245 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET,
246 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_I2C,
247};
248
249/* Platform default channels */
250static const int mlxplat_default_channels[][MLXPLAT_CPLD_GRP_CHNL_NUM] = {
251 {
252 MLXPLAT_CPLD_CH1, MLXPLAT_CPLD_CH1 + 1, MLXPLAT_CPLD_CH1 + 2,
253 MLXPLAT_CPLD_CH1 + 3, MLXPLAT_CPLD_CH1 + 4, MLXPLAT_CPLD_CH1 +
254 5, MLXPLAT_CPLD_CH1 + 6, MLXPLAT_CPLD_CH1 + 7
255 },
256 {
257 MLXPLAT_CPLD_CH2, MLXPLAT_CPLD_CH2 + 1, MLXPLAT_CPLD_CH2 + 2,
258 MLXPLAT_CPLD_CH2 + 3, MLXPLAT_CPLD_CH2 + 4, MLXPLAT_CPLD_CH2 +
259 5, MLXPLAT_CPLD_CH2 + 6, MLXPLAT_CPLD_CH2 + 7
260 },
261};
262
263/* Platform channels for MSN21xx system family */
264static const int mlxplat_msn21xx_channels[] = { 1, 2, 3, 4, 5, 6, 7, 8 };
265
266/* Platform mux data */
267static struct i2c_mux_reg_platform_data mlxplat_default_mux_data[] = {
268 {
269 .parent = 1,
270 .base_nr = MLXPLAT_CPLD_CH1,
271 .write_only = 1,
272 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1,
273 .reg_size = 1,
274 .idle_in_use = 1,
275 },
276 {
277 .parent = 1,
278 .base_nr = MLXPLAT_CPLD_CH2,
279 .write_only = 1,
280 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2,
281 .reg_size = 1,
282 .idle_in_use = 1,
283 },
284
285};
286
287/* Platform mux configuration variables */
288static int mlxplat_max_adap_num;
289static int mlxplat_mux_num;
290static struct i2c_mux_reg_platform_data *mlxplat_mux_data;
291
292/* Platform extended mux data */
293static struct i2c_mux_reg_platform_data mlxplat_extended_mux_data[] = {
294 {
295 .parent = 1,
296 .base_nr = MLXPLAT_CPLD_CH1,
297 .write_only = 1,
298 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1,
299 .reg_size = 1,
300 .idle_in_use = 1,
301 },
302 {
303 .parent = 1,
304 .base_nr = MLXPLAT_CPLD_CH2,
305 .write_only = 1,
306 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3,
307 .reg_size = 1,
308 .idle_in_use = 1,
309 },
310 {
311 .parent = 1,
312 .base_nr = MLXPLAT_CPLD_CH3,
313 .write_only = 1,
314 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2,
315 .reg_size = 1,
316 .idle_in_use = 1,
317 },
318
319};
320
321/* Platform hotplug devices */
322static struct i2c_board_info mlxplat_mlxcpld_psu[] = {
323 {
324 I2C_BOARD_INFO("24c02", 0x51),
325 },
326 {
327 I2C_BOARD_INFO("24c02", 0x50),
328 },
329};
330
331static struct i2c_board_info mlxplat_mlxcpld_ng_psu[] = {
332 {
333 I2C_BOARD_INFO("24c32", 0x51),
334 },
335 {
336 I2C_BOARD_INFO("24c32", 0x50),
337 },
338};
339
340static struct i2c_board_info mlxplat_mlxcpld_pwr[] = {
341 {
342 I2C_BOARD_INFO("dps460", 0x59),
343 },
344 {
345 I2C_BOARD_INFO("dps460", 0x58),
346 },
347};
348
349static struct i2c_board_info mlxplat_mlxcpld_ext_pwr[] = {
350 {
351 I2C_BOARD_INFO("dps460", 0x5b),
352 },
353 {
354 I2C_BOARD_INFO("dps460", 0x5a),
355 },
356};
357
358static struct i2c_board_info mlxplat_mlxcpld_fan[] = {
359 {
360 I2C_BOARD_INFO("24c32", 0x50),
361 },
362 {
363 I2C_BOARD_INFO("24c32", 0x50),
364 },
365 {
366 I2C_BOARD_INFO("24c32", 0x50),
367 },
368 {
369 I2C_BOARD_INFO("24c32", 0x50),
370 },
371};
372
373/* Platform hotplug comex carrier system family data */
374static struct mlxreg_core_data mlxplat_mlxcpld_comex_psu_items_data[] = {
375 {
376 .label = "psu1",
377 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
378 .mask = BIT(0),
379 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
380 },
381 {
382 .label = "psu2",
383 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
384 .mask = BIT(1),
385 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
386 },
387};
388
389/* Platform hotplug default data */
390static struct mlxreg_core_data mlxplat_mlxcpld_default_psu_items_data[] = {
391 {
392 .label = "psu1",
393 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
394 .mask = BIT(0),
395 .hpdev.brdinfo = &mlxplat_mlxcpld_psu[0],
396 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR,
397 },
398 {
399 .label = "psu2",
400 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
401 .mask = BIT(1),
402 .hpdev.brdinfo = &mlxplat_mlxcpld_psu[1],
403 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR,
404 },
405};
406
407static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_items_data[] = {
408 {
409 .label = "pwr1",
410 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
411 .mask = BIT(0),
412 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0],
413 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR,
414 },
415 {
416 .label = "pwr2",
417 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
418 .mask = BIT(1),
419 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1],
420 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR,
421 },
422};
423
424static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = {
425 {
426 .label = "fan1",
427 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
428 .mask = BIT(0),
429 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[0],
430 .hpdev.nr = MLXPLAT_CPLD_FAN1_DEFAULT_NR,
431 },
432 {
433 .label = "fan2",
434 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
435 .mask = BIT(1),
436 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[1],
437 .hpdev.nr = MLXPLAT_CPLD_FAN2_DEFAULT_NR,
438 },
439 {
440 .label = "fan3",
441 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
442 .mask = BIT(2),
443 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[2],
444 .hpdev.nr = MLXPLAT_CPLD_FAN3_DEFAULT_NR,
445 },
446 {
447 .label = "fan4",
448 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
449 .mask = BIT(3),
450 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[3],
451 .hpdev.nr = MLXPLAT_CPLD_FAN4_DEFAULT_NR,
452 },
453};
454
455static struct mlxreg_core_data mlxplat_mlxcpld_default_asic_items_data[] = {
456 {
457 .label = "asic1",
458 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
459 .mask = MLXPLAT_CPLD_ASIC_MASK,
460 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
461 },
462};
463
464static struct mlxreg_core_item mlxplat_mlxcpld_default_items[] = {
465 {
466 .data = mlxplat_mlxcpld_default_psu_items_data,
467 .aggr_mask = MLXPLAT_CPLD_AGGR_PSU_MASK_DEF,
468 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
469 .mask = MLXPLAT_CPLD_PSU_MASK,
470 .count = ARRAY_SIZE(mlxplat_mlxcpld_psu),
471 .inversed = 1,
472 .health = false,
473 },
474 {
475 .data = mlxplat_mlxcpld_default_pwr_items_data,
476 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF,
477 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
478 .mask = MLXPLAT_CPLD_PWR_MASK,
479 .count = ARRAY_SIZE(mlxplat_mlxcpld_pwr),
480 .inversed = 0,
481 .health = false,
482 },
483 {
484 .data = mlxplat_mlxcpld_default_fan_items_data,
485 .aggr_mask = MLXPLAT_CPLD_AGGR_FAN_MASK_DEF,
486 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
487 .mask = MLXPLAT_CPLD_FAN_MASK,
488 .count = ARRAY_SIZE(mlxplat_mlxcpld_fan),
489 .inversed = 1,
490 .health = false,
491 },
492 {
493 .data = mlxplat_mlxcpld_default_asic_items_data,
494 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
495 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
496 .mask = MLXPLAT_CPLD_ASIC_MASK,
497 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
498 .inversed = 0,
499 .health = true,
500 },
501};
502
503static struct mlxreg_core_item mlxplat_mlxcpld_comex_items[] = {
504 {
505 .data = mlxplat_mlxcpld_comex_psu_items_data,
506 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER,
507 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
508 .mask = MLXPLAT_CPLD_PSU_MASK,
509 .count = ARRAY_SIZE(mlxplat_mlxcpld_psu),
510 .inversed = 1,
511 .health = false,
512 },
513 {
514 .data = mlxplat_mlxcpld_default_pwr_items_data,
515 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER,
516 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
517 .mask = MLXPLAT_CPLD_PWR_MASK,
518 .count = ARRAY_SIZE(mlxplat_mlxcpld_pwr),
519 .inversed = 0,
520 .health = false,
521 },
522 {
523 .data = mlxplat_mlxcpld_default_fan_items_data,
524 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER,
525 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
526 .mask = MLXPLAT_CPLD_FAN_MASK,
527 .count = ARRAY_SIZE(mlxplat_mlxcpld_fan),
528 .inversed = 1,
529 .health = false,
530 },
531 {
532 .data = mlxplat_mlxcpld_default_asic_items_data,
533 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
534 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
535 .mask = MLXPLAT_CPLD_ASIC_MASK,
536 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
537 .inversed = 0,
538 .health = true,
539 },
540};
541
542static
543struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_data = {
544 .items = mlxplat_mlxcpld_default_items,
545 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_items),
546 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
547 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
548 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
549 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
550};
551
552static
553struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_comex_data = {
554 .items = mlxplat_mlxcpld_comex_items,
555 .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_items),
556 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
557 .mask = MLXPLAT_CPLD_AGGR_MASK_CARR_DEF,
558 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET,
559 .mask_low = MLXPLAT_CPLD_LOW_AGGRCX_MASK,
560};
561
562static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_pwr_items_data[] = {
563 {
564 .label = "pwr1",
565 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
566 .mask = BIT(0),
567 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
568 },
569 {
570 .label = "pwr2",
571 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
572 .mask = BIT(1),
573 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
574 },
575};
576
577/* Platform hotplug MSN21xx system family data */
578static struct mlxreg_core_item mlxplat_mlxcpld_msn21xx_items[] = {
579 {
580 .data = mlxplat_mlxcpld_msn21xx_pwr_items_data,
581 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF,
582 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
583 .mask = MLXPLAT_CPLD_PWR_MASK,
584 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_pwr_items_data),
585 .inversed = 0,
586 .health = false,
587 },
588 {
589 .data = mlxplat_mlxcpld_default_asic_items_data,
590 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
591 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
592 .mask = MLXPLAT_CPLD_ASIC_MASK,
593 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
594 .inversed = 0,
595 .health = true,
596 },
597};
598
599static
600struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn21xx_data = {
601 .items = mlxplat_mlxcpld_msn21xx_items,
602 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_items),
603 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
604 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
605 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
606 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
607};
608
609/* Platform hotplug msn274x system family data */
610static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_psu_items_data[] = {
611 {
612 .label = "psu1",
613 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
614 .mask = BIT(0),
615 .hpdev.brdinfo = &mlxplat_mlxcpld_psu[0],
616 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
617 },
618 {
619 .label = "psu2",
620 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
621 .mask = BIT(1),
622 .hpdev.brdinfo = &mlxplat_mlxcpld_psu[1],
623 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
624 },
625};
626
627static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_pwr_items_data[] = {
628 {
629 .label = "pwr1",
630 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
631 .mask = BIT(0),
632 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0],
633 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
634 },
635 {
636 .label = "pwr2",
637 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
638 .mask = BIT(1),
639 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1],
640 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
641 },
642};
643
644static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_fan_items_data[] = {
645 {
646 .label = "fan1",
647 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
648 .mask = BIT(0),
649 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
650 },
651 {
652 .label = "fan2",
653 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
654 .mask = BIT(1),
655 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
656 },
657 {
658 .label = "fan3",
659 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
660 .mask = BIT(2),
661 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
662 },
663 {
664 .label = "fan4",
665 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
666 .mask = BIT(3),
667 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
668 },
669};
670
671static struct mlxreg_core_item mlxplat_mlxcpld_msn274x_items[] = {
672 {
673 .data = mlxplat_mlxcpld_msn274x_psu_items_data,
674 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
675 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
676 .mask = MLXPLAT_CPLD_PSU_MASK,
677 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_psu_items_data),
678 .inversed = 1,
679 .health = false,
680 },
681 {
682 .data = mlxplat_mlxcpld_default_ng_pwr_items_data,
683 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
684 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
685 .mask = MLXPLAT_CPLD_PWR_MASK,
686 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data),
687 .inversed = 0,
688 .health = false,
689 },
690 {
691 .data = mlxplat_mlxcpld_msn274x_fan_items_data,
692 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
693 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
694 .mask = MLXPLAT_CPLD_FAN_MASK,
695 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_fan_items_data),
696 .inversed = 1,
697 .health = false,
698 },
699 {
700 .data = mlxplat_mlxcpld_default_asic_items_data,
701 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
702 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
703 .mask = MLXPLAT_CPLD_ASIC_MASK,
704 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
705 .inversed = 0,
706 .health = true,
707 },
708};
709
710static
711struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn274x_data = {
712 .items = mlxplat_mlxcpld_msn274x_items,
713 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_items),
714 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
715 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
716 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
717 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
718};
719
720/* Platform hotplug MSN201x system family data */
721static struct mlxreg_core_data mlxplat_mlxcpld_msn201x_pwr_items_data[] = {
722 {
723 .label = "pwr1",
724 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
725 .mask = BIT(0),
726 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
727 },
728 {
729 .label = "pwr2",
730 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
731 .mask = BIT(1),
732 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
733 },
734};
735
736static struct mlxreg_core_item mlxplat_mlxcpld_msn201x_items[] = {
737 {
738 .data = mlxplat_mlxcpld_msn201x_pwr_items_data,
739 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF,
740 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
741 .mask = MLXPLAT_CPLD_PWR_MASK,
742 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_pwr_items_data),
743 .inversed = 0,
744 .health = false,
745 },
746 {
747 .data = mlxplat_mlxcpld_default_asic_items_data,
748 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
749 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
750 .mask = MLXPLAT_CPLD_ASIC_MASK,
751 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
752 .inversed = 0,
753 .health = true,
754 },
755};
756
757static
758struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn201x_data = {
759 .items = mlxplat_mlxcpld_msn201x_items,
760 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_items),
761 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
762 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
763 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
764 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
765};
766
767/* Platform hotplug next generation system family data */
768static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_psu_items_data[] = {
769 {
770 .label = "psu1",
771 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
772 .mask = BIT(0),
773 .hpdev.brdinfo = &mlxplat_mlxcpld_ng_psu[0],
774 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
775 },
776 {
777 .label = "psu2",
778 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
779 .mask = BIT(1),
780 .hpdev.brdinfo = &mlxplat_mlxcpld_ng_psu[1],
781 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
782 },
783};
784
785static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_fan_items_data[] = {
786 {
787 .label = "fan1",
788 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
789 .mask = BIT(0),
790 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
791 .bit = BIT(0),
792 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
793 },
794 {
795 .label = "fan2",
796 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
797 .mask = BIT(1),
798 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
799 .bit = BIT(1),
800 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
801 },
802 {
803 .label = "fan3",
804 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
805 .mask = BIT(2),
806 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
807 .bit = BIT(2),
808 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
809 },
810 {
811 .label = "fan4",
812 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
813 .mask = BIT(3),
814 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
815 .bit = BIT(3),
816 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
817 },
818 {
819 .label = "fan5",
820 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
821 .mask = BIT(4),
822 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
823 .bit = BIT(4),
824 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
825 },
826 {
827 .label = "fan6",
828 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
829 .mask = BIT(5),
830 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
831 .bit = BIT(5),
832 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
833 },
834};
835
836static struct mlxreg_core_item mlxplat_mlxcpld_default_ng_items[] = {
837 {
838 .data = mlxplat_mlxcpld_default_ng_psu_items_data,
839 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
840 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
841 .mask = MLXPLAT_CPLD_PSU_MASK,
842 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_psu_items_data),
843 .inversed = 1,
844 .health = false,
845 },
846 {
847 .data = mlxplat_mlxcpld_default_ng_pwr_items_data,
848 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
849 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
850 .mask = MLXPLAT_CPLD_PWR_MASK,
851 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data),
852 .inversed = 0,
853 .health = false,
854 },
855 {
856 .data = mlxplat_mlxcpld_default_ng_fan_items_data,
857 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
858 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
859 .mask = MLXPLAT_CPLD_FAN_NG_MASK,
860 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data),
861 .inversed = 1,
862 .health = false,
863 },
864 {
865 .data = mlxplat_mlxcpld_default_asic_items_data,
866 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
867 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
868 .mask = MLXPLAT_CPLD_ASIC_MASK,
869 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
870 .inversed = 0,
871 .health = true,
872 },
873};
874
875static
876struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_ng_data = {
877 .items = mlxplat_mlxcpld_default_ng_items,
878 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_items),
879 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
880 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX,
881 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
882 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
883};
884
885/* Platform hotplug extended system family data */
886static struct mlxreg_core_data mlxplat_mlxcpld_ext_psu_items_data[] = {
887 {
888 .label = "psu1",
889 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
890 .mask = BIT(0),
891 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
892 },
893 {
894 .label = "psu2",
895 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
896 .mask = BIT(1),
897 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
898 },
899 {
900 .label = "psu3",
901 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
902 .mask = BIT(2),
903 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
904 },
905 {
906 .label = "psu4",
907 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
908 .mask = BIT(3),
909 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
910 },
911};
912
913static struct mlxreg_core_data mlxplat_mlxcpld_ext_pwr_items_data[] = {
914 {
915 .label = "pwr1",
916 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
917 .mask = BIT(0),
918 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0],
919 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
920 },
921 {
922 .label = "pwr2",
923 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
924 .mask = BIT(1),
925 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1],
926 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
927 },
928 {
929 .label = "pwr3",
930 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
931 .mask = BIT(2),
932 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0],
933 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
934 },
935 {
936 .label = "pwr4",
937 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
938 .mask = BIT(3),
939 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1],
940 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
941 },
942};
943
944static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = {
945 {
946 .data = mlxplat_mlxcpld_ext_psu_items_data,
947 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
948 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
949 .mask = MLXPLAT_CPLD_PSU_EXT_MASK,
950 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
951 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data),
952 .inversed = 1,
953 .health = false,
954 },
955 {
956 .data = mlxplat_mlxcpld_ext_pwr_items_data,
957 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
958 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
959 .mask = MLXPLAT_CPLD_PWR_EXT_MASK,
960 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
961 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data),
962 .inversed = 0,
963 .health = false,
964 },
965 {
966 .data = mlxplat_mlxcpld_default_ng_fan_items_data,
967 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
968 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
969 .mask = MLXPLAT_CPLD_FAN_NG_MASK,
970 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data),
971 .inversed = 1,
972 .health = false,
973 },
974 {
975 .data = mlxplat_mlxcpld_default_asic_items_data,
976 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
977 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
978 .mask = MLXPLAT_CPLD_ASIC_MASK,
979 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
980 .inversed = 0,
981 .health = true,
982 },
983};
984
985static
986struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = {
987 .items = mlxplat_mlxcpld_ext_items,
988 .counter = ARRAY_SIZE(mlxplat_mlxcpld_ext_items),
989 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
990 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX,
991 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
992 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
993};
994
995/* Platform led default data */
996static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = {
997 {
998 .label = "status:green",
999 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
1000 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1001 },
1002 {
1003 .label = "status:red",
1004 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
1005 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
1006 },
1007 {
1008 .label = "psu:green",
1009 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
1010 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
1011 },
1012 {
1013 .label = "psu:red",
1014 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
1015 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
1016 },
1017 {
1018 .label = "fan1:green",
1019 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
1020 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1021 },
1022 {
1023 .label = "fan1:red",
1024 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
1025 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1026 },
1027 {
1028 .label = "fan2:green",
1029 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
1030 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
1031 },
1032 {
1033 .label = "fan2:red",
1034 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
1035 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
1036 },
1037 {
1038 .label = "fan3:green",
1039 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
1040 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1041 },
1042 {
1043 .label = "fan3:red",
1044 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
1045 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1046 },
1047 {
1048 .label = "fan4:green",
1049 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
1050 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
1051 },
1052 {
1053 .label = "fan4:red",
1054 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
1055 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
1056 },
1057};
1058
1059static struct mlxreg_core_platform_data mlxplat_default_led_data = {
1060 .data = mlxplat_mlxcpld_default_led_data,
1061 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_data),
1062};
1063
1064/* Platform led MSN21xx system family data */
1065static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_led_data[] = {
1066 {
1067 .label = "status:green",
1068 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
1069 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1070 },
1071 {
1072 .label = "status:red",
1073 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
1074 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
1075 },
1076 {
1077 .label = "fan:green",
1078 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
1079 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1080 },
1081 {
1082 .label = "fan:red",
1083 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
1084 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1085 },
1086 {
1087 .label = "psu1:green",
1088 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
1089 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1090 },
1091 {
1092 .label = "psu1:red",
1093 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
1094 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1095 },
1096 {
1097 .label = "psu2:green",
1098 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
1099 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
1100 },
1101 {
1102 .label = "psu2:red",
1103 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
1104 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
1105 },
1106 {
1107 .label = "uid:blue",
1108 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
1109 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1110 },
1111};
1112
1113static struct mlxreg_core_platform_data mlxplat_msn21xx_led_data = {
1114 .data = mlxplat_mlxcpld_msn21xx_led_data,
1115 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_led_data),
1116};
1117
1118/* Platform led for default data for 200GbE systems */
1119static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_led_data[] = {
1120 {
1121 .label = "status:green",
1122 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
1123 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1124 },
1125 {
1126 .label = "status:orange",
1127 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
1128 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
1129 },
1130 {
1131 .label = "psu:green",
1132 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
1133 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
1134 },
1135 {
1136 .label = "psu:orange",
1137 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
1138 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
1139 },
1140 {
1141 .label = "fan1:green",
1142 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
1143 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1144 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
1145 .bit = BIT(0),
1146 },
1147 {
1148 .label = "fan1:orange",
1149 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
1150 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1151 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
1152 .bit = BIT(0),
1153 },
1154 {
1155 .label = "fan2:green",
1156 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
1157 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
1158 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
1159 .bit = BIT(1),
1160 },
1161 {
1162 .label = "fan2:orange",
1163 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
1164 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
1165 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
1166 .bit = BIT(1),
1167 },
1168 {
1169 .label = "fan3:green",
1170 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
1171 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1172 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
1173 .bit = BIT(2),
1174 },
1175 {
1176 .label = "fan3:orange",
1177 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
1178 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1179 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
1180 .bit = BIT(2),
1181 },
1182 {
1183 .label = "fan4:green",
1184 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
1185 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
1186 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
1187 .bit = BIT(3),
1188 },
1189 {
1190 .label = "fan4:orange",
1191 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
1192 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
1193 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
1194 .bit = BIT(3),
1195 },
1196 {
1197 .label = "fan5:green",
1198 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
1199 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1200 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
1201 .bit = BIT(4),
1202 },
1203 {
1204 .label = "fan5:orange",
1205 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
1206 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1207 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
1208 .bit = BIT(4),
1209 },
1210 {
1211 .label = "fan6:green",
1212 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
1213 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
1214 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
1215 .bit = BIT(5),
1216 },
1217 {
1218 .label = "fan6:orange",
1219 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
1220 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
1221 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
1222 .bit = BIT(5),
1223 },
1224 {
1225 .label = "uid:blue",
1226 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
1227 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1228 },
1229};
1230
1231static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = {
1232 .data = mlxplat_mlxcpld_default_ng_led_data,
1233 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data),
1234};
1235
1236/* Platform led for Comex based 100GbE systems */
1237static struct mlxreg_core_data mlxplat_mlxcpld_comex_100G_led_data[] = {
1238 {
1239 .label = "status:green",
1240 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
1241 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1242 },
1243 {
1244 .label = "status:red",
1245 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
1246 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
1247 },
1248 {
1249 .label = "psu:green",
1250 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
1251 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
1252 },
1253 {
1254 .label = "psu:red",
1255 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
1256 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
1257 },
1258 {
1259 .label = "fan1:green",
1260 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
1261 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1262 },
1263 {
1264 .label = "fan1:red",
1265 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
1266 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1267 },
1268 {
1269 .label = "fan2:green",
1270 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
1271 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
1272 },
1273 {
1274 .label = "fan2:red",
1275 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
1276 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
1277 },
1278 {
1279 .label = "fan3:green",
1280 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
1281 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1282 },
1283 {
1284 .label = "fan3:red",
1285 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
1286 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1287 },
1288 {
1289 .label = "fan4:green",
1290 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
1291 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
1292 },
1293 {
1294 .label = "fan4:red",
1295 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
1296 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
1297 },
1298 {
1299 .label = "uid:blue",
1300 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
1301 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
1302 },
1303};
1304
1305static struct mlxreg_core_platform_data mlxplat_comex_100G_led_data = {
1306 .data = mlxplat_mlxcpld_comex_100G_led_data,
1307 .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_100G_led_data),
1308};
1309
1310/* Platform register access default */
1311static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = {
1312 {
1313 .label = "cpld1_version",
1314 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
1315 .bit = GENMASK(7, 0),
1316 .mode = 0444,
1317 },
1318 {
1319 .label = "cpld2_version",
1320 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
1321 .bit = GENMASK(7, 0),
1322 .mode = 0444,
1323 },
1324 {
1325 .label = "cpld1_pn",
1326 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
1327 .bit = GENMASK(15, 0),
1328 .mode = 0444,
1329 .regnum = 2,
1330 },
1331 {
1332 .label = "cpld2_pn",
1333 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
1334 .bit = GENMASK(15, 0),
1335 .mode = 0444,
1336 .regnum = 2,
1337 },
1338 {
1339 .label = "cpld1_version_min",
1340 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
1341 .bit = GENMASK(7, 0),
1342 .mode = 0444,
1343 },
1344 {
1345 .label = "cpld2_version_min",
1346 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
1347 .bit = GENMASK(7, 0),
1348 .mode = 0444,
1349 },
1350 {
1351 .label = "reset_long_pb",
1352 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1353 .mask = GENMASK(7, 0) & ~BIT(0),
1354 .mode = 0444,
1355 },
1356 {
1357 .label = "reset_short_pb",
1358 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1359 .mask = GENMASK(7, 0) & ~BIT(1),
1360 .mode = 0444,
1361 },
1362 {
1363 .label = "reset_aux_pwr_or_ref",
1364 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1365 .mask = GENMASK(7, 0) & ~BIT(2),
1366 .mode = 0444,
1367 },
1368 {
1369 .label = "reset_main_pwr_fail",
1370 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1371 .mask = GENMASK(7, 0) & ~BIT(3),
1372 .mode = 0444,
1373 },
1374 {
1375 .label = "reset_sw_reset",
1376 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1377 .mask = GENMASK(7, 0) & ~BIT(4),
1378 .mode = 0444,
1379 },
1380 {
1381 .label = "reset_fw_reset",
1382 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1383 .mask = GENMASK(7, 0) & ~BIT(5),
1384 .mode = 0444,
1385 },
1386 {
1387 .label = "reset_hotswap_or_wd",
1388 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1389 .mask = GENMASK(7, 0) & ~BIT(6),
1390 .mode = 0444,
1391 },
1392 {
1393 .label = "reset_asic_thermal",
1394 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1395 .mask = GENMASK(7, 0) & ~BIT(7),
1396 .mode = 0444,
1397 },
1398 {
1399 .label = "psu1_on",
1400 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
1401 .mask = GENMASK(7, 0) & ~BIT(0),
1402 .mode = 0200,
1403 },
1404 {
1405 .label = "psu2_on",
1406 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
1407 .mask = GENMASK(7, 0) & ~BIT(1),
1408 .mode = 0200,
1409 },
1410 {
1411 .label = "pwr_cycle",
1412 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
1413 .mask = GENMASK(7, 0) & ~BIT(2),
1414 .mode = 0200,
1415 },
1416 {
1417 .label = "pwr_down",
1418 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
1419 .mask = GENMASK(7, 0) & ~BIT(3),
1420 .mode = 0200,
1421 },
1422 {
1423 .label = "select_iio",
1424 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
1425 .mask = GENMASK(7, 0) & ~BIT(6),
1426 .mode = 0644,
1427 },
1428 {
1429 .label = "asic_health",
1430 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
1431 .mask = MLXPLAT_CPLD_ASIC_MASK,
1432 .bit = 1,
1433 .mode = 0444,
1434 },
1435};
1436
1437static struct mlxreg_core_platform_data mlxplat_default_regs_io_data = {
1438 .data = mlxplat_mlxcpld_default_regs_io_data,
1439 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data),
1440};
1441
1442/* Platform register access MSN21xx, MSN201x, MSN274x systems families data */
1443static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = {
1444 {
1445 .label = "cpld1_version",
1446 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
1447 .bit = GENMASK(7, 0),
1448 .mode = 0444,
1449 },
1450 {
1451 .label = "cpld2_version",
1452 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
1453 .bit = GENMASK(7, 0),
1454 .mode = 0444,
1455 },
1456 {
1457 .label = "cpld1_pn",
1458 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
1459 .bit = GENMASK(15, 0),
1460 .mode = 0444,
1461 .regnum = 2,
1462 },
1463 {
1464 .label = "cpld2_pn",
1465 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
1466 .bit = GENMASK(15, 0),
1467 .mode = 0444,
1468 .regnum = 2,
1469 },
1470 {
1471 .label = "cpld1_version_min",
1472 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
1473 .bit = GENMASK(7, 0),
1474 .mode = 0444,
1475 },
1476 {
1477 .label = "cpld2_version_min",
1478 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
1479 .bit = GENMASK(7, 0),
1480 .mode = 0444,
1481 },
1482 {
1483 .label = "reset_long_pb",
1484 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1485 .mask = GENMASK(7, 0) & ~BIT(0),
1486 .mode = 0444,
1487 },
1488 {
1489 .label = "reset_short_pb",
1490 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1491 .mask = GENMASK(7, 0) & ~BIT(1),
1492 .mode = 0444,
1493 },
1494 {
1495 .label = "reset_aux_pwr_or_ref",
1496 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1497 .mask = GENMASK(7, 0) & ~BIT(2),
1498 .mode = 0444,
1499 },
1500 {
1501 .label = "reset_sw_reset",
1502 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1503 .mask = GENMASK(7, 0) & ~BIT(3),
1504 .mode = 0444,
1505 },
1506 {
1507 .label = "reset_main_pwr_fail",
1508 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1509 .mask = GENMASK(7, 0) & ~BIT(4),
1510 .mode = 0444,
1511 },
1512 {
1513 .label = "reset_asic_thermal",
1514 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1515 .mask = GENMASK(7, 0) & ~BIT(5),
1516 .mode = 0444,
1517 },
1518 {
1519 .label = "reset_hotswap_or_halt",
1520 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1521 .mask = GENMASK(7, 0) & ~BIT(6),
1522 .mode = 0444,
1523 },
1524 {
1525 .label = "reset_sff_wd",
1526 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
1527 .mask = GENMASK(7, 0) & ~BIT(6),
1528 .mode = 0444,
1529 },
1530 {
1531 .label = "psu1_on",
1532 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
1533 .mask = GENMASK(7, 0) & ~BIT(0),
1534 .mode = 0200,
1535 },
1536 {
1537 .label = "psu2_on",
1538 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
1539 .mask = GENMASK(7, 0) & ~BIT(1),
1540 .mode = 0200,
1541 },
1542 {
1543 .label = "pwr_cycle",
1544 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
1545 .mask = GENMASK(7, 0) & ~BIT(2),
1546 .mode = 0200,
1547 },
1548 {
1549 .label = "pwr_down",
1550 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
1551 .mask = GENMASK(7, 0) & ~BIT(3),
1552 .mode = 0200,
1553 },
1554 {
1555 .label = "select_iio",
1556 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
1557 .mask = GENMASK(7, 0) & ~BIT(6),
1558 .mode = 0644,
1559 },
1560 {
1561 .label = "asic_health",
1562 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
1563 .mask = MLXPLAT_CPLD_ASIC_MASK,
1564 .bit = 1,
1565 .mode = 0444,
1566 },
1567};
1568
1569static struct mlxreg_core_platform_data mlxplat_msn21xx_regs_io_data = {
1570 .data = mlxplat_mlxcpld_msn21xx_regs_io_data,
1571 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data),
1572};
1573
1574/* Platform register access for next generation systems families data */
1575static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
1576 {
1577 .label = "cpld1_version",
1578 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
1579 .bit = GENMASK(7, 0),
1580 .mode = 0444,
1581 },
1582 {
1583 .label = "cpld2_version",
1584 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
1585 .bit = GENMASK(7, 0),
1586 .mode = 0444,
1587 },
1588 {
1589 .label = "cpld3_version",
1590 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET,
1591 .bit = GENMASK(7, 0),
1592 .mode = 0444,
1593 },
1594 {
1595 .label = "cpld4_version",
1596 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET,
1597 .bit = GENMASK(7, 0),
1598 .mode = 0444,
1599 },
1600 {
1601 .label = "cpld1_pn",
1602 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
1603 .bit = GENMASK(15, 0),
1604 .mode = 0444,
1605 .regnum = 2,
1606 },
1607 {
1608 .label = "cpld2_pn",
1609 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
1610 .bit = GENMASK(15, 0),
1611 .mode = 0444,
1612 .regnum = 2,
1613 },
1614 {
1615 .label = "cpld3_pn",
1616 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET,
1617 .bit = GENMASK(15, 0),
1618 .mode = 0444,
1619 .regnum = 2,
1620 },
1621 {
1622 .label = "cpld4_pn",
1623 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET,
1624 .bit = GENMASK(15, 0),
1625 .mode = 0444,
1626 .regnum = 2,
1627 },
1628 {
1629 .label = "cpld1_version_min",
1630 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
1631 .bit = GENMASK(7, 0),
1632 .mode = 0444,
1633 },
1634 {
1635 .label = "cpld2_version_min",
1636 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
1637 .bit = GENMASK(7, 0),
1638 .mode = 0444,
1639 },
1640 {
1641 .label = "cpld3_version_min",
1642 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET,
1643 .bit = GENMASK(7, 0),
1644 .mode = 0444,
1645 },
1646 {
1647 .label = "cpld4_version_min",
1648 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET,
1649 .bit = GENMASK(7, 0),
1650 .mode = 0444,
1651 },
1652 {
1653 .label = "reset_long_pb",
1654 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1655 .mask = GENMASK(7, 0) & ~BIT(0),
1656 .mode = 0444,
1657 },
1658 {
1659 .label = "reset_short_pb",
1660 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1661 .mask = GENMASK(7, 0) & ~BIT(1),
1662 .mode = 0444,
1663 },
1664 {
1665 .label = "reset_aux_pwr_or_ref",
1666 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1667 .mask = GENMASK(7, 0) & ~BIT(2),
1668 .mode = 0444,
1669 },
1670 {
1671 .label = "reset_from_comex",
1672 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1673 .mask = GENMASK(7, 0) & ~BIT(4),
1674 .mode = 0444,
1675 },
1676 {
1677 .label = "reset_from_asic",
1678 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1679 .mask = GENMASK(7, 0) & ~BIT(5),
1680 .mode = 0444,
1681 },
1682 {
1683 .label = "reset_swb_wd",
1684 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1685 .mask = GENMASK(7, 0) & ~BIT(6),
1686 .mode = 0444,
1687 },
1688 {
1689 .label = "reset_asic_thermal",
1690 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1691 .mask = GENMASK(7, 0) & ~BIT(7),
1692 .mode = 0444,
1693 },
1694 {
1695 .label = "reset_comex_pwr_fail",
1696 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
1697 .mask = GENMASK(7, 0) & ~BIT(3),
1698 .mode = 0444,
1699 },
1700 {
1701 .label = "reset_platform",
1702 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
1703 .mask = GENMASK(7, 0) & ~BIT(4),
1704 .mode = 0444,
1705 },
1706 {
1707 .label = "reset_soc",
1708 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
1709 .mask = GENMASK(7, 0) & ~BIT(5),
1710 .mode = 0444,
1711 },
1712 {
1713 .label = "reset_comex_wd",
1714 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
1715 .mask = GENMASK(7, 0) & ~BIT(6),
1716 .mode = 0444,
1717 },
1718 {
1719 .label = "reset_voltmon_upgrade_fail",
1720 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
1721 .mask = GENMASK(7, 0) & ~BIT(0),
1722 .mode = 0444,
1723 },
1724 {
1725 .label = "reset_system",
1726 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
1727 .mask = GENMASK(7, 0) & ~BIT(1),
1728 .mode = 0444,
1729 },
1730 {
1731 .label = "reset_sw_pwr_off",
1732 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
1733 .mask = GENMASK(7, 0) & ~BIT(2),
1734 .mode = 0444,
1735 },
1736 {
1737 .label = "reset_comex_thermal",
1738 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
1739 .mask = GENMASK(7, 0) & ~BIT(3),
1740 .mode = 0444,
1741 },
1742 {
1743 .label = "reset_reload_bios",
1744 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
1745 .mask = GENMASK(7, 0) & ~BIT(5),
1746 .mode = 0444,
1747 },
1748 {
1749 .label = "reset_ac_pwr_fail",
1750 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
1751 .mask = GENMASK(7, 0) & ~BIT(6),
1752 .mode = 0444,
1753 },
1754 {
1755 .label = "psu1_on",
1756 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
1757 .mask = GENMASK(7, 0) & ~BIT(0),
1758 .mode = 0200,
1759 },
1760 {
1761 .label = "psu2_on",
1762 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
1763 .mask = GENMASK(7, 0) & ~BIT(1),
1764 .mode = 0200,
1765 },
1766 {
1767 .label = "pwr_cycle",
1768 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
1769 .mask = GENMASK(7, 0) & ~BIT(2),
1770 .mode = 0200,
1771 },
1772 {
1773 .label = "pwr_down",
1774 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
1775 .mask = GENMASK(7, 0) & ~BIT(3),
1776 .mode = 0200,
1777 },
1778 {
1779 .label = "jtag_enable",
1780 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
1781 .mask = GENMASK(7, 0) & ~BIT(4),
1782 .mode = 0644,
1783 },
1784 {
1785 .label = "asic_health",
1786 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
1787 .mask = MLXPLAT_CPLD_ASIC_MASK,
1788 .bit = 1,
1789 .mode = 0444,
1790 },
1791 {
1792 .label = "fan_dir",
1793 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION,
1794 .bit = GENMASK(7, 0),
1795 .mode = 0444,
1796 },
1797 {
1798 .label = "voltreg_update_status",
1799 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET,
1800 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK,
1801 .bit = 5,
1802 .mode = 0444,
1803 },
1804 {
1805 .label = "vpd_wp",
1806 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
1807 .mask = GENMASK(7, 0) & ~BIT(3),
1808 .mode = 0644,
1809 },
1810 {
1811 .label = "pcie_asic_reset_dis",
1812 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
1813 .mask = GENMASK(7, 0) & ~BIT(4),
1814 .mode = 0644,
1815 },
1816 {
1817 .label = "config1",
1818 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET,
1819 .bit = GENMASK(7, 0),
1820 .mode = 0444,
1821 },
1822 {
1823 .label = "config2",
1824 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET,
1825 .bit = GENMASK(7, 0),
1826 .mode = 0444,
1827 },
1828 {
1829 .label = "ufm_version",
1830 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET,
1831 .bit = GENMASK(7, 0),
1832 .mode = 0444,
1833 },
1834};
1835
1836static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = {
1837 .data = mlxplat_mlxcpld_default_ng_regs_io_data,
1838 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data),
1839};
1840
1841/* Platform FAN default */
1842static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = {
1843 {
1844 .label = "pwm1",
1845 .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET,
1846 },
1847 {
1848 .label = "tacho1",
1849 .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET,
1850 .mask = GENMASK(7, 0),
1851 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
1852 .bit = BIT(0),
1853 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1854
1855 },
1856 {
1857 .label = "tacho2",
1858 .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET,
1859 .mask = GENMASK(7, 0),
1860 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
1861 .bit = BIT(1),
1862 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1863 },
1864 {
1865 .label = "tacho3",
1866 .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET,
1867 .mask = GENMASK(7, 0),
1868 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
1869 .bit = BIT(2),
1870 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1871 },
1872 {
1873 .label = "tacho4",
1874 .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET,
1875 .mask = GENMASK(7, 0),
1876 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
1877 .bit = BIT(3),
1878 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1879 },
1880 {
1881 .label = "tacho5",
1882 .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET,
1883 .mask = GENMASK(7, 0),
1884 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
1885 .bit = BIT(4),
1886 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1887 },
1888 {
1889 .label = "tacho6",
1890 .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET,
1891 .mask = GENMASK(7, 0),
1892 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
1893 .bit = BIT(5),
1894 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1895 },
1896 {
1897 .label = "tacho7",
1898 .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET,
1899 .mask = GENMASK(7, 0),
1900 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
1901 .bit = BIT(6),
1902 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1903 },
1904 {
1905 .label = "tacho8",
1906 .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET,
1907 .mask = GENMASK(7, 0),
1908 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
1909 .bit = BIT(7),
1910 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1911 },
1912 {
1913 .label = "tacho9",
1914 .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET,
1915 .mask = GENMASK(7, 0),
1916 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
1917 .bit = BIT(0),
1918 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1919 },
1920 {
1921 .label = "tacho10",
1922 .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET,
1923 .mask = GENMASK(7, 0),
1924 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
1925 .bit = BIT(1),
1926 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1927 },
1928 {
1929 .label = "tacho11",
1930 .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET,
1931 .mask = GENMASK(7, 0),
1932 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
1933 .bit = BIT(2),
1934 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1935 },
1936 {
1937 .label = "tacho12",
1938 .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET,
1939 .mask = GENMASK(7, 0),
1940 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
1941 .bit = BIT(3),
1942 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1943 },
1944 {
1945 .label = "conf",
1946 .capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET,
1947 },
1948};
1949
1950static struct mlxreg_core_platform_data mlxplat_default_fan_data = {
1951 .data = mlxplat_mlxcpld_default_fan_data,
1952 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_data),
1953};
1954
1955/* Watchdog type1: hardware implementation version1
1956 * (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems).
1957 */
1958static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type1[] = {
1959 {
1960 .label = "action",
1961 .reg = MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET,
1962 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
1963 .bit = 0,
1964 },
1965 {
1966 .label = "timeout",
1967 .reg = MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET,
1968 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK,
1969 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
1970 },
1971 {
1972 .label = "ping",
1973 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET,
1974 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK,
1975 .bit = 0,
1976 },
1977 {
1978 .label = "reset",
1979 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1980 .mask = GENMASK(7, 0) & ~BIT(6),
1981 .bit = 6,
1982 },
1983};
1984
1985static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type1[] = {
1986 {
1987 .label = "action",
1988 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
1989 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
1990 .bit = 4,
1991 },
1992 {
1993 .label = "timeout",
1994 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
1995 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK,
1996 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
1997 },
1998 {
1999 .label = "ping",
2000 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET,
2001 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK,
2002 .bit = 1,
2003 },
2004};
2005
2006static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type1[] = {
2007 {
2008 .data = mlxplat_mlxcpld_wd_main_regs_type1,
2009 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type1),
2010 .version = MLX_WDT_TYPE1,
2011 .identity = "mlx-wdt-main",
2012 },
2013 {
2014 .data = mlxplat_mlxcpld_wd_aux_regs_type1,
2015 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type1),
2016 .version = MLX_WDT_TYPE1,
2017 .identity = "mlx-wdt-aux",
2018 },
2019};
2020
2021/* Watchdog type2: hardware implementation version 2
2022 * (all systems except (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140).
2023 */
2024static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type2[] = {
2025 {
2026 .label = "action",
2027 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
2028 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
2029 .bit = 0,
2030 },
2031 {
2032 .label = "timeout",
2033 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
2034 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
2035 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
2036 },
2037 {
2038 .label = "timeleft",
2039 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET,
2040 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
2041 },
2042 {
2043 .label = "ping",
2044 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
2045 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
2046 .bit = 0,
2047 },
2048 {
2049 .label = "reset",
2050 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2051 .mask = GENMASK(7, 0) & ~BIT(6),
2052 .bit = 6,
2053 },
2054};
2055
2056static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type2[] = {
2057 {
2058 .label = "action",
2059 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
2060 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
2061 .bit = 4,
2062 },
2063 {
2064 .label = "timeout",
2065 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET,
2066 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
2067 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
2068 },
2069 {
2070 .label = "timeleft",
2071 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET,
2072 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
2073 },
2074 {
2075 .label = "ping",
2076 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
2077 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
2078 .bit = 4,
2079 },
2080};
2081
2082static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type2[] = {
2083 {
2084 .data = mlxplat_mlxcpld_wd_main_regs_type2,
2085 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type2),
2086 .version = MLX_WDT_TYPE2,
2087 .identity = "mlx-wdt-main",
2088 },
2089 {
2090 .data = mlxplat_mlxcpld_wd_aux_regs_type2,
2091 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type2),
2092 .version = MLX_WDT_TYPE2,
2093 .identity = "mlx-wdt-aux",
2094 },
2095};
2096
2097/* Watchdog type3: hardware implementation version 3
2098 * Can be on all systems. It's differentiated by WD capability bit.
2099 * Old systems (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140)
2100 * still have only one main watchdog.
2101 */
2102static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type3[] = {
2103 {
2104 .label = "action",
2105 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
2106 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
2107 .bit = 0,
2108 },
2109 {
2110 .label = "timeout",
2111 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
2112 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
2113 .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT,
2114 },
2115 {
2116 .label = "timeleft",
2117 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
2118 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
2119 },
2120 {
2121 .label = "ping",
2122 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
2123 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
2124 .bit = 0,
2125 },
2126 {
2127 .label = "reset",
2128 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2129 .mask = GENMASK(7, 0) & ~BIT(6),
2130 .bit = 6,
2131 },
2132};
2133
2134static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type3[] = {
2135 {
2136 .label = "action",
2137 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
2138 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
2139 .bit = 4,
2140 },
2141 {
2142 .label = "timeout",
2143 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET,
2144 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
2145 .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT,
2146 },
2147 {
2148 .label = "timeleft",
2149 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET,
2150 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
2151 },
2152 {
2153 .label = "ping",
2154 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
2155 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
2156 .bit = 4,
2157 },
2158};
2159
2160static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type3[] = {
2161 {
2162 .data = mlxplat_mlxcpld_wd_main_regs_type3,
2163 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type3),
2164 .version = MLX_WDT_TYPE3,
2165 .identity = "mlx-wdt-main",
2166 },
2167 {
2168 .data = mlxplat_mlxcpld_wd_aux_regs_type3,
2169 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type3),
2170 .version = MLX_WDT_TYPE3,
2171 .identity = "mlx-wdt-aux",
2172 },
2173};
2174
2175static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
2176{
2177 switch (reg) {
2178 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
2179 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
2180 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
2181 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
2182 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
2183 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET:
2184 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
2185 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET:
2186 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
2187 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET:
2188 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
2189 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
2190 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET:
2191 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:
2192 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
2193 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
2194 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
2195 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
2196 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET:
2197 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET:
2198 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
2199 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
2200 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET:
2201 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET:
2202 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET:
2203 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET:
2204 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
2205 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:
2206 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET:
2207 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
2208 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
2209 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET:
2210 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
2211 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
2212 return true;
2213 }
2214 return false;
2215}
2216
2217static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
2218{
2219 switch (reg) {
2220 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
2221 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
2222 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
2223 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
2224 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET:
2225 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET:
2226 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET:
2227 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET:
2228 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
2229 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
2230 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
2231 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
2232 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
2233 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
2234 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
2235 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
2236 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:
2237 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET:
2238 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET:
2239 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
2240 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET:
2241 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
2242 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET:
2243 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
2244 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
2245 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:
2246 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
2247 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET:
2248 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET:
2249 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET:
2250 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:
2251 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
2252 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
2253 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
2254 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:
2255 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
2256 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
2257 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET:
2258 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET:
2259 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET:
2260 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:
2261 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
2262 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
2263 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET:
2264 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET:
2265 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET:
2266 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET:
2267 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
2268 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:
2269 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET:
2270 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
2271 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
2272 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET:
2273 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET:
2274 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET:
2275 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET:
2276 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET:
2277 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
2278 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:
2279 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:
2280 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET:
2281 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET:
2282 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET:
2283 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET:
2284 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET:
2285 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET:
2286 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET:
2287 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET:
2288 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:
2289 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:
2290 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
2291 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:
2292 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:
2293 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET:
2294 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET:
2295 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET:
2296 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET:
2297 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET:
2298 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET:
2299 return true;
2300 }
2301 return false;
2302}
2303
2304static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
2305{
2306 switch (reg) {
2307 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
2308 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
2309 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
2310 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
2311 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET:
2312 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET:
2313 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET:
2314 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET:
2315 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
2316 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
2317 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
2318 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
2319 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
2320 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
2321 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
2322 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
2323 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:
2324 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET:
2325 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET:
2326 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
2327 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
2328 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
2329 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
2330 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:
2331 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
2332 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET:
2333 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET:
2334 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET:
2335 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:
2336 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
2337 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
2338 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
2339 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:
2340 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
2341 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
2342 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET:
2343 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET:
2344 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET:
2345 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:
2346 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
2347 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
2348 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
2349 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:
2350 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
2351 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
2352 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET:
2353 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET:
2354 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET:
2355 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET:
2356 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
2357 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:
2358 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:
2359 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET:
2360 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET:
2361 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET:
2362 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET:
2363 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET:
2364 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET:
2365 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET:
2366 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET:
2367 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:
2368 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:
2369 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
2370 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:
2371 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:
2372 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET:
2373 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET:
2374 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET:
2375 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET:
2376 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET:
2377 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET:
2378 return true;
2379 }
2380 return false;
2381}
2382
2383static const struct reg_default mlxplat_mlxcpld_regmap_default[] = {
2384 { MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, 0x00 },
2385 { MLXPLAT_CPLD_LPC_REG_WP2_OFFSET, 0x00 },
2386 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
2387 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 },
2388};
2389
2390static const struct reg_default mlxplat_mlxcpld_regmap_ng[] = {
2391 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
2392 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 },
2393};
2394
2395static const struct reg_default mlxplat_mlxcpld_regmap_comex_default[] = {
2396 { MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET,
2397 MLXPLAT_CPLD_LOW_AGGRCX_MASK },
2398 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
2399};
2400
2401static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = {
2402 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
2403 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 },
2404 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 },
2405 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 },
2406};
2407
2408struct mlxplat_mlxcpld_regmap_context {
2409 void __iomem *base;
2410};
2411
2412static struct mlxplat_mlxcpld_regmap_context mlxplat_mlxcpld_regmap_ctx;
2413
2414static int
2415mlxplat_mlxcpld_reg_read(void *context, unsigned int reg, unsigned int *val)
2416{
2417 struct mlxplat_mlxcpld_regmap_context *ctx = context;
2418
2419 *val = ioread8(ctx->base + reg);
2420 return 0;
2421}
2422
2423static int
2424mlxplat_mlxcpld_reg_write(void *context, unsigned int reg, unsigned int val)
2425{
2426 struct mlxplat_mlxcpld_regmap_context *ctx = context;
2427
2428 iowrite8(val, ctx->base + reg);
2429 return 0;
2430}
2431
2432static const struct regmap_config mlxplat_mlxcpld_regmap_config = {
2433 .reg_bits = 8,
2434 .val_bits = 8,
2435 .max_register = 255,
2436 .cache_type = REGCACHE_FLAT,
2437 .writeable_reg = mlxplat_mlxcpld_writeable_reg,
2438 .readable_reg = mlxplat_mlxcpld_readable_reg,
2439 .volatile_reg = mlxplat_mlxcpld_volatile_reg,
2440 .reg_defaults = mlxplat_mlxcpld_regmap_default,
2441 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_default),
2442 .reg_read = mlxplat_mlxcpld_reg_read,
2443 .reg_write = mlxplat_mlxcpld_reg_write,
2444};
2445
2446static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng = {
2447 .reg_bits = 8,
2448 .val_bits = 8,
2449 .max_register = 255,
2450 .cache_type = REGCACHE_FLAT,
2451 .writeable_reg = mlxplat_mlxcpld_writeable_reg,
2452 .readable_reg = mlxplat_mlxcpld_readable_reg,
2453 .volatile_reg = mlxplat_mlxcpld_volatile_reg,
2454 .reg_defaults = mlxplat_mlxcpld_regmap_ng,
2455 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng),
2456 .reg_read = mlxplat_mlxcpld_reg_read,
2457 .reg_write = mlxplat_mlxcpld_reg_write,
2458};
2459
2460static const struct regmap_config mlxplat_mlxcpld_regmap_config_comex = {
2461 .reg_bits = 8,
2462 .val_bits = 8,
2463 .max_register = 255,
2464 .cache_type = REGCACHE_FLAT,
2465 .writeable_reg = mlxplat_mlxcpld_writeable_reg,
2466 .readable_reg = mlxplat_mlxcpld_readable_reg,
2467 .volatile_reg = mlxplat_mlxcpld_volatile_reg,
2468 .reg_defaults = mlxplat_mlxcpld_regmap_comex_default,
2469 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_comex_default),
2470 .reg_read = mlxplat_mlxcpld_reg_read,
2471 .reg_write = mlxplat_mlxcpld_reg_write,
2472};
2473
2474static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng400 = {
2475 .reg_bits = 8,
2476 .val_bits = 8,
2477 .max_register = 255,
2478 .cache_type = REGCACHE_FLAT,
2479 .writeable_reg = mlxplat_mlxcpld_writeable_reg,
2480 .readable_reg = mlxplat_mlxcpld_readable_reg,
2481 .volatile_reg = mlxplat_mlxcpld_volatile_reg,
2482 .reg_defaults = mlxplat_mlxcpld_regmap_ng400,
2483 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng400),
2484 .reg_read = mlxplat_mlxcpld_reg_read,
2485 .reg_write = mlxplat_mlxcpld_reg_write,
2486};
2487
2488static struct resource mlxplat_mlxcpld_resources[] = {
2489 [0] = DEFINE_RES_IRQ_NAMED(17, "mlxreg-hotplug"),
2490};
2491
2492static struct platform_device *mlxplat_dev;
2493static struct mlxreg_core_hotplug_platform_data *mlxplat_i2c;
2494static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug;
2495static struct mlxreg_core_platform_data *mlxplat_led;
2496static struct mlxreg_core_platform_data *mlxplat_regs_io;
2497static struct mlxreg_core_platform_data *mlxplat_fan;
2498static struct mlxreg_core_platform_data
2499 *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS];
2500static const struct regmap_config *mlxplat_regmap_config;
2501
2502static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi)
2503{
2504 int i;
2505
2506 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
2507 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
2508 mlxplat_mux_data = mlxplat_default_mux_data;
2509 for (i = 0; i < mlxplat_mux_num; i++) {
2510 mlxplat_mux_data[i].values = mlxplat_default_channels[i];
2511 mlxplat_mux_data[i].n_values =
2512 ARRAY_SIZE(mlxplat_default_channels[i]);
2513 }
2514 mlxplat_hotplug = &mlxplat_mlxcpld_default_data;
2515 mlxplat_hotplug->deferred_nr =
2516 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
2517 mlxplat_led = &mlxplat_default_led_data;
2518 mlxplat_regs_io = &mlxplat_default_regs_io_data;
2519 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
2520
2521 return 1;
2522}
2523
2524static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi)
2525{
2526 int i;
2527
2528 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
2529 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
2530 mlxplat_mux_data = mlxplat_default_mux_data;
2531 for (i = 0; i < mlxplat_mux_num; i++) {
2532 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
2533 mlxplat_mux_data[i].n_values =
2534 ARRAY_SIZE(mlxplat_msn21xx_channels);
2535 }
2536 mlxplat_hotplug = &mlxplat_mlxcpld_msn21xx_data;
2537 mlxplat_hotplug->deferred_nr =
2538 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
2539 mlxplat_led = &mlxplat_msn21xx_led_data;
2540 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
2541 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
2542
2543 return 1;
2544}
2545
2546static int __init mlxplat_dmi_msn274x_matched(const struct dmi_system_id *dmi)
2547{
2548 int i;
2549
2550 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
2551 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
2552 mlxplat_mux_data = mlxplat_default_mux_data;
2553 for (i = 0; i < mlxplat_mux_num; i++) {
2554 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
2555 mlxplat_mux_data[i].n_values =
2556 ARRAY_SIZE(mlxplat_msn21xx_channels);
2557 }
2558 mlxplat_hotplug = &mlxplat_mlxcpld_msn274x_data;
2559 mlxplat_hotplug->deferred_nr =
2560 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
2561 mlxplat_led = &mlxplat_default_led_data;
2562 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
2563 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
2564
2565 return 1;
2566}
2567
2568static int __init mlxplat_dmi_msn201x_matched(const struct dmi_system_id *dmi)
2569{
2570 int i;
2571
2572 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
2573 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
2574 mlxplat_mux_data = mlxplat_default_mux_data;
2575 for (i = 0; i < mlxplat_mux_num; i++) {
2576 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
2577 mlxplat_mux_data[i].n_values =
2578 ARRAY_SIZE(mlxplat_msn21xx_channels);
2579 }
2580 mlxplat_hotplug = &mlxplat_mlxcpld_msn201x_data;
2581 mlxplat_hotplug->deferred_nr =
2582 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
2583 mlxplat_led = &mlxplat_msn21xx_led_data;
2584 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
2585 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
2586
2587 return 1;
2588}
2589
2590static int __init mlxplat_dmi_qmb7xx_matched(const struct dmi_system_id *dmi)
2591{
2592 int i;
2593
2594 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
2595 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
2596 mlxplat_mux_data = mlxplat_default_mux_data;
2597 for (i = 0; i < mlxplat_mux_num; i++) {
2598 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
2599 mlxplat_mux_data[i].n_values =
2600 ARRAY_SIZE(mlxplat_msn21xx_channels);
2601 }
2602 mlxplat_hotplug = &mlxplat_mlxcpld_default_ng_data;
2603 mlxplat_hotplug->deferred_nr =
2604 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
2605 mlxplat_led = &mlxplat_default_ng_led_data;
2606 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
2607 mlxplat_fan = &mlxplat_default_fan_data;
2608 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
2609 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
2610 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
2611 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng;
2612
2613 return 1;
2614}
2615
2616static int __init mlxplat_dmi_comex_matched(const struct dmi_system_id *dmi)
2617{
2618 int i;
2619
2620 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM;
2621 mlxplat_mux_num = ARRAY_SIZE(mlxplat_extended_mux_data);
2622 mlxplat_mux_data = mlxplat_extended_mux_data;
2623 for (i = 0; i < mlxplat_mux_num; i++) {
2624 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
2625 mlxplat_mux_data[i].n_values =
2626 ARRAY_SIZE(mlxplat_msn21xx_channels);
2627 }
2628 mlxplat_hotplug = &mlxplat_mlxcpld_comex_data;
2629 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM;
2630 mlxplat_led = &mlxplat_comex_100G_led_data;
2631 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
2632 mlxplat_fan = &mlxplat_default_fan_data;
2633 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
2634 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
2635 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_comex;
2636
2637 return 1;
2638}
2639
2640static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi)
2641{
2642 int i;
2643
2644 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
2645 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
2646 mlxplat_mux_data = mlxplat_default_mux_data;
2647 for (i = 0; i < mlxplat_mux_num; i++) {
2648 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
2649 mlxplat_mux_data[i].n_values =
2650 ARRAY_SIZE(mlxplat_msn21xx_channels);
2651 }
2652 mlxplat_hotplug = &mlxplat_mlxcpld_ext_data;
2653 mlxplat_hotplug->deferred_nr =
2654 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
2655 mlxplat_led = &mlxplat_default_ng_led_data;
2656 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
2657 mlxplat_fan = &mlxplat_default_fan_data;
2658 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
2659 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
2660 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
2661 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400;
2662
2663 return 1;
2664}
2665
2666static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
2667 {
2668 .callback = mlxplat_dmi_default_matched,
2669 .matches = {
2670 DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"),
2671 },
2672 },
2673 {
2674 .callback = mlxplat_dmi_msn21xx_matched,
2675 .matches = {
2676 DMI_MATCH(DMI_BOARD_NAME, "VMOD0002"),
2677 },
2678 },
2679 {
2680 .callback = mlxplat_dmi_msn274x_matched,
2681 .matches = {
2682 DMI_MATCH(DMI_BOARD_NAME, "VMOD0003"),
2683 },
2684 },
2685 {
2686 .callback = mlxplat_dmi_msn201x_matched,
2687 .matches = {
2688 DMI_MATCH(DMI_BOARD_NAME, "VMOD0004"),
2689 },
2690 },
2691 {
2692 .callback = mlxplat_dmi_qmb7xx_matched,
2693 .matches = {
2694 DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"),
2695 },
2696 },
2697 {
2698 .callback = mlxplat_dmi_qmb7xx_matched,
2699 .matches = {
2700 DMI_MATCH(DMI_BOARD_NAME, "VMOD0007"),
2701 },
2702 },
2703 {
2704 .callback = mlxplat_dmi_comex_matched,
2705 .matches = {
2706 DMI_MATCH(DMI_BOARD_NAME, "VMOD0009"),
2707 },
2708 },
2709 {
2710 .callback = mlxplat_dmi_ng400_matched,
2711 .matches = {
2712 DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"),
2713 },
2714 },
2715 {
2716 .callback = mlxplat_dmi_msn274x_matched,
2717 .matches = {
2718 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
2719 DMI_MATCH(DMI_PRODUCT_NAME, "MSN274"),
2720 },
2721 },
2722 {
2723 .callback = mlxplat_dmi_default_matched,
2724 .matches = {
2725 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
2726 DMI_MATCH(DMI_PRODUCT_NAME, "MSN24"),
2727 },
2728 },
2729 {
2730 .callback = mlxplat_dmi_default_matched,
2731 .matches = {
2732 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
2733 DMI_MATCH(DMI_PRODUCT_NAME, "MSN27"),
2734 },
2735 },
2736 {
2737 .callback = mlxplat_dmi_default_matched,
2738 .matches = {
2739 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
2740 DMI_MATCH(DMI_PRODUCT_NAME, "MSB"),
2741 },
2742 },
2743 {
2744 .callback = mlxplat_dmi_default_matched,
2745 .matches = {
2746 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
2747 DMI_MATCH(DMI_PRODUCT_NAME, "MSX"),
2748 },
2749 },
2750 {
2751 .callback = mlxplat_dmi_msn21xx_matched,
2752 .matches = {
2753 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
2754 DMI_MATCH(DMI_PRODUCT_NAME, "MSN21"),
2755 },
2756 },
2757 {
2758 .callback = mlxplat_dmi_msn201x_matched,
2759 .matches = {
2760 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
2761 DMI_MATCH(DMI_PRODUCT_NAME, "MSN201"),
2762 },
2763 },
2764 {
2765 .callback = mlxplat_dmi_qmb7xx_matched,
2766 .matches = {
2767 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
2768 DMI_MATCH(DMI_PRODUCT_NAME, "MQM87"),
2769 },
2770 },
2771 {
2772 .callback = mlxplat_dmi_qmb7xx_matched,
2773 .matches = {
2774 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
2775 DMI_MATCH(DMI_PRODUCT_NAME, "MSN37"),
2776 },
2777 },
2778 {
2779 .callback = mlxplat_dmi_qmb7xx_matched,
2780 .matches = {
2781 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
2782 DMI_MATCH(DMI_PRODUCT_NAME, "MSN34"),
2783 },
2784 },
2785 {
2786 .callback = mlxplat_dmi_qmb7xx_matched,
2787 .matches = {
2788 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
2789 DMI_MATCH(DMI_PRODUCT_NAME, "MSN38"),
2790 },
2791 },
2792 { }
2793};
2794
2795MODULE_DEVICE_TABLE(dmi, mlxplat_dmi_table);
2796
2797static int mlxplat_mlxcpld_verify_bus_topology(int *nr)
2798{
2799 struct i2c_adapter *search_adap;
2800 int shift, i;
2801
2802 /* Scan adapters from expected id to verify it is free. */
2803 *nr = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR;
2804 for (i = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; i <
2805 mlxplat_max_adap_num; i++) {
2806 search_adap = i2c_get_adapter(i);
2807 if (search_adap) {
2808 i2c_put_adapter(search_adap);
2809 continue;
2810 }
2811
2812 /* Return if expected parent adapter is free. */
2813 if (i == MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR)
2814 return 0;
2815 break;
2816 }
2817
2818 /* Return with error if free id for adapter is not found. */
2819 if (i == mlxplat_max_adap_num)
2820 return -ENODEV;
2821
2822 /* Shift adapter ids, since expected parent adapter is not free. */
2823 *nr = i;
2824 for (i = 0; i < mlxplat_mux_num; i++) {
2825 shift = *nr - mlxplat_mux_data[i].parent;
2826 mlxplat_mux_data[i].parent = *nr;
2827 mlxplat_mux_data[i].base_nr += shift;
2828 if (shift > 0)
2829 mlxplat_hotplug->shift_nr = shift;
2830 }
2831
2832 return 0;
2833}
2834
2835static int mlxplat_mlxcpld_check_wd_capability(void *regmap)
2836{
2837 u32 regval;
2838 int i, rc;
2839
2840 rc = regmap_read(regmap, MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
2841 ®val);
2842 if (rc)
2843 return rc;
2844
2845 if (!(regval & ~MLXPLAT_CPLD_WD_CPBLTY_MASK)) {
2846 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type3); i++) {
2847 if (mlxplat_wd_data[i])
2848 mlxplat_wd_data[i] =
2849 &mlxplat_mlxcpld_wd_set_type3[i];
2850 }
2851 }
2852
2853 return 0;
2854}
2855
2856static int __init mlxplat_init(void)
2857{
2858 struct mlxplat_priv *priv;
2859 int i, j, nr, err;
2860
2861 if (!dmi_check_system(mlxplat_dmi_table))
2862 return -ENODEV;
2863
2864 mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, -1,
2865 mlxplat_lpc_resources,
2866 ARRAY_SIZE(mlxplat_lpc_resources));
2867
2868 if (IS_ERR(mlxplat_dev))
2869 return PTR_ERR(mlxplat_dev);
2870
2871 priv = devm_kzalloc(&mlxplat_dev->dev, sizeof(struct mlxplat_priv),
2872 GFP_KERNEL);
2873 if (!priv) {
2874 err = -ENOMEM;
2875 goto fail_alloc;
2876 }
2877 platform_set_drvdata(mlxplat_dev, priv);
2878
2879 mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev,
2880 mlxplat_lpc_resources[1].start, 1);
2881 if (!mlxplat_mlxcpld_regmap_ctx.base) {
2882 err = -ENOMEM;
2883 goto fail_alloc;
2884 }
2885
2886 if (!mlxplat_regmap_config)
2887 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config;
2888
2889 priv->regmap = devm_regmap_init(&mlxplat_dev->dev, NULL,
2890 &mlxplat_mlxcpld_regmap_ctx,
2891 mlxplat_regmap_config);
2892 if (IS_ERR(priv->regmap)) {
2893 err = PTR_ERR(priv->regmap);
2894 goto fail_alloc;
2895 }
2896
2897 err = mlxplat_mlxcpld_verify_bus_topology(&nr);
2898 if (nr < 0)
2899 goto fail_alloc;
2900
2901 nr = (nr == mlxplat_max_adap_num) ? -1 : nr;
2902 if (mlxplat_i2c)
2903 mlxplat_i2c->regmap = priv->regmap;
2904 priv->pdev_i2c = platform_device_register_resndata(
2905 &mlxplat_dev->dev, "i2c_mlxcpld",
2906 nr, mlxplat_mlxcpld_resources,
2907 ARRAY_SIZE(mlxplat_mlxcpld_resources),
2908 mlxplat_i2c, sizeof(*mlxplat_i2c));
2909 if (IS_ERR(priv->pdev_i2c)) {
2910 err = PTR_ERR(priv->pdev_i2c);
2911 goto fail_alloc;
2912 }
2913
2914 for (i = 0; i < mlxplat_mux_num; i++) {
2915 priv->pdev_mux[i] = platform_device_register_resndata(
2916 &priv->pdev_i2c->dev,
2917 "i2c-mux-reg", i, NULL,
2918 0, &mlxplat_mux_data[i],
2919 sizeof(mlxplat_mux_data[i]));
2920 if (IS_ERR(priv->pdev_mux[i])) {
2921 err = PTR_ERR(priv->pdev_mux[i]);
2922 goto fail_platform_mux_register;
2923 }
2924 }
2925
2926 /* Add hotplug driver */
2927 mlxplat_hotplug->regmap = priv->regmap;
2928 priv->pdev_hotplug = platform_device_register_resndata(
2929 &mlxplat_dev->dev, "mlxreg-hotplug",
2930 PLATFORM_DEVID_NONE,
2931 mlxplat_mlxcpld_resources,
2932 ARRAY_SIZE(mlxplat_mlxcpld_resources),
2933 mlxplat_hotplug, sizeof(*mlxplat_hotplug));
2934 if (IS_ERR(priv->pdev_hotplug)) {
2935 err = PTR_ERR(priv->pdev_hotplug);
2936 goto fail_platform_mux_register;
2937 }
2938
2939 /* Set default registers. */
2940 for (j = 0; j < mlxplat_regmap_config->num_reg_defaults; j++) {
2941 err = regmap_write(priv->regmap,
2942 mlxplat_regmap_config->reg_defaults[j].reg,
2943 mlxplat_regmap_config->reg_defaults[j].def);
2944 if (err)
2945 goto fail_platform_mux_register;
2946 }
2947
2948 /* Add LED driver. */
2949 mlxplat_led->regmap = priv->regmap;
2950 priv->pdev_led = platform_device_register_resndata(
2951 &mlxplat_dev->dev, "leds-mlxreg",
2952 PLATFORM_DEVID_NONE, NULL, 0,
2953 mlxplat_led, sizeof(*mlxplat_led));
2954 if (IS_ERR(priv->pdev_led)) {
2955 err = PTR_ERR(priv->pdev_led);
2956 goto fail_platform_hotplug_register;
2957 }
2958
2959 /* Add registers io access driver. */
2960 if (mlxplat_regs_io) {
2961 mlxplat_regs_io->regmap = priv->regmap;
2962 priv->pdev_io_regs = platform_device_register_resndata(
2963 &mlxplat_dev->dev, "mlxreg-io",
2964 PLATFORM_DEVID_NONE, NULL, 0,
2965 mlxplat_regs_io,
2966 sizeof(*mlxplat_regs_io));
2967 if (IS_ERR(priv->pdev_io_regs)) {
2968 err = PTR_ERR(priv->pdev_io_regs);
2969 goto fail_platform_led_register;
2970 }
2971 }
2972
2973 /* Add FAN driver. */
2974 if (mlxplat_fan) {
2975 mlxplat_fan->regmap = priv->regmap;
2976 priv->pdev_fan = platform_device_register_resndata(
2977 &mlxplat_dev->dev, "mlxreg-fan",
2978 PLATFORM_DEVID_NONE, NULL, 0,
2979 mlxplat_fan,
2980 sizeof(*mlxplat_fan));
2981 if (IS_ERR(priv->pdev_fan)) {
2982 err = PTR_ERR(priv->pdev_fan);
2983 goto fail_platform_io_regs_register;
2984 }
2985 }
2986
2987 /* Add WD drivers. */
2988 err = mlxplat_mlxcpld_check_wd_capability(priv->regmap);
2989 if (err)
2990 goto fail_platform_wd_register;
2991 for (j = 0; j < MLXPLAT_CPLD_WD_MAX_DEVS; j++) {
2992 if (mlxplat_wd_data[j]) {
2993 mlxplat_wd_data[j]->regmap = priv->regmap;
2994 priv->pdev_wd[j] = platform_device_register_resndata(
2995 &mlxplat_dev->dev, "mlx-wdt",
2996 j, NULL, 0,
2997 mlxplat_wd_data[j],
2998 sizeof(*mlxplat_wd_data[j]));
2999 if (IS_ERR(priv->pdev_wd[j])) {
3000 err = PTR_ERR(priv->pdev_wd[j]);
3001 goto fail_platform_wd_register;
3002 }
3003 }
3004 }
3005
3006 /* Sync registers with hardware. */
3007 regcache_mark_dirty(priv->regmap);
3008 err = regcache_sync(priv->regmap);
3009 if (err)
3010 goto fail_platform_wd_register;
3011
3012 return 0;
3013
3014fail_platform_wd_register:
3015 while (--j >= 0)
3016 platform_device_unregister(priv->pdev_wd[j]);
3017 if (mlxplat_fan)
3018 platform_device_unregister(priv->pdev_fan);
3019fail_platform_io_regs_register:
3020 if (mlxplat_regs_io)
3021 platform_device_unregister(priv->pdev_io_regs);
3022fail_platform_led_register:
3023 platform_device_unregister(priv->pdev_led);
3024fail_platform_hotplug_register:
3025 platform_device_unregister(priv->pdev_hotplug);
3026fail_platform_mux_register:
3027 while (--i >= 0)
3028 platform_device_unregister(priv->pdev_mux[i]);
3029 platform_device_unregister(priv->pdev_i2c);
3030fail_alloc:
3031 platform_device_unregister(mlxplat_dev);
3032
3033 return err;
3034}
3035module_init(mlxplat_init);
3036
3037static void __exit mlxplat_exit(void)
3038{
3039 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);
3040 int i;
3041
3042 for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--)
3043 platform_device_unregister(priv->pdev_wd[i]);
3044 if (priv->pdev_fan)
3045 platform_device_unregister(priv->pdev_fan);
3046 if (priv->pdev_io_regs)
3047 platform_device_unregister(priv->pdev_io_regs);
3048 platform_device_unregister(priv->pdev_led);
3049 platform_device_unregister(priv->pdev_hotplug);
3050
3051 for (i = mlxplat_mux_num - 1; i >= 0 ; i--)
3052 platform_device_unregister(priv->pdev_mux[i]);
3053
3054 platform_device_unregister(priv->pdev_i2c);
3055 platform_device_unregister(mlxplat_dev);
3056}
3057module_exit(mlxplat_exit);
3058
3059MODULE_AUTHOR("Vadim Pasternak (vadimp@mellanox.com)");
3060MODULE_DESCRIPTION("Mellanox platform driver");
3061MODULE_LICENSE("Dual BSD/GPL");