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1#include <linux/delay.h>
2#include <linux/pci.h>
3#include <linux/module.h>
4#include <linux/sched.h>
5#include <linux/slab.h>
6#include <linux/ioport.h>
7#include <linux/wait.h>
8
9#include "pci.h"
10
11/*
12 * This interrupt-safe spinlock protects all accesses to PCI
13 * configuration space.
14 */
15
16static DEFINE_RAW_SPINLOCK(pci_lock);
17
18/*
19 * Wrappers for all PCI configuration access functions. They just check
20 * alignment, do locking and call the low-level functions pointed to
21 * by pci_dev->ops.
22 */
23
24#define PCI_byte_BAD 0
25#define PCI_word_BAD (pos & 1)
26#define PCI_dword_BAD (pos & 3)
27
28#define PCI_OP_READ(size,type,len) \
29int pci_bus_read_config_##size \
30 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
31{ \
32 int res; \
33 unsigned long flags; \
34 u32 data = 0; \
35 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
36 raw_spin_lock_irqsave(&pci_lock, flags); \
37 res = bus->ops->read(bus, devfn, pos, len, &data); \
38 *value = (type)data; \
39 raw_spin_unlock_irqrestore(&pci_lock, flags); \
40 return res; \
41}
42
43#define PCI_OP_WRITE(size,type,len) \
44int pci_bus_write_config_##size \
45 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
46{ \
47 int res; \
48 unsigned long flags; \
49 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
50 raw_spin_lock_irqsave(&pci_lock, flags); \
51 res = bus->ops->write(bus, devfn, pos, len, value); \
52 raw_spin_unlock_irqrestore(&pci_lock, flags); \
53 return res; \
54}
55
56PCI_OP_READ(byte, u8, 1)
57PCI_OP_READ(word, u16, 2)
58PCI_OP_READ(dword, u32, 4)
59PCI_OP_WRITE(byte, u8, 1)
60PCI_OP_WRITE(word, u16, 2)
61PCI_OP_WRITE(dword, u32, 4)
62
63EXPORT_SYMBOL(pci_bus_read_config_byte);
64EXPORT_SYMBOL(pci_bus_read_config_word);
65EXPORT_SYMBOL(pci_bus_read_config_dword);
66EXPORT_SYMBOL(pci_bus_write_config_byte);
67EXPORT_SYMBOL(pci_bus_write_config_word);
68EXPORT_SYMBOL(pci_bus_write_config_dword);
69
70/**
71 * pci_bus_set_ops - Set raw operations of pci bus
72 * @bus: pci bus struct
73 * @ops: new raw operations
74 *
75 * Return previous raw operations
76 */
77struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
78{
79 struct pci_ops *old_ops;
80 unsigned long flags;
81
82 raw_spin_lock_irqsave(&pci_lock, flags);
83 old_ops = bus->ops;
84 bus->ops = ops;
85 raw_spin_unlock_irqrestore(&pci_lock, flags);
86 return old_ops;
87}
88EXPORT_SYMBOL(pci_bus_set_ops);
89
90/**
91 * pci_read_vpd - Read one entry from Vital Product Data
92 * @dev: pci device struct
93 * @pos: offset in vpd space
94 * @count: number of bytes to read
95 * @buf: pointer to where to store result
96 *
97 */
98ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
99{
100 if (!dev->vpd || !dev->vpd->ops)
101 return -ENODEV;
102 return dev->vpd->ops->read(dev, pos, count, buf);
103}
104EXPORT_SYMBOL(pci_read_vpd);
105
106/**
107 * pci_write_vpd - Write entry to Vital Product Data
108 * @dev: pci device struct
109 * @pos: offset in vpd space
110 * @count: number of bytes to write
111 * @buf: buffer containing write data
112 *
113 */
114ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
115{
116 if (!dev->vpd || !dev->vpd->ops)
117 return -ENODEV;
118 return dev->vpd->ops->write(dev, pos, count, buf);
119}
120EXPORT_SYMBOL(pci_write_vpd);
121
122/*
123 * The following routines are to prevent the user from accessing PCI config
124 * space when it's unsafe to do so. Some devices require this during BIST and
125 * we're required to prevent it during D-state transitions.
126 *
127 * We have a bit per device to indicate it's blocked and a global wait queue
128 * for callers to sleep on until devices are unblocked.
129 */
130static DECLARE_WAIT_QUEUE_HEAD(pci_ucfg_wait);
131
132static noinline void pci_wait_ucfg(struct pci_dev *dev)
133{
134 DECLARE_WAITQUEUE(wait, current);
135
136 __add_wait_queue(&pci_ucfg_wait, &wait);
137 do {
138 set_current_state(TASK_UNINTERRUPTIBLE);
139 raw_spin_unlock_irq(&pci_lock);
140 schedule();
141 raw_spin_lock_irq(&pci_lock);
142 } while (dev->block_ucfg_access);
143 __remove_wait_queue(&pci_ucfg_wait, &wait);
144}
145
146/* Returns 0 on success, negative values indicate error. */
147#define PCI_USER_READ_CONFIG(size,type) \
148int pci_user_read_config_##size \
149 (struct pci_dev *dev, int pos, type *val) \
150{ \
151 int ret = 0; \
152 u32 data = -1; \
153 if (PCI_##size##_BAD) \
154 return -EINVAL; \
155 raw_spin_lock_irq(&pci_lock); \
156 if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \
157 ret = dev->bus->ops->read(dev->bus, dev->devfn, \
158 pos, sizeof(type), &data); \
159 raw_spin_unlock_irq(&pci_lock); \
160 *val = (type)data; \
161 if (ret > 0) \
162 ret = -EINVAL; \
163 return ret; \
164}
165
166/* Returns 0 on success, negative values indicate error. */
167#define PCI_USER_WRITE_CONFIG(size,type) \
168int pci_user_write_config_##size \
169 (struct pci_dev *dev, int pos, type val) \
170{ \
171 int ret = -EIO; \
172 if (PCI_##size##_BAD) \
173 return -EINVAL; \
174 raw_spin_lock_irq(&pci_lock); \
175 if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \
176 ret = dev->bus->ops->write(dev->bus, dev->devfn, \
177 pos, sizeof(type), val); \
178 raw_spin_unlock_irq(&pci_lock); \
179 if (ret > 0) \
180 ret = -EINVAL; \
181 return ret; \
182}
183
184PCI_USER_READ_CONFIG(byte, u8)
185PCI_USER_READ_CONFIG(word, u16)
186PCI_USER_READ_CONFIG(dword, u32)
187PCI_USER_WRITE_CONFIG(byte, u8)
188PCI_USER_WRITE_CONFIG(word, u16)
189PCI_USER_WRITE_CONFIG(dword, u32)
190
191/* VPD access through PCI 2.2+ VPD capability */
192
193#define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1)
194
195struct pci_vpd_pci22 {
196 struct pci_vpd base;
197 struct mutex lock;
198 u16 flag;
199 bool busy;
200 u8 cap;
201};
202
203/*
204 * Wait for last operation to complete.
205 * This code has to spin since there is no other notification from the PCI
206 * hardware. Since the VPD is often implemented by serial attachment to an
207 * EEPROM, it may take many milliseconds to complete.
208 *
209 * Returns 0 on success, negative values indicate error.
210 */
211static int pci_vpd_pci22_wait(struct pci_dev *dev)
212{
213 struct pci_vpd_pci22 *vpd =
214 container_of(dev->vpd, struct pci_vpd_pci22, base);
215 unsigned long timeout = jiffies + HZ/20 + 2;
216 u16 status;
217 int ret;
218
219 if (!vpd->busy)
220 return 0;
221
222 for (;;) {
223 ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
224 &status);
225 if (ret < 0)
226 return ret;
227
228 if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
229 vpd->busy = false;
230 return 0;
231 }
232
233 if (time_after(jiffies, timeout)) {
234 dev_printk(KERN_DEBUG, &dev->dev,
235 "vpd r/w failed. This is likely a firmware "
236 "bug on this device. Contact the card "
237 "vendor for a firmware update.");
238 return -ETIMEDOUT;
239 }
240 if (fatal_signal_pending(current))
241 return -EINTR;
242 if (!cond_resched())
243 udelay(10);
244 }
245}
246
247static ssize_t pci_vpd_pci22_read(struct pci_dev *dev, loff_t pos, size_t count,
248 void *arg)
249{
250 struct pci_vpd_pci22 *vpd =
251 container_of(dev->vpd, struct pci_vpd_pci22, base);
252 int ret;
253 loff_t end = pos + count;
254 u8 *buf = arg;
255
256 if (pos < 0 || pos > vpd->base.len || end > vpd->base.len)
257 return -EINVAL;
258
259 if (mutex_lock_killable(&vpd->lock))
260 return -EINTR;
261
262 ret = pci_vpd_pci22_wait(dev);
263 if (ret < 0)
264 goto out;
265
266 while (pos < end) {
267 u32 val;
268 unsigned int i, skip;
269
270 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
271 pos & ~3);
272 if (ret < 0)
273 break;
274 vpd->busy = true;
275 vpd->flag = PCI_VPD_ADDR_F;
276 ret = pci_vpd_pci22_wait(dev);
277 if (ret < 0)
278 break;
279
280 ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
281 if (ret < 0)
282 break;
283
284 skip = pos & 3;
285 for (i = 0; i < sizeof(u32); i++) {
286 if (i >= skip) {
287 *buf++ = val;
288 if (++pos == end)
289 break;
290 }
291 val >>= 8;
292 }
293 }
294out:
295 mutex_unlock(&vpd->lock);
296 return ret ? ret : count;
297}
298
299static ssize_t pci_vpd_pci22_write(struct pci_dev *dev, loff_t pos, size_t count,
300 const void *arg)
301{
302 struct pci_vpd_pci22 *vpd =
303 container_of(dev->vpd, struct pci_vpd_pci22, base);
304 const u8 *buf = arg;
305 loff_t end = pos + count;
306 int ret = 0;
307
308 if (pos < 0 || (pos & 3) || (count & 3) || end > vpd->base.len)
309 return -EINVAL;
310
311 if (mutex_lock_killable(&vpd->lock))
312 return -EINTR;
313
314 ret = pci_vpd_pci22_wait(dev);
315 if (ret < 0)
316 goto out;
317
318 while (pos < end) {
319 u32 val;
320
321 val = *buf++;
322 val |= *buf++ << 8;
323 val |= *buf++ << 16;
324 val |= *buf++ << 24;
325
326 ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
327 if (ret < 0)
328 break;
329 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
330 pos | PCI_VPD_ADDR_F);
331 if (ret < 0)
332 break;
333
334 vpd->busy = true;
335 vpd->flag = 0;
336 ret = pci_vpd_pci22_wait(dev);
337 if (ret < 0)
338 break;
339
340 pos += sizeof(u32);
341 }
342out:
343 mutex_unlock(&vpd->lock);
344 return ret ? ret : count;
345}
346
347static void pci_vpd_pci22_release(struct pci_dev *dev)
348{
349 kfree(container_of(dev->vpd, struct pci_vpd_pci22, base));
350}
351
352static const struct pci_vpd_ops pci_vpd_pci22_ops = {
353 .read = pci_vpd_pci22_read,
354 .write = pci_vpd_pci22_write,
355 .release = pci_vpd_pci22_release,
356};
357
358int pci_vpd_pci22_init(struct pci_dev *dev)
359{
360 struct pci_vpd_pci22 *vpd;
361 u8 cap;
362
363 cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
364 if (!cap)
365 return -ENODEV;
366 vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
367 if (!vpd)
368 return -ENOMEM;
369
370 vpd->base.len = PCI_VPD_PCI22_SIZE;
371 vpd->base.ops = &pci_vpd_pci22_ops;
372 mutex_init(&vpd->lock);
373 vpd->cap = cap;
374 vpd->busy = false;
375 dev->vpd = &vpd->base;
376 return 0;
377}
378
379/**
380 * pci_vpd_truncate - Set available Vital Product Data size
381 * @dev: pci device struct
382 * @size: available memory in bytes
383 *
384 * Adjust size of available VPD area.
385 */
386int pci_vpd_truncate(struct pci_dev *dev, size_t size)
387{
388 if (!dev->vpd)
389 return -EINVAL;
390
391 /* limited by the access method */
392 if (size > dev->vpd->len)
393 return -EINVAL;
394
395 dev->vpd->len = size;
396 if (dev->vpd->attr)
397 dev->vpd->attr->size = size;
398
399 return 0;
400}
401EXPORT_SYMBOL(pci_vpd_truncate);
402
403/**
404 * pci_block_user_cfg_access - Block userspace PCI config reads/writes
405 * @dev: pci device struct
406 *
407 * When user access is blocked, any reads or writes to config space will
408 * sleep until access is unblocked again. We don't allow nesting of
409 * block/unblock calls.
410 */
411void pci_block_user_cfg_access(struct pci_dev *dev)
412{
413 unsigned long flags;
414 int was_blocked;
415
416 raw_spin_lock_irqsave(&pci_lock, flags);
417 was_blocked = dev->block_ucfg_access;
418 dev->block_ucfg_access = 1;
419 raw_spin_unlock_irqrestore(&pci_lock, flags);
420
421 /* If we BUG() inside the pci_lock, we're guaranteed to hose
422 * the machine */
423 BUG_ON(was_blocked);
424}
425EXPORT_SYMBOL_GPL(pci_block_user_cfg_access);
426
427/**
428 * pci_unblock_user_cfg_access - Unblock userspace PCI config reads/writes
429 * @dev: pci device struct
430 *
431 * This function allows userspace PCI config accesses to resume.
432 */
433void pci_unblock_user_cfg_access(struct pci_dev *dev)
434{
435 unsigned long flags;
436
437 raw_spin_lock_irqsave(&pci_lock, flags);
438
439 /* This indicates a problem in the caller, but we don't need
440 * to kill them, unlike a double-block above. */
441 WARN_ON(!dev->block_ucfg_access);
442
443 dev->block_ucfg_access = 0;
444 wake_up_all(&pci_ucfg_wait);
445 raw_spin_unlock_irqrestore(&pci_lock, flags);
446}
447EXPORT_SYMBOL_GPL(pci_unblock_user_cfg_access);
1// SPDX-License-Identifier: GPL-2.0
2#include <linux/pci.h>
3#include <linux/module.h>
4#include <linux/slab.h>
5#include <linux/ioport.h>
6#include <linux/wait.h>
7
8#include "pci.h"
9
10/*
11 * This interrupt-safe spinlock protects all accesses to PCI
12 * configuration space.
13 */
14
15DEFINE_RAW_SPINLOCK(pci_lock);
16
17/*
18 * Wrappers for all PCI configuration access functions. They just check
19 * alignment, do locking and call the low-level functions pointed to
20 * by pci_dev->ops.
21 */
22
23#define PCI_byte_BAD 0
24#define PCI_word_BAD (pos & 1)
25#define PCI_dword_BAD (pos & 3)
26
27#ifdef CONFIG_PCI_LOCKLESS_CONFIG
28# define pci_lock_config(f) do { (void)(f); } while (0)
29# define pci_unlock_config(f) do { (void)(f); } while (0)
30#else
31# define pci_lock_config(f) raw_spin_lock_irqsave(&pci_lock, f)
32# define pci_unlock_config(f) raw_spin_unlock_irqrestore(&pci_lock, f)
33#endif
34
35#define PCI_OP_READ(size, type, len) \
36int noinline pci_bus_read_config_##size \
37 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
38{ \
39 int res; \
40 unsigned long flags; \
41 u32 data = 0; \
42 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
43 pci_lock_config(flags); \
44 res = bus->ops->read(bus, devfn, pos, len, &data); \
45 *value = (type)data; \
46 pci_unlock_config(flags); \
47 return res; \
48}
49
50#define PCI_OP_WRITE(size, type, len) \
51int noinline pci_bus_write_config_##size \
52 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
53{ \
54 int res; \
55 unsigned long flags; \
56 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
57 pci_lock_config(flags); \
58 res = bus->ops->write(bus, devfn, pos, len, value); \
59 pci_unlock_config(flags); \
60 return res; \
61}
62
63PCI_OP_READ(byte, u8, 1)
64PCI_OP_READ(word, u16, 2)
65PCI_OP_READ(dword, u32, 4)
66PCI_OP_WRITE(byte, u8, 1)
67PCI_OP_WRITE(word, u16, 2)
68PCI_OP_WRITE(dword, u32, 4)
69
70EXPORT_SYMBOL(pci_bus_read_config_byte);
71EXPORT_SYMBOL(pci_bus_read_config_word);
72EXPORT_SYMBOL(pci_bus_read_config_dword);
73EXPORT_SYMBOL(pci_bus_write_config_byte);
74EXPORT_SYMBOL(pci_bus_write_config_word);
75EXPORT_SYMBOL(pci_bus_write_config_dword);
76
77int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
78 int where, int size, u32 *val)
79{
80 void __iomem *addr;
81
82 addr = bus->ops->map_bus(bus, devfn, where);
83 if (!addr) {
84 *val = ~0;
85 return PCIBIOS_DEVICE_NOT_FOUND;
86 }
87
88 if (size == 1)
89 *val = readb(addr);
90 else if (size == 2)
91 *val = readw(addr);
92 else
93 *val = readl(addr);
94
95 return PCIBIOS_SUCCESSFUL;
96}
97EXPORT_SYMBOL_GPL(pci_generic_config_read);
98
99int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
100 int where, int size, u32 val)
101{
102 void __iomem *addr;
103
104 addr = bus->ops->map_bus(bus, devfn, where);
105 if (!addr)
106 return PCIBIOS_DEVICE_NOT_FOUND;
107
108 if (size == 1)
109 writeb(val, addr);
110 else if (size == 2)
111 writew(val, addr);
112 else
113 writel(val, addr);
114
115 return PCIBIOS_SUCCESSFUL;
116}
117EXPORT_SYMBOL_GPL(pci_generic_config_write);
118
119int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
120 int where, int size, u32 *val)
121{
122 void __iomem *addr;
123
124 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
125 if (!addr) {
126 *val = ~0;
127 return PCIBIOS_DEVICE_NOT_FOUND;
128 }
129
130 *val = readl(addr);
131
132 if (size <= 2)
133 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
134
135 return PCIBIOS_SUCCESSFUL;
136}
137EXPORT_SYMBOL_GPL(pci_generic_config_read32);
138
139int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
140 int where, int size, u32 val)
141{
142 void __iomem *addr;
143 u32 mask, tmp;
144
145 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
146 if (!addr)
147 return PCIBIOS_DEVICE_NOT_FOUND;
148
149 if (size == 4) {
150 writel(val, addr);
151 return PCIBIOS_SUCCESSFUL;
152 }
153
154 /*
155 * In general, hardware that supports only 32-bit writes on PCI is
156 * not spec-compliant. For example, software may perform a 16-bit
157 * write. If the hardware only supports 32-bit accesses, we must
158 * do a 32-bit read, merge in the 16 bits we intend to write,
159 * followed by a 32-bit write. If the 16 bits we *don't* intend to
160 * write happen to have any RW1C (write-one-to-clear) bits set, we
161 * just inadvertently cleared something we shouldn't have.
162 */
163 dev_warn_ratelimited(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
164 size, pci_domain_nr(bus), bus->number,
165 PCI_SLOT(devfn), PCI_FUNC(devfn), where);
166
167 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
168 tmp = readl(addr) & mask;
169 tmp |= val << ((where & 0x3) * 8);
170 writel(tmp, addr);
171
172 return PCIBIOS_SUCCESSFUL;
173}
174EXPORT_SYMBOL_GPL(pci_generic_config_write32);
175
176/**
177 * pci_bus_set_ops - Set raw operations of pci bus
178 * @bus: pci bus struct
179 * @ops: new raw operations
180 *
181 * Return previous raw operations
182 */
183struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
184{
185 struct pci_ops *old_ops;
186 unsigned long flags;
187
188 raw_spin_lock_irqsave(&pci_lock, flags);
189 old_ops = bus->ops;
190 bus->ops = ops;
191 raw_spin_unlock_irqrestore(&pci_lock, flags);
192 return old_ops;
193}
194EXPORT_SYMBOL(pci_bus_set_ops);
195
196/*
197 * The following routines are to prevent the user from accessing PCI config
198 * space when it's unsafe to do so. Some devices require this during BIST and
199 * we're required to prevent it during D-state transitions.
200 *
201 * We have a bit per device to indicate it's blocked and a global wait queue
202 * for callers to sleep on until devices are unblocked.
203 */
204static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
205
206static noinline void pci_wait_cfg(struct pci_dev *dev)
207 __must_hold(&pci_lock)
208{
209 do {
210 raw_spin_unlock_irq(&pci_lock);
211 wait_event(pci_cfg_wait, !dev->block_cfg_access);
212 raw_spin_lock_irq(&pci_lock);
213 } while (dev->block_cfg_access);
214}
215
216/* Returns 0 on success, negative values indicate error. */
217#define PCI_USER_READ_CONFIG(size, type) \
218int pci_user_read_config_##size \
219 (struct pci_dev *dev, int pos, type *val) \
220{ \
221 int ret = PCIBIOS_SUCCESSFUL; \
222 u32 data = -1; \
223 if (PCI_##size##_BAD) \
224 return -EINVAL; \
225 raw_spin_lock_irq(&pci_lock); \
226 if (unlikely(dev->block_cfg_access)) \
227 pci_wait_cfg(dev); \
228 ret = dev->bus->ops->read(dev->bus, dev->devfn, \
229 pos, sizeof(type), &data); \
230 raw_spin_unlock_irq(&pci_lock); \
231 *val = (type)data; \
232 return pcibios_err_to_errno(ret); \
233} \
234EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
235
236/* Returns 0 on success, negative values indicate error. */
237#define PCI_USER_WRITE_CONFIG(size, type) \
238int pci_user_write_config_##size \
239 (struct pci_dev *dev, int pos, type val) \
240{ \
241 int ret = PCIBIOS_SUCCESSFUL; \
242 if (PCI_##size##_BAD) \
243 return -EINVAL; \
244 raw_spin_lock_irq(&pci_lock); \
245 if (unlikely(dev->block_cfg_access)) \
246 pci_wait_cfg(dev); \
247 ret = dev->bus->ops->write(dev->bus, dev->devfn, \
248 pos, sizeof(type), val); \
249 raw_spin_unlock_irq(&pci_lock); \
250 return pcibios_err_to_errno(ret); \
251} \
252EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
253
254PCI_USER_READ_CONFIG(byte, u8)
255PCI_USER_READ_CONFIG(word, u16)
256PCI_USER_READ_CONFIG(dword, u32)
257PCI_USER_WRITE_CONFIG(byte, u8)
258PCI_USER_WRITE_CONFIG(word, u16)
259PCI_USER_WRITE_CONFIG(dword, u32)
260
261/**
262 * pci_cfg_access_lock - Lock PCI config reads/writes
263 * @dev: pci device struct
264 *
265 * When access is locked, any userspace reads or writes to config
266 * space and concurrent lock requests will sleep until access is
267 * allowed via pci_cfg_access_unlock() again.
268 */
269void pci_cfg_access_lock(struct pci_dev *dev)
270{
271 might_sleep();
272
273 raw_spin_lock_irq(&pci_lock);
274 if (dev->block_cfg_access)
275 pci_wait_cfg(dev);
276 dev->block_cfg_access = 1;
277 raw_spin_unlock_irq(&pci_lock);
278}
279EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
280
281/**
282 * pci_cfg_access_trylock - try to lock PCI config reads/writes
283 * @dev: pci device struct
284 *
285 * Same as pci_cfg_access_lock, but will return 0 if access is
286 * already locked, 1 otherwise. This function can be used from
287 * atomic contexts.
288 */
289bool pci_cfg_access_trylock(struct pci_dev *dev)
290{
291 unsigned long flags;
292 bool locked = true;
293
294 raw_spin_lock_irqsave(&pci_lock, flags);
295 if (dev->block_cfg_access)
296 locked = false;
297 else
298 dev->block_cfg_access = 1;
299 raw_spin_unlock_irqrestore(&pci_lock, flags);
300
301 return locked;
302}
303EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
304
305/**
306 * pci_cfg_access_unlock - Unlock PCI config reads/writes
307 * @dev: pci device struct
308 *
309 * This function allows PCI config accesses to resume.
310 */
311void pci_cfg_access_unlock(struct pci_dev *dev)
312{
313 unsigned long flags;
314
315 raw_spin_lock_irqsave(&pci_lock, flags);
316
317 /*
318 * This indicates a problem in the caller, but we don't need
319 * to kill them, unlike a double-block above.
320 */
321 WARN_ON(!dev->block_cfg_access);
322
323 dev->block_cfg_access = 0;
324 raw_spin_unlock_irqrestore(&pci_lock, flags);
325
326 wake_up_all(&pci_cfg_wait);
327}
328EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
329
330static inline int pcie_cap_version(const struct pci_dev *dev)
331{
332 return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
333}
334
335bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
336{
337 int type = pci_pcie_type(dev);
338
339 return type == PCI_EXP_TYPE_ENDPOINT ||
340 type == PCI_EXP_TYPE_LEG_END ||
341 type == PCI_EXP_TYPE_ROOT_PORT ||
342 type == PCI_EXP_TYPE_UPSTREAM ||
343 type == PCI_EXP_TYPE_DOWNSTREAM ||
344 type == PCI_EXP_TYPE_PCI_BRIDGE ||
345 type == PCI_EXP_TYPE_PCIE_BRIDGE;
346}
347
348static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
349{
350 return pcie_downstream_port(dev) &&
351 pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
352}
353
354bool pcie_cap_has_rtctl(const struct pci_dev *dev)
355{
356 int type = pci_pcie_type(dev);
357
358 return type == PCI_EXP_TYPE_ROOT_PORT ||
359 type == PCI_EXP_TYPE_RC_EC;
360}
361
362static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
363{
364 if (!pci_is_pcie(dev))
365 return false;
366
367 switch (pos) {
368 case PCI_EXP_FLAGS:
369 return true;
370 case PCI_EXP_DEVCAP:
371 case PCI_EXP_DEVCTL:
372 case PCI_EXP_DEVSTA:
373 return true;
374 case PCI_EXP_LNKCAP:
375 case PCI_EXP_LNKCTL:
376 case PCI_EXP_LNKSTA:
377 return pcie_cap_has_lnkctl(dev);
378 case PCI_EXP_SLTCAP:
379 case PCI_EXP_SLTCTL:
380 case PCI_EXP_SLTSTA:
381 return pcie_cap_has_sltctl(dev);
382 case PCI_EXP_RTCTL:
383 case PCI_EXP_RTCAP:
384 case PCI_EXP_RTSTA:
385 return pcie_cap_has_rtctl(dev);
386 case PCI_EXP_DEVCAP2:
387 case PCI_EXP_DEVCTL2:
388 case PCI_EXP_LNKCAP2:
389 case PCI_EXP_LNKCTL2:
390 case PCI_EXP_LNKSTA2:
391 return pcie_cap_version(dev) > 1;
392 default:
393 return false;
394 }
395}
396
397/*
398 * Note that these accessor functions are only for the "PCI Express
399 * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
400 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
401 */
402int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
403{
404 int ret;
405
406 *val = 0;
407 if (pos & 1)
408 return PCIBIOS_BAD_REGISTER_NUMBER;
409
410 if (pcie_capability_reg_implemented(dev, pos)) {
411 ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
412 /*
413 * Reset *val to 0 if pci_read_config_word() fails, it may
414 * have been written as 0xFFFF if hardware error happens
415 * during pci_read_config_word().
416 */
417 if (ret)
418 *val = 0;
419 return ret;
420 }
421
422 /*
423 * For Functions that do not implement the Slot Capabilities,
424 * Slot Status, and Slot Control registers, these spaces must
425 * be hardwired to 0b, with the exception of the Presence Detect
426 * State bit in the Slot Status register of Downstream Ports,
427 * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
428 */
429 if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
430 pos == PCI_EXP_SLTSTA)
431 *val = PCI_EXP_SLTSTA_PDS;
432
433 return 0;
434}
435EXPORT_SYMBOL(pcie_capability_read_word);
436
437int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
438{
439 int ret;
440
441 *val = 0;
442 if (pos & 3)
443 return PCIBIOS_BAD_REGISTER_NUMBER;
444
445 if (pcie_capability_reg_implemented(dev, pos)) {
446 ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
447 /*
448 * Reset *val to 0 if pci_read_config_dword() fails, it may
449 * have been written as 0xFFFFFFFF if hardware error happens
450 * during pci_read_config_dword().
451 */
452 if (ret)
453 *val = 0;
454 return ret;
455 }
456
457 if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
458 pos == PCI_EXP_SLTSTA)
459 *val = PCI_EXP_SLTSTA_PDS;
460
461 return 0;
462}
463EXPORT_SYMBOL(pcie_capability_read_dword);
464
465int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
466{
467 if (pos & 1)
468 return PCIBIOS_BAD_REGISTER_NUMBER;
469
470 if (!pcie_capability_reg_implemented(dev, pos))
471 return 0;
472
473 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
474}
475EXPORT_SYMBOL(pcie_capability_write_word);
476
477int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
478{
479 if (pos & 3)
480 return PCIBIOS_BAD_REGISTER_NUMBER;
481
482 if (!pcie_capability_reg_implemented(dev, pos))
483 return 0;
484
485 return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
486}
487EXPORT_SYMBOL(pcie_capability_write_dword);
488
489int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
490 u16 clear, u16 set)
491{
492 int ret;
493 u16 val;
494
495 ret = pcie_capability_read_word(dev, pos, &val);
496 if (!ret) {
497 val &= ~clear;
498 val |= set;
499 ret = pcie_capability_write_word(dev, pos, val);
500 }
501
502 return ret;
503}
504EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
505
506int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
507 u32 clear, u32 set)
508{
509 int ret;
510 u32 val;
511
512 ret = pcie_capability_read_dword(dev, pos, &val);
513 if (!ret) {
514 val &= ~clear;
515 val |= set;
516 ret = pcie_capability_write_dword(dev, pos, val);
517 }
518
519 return ret;
520}
521EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);
522
523int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
524{
525 if (pci_dev_is_disconnected(dev)) {
526 *val = ~0;
527 return PCIBIOS_DEVICE_NOT_FOUND;
528 }
529 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
530}
531EXPORT_SYMBOL(pci_read_config_byte);
532
533int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
534{
535 if (pci_dev_is_disconnected(dev)) {
536 *val = ~0;
537 return PCIBIOS_DEVICE_NOT_FOUND;
538 }
539 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
540}
541EXPORT_SYMBOL(pci_read_config_word);
542
543int pci_read_config_dword(const struct pci_dev *dev, int where,
544 u32 *val)
545{
546 if (pci_dev_is_disconnected(dev)) {
547 *val = ~0;
548 return PCIBIOS_DEVICE_NOT_FOUND;
549 }
550 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
551}
552EXPORT_SYMBOL(pci_read_config_dword);
553
554int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
555{
556 if (pci_dev_is_disconnected(dev))
557 return PCIBIOS_DEVICE_NOT_FOUND;
558 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
559}
560EXPORT_SYMBOL(pci_write_config_byte);
561
562int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
563{
564 if (pci_dev_is_disconnected(dev))
565 return PCIBIOS_DEVICE_NOT_FOUND;
566 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
567}
568EXPORT_SYMBOL(pci_write_config_word);
569
570int pci_write_config_dword(const struct pci_dev *dev, int where,
571 u32 val)
572{
573 if (pci_dev_is_disconnected(dev))
574 return PCIBIOS_DEVICE_NOT_FOUND;
575 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
576}
577EXPORT_SYMBOL(pci_write_config_dword);