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1/*
2 * drivers/net/phy/national.c
3 *
4 * Driver for National Semiconductor PHYs
5 *
6 * Author: Stuart Menefy <stuart.menefy@st.com>
7 * Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
8 *
9 * Copyright (c) 2008 STMicroelectronics Limited
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/mii.h>
21#include <linux/ethtool.h>
22#include <linux/phy.h>
23#include <linux/netdevice.h>
24
25/* DP83865 phy identifier values */
26#define DP83865_PHY_ID 0x20005c7a
27
28#define DP83865_INT_STATUS 0x14
29#define DP83865_INT_MASK 0x15
30#define DP83865_INT_CLEAR 0x17
31
32#define DP83865_INT_REMOTE_FAULT 0x0008
33#define DP83865_INT_ANE_COMPLETED 0x0010
34#define DP83865_INT_LINK_CHANGE 0xe000
35#define DP83865_INT_MASK_DEFAULT (DP83865_INT_REMOTE_FAULT | \
36 DP83865_INT_ANE_COMPLETED | \
37 DP83865_INT_LINK_CHANGE)
38
39/* Advanced proprietary configuration */
40#define NS_EXP_MEM_CTL 0x16
41#define NS_EXP_MEM_DATA 0x1d
42#define NS_EXP_MEM_ADD 0x1e
43
44#define LED_CTRL_REG 0x13
45#define AN_FALLBACK_AN 0x0001
46#define AN_FALLBACK_CRC 0x0002
47#define AN_FALLBACK_IE 0x0004
48#define ALL_FALLBACK_ON (AN_FALLBACK_AN | AN_FALLBACK_CRC | AN_FALLBACK_IE)
49
50enum hdx_loopback {
51 hdx_loopback_on = 0,
52 hdx_loopback_off = 1,
53};
54
55static u8 ns_exp_read(struct phy_device *phydev, u16 reg)
56{
57 phy_write(phydev, NS_EXP_MEM_ADD, reg);
58 return phy_read(phydev, NS_EXP_MEM_DATA);
59}
60
61static void ns_exp_write(struct phy_device *phydev, u16 reg, u8 data)
62{
63 phy_write(phydev, NS_EXP_MEM_ADD, reg);
64 phy_write(phydev, NS_EXP_MEM_DATA, data);
65}
66
67static int ns_config_intr(struct phy_device *phydev)
68{
69 int err;
70
71 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
72 err = phy_write(phydev, DP83865_INT_MASK,
73 DP83865_INT_MASK_DEFAULT);
74 else
75 err = phy_write(phydev, DP83865_INT_MASK, 0);
76
77 return err;
78}
79
80static int ns_ack_interrupt(struct phy_device *phydev)
81{
82 int ret = phy_read(phydev, DP83865_INT_STATUS);
83 if (ret < 0)
84 return ret;
85
86 /* Clear the interrupt status bit by writing a “1”
87 * to the corresponding bit in INT_CLEAR (2:0 are reserved) */
88 ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7);
89
90 return ret;
91}
92
93static void ns_giga_speed_fallback(struct phy_device *phydev, int mode)
94{
95 int bmcr = phy_read(phydev, MII_BMCR);
96
97 phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN));
98
99 /* Enable 8 bit expended memory read/write (no auto increment) */
100 phy_write(phydev, NS_EXP_MEM_CTL, 0);
101 phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0);
102 phy_write(phydev, NS_EXP_MEM_DATA, 0x0008);
103 phy_write(phydev, MII_BMCR, (bmcr & ~BMCR_PDOWN));
104 phy_write(phydev, LED_CTRL_REG, mode);
105}
106
107static void ns_10_base_t_hdx_loopack(struct phy_device *phydev, int disable)
108{
109 if (disable)
110 ns_exp_write(phydev, 0x1c0, ns_exp_read(phydev, 0x1c0) | 1);
111 else
112 ns_exp_write(phydev, 0x1c0,
113 ns_exp_read(phydev, 0x1c0) & 0xfffe);
114
115 printk(KERN_DEBUG "DP83865 PHY: 10BASE-T HDX loopback %s\n",
116 (ns_exp_read(phydev, 0x1c0) & 0x0001) ? "off" : "on");
117}
118
119static int ns_config_init(struct phy_device *phydev)
120{
121 ns_giga_speed_fallback(phydev, ALL_FALLBACK_ON);
122 /* In the latest MAC or switches design, the 10 Mbps loopback
123 is desired to be turned off. */
124 ns_10_base_t_hdx_loopack(phydev, hdx_loopback_off);
125 return ns_ack_interrupt(phydev);
126}
127
128static struct phy_driver dp83865_driver = {
129 .phy_id = DP83865_PHY_ID,
130 .phy_id_mask = 0xfffffff0,
131 .name = "NatSemi DP83865",
132 .features = PHY_GBIT_FEATURES | SUPPORTED_Pause | SUPPORTED_Asym_Pause,
133 .flags = PHY_HAS_INTERRUPT,
134 .config_init = ns_config_init,
135 .config_aneg = genphy_config_aneg,
136 .read_status = genphy_read_status,
137 .ack_interrupt = ns_ack_interrupt,
138 .config_intr = ns_config_intr,
139 .driver = {.owner = THIS_MODULE,}
140};
141
142static int __init ns_init(void)
143{
144 return phy_driver_register(&dp83865_driver);
145}
146
147static void __exit ns_exit(void)
148{
149 phy_driver_unregister(&dp83865_driver);
150}
151
152MODULE_DESCRIPTION("NatSemi PHY driver");
153MODULE_AUTHOR("Stuart Menefy");
154MODULE_LICENSE("GPL");
155
156module_init(ns_init);
157module_exit(ns_exit);
158
159static struct mdio_device_id __maybe_unused ns_tbl[] = {
160 { DP83865_PHY_ID, 0xfffffff0 },
161 { }
162};
163
164MODULE_DEVICE_TABLE(mdio, ns_tbl);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/national.c
4 *
5 * Driver for National Semiconductor PHYs
6 *
7 * Author: Stuart Menefy <stuart.menefy@st.com>
8 * Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9 *
10 * Copyright (c) 2008 STMicroelectronics Limited
11 */
12
13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/mii.h>
18#include <linux/ethtool.h>
19#include <linux/phy.h>
20#include <linux/netdevice.h>
21
22#define DEBUG
23
24/* DP83865 phy identifier values */
25#define DP83865_PHY_ID 0x20005c7a
26
27#define DP83865_INT_STATUS 0x14
28#define DP83865_INT_MASK 0x15
29#define DP83865_INT_CLEAR 0x17
30
31#define DP83865_INT_REMOTE_FAULT 0x0008
32#define DP83865_INT_ANE_COMPLETED 0x0010
33#define DP83865_INT_LINK_CHANGE 0xe000
34#define DP83865_INT_MASK_DEFAULT (DP83865_INT_REMOTE_FAULT | \
35 DP83865_INT_ANE_COMPLETED | \
36 DP83865_INT_LINK_CHANGE)
37
38/* Advanced proprietary configuration */
39#define NS_EXP_MEM_CTL 0x16
40#define NS_EXP_MEM_DATA 0x1d
41#define NS_EXP_MEM_ADD 0x1e
42
43#define LED_CTRL_REG 0x13
44#define AN_FALLBACK_AN 0x0001
45#define AN_FALLBACK_CRC 0x0002
46#define AN_FALLBACK_IE 0x0004
47#define ALL_FALLBACK_ON (AN_FALLBACK_AN | AN_FALLBACK_CRC | AN_FALLBACK_IE)
48
49enum hdx_loopback {
50 hdx_loopback_on = 0,
51 hdx_loopback_off = 1,
52};
53
54static u8 ns_exp_read(struct phy_device *phydev, u16 reg)
55{
56 phy_write(phydev, NS_EXP_MEM_ADD, reg);
57 return phy_read(phydev, NS_EXP_MEM_DATA);
58}
59
60static void ns_exp_write(struct phy_device *phydev, u16 reg, u8 data)
61{
62 phy_write(phydev, NS_EXP_MEM_ADD, reg);
63 phy_write(phydev, NS_EXP_MEM_DATA, data);
64}
65
66static int ns_config_intr(struct phy_device *phydev)
67{
68 int err;
69
70 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
71 err = phy_write(phydev, DP83865_INT_MASK,
72 DP83865_INT_MASK_DEFAULT);
73 else
74 err = phy_write(phydev, DP83865_INT_MASK, 0);
75
76 return err;
77}
78
79static int ns_ack_interrupt(struct phy_device *phydev)
80{
81 int ret = phy_read(phydev, DP83865_INT_STATUS);
82 if (ret < 0)
83 return ret;
84
85 /* Clear the interrupt status bit by writing a “1”
86 * to the corresponding bit in INT_CLEAR (2:0 are reserved) */
87 ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7);
88
89 return ret;
90}
91
92static void ns_giga_speed_fallback(struct phy_device *phydev, int mode)
93{
94 int bmcr = phy_read(phydev, MII_BMCR);
95
96 phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN));
97
98 /* Enable 8 bit expended memory read/write (no auto increment) */
99 phy_write(phydev, NS_EXP_MEM_CTL, 0);
100 phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0);
101 phy_write(phydev, NS_EXP_MEM_DATA, 0x0008);
102 phy_write(phydev, MII_BMCR, (bmcr & ~BMCR_PDOWN));
103 phy_write(phydev, LED_CTRL_REG, mode);
104}
105
106static void ns_10_base_t_hdx_loopack(struct phy_device *phydev, int disable)
107{
108 u16 lb_dis = BIT(1);
109
110 if (disable)
111 ns_exp_write(phydev, 0x1c0,
112 ns_exp_read(phydev, 0x1c0) | lb_dis);
113 else
114 ns_exp_write(phydev, 0x1c0,
115 ns_exp_read(phydev, 0x1c0) & ~lb_dis);
116
117 pr_debug("10BASE-T HDX loopback %s\n",
118 (ns_exp_read(phydev, 0x1c0) & lb_dis) ? "off" : "on");
119}
120
121static int ns_config_init(struct phy_device *phydev)
122{
123 ns_giga_speed_fallback(phydev, ALL_FALLBACK_ON);
124 /* In the latest MAC or switches design, the 10 Mbps loopback
125 is desired to be turned off. */
126 ns_10_base_t_hdx_loopack(phydev, hdx_loopback_off);
127 return ns_ack_interrupt(phydev);
128}
129
130static struct phy_driver dp83865_driver[] = { {
131 .phy_id = DP83865_PHY_ID,
132 .phy_id_mask = 0xfffffff0,
133 .name = "NatSemi DP83865",
134 /* PHY_GBIT_FEATURES */
135 .config_init = ns_config_init,
136 .ack_interrupt = ns_ack_interrupt,
137 .config_intr = ns_config_intr,
138} };
139
140module_phy_driver(dp83865_driver);
141
142MODULE_DESCRIPTION("NatSemi PHY driver");
143MODULE_AUTHOR("Stuart Menefy");
144MODULE_LICENSE("GPL");
145
146static struct mdio_device_id __maybe_unused ns_tbl[] = {
147 { DP83865_PHY_ID, 0xfffffff0 },
148 { }
149};
150
151MODULE_DEVICE_TABLE(mdio, ns_tbl);