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1// SPDX-License-Identifier: GPL-2.0
2/* SuperH Ethernet device driver
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
6 * Copyright (C) 2008-2014 Renesas Solutions Corp.
7 * Copyright (C) 2013-2017 Cogent Embedded, Inc.
8 * Copyright (C) 2014 Codethink Limited
9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/spinlock.h>
14#include <linux/interrupt.h>
15#include <linux/dma-mapping.h>
16#include <linux/etherdevice.h>
17#include <linux/delay.h>
18#include <linux/platform_device.h>
19#include <linux/mdio-bitbang.h>
20#include <linux/netdevice.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/of_irq.h>
24#include <linux/of_net.h>
25#include <linux/phy.h>
26#include <linux/cache.h>
27#include <linux/io.h>
28#include <linux/pm_runtime.h>
29#include <linux/slab.h>
30#include <linux/ethtool.h>
31#include <linux/if_vlan.h>
32#include <linux/sh_eth.h>
33#include <linux/of_mdio.h>
34
35#include "sh_eth.h"
36
37#define SH_ETH_DEF_MSG_ENABLE \
38 (NETIF_MSG_LINK | \
39 NETIF_MSG_TIMER | \
40 NETIF_MSG_RX_ERR| \
41 NETIF_MSG_TX_ERR)
42
43#define SH_ETH_OFFSET_INVALID ((u16)~0)
44
45#define SH_ETH_OFFSET_DEFAULTS \
46 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
47
48static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
49 SH_ETH_OFFSET_DEFAULTS,
50
51 [EDSR] = 0x0000,
52 [EDMR] = 0x0400,
53 [EDTRR] = 0x0408,
54 [EDRRR] = 0x0410,
55 [EESR] = 0x0428,
56 [EESIPR] = 0x0430,
57 [TDLAR] = 0x0010,
58 [TDFAR] = 0x0014,
59 [TDFXR] = 0x0018,
60 [TDFFR] = 0x001c,
61 [RDLAR] = 0x0030,
62 [RDFAR] = 0x0034,
63 [RDFXR] = 0x0038,
64 [RDFFR] = 0x003c,
65 [TRSCER] = 0x0438,
66 [RMFCR] = 0x0440,
67 [TFTR] = 0x0448,
68 [FDR] = 0x0450,
69 [RMCR] = 0x0458,
70 [RPADIR] = 0x0460,
71 [FCFTR] = 0x0468,
72 [CSMR] = 0x04E4,
73
74 [ECMR] = 0x0500,
75 [ECSR] = 0x0510,
76 [ECSIPR] = 0x0518,
77 [PIR] = 0x0520,
78 [PSR] = 0x0528,
79 [PIPR] = 0x052c,
80 [RFLR] = 0x0508,
81 [APR] = 0x0554,
82 [MPR] = 0x0558,
83 [PFTCR] = 0x055c,
84 [PFRCR] = 0x0560,
85 [TPAUSER] = 0x0564,
86 [GECMR] = 0x05b0,
87 [BCULR] = 0x05b4,
88 [MAHR] = 0x05c0,
89 [MALR] = 0x05c8,
90 [TROCR] = 0x0700,
91 [CDCR] = 0x0708,
92 [LCCR] = 0x0710,
93 [CEFCR] = 0x0740,
94 [FRECR] = 0x0748,
95 [TSFRCR] = 0x0750,
96 [TLFRCR] = 0x0758,
97 [RFCR] = 0x0760,
98 [CERCR] = 0x0768,
99 [CEECR] = 0x0770,
100 [MAFCR] = 0x0778,
101 [RMII_MII] = 0x0790,
102
103 [ARSTR] = 0x0000,
104 [TSU_CTRST] = 0x0004,
105 [TSU_FWEN0] = 0x0010,
106 [TSU_FWEN1] = 0x0014,
107 [TSU_FCM] = 0x0018,
108 [TSU_BSYSL0] = 0x0020,
109 [TSU_BSYSL1] = 0x0024,
110 [TSU_PRISL0] = 0x0028,
111 [TSU_PRISL1] = 0x002c,
112 [TSU_FWSL0] = 0x0030,
113 [TSU_FWSL1] = 0x0034,
114 [TSU_FWSLC] = 0x0038,
115 [TSU_QTAGM0] = 0x0040,
116 [TSU_QTAGM1] = 0x0044,
117 [TSU_FWSR] = 0x0050,
118 [TSU_FWINMK] = 0x0054,
119 [TSU_ADQT0] = 0x0048,
120 [TSU_ADQT1] = 0x004c,
121 [TSU_VTAG0] = 0x0058,
122 [TSU_VTAG1] = 0x005c,
123 [TSU_ADSBSY] = 0x0060,
124 [TSU_TEN] = 0x0064,
125 [TSU_POST1] = 0x0070,
126 [TSU_POST2] = 0x0074,
127 [TSU_POST3] = 0x0078,
128 [TSU_POST4] = 0x007c,
129 [TSU_ADRH0] = 0x0100,
130
131 [TXNLCR0] = 0x0080,
132 [TXALCR0] = 0x0084,
133 [RXNLCR0] = 0x0088,
134 [RXALCR0] = 0x008c,
135 [FWNLCR0] = 0x0090,
136 [FWALCR0] = 0x0094,
137 [TXNLCR1] = 0x00a0,
138 [TXALCR1] = 0x00a4,
139 [RXNLCR1] = 0x00a8,
140 [RXALCR1] = 0x00ac,
141 [FWNLCR1] = 0x00b0,
142 [FWALCR1] = 0x00b4,
143};
144
145static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
146 SH_ETH_OFFSET_DEFAULTS,
147
148 [ECMR] = 0x0300,
149 [RFLR] = 0x0308,
150 [ECSR] = 0x0310,
151 [ECSIPR] = 0x0318,
152 [PIR] = 0x0320,
153 [PSR] = 0x0328,
154 [RDMLR] = 0x0340,
155 [IPGR] = 0x0350,
156 [APR] = 0x0354,
157 [MPR] = 0x0358,
158 [RFCF] = 0x0360,
159 [TPAUSER] = 0x0364,
160 [TPAUSECR] = 0x0368,
161 [MAHR] = 0x03c0,
162 [MALR] = 0x03c8,
163 [TROCR] = 0x03d0,
164 [CDCR] = 0x03d4,
165 [LCCR] = 0x03d8,
166 [CNDCR] = 0x03dc,
167 [CEFCR] = 0x03e4,
168 [FRECR] = 0x03e8,
169 [TSFRCR] = 0x03ec,
170 [TLFRCR] = 0x03f0,
171 [RFCR] = 0x03f4,
172 [MAFCR] = 0x03f8,
173
174 [EDMR] = 0x0200,
175 [EDTRR] = 0x0208,
176 [EDRRR] = 0x0210,
177 [TDLAR] = 0x0218,
178 [RDLAR] = 0x0220,
179 [EESR] = 0x0228,
180 [EESIPR] = 0x0230,
181 [TRSCER] = 0x0238,
182 [RMFCR] = 0x0240,
183 [TFTR] = 0x0248,
184 [FDR] = 0x0250,
185 [RMCR] = 0x0258,
186 [TFUCR] = 0x0264,
187 [RFOCR] = 0x0268,
188 [RMIIMODE] = 0x026c,
189 [FCFTR] = 0x0270,
190 [TRIMD] = 0x027c,
191};
192
193static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
194 SH_ETH_OFFSET_DEFAULTS,
195
196 [ECMR] = 0x0100,
197 [RFLR] = 0x0108,
198 [ECSR] = 0x0110,
199 [ECSIPR] = 0x0118,
200 [PIR] = 0x0120,
201 [PSR] = 0x0128,
202 [RDMLR] = 0x0140,
203 [IPGR] = 0x0150,
204 [APR] = 0x0154,
205 [MPR] = 0x0158,
206 [TPAUSER] = 0x0164,
207 [RFCF] = 0x0160,
208 [TPAUSECR] = 0x0168,
209 [BCFRR] = 0x016c,
210 [MAHR] = 0x01c0,
211 [MALR] = 0x01c8,
212 [TROCR] = 0x01d0,
213 [CDCR] = 0x01d4,
214 [LCCR] = 0x01d8,
215 [CNDCR] = 0x01dc,
216 [CEFCR] = 0x01e4,
217 [FRECR] = 0x01e8,
218 [TSFRCR] = 0x01ec,
219 [TLFRCR] = 0x01f0,
220 [RFCR] = 0x01f4,
221 [MAFCR] = 0x01f8,
222 [RTRATE] = 0x01fc,
223
224 [EDMR] = 0x0000,
225 [EDTRR] = 0x0008,
226 [EDRRR] = 0x0010,
227 [TDLAR] = 0x0018,
228 [RDLAR] = 0x0020,
229 [EESR] = 0x0028,
230 [EESIPR] = 0x0030,
231 [TRSCER] = 0x0038,
232 [RMFCR] = 0x0040,
233 [TFTR] = 0x0048,
234 [FDR] = 0x0050,
235 [RMCR] = 0x0058,
236 [TFUCR] = 0x0064,
237 [RFOCR] = 0x0068,
238 [FCFTR] = 0x0070,
239 [RPADIR] = 0x0078,
240 [TRIMD] = 0x007c,
241 [RBWAR] = 0x00c8,
242 [RDFAR] = 0x00cc,
243 [TBRAR] = 0x00d4,
244 [TDFAR] = 0x00d8,
245};
246
247static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
248 SH_ETH_OFFSET_DEFAULTS,
249
250 [EDMR] = 0x0000,
251 [EDTRR] = 0x0004,
252 [EDRRR] = 0x0008,
253 [TDLAR] = 0x000c,
254 [RDLAR] = 0x0010,
255 [EESR] = 0x0014,
256 [EESIPR] = 0x0018,
257 [TRSCER] = 0x001c,
258 [RMFCR] = 0x0020,
259 [TFTR] = 0x0024,
260 [FDR] = 0x0028,
261 [RMCR] = 0x002c,
262 [EDOCR] = 0x0030,
263 [FCFTR] = 0x0034,
264 [RPADIR] = 0x0038,
265 [TRIMD] = 0x003c,
266 [RBWAR] = 0x0040,
267 [RDFAR] = 0x0044,
268 [TBRAR] = 0x004c,
269 [TDFAR] = 0x0050,
270
271 [ECMR] = 0x0160,
272 [ECSR] = 0x0164,
273 [ECSIPR] = 0x0168,
274 [PIR] = 0x016c,
275 [MAHR] = 0x0170,
276 [MALR] = 0x0174,
277 [RFLR] = 0x0178,
278 [PSR] = 0x017c,
279 [TROCR] = 0x0180,
280 [CDCR] = 0x0184,
281 [LCCR] = 0x0188,
282 [CNDCR] = 0x018c,
283 [CEFCR] = 0x0194,
284 [FRECR] = 0x0198,
285 [TSFRCR] = 0x019c,
286 [TLFRCR] = 0x01a0,
287 [RFCR] = 0x01a4,
288 [MAFCR] = 0x01a8,
289 [IPGR] = 0x01b4,
290 [APR] = 0x01b8,
291 [MPR] = 0x01bc,
292 [TPAUSER] = 0x01c4,
293 [BCFR] = 0x01cc,
294
295 [ARSTR] = 0x0000,
296 [TSU_CTRST] = 0x0004,
297 [TSU_FWEN0] = 0x0010,
298 [TSU_FWEN1] = 0x0014,
299 [TSU_FCM] = 0x0018,
300 [TSU_BSYSL0] = 0x0020,
301 [TSU_BSYSL1] = 0x0024,
302 [TSU_PRISL0] = 0x0028,
303 [TSU_PRISL1] = 0x002c,
304 [TSU_FWSL0] = 0x0030,
305 [TSU_FWSL1] = 0x0034,
306 [TSU_FWSLC] = 0x0038,
307 [TSU_QTAGM0] = 0x0040,
308 [TSU_QTAGM1] = 0x0044,
309 [TSU_ADQT0] = 0x0048,
310 [TSU_ADQT1] = 0x004c,
311 [TSU_FWSR] = 0x0050,
312 [TSU_FWINMK] = 0x0054,
313 [TSU_ADSBSY] = 0x0060,
314 [TSU_TEN] = 0x0064,
315 [TSU_POST1] = 0x0070,
316 [TSU_POST2] = 0x0074,
317 [TSU_POST3] = 0x0078,
318 [TSU_POST4] = 0x007c,
319
320 [TXNLCR0] = 0x0080,
321 [TXALCR0] = 0x0084,
322 [RXNLCR0] = 0x0088,
323 [RXALCR0] = 0x008c,
324 [FWNLCR0] = 0x0090,
325 [FWALCR0] = 0x0094,
326 [TXNLCR1] = 0x00a0,
327 [TXALCR1] = 0x00a4,
328 [RXNLCR1] = 0x00a8,
329 [RXALCR1] = 0x00ac,
330 [FWNLCR1] = 0x00b0,
331 [FWALCR1] = 0x00b4,
332
333 [TSU_ADRH0] = 0x0100,
334};
335
336static void sh_eth_rcv_snd_disable(struct net_device *ndev);
337static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
338
339static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
340{
341 struct sh_eth_private *mdp = netdev_priv(ndev);
342 u16 offset = mdp->reg_offset[enum_index];
343
344 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
345 return;
346
347 iowrite32(data, mdp->addr + offset);
348}
349
350static u32 sh_eth_read(struct net_device *ndev, int enum_index)
351{
352 struct sh_eth_private *mdp = netdev_priv(ndev);
353 u16 offset = mdp->reg_offset[enum_index];
354
355 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
356 return ~0U;
357
358 return ioread32(mdp->addr + offset);
359}
360
361static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
362 u32 set)
363{
364 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
365 enum_index);
366}
367
368static u16 sh_eth_tsu_get_offset(struct sh_eth_private *mdp, int enum_index)
369{
370 return mdp->reg_offset[enum_index];
371}
372
373static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
374 int enum_index)
375{
376 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index);
377
378 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
379 return;
380
381 iowrite32(data, mdp->tsu_addr + offset);
382}
383
384static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
385{
386 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index);
387
388 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
389 return ~0U;
390
391 return ioread32(mdp->tsu_addr + offset);
392}
393
394static void sh_eth_soft_swap(char *src, int len)
395{
396#ifdef __LITTLE_ENDIAN
397 u32 *p = (u32 *)src;
398 u32 *maxp = p + DIV_ROUND_UP(len, sizeof(u32));
399
400 for (; p < maxp; p++)
401 *p = swab32(*p);
402#endif
403}
404
405static void sh_eth_select_mii(struct net_device *ndev)
406{
407 struct sh_eth_private *mdp = netdev_priv(ndev);
408 u32 value;
409
410 switch (mdp->phy_interface) {
411 case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID:
412 value = 0x3;
413 break;
414 case PHY_INTERFACE_MODE_GMII:
415 value = 0x2;
416 break;
417 case PHY_INTERFACE_MODE_MII:
418 value = 0x1;
419 break;
420 case PHY_INTERFACE_MODE_RMII:
421 value = 0x0;
422 break;
423 default:
424 netdev_warn(ndev,
425 "PHY interface mode was not setup. Set to MII.\n");
426 value = 0x1;
427 break;
428 }
429
430 sh_eth_write(ndev, value, RMII_MII);
431}
432
433static void sh_eth_set_duplex(struct net_device *ndev)
434{
435 struct sh_eth_private *mdp = netdev_priv(ndev);
436
437 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
438}
439
440static void sh_eth_chip_reset(struct net_device *ndev)
441{
442 struct sh_eth_private *mdp = netdev_priv(ndev);
443
444 /* reset device */
445 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
446 mdelay(1);
447}
448
449static int sh_eth_soft_reset(struct net_device *ndev)
450{
451 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
452 mdelay(3);
453 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
454
455 return 0;
456}
457
458static int sh_eth_check_soft_reset(struct net_device *ndev)
459{
460 int cnt;
461
462 for (cnt = 100; cnt > 0; cnt--) {
463 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
464 return 0;
465 mdelay(1);
466 }
467
468 netdev_err(ndev, "Device reset failed\n");
469 return -ETIMEDOUT;
470}
471
472static int sh_eth_soft_reset_gether(struct net_device *ndev)
473{
474 struct sh_eth_private *mdp = netdev_priv(ndev);
475 int ret;
476
477 sh_eth_write(ndev, EDSR_ENALL, EDSR);
478 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
479
480 ret = sh_eth_check_soft_reset(ndev);
481 if (ret)
482 return ret;
483
484 /* Table Init */
485 sh_eth_write(ndev, 0, TDLAR);
486 sh_eth_write(ndev, 0, TDFAR);
487 sh_eth_write(ndev, 0, TDFXR);
488 sh_eth_write(ndev, 0, TDFFR);
489 sh_eth_write(ndev, 0, RDLAR);
490 sh_eth_write(ndev, 0, RDFAR);
491 sh_eth_write(ndev, 0, RDFXR);
492 sh_eth_write(ndev, 0, RDFFR);
493
494 /* Reset HW CRC register */
495 if (mdp->cd->csmr)
496 sh_eth_write(ndev, 0, CSMR);
497
498 /* Select MII mode */
499 if (mdp->cd->select_mii)
500 sh_eth_select_mii(ndev);
501
502 return ret;
503}
504
505static void sh_eth_set_rate_gether(struct net_device *ndev)
506{
507 struct sh_eth_private *mdp = netdev_priv(ndev);
508
509 if (WARN_ON(!mdp->cd->gecmr))
510 return;
511
512 switch (mdp->speed) {
513 case 10: /* 10BASE */
514 sh_eth_write(ndev, GECMR_10, GECMR);
515 break;
516 case 100:/* 100BASE */
517 sh_eth_write(ndev, GECMR_100, GECMR);
518 break;
519 case 1000: /* 1000BASE */
520 sh_eth_write(ndev, GECMR_1000, GECMR);
521 break;
522 }
523}
524
525#ifdef CONFIG_OF
526/* R7S72100 */
527static struct sh_eth_cpu_data r7s72100_data = {
528 .soft_reset = sh_eth_soft_reset_gether,
529
530 .chip_reset = sh_eth_chip_reset,
531 .set_duplex = sh_eth_set_duplex,
532
533 .register_type = SH_ETH_REG_GIGABIT,
534
535 .edtrr_trns = EDTRR_TRNS_GETHER,
536 .ecsr_value = ECSR_ICD,
537 .ecsipr_value = ECSIPR_ICDIP,
538 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
539 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
540 EESIPR_ECIIP |
541 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
542 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
543 EESIPR_RMAFIP | EESIPR_RRFIP |
544 EESIPR_RTLFIP | EESIPR_RTSFIP |
545 EESIPR_PREIP | EESIPR_CERFIP,
546
547 .tx_check = EESR_TC1 | EESR_FTC,
548 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
549 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
550 EESR_TDE,
551 .fdr_value = 0x0000070f,
552
553 .no_psr = 1,
554 .apr = 1,
555 .mpr = 1,
556 .tpauser = 1,
557 .hw_swap = 1,
558 .rpadir = 1,
559 .no_trimd = 1,
560 .no_ade = 1,
561 .xdfar_rw = 1,
562 .csmr = 1,
563 .rx_csum = 1,
564 .tsu = 1,
565 .no_tx_cntrs = 1,
566};
567
568static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
569{
570 sh_eth_chip_reset(ndev);
571
572 sh_eth_select_mii(ndev);
573}
574
575/* R8A7740 */
576static struct sh_eth_cpu_data r8a7740_data = {
577 .soft_reset = sh_eth_soft_reset_gether,
578
579 .chip_reset = sh_eth_chip_reset_r8a7740,
580 .set_duplex = sh_eth_set_duplex,
581 .set_rate = sh_eth_set_rate_gether,
582
583 .register_type = SH_ETH_REG_GIGABIT,
584
585 .edtrr_trns = EDTRR_TRNS_GETHER,
586 .ecsr_value = ECSR_ICD | ECSR_MPD,
587 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
588 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
589 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
590 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
591 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
592 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
593 EESIPR_CEEFIP | EESIPR_CELFIP |
594 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
595 EESIPR_PREIP | EESIPR_CERFIP,
596
597 .tx_check = EESR_TC1 | EESR_FTC,
598 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
599 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
600 EESR_TDE,
601 .fdr_value = 0x0000070f,
602
603 .apr = 1,
604 .mpr = 1,
605 .tpauser = 1,
606 .gecmr = 1,
607 .bculr = 1,
608 .hw_swap = 1,
609 .rpadir = 1,
610 .no_trimd = 1,
611 .no_ade = 1,
612 .xdfar_rw = 1,
613 .csmr = 1,
614 .rx_csum = 1,
615 .tsu = 1,
616 .select_mii = 1,
617 .magic = 1,
618 .cexcr = 1,
619};
620
621/* There is CPU dependent code */
622static void sh_eth_set_rate_rcar(struct net_device *ndev)
623{
624 struct sh_eth_private *mdp = netdev_priv(ndev);
625
626 switch (mdp->speed) {
627 case 10: /* 10BASE */
628 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
629 break;
630 case 100:/* 100BASE */
631 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
632 break;
633 }
634}
635
636/* R-Car Gen1 */
637static struct sh_eth_cpu_data rcar_gen1_data = {
638 .soft_reset = sh_eth_soft_reset,
639
640 .set_duplex = sh_eth_set_duplex,
641 .set_rate = sh_eth_set_rate_rcar,
642
643 .register_type = SH_ETH_REG_FAST_RCAR,
644
645 .edtrr_trns = EDTRR_TRNS_ETHER,
646 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
647 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
648 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
649 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
650 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
651 EESIPR_RMAFIP | EESIPR_RRFIP |
652 EESIPR_RTLFIP | EESIPR_RTSFIP |
653 EESIPR_PREIP | EESIPR_CERFIP,
654
655 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
656 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
657 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
658 .fdr_value = 0x00000f0f,
659
660 .apr = 1,
661 .mpr = 1,
662 .tpauser = 1,
663 .hw_swap = 1,
664 .no_xdfar = 1,
665};
666
667/* R-Car Gen2 and RZ/G1 */
668static struct sh_eth_cpu_data rcar_gen2_data = {
669 .soft_reset = sh_eth_soft_reset,
670
671 .set_duplex = sh_eth_set_duplex,
672 .set_rate = sh_eth_set_rate_rcar,
673
674 .register_type = SH_ETH_REG_FAST_RCAR,
675
676 .edtrr_trns = EDTRR_TRNS_ETHER,
677 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
678 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
679 ECSIPR_MPDIP,
680 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
681 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
682 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
683 EESIPR_RMAFIP | EESIPR_RRFIP |
684 EESIPR_RTLFIP | EESIPR_RTSFIP |
685 EESIPR_PREIP | EESIPR_CERFIP,
686
687 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
688 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
689 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
690 .fdr_value = 0x00000f0f,
691
692 .trscer_err_mask = DESC_I_RINT8,
693
694 .apr = 1,
695 .mpr = 1,
696 .tpauser = 1,
697 .hw_swap = 1,
698 .no_xdfar = 1,
699 .rmiimode = 1,
700 .magic = 1,
701};
702
703/* R8A77980 */
704static struct sh_eth_cpu_data r8a77980_data = {
705 .soft_reset = sh_eth_soft_reset_gether,
706
707 .set_duplex = sh_eth_set_duplex,
708 .set_rate = sh_eth_set_rate_gether,
709
710 .register_type = SH_ETH_REG_GIGABIT,
711
712 .edtrr_trns = EDTRR_TRNS_GETHER,
713 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
714 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
715 ECSIPR_MPDIP,
716 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
717 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
718 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
719 EESIPR_RMAFIP | EESIPR_RRFIP |
720 EESIPR_RTLFIP | EESIPR_RTSFIP |
721 EESIPR_PREIP | EESIPR_CERFIP,
722
723 .tx_check = EESR_FTC | EESR_CD | EESR_TRO,
724 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
725 EESR_RFE | EESR_RDE | EESR_RFRMER |
726 EESR_TFE | EESR_TDE | EESR_ECI,
727 .fdr_value = 0x0000070f,
728
729 .apr = 1,
730 .mpr = 1,
731 .tpauser = 1,
732 .gecmr = 1,
733 .bculr = 1,
734 .hw_swap = 1,
735 .nbst = 1,
736 .rpadir = 1,
737 .no_trimd = 1,
738 .no_ade = 1,
739 .xdfar_rw = 1,
740 .csmr = 1,
741 .rx_csum = 1,
742 .select_mii = 1,
743 .magic = 1,
744 .cexcr = 1,
745};
746
747/* R7S9210 */
748static struct sh_eth_cpu_data r7s9210_data = {
749 .soft_reset = sh_eth_soft_reset,
750
751 .set_duplex = sh_eth_set_duplex,
752 .set_rate = sh_eth_set_rate_rcar,
753
754 .register_type = SH_ETH_REG_FAST_SH4,
755
756 .edtrr_trns = EDTRR_TRNS_ETHER,
757 .ecsr_value = ECSR_ICD,
758 .ecsipr_value = ECSIPR_ICDIP,
759 .eesipr_value = EESIPR_TWBIP | EESIPR_TABTIP | EESIPR_RABTIP |
760 EESIPR_RFCOFIP | EESIPR_ECIIP | EESIPR_FTCIP |
761 EESIPR_TDEIP | EESIPR_TFUFIP | EESIPR_FRIP |
762 EESIPR_RDEIP | EESIPR_RFOFIP | EESIPR_CNDIP |
763 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
764 EESIPR_RMAFIP | EESIPR_RRFIP | EESIPR_RTLFIP |
765 EESIPR_RTSFIP | EESIPR_PREIP | EESIPR_CERFIP,
766
767 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
768 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
769 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
770
771 .fdr_value = 0x0000070f,
772
773 .apr = 1,
774 .mpr = 1,
775 .tpauser = 1,
776 .hw_swap = 1,
777 .rpadir = 1,
778 .no_ade = 1,
779 .xdfar_rw = 1,
780};
781#endif /* CONFIG_OF */
782
783static void sh_eth_set_rate_sh7724(struct net_device *ndev)
784{
785 struct sh_eth_private *mdp = netdev_priv(ndev);
786
787 switch (mdp->speed) {
788 case 10: /* 10BASE */
789 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
790 break;
791 case 100:/* 100BASE */
792 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
793 break;
794 }
795}
796
797/* SH7724 */
798static struct sh_eth_cpu_data sh7724_data = {
799 .soft_reset = sh_eth_soft_reset,
800
801 .set_duplex = sh_eth_set_duplex,
802 .set_rate = sh_eth_set_rate_sh7724,
803
804 .register_type = SH_ETH_REG_FAST_SH4,
805
806 .edtrr_trns = EDTRR_TRNS_ETHER,
807 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
808 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
809 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
810 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
811 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
812 EESIPR_RMAFIP | EESIPR_RRFIP |
813 EESIPR_RTLFIP | EESIPR_RTSFIP |
814 EESIPR_PREIP | EESIPR_CERFIP,
815
816 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
817 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
818 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
819
820 .apr = 1,
821 .mpr = 1,
822 .tpauser = 1,
823 .hw_swap = 1,
824 .rpadir = 1,
825};
826
827static void sh_eth_set_rate_sh7757(struct net_device *ndev)
828{
829 struct sh_eth_private *mdp = netdev_priv(ndev);
830
831 switch (mdp->speed) {
832 case 10: /* 10BASE */
833 sh_eth_write(ndev, 0, RTRATE);
834 break;
835 case 100:/* 100BASE */
836 sh_eth_write(ndev, 1, RTRATE);
837 break;
838 }
839}
840
841/* SH7757 */
842static struct sh_eth_cpu_data sh7757_data = {
843 .soft_reset = sh_eth_soft_reset,
844
845 .set_duplex = sh_eth_set_duplex,
846 .set_rate = sh_eth_set_rate_sh7757,
847
848 .register_type = SH_ETH_REG_FAST_SH4,
849
850 .edtrr_trns = EDTRR_TRNS_ETHER,
851 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
852 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
853 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
854 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
855 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
856 EESIPR_CEEFIP | EESIPR_CELFIP |
857 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
858 EESIPR_PREIP | EESIPR_CERFIP,
859
860 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
861 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
862 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
863
864 .irq_flags = IRQF_SHARED,
865 .apr = 1,
866 .mpr = 1,
867 .tpauser = 1,
868 .hw_swap = 1,
869 .no_ade = 1,
870 .rpadir = 1,
871 .rtrate = 1,
872 .dual_port = 1,
873};
874
875#define SH_GIGA_ETH_BASE 0xfee00000UL
876#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
877#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
878static void sh_eth_chip_reset_giga(struct net_device *ndev)
879{
880 u32 mahr[2], malr[2];
881 int i;
882
883 /* save MAHR and MALR */
884 for (i = 0; i < 2; i++) {
885 malr[i] = ioread32((void *)GIGA_MALR(i));
886 mahr[i] = ioread32((void *)GIGA_MAHR(i));
887 }
888
889 sh_eth_chip_reset(ndev);
890
891 /* restore MAHR and MALR */
892 for (i = 0; i < 2; i++) {
893 iowrite32(malr[i], (void *)GIGA_MALR(i));
894 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
895 }
896}
897
898static void sh_eth_set_rate_giga(struct net_device *ndev)
899{
900 struct sh_eth_private *mdp = netdev_priv(ndev);
901
902 if (WARN_ON(!mdp->cd->gecmr))
903 return;
904
905 switch (mdp->speed) {
906 case 10: /* 10BASE */
907 sh_eth_write(ndev, 0x00000000, GECMR);
908 break;
909 case 100:/* 100BASE */
910 sh_eth_write(ndev, 0x00000010, GECMR);
911 break;
912 case 1000: /* 1000BASE */
913 sh_eth_write(ndev, 0x00000020, GECMR);
914 break;
915 }
916}
917
918/* SH7757(GETHERC) */
919static struct sh_eth_cpu_data sh7757_data_giga = {
920 .soft_reset = sh_eth_soft_reset_gether,
921
922 .chip_reset = sh_eth_chip_reset_giga,
923 .set_duplex = sh_eth_set_duplex,
924 .set_rate = sh_eth_set_rate_giga,
925
926 .register_type = SH_ETH_REG_GIGABIT,
927
928 .edtrr_trns = EDTRR_TRNS_GETHER,
929 .ecsr_value = ECSR_ICD | ECSR_MPD,
930 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
931 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
932 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
933 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
934 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
935 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
936 EESIPR_CEEFIP | EESIPR_CELFIP |
937 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
938 EESIPR_PREIP | EESIPR_CERFIP,
939
940 .tx_check = EESR_TC1 | EESR_FTC,
941 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
942 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
943 EESR_TDE,
944 .fdr_value = 0x0000072f,
945
946 .irq_flags = IRQF_SHARED,
947 .apr = 1,
948 .mpr = 1,
949 .tpauser = 1,
950 .gecmr = 1,
951 .bculr = 1,
952 .hw_swap = 1,
953 .rpadir = 1,
954 .no_trimd = 1,
955 .no_ade = 1,
956 .xdfar_rw = 1,
957 .tsu = 1,
958 .cexcr = 1,
959 .dual_port = 1,
960};
961
962/* SH7734 */
963static struct sh_eth_cpu_data sh7734_data = {
964 .soft_reset = sh_eth_soft_reset_gether,
965
966 .chip_reset = sh_eth_chip_reset,
967 .set_duplex = sh_eth_set_duplex,
968 .set_rate = sh_eth_set_rate_gether,
969
970 .register_type = SH_ETH_REG_GIGABIT,
971
972 .edtrr_trns = EDTRR_TRNS_GETHER,
973 .ecsr_value = ECSR_ICD | ECSR_MPD,
974 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
975 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
976 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
977 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
978 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
979 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
980 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
981 EESIPR_PREIP | EESIPR_CERFIP,
982
983 .tx_check = EESR_TC1 | EESR_FTC,
984 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
985 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
986 EESR_TDE,
987
988 .apr = 1,
989 .mpr = 1,
990 .tpauser = 1,
991 .gecmr = 1,
992 .bculr = 1,
993 .hw_swap = 1,
994 .no_trimd = 1,
995 .no_ade = 1,
996 .xdfar_rw = 1,
997 .tsu = 1,
998 .csmr = 1,
999 .rx_csum = 1,
1000 .select_mii = 1,
1001 .magic = 1,
1002 .cexcr = 1,
1003};
1004
1005/* SH7763 */
1006static struct sh_eth_cpu_data sh7763_data = {
1007 .soft_reset = sh_eth_soft_reset_gether,
1008
1009 .chip_reset = sh_eth_chip_reset,
1010 .set_duplex = sh_eth_set_duplex,
1011 .set_rate = sh_eth_set_rate_gether,
1012
1013 .register_type = SH_ETH_REG_GIGABIT,
1014
1015 .edtrr_trns = EDTRR_TRNS_GETHER,
1016 .ecsr_value = ECSR_ICD | ECSR_MPD,
1017 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
1018 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1019 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1020 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1021 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1022 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1023 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1024 EESIPR_PREIP | EESIPR_CERFIP,
1025
1026 .tx_check = EESR_TC1 | EESR_FTC,
1027 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1028 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
1029
1030 .apr = 1,
1031 .mpr = 1,
1032 .tpauser = 1,
1033 .gecmr = 1,
1034 .bculr = 1,
1035 .hw_swap = 1,
1036 .no_trimd = 1,
1037 .no_ade = 1,
1038 .xdfar_rw = 1,
1039 .tsu = 1,
1040 .irq_flags = IRQF_SHARED,
1041 .magic = 1,
1042 .cexcr = 1,
1043 .rx_csum = 1,
1044 .dual_port = 1,
1045};
1046
1047static struct sh_eth_cpu_data sh7619_data = {
1048 .soft_reset = sh_eth_soft_reset,
1049
1050 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1051
1052 .edtrr_trns = EDTRR_TRNS_ETHER,
1053 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1054 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1055 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1056 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1057 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1058 EESIPR_CEEFIP | EESIPR_CELFIP |
1059 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1060 EESIPR_PREIP | EESIPR_CERFIP,
1061
1062 .apr = 1,
1063 .mpr = 1,
1064 .tpauser = 1,
1065 .hw_swap = 1,
1066};
1067
1068static struct sh_eth_cpu_data sh771x_data = {
1069 .soft_reset = sh_eth_soft_reset,
1070
1071 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1072
1073 .edtrr_trns = EDTRR_TRNS_ETHER,
1074 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1075 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1076 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1077 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1078 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1079 EESIPR_CEEFIP | EESIPR_CELFIP |
1080 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1081 EESIPR_PREIP | EESIPR_CERFIP,
1082 .tsu = 1,
1083 .dual_port = 1,
1084};
1085
1086static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
1087{
1088 if (!cd->ecsr_value)
1089 cd->ecsr_value = DEFAULT_ECSR_INIT;
1090
1091 if (!cd->ecsipr_value)
1092 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
1093
1094 if (!cd->fcftr_value)
1095 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
1096 DEFAULT_FIFO_F_D_RFD;
1097
1098 if (!cd->fdr_value)
1099 cd->fdr_value = DEFAULT_FDR_INIT;
1100
1101 if (!cd->tx_check)
1102 cd->tx_check = DEFAULT_TX_CHECK;
1103
1104 if (!cd->eesr_err_check)
1105 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
1106
1107 if (!cd->trscer_err_mask)
1108 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
1109}
1110
1111static void sh_eth_set_receive_align(struct sk_buff *skb)
1112{
1113 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
1114
1115 if (reserve)
1116 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
1117}
1118
1119/* Program the hardware MAC address from dev->dev_addr. */
1120static void update_mac_address(struct net_device *ndev)
1121{
1122 sh_eth_write(ndev,
1123 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1124 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
1125 sh_eth_write(ndev,
1126 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1127}
1128
1129/* Get MAC address from SuperH MAC address register
1130 *
1131 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1132 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1133 * When you want use this device, you must set MAC address in bootloader.
1134 *
1135 */
1136static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1137{
1138 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1139 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1140 } else {
1141 u32 mahr = sh_eth_read(ndev, MAHR);
1142 u32 malr = sh_eth_read(ndev, MALR);
1143
1144 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1145 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1146 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
1147 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
1148 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
1149 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
1150 }
1151}
1152
1153struct bb_info {
1154 void (*set_gate)(void *addr);
1155 struct mdiobb_ctrl ctrl;
1156 void *addr;
1157};
1158
1159static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1160{
1161 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1162 u32 pir;
1163
1164 if (bitbang->set_gate)
1165 bitbang->set_gate(bitbang->addr);
1166
1167 pir = ioread32(bitbang->addr);
1168 if (set)
1169 pir |= mask;
1170 else
1171 pir &= ~mask;
1172 iowrite32(pir, bitbang->addr);
1173}
1174
1175/* Data I/O pin control */
1176static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1177{
1178 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1179}
1180
1181/* Set bit data*/
1182static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1183{
1184 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1185}
1186
1187/* Get bit data*/
1188static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1189{
1190 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1191
1192 if (bitbang->set_gate)
1193 bitbang->set_gate(bitbang->addr);
1194
1195 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1196}
1197
1198/* MDC pin control */
1199static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1200{
1201 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1202}
1203
1204/* mdio bus control struct */
1205static struct mdiobb_ops bb_ops = {
1206 .owner = THIS_MODULE,
1207 .set_mdc = sh_mdc_ctrl,
1208 .set_mdio_dir = sh_mmd_ctrl,
1209 .set_mdio_data = sh_set_mdio,
1210 .get_mdio_data = sh_get_mdio,
1211};
1212
1213/* free Tx skb function */
1214static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1215{
1216 struct sh_eth_private *mdp = netdev_priv(ndev);
1217 struct sh_eth_txdesc *txdesc;
1218 int free_num = 0;
1219 int entry;
1220 bool sent;
1221
1222 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1223 entry = mdp->dirty_tx % mdp->num_tx_ring;
1224 txdesc = &mdp->tx_ring[entry];
1225 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1226 if (sent_only && !sent)
1227 break;
1228 /* TACT bit must be checked before all the following reads */
1229 dma_rmb();
1230 netif_info(mdp, tx_done, ndev,
1231 "tx entry %d status 0x%08x\n",
1232 entry, le32_to_cpu(txdesc->status));
1233 /* Free the original skb. */
1234 if (mdp->tx_skbuff[entry]) {
1235 dma_unmap_single(&mdp->pdev->dev,
1236 le32_to_cpu(txdesc->addr),
1237 le32_to_cpu(txdesc->len) >> 16,
1238 DMA_TO_DEVICE);
1239 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1240 mdp->tx_skbuff[entry] = NULL;
1241 free_num++;
1242 }
1243 txdesc->status = cpu_to_le32(TD_TFP);
1244 if (entry >= mdp->num_tx_ring - 1)
1245 txdesc->status |= cpu_to_le32(TD_TDLE);
1246
1247 if (sent) {
1248 ndev->stats.tx_packets++;
1249 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1250 }
1251 }
1252 return free_num;
1253}
1254
1255/* free skb and descriptor buffer */
1256static void sh_eth_ring_free(struct net_device *ndev)
1257{
1258 struct sh_eth_private *mdp = netdev_priv(ndev);
1259 int ringsize, i;
1260
1261 if (mdp->rx_ring) {
1262 for (i = 0; i < mdp->num_rx_ring; i++) {
1263 if (mdp->rx_skbuff[i]) {
1264 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1265
1266 dma_unmap_single(&mdp->pdev->dev,
1267 le32_to_cpu(rxdesc->addr),
1268 ALIGN(mdp->rx_buf_sz, 32),
1269 DMA_FROM_DEVICE);
1270 }
1271 }
1272 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1273 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring,
1274 mdp->rx_desc_dma);
1275 mdp->rx_ring = NULL;
1276 }
1277
1278 /* Free Rx skb ringbuffer */
1279 if (mdp->rx_skbuff) {
1280 for (i = 0; i < mdp->num_rx_ring; i++)
1281 dev_kfree_skb(mdp->rx_skbuff[i]);
1282 }
1283 kfree(mdp->rx_skbuff);
1284 mdp->rx_skbuff = NULL;
1285
1286 if (mdp->tx_ring) {
1287 sh_eth_tx_free(ndev, false);
1288
1289 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1290 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring,
1291 mdp->tx_desc_dma);
1292 mdp->tx_ring = NULL;
1293 }
1294
1295 /* Free Tx skb ringbuffer */
1296 kfree(mdp->tx_skbuff);
1297 mdp->tx_skbuff = NULL;
1298}
1299
1300/* format skb and descriptor buffer */
1301static void sh_eth_ring_format(struct net_device *ndev)
1302{
1303 struct sh_eth_private *mdp = netdev_priv(ndev);
1304 int i;
1305 struct sk_buff *skb;
1306 struct sh_eth_rxdesc *rxdesc = NULL;
1307 struct sh_eth_txdesc *txdesc = NULL;
1308 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1309 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1310 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1311 dma_addr_t dma_addr;
1312 u32 buf_len;
1313
1314 mdp->cur_rx = 0;
1315 mdp->cur_tx = 0;
1316 mdp->dirty_rx = 0;
1317 mdp->dirty_tx = 0;
1318
1319 memset(mdp->rx_ring, 0, rx_ringsize);
1320
1321 /* build Rx ring buffer */
1322 for (i = 0; i < mdp->num_rx_ring; i++) {
1323 /* skb */
1324 mdp->rx_skbuff[i] = NULL;
1325 skb = netdev_alloc_skb(ndev, skbuff_size);
1326 if (skb == NULL)
1327 break;
1328 sh_eth_set_receive_align(skb);
1329
1330 /* The size of the buffer is a multiple of 32 bytes. */
1331 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1332 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len,
1333 DMA_FROM_DEVICE);
1334 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1335 kfree_skb(skb);
1336 break;
1337 }
1338 mdp->rx_skbuff[i] = skb;
1339
1340 /* RX descriptor */
1341 rxdesc = &mdp->rx_ring[i];
1342 rxdesc->len = cpu_to_le32(buf_len << 16);
1343 rxdesc->addr = cpu_to_le32(dma_addr);
1344 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1345
1346 /* Rx descriptor address set */
1347 if (i == 0) {
1348 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1349 if (mdp->cd->xdfar_rw)
1350 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1351 }
1352 }
1353
1354 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1355
1356 /* Mark the last entry as wrapping the ring. */
1357 if (rxdesc)
1358 rxdesc->status |= cpu_to_le32(RD_RDLE);
1359
1360 memset(mdp->tx_ring, 0, tx_ringsize);
1361
1362 /* build Tx ring buffer */
1363 for (i = 0; i < mdp->num_tx_ring; i++) {
1364 mdp->tx_skbuff[i] = NULL;
1365 txdesc = &mdp->tx_ring[i];
1366 txdesc->status = cpu_to_le32(TD_TFP);
1367 txdesc->len = cpu_to_le32(0);
1368 if (i == 0) {
1369 /* Tx descriptor address set */
1370 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1371 if (mdp->cd->xdfar_rw)
1372 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1373 }
1374 }
1375
1376 txdesc->status |= cpu_to_le32(TD_TDLE);
1377}
1378
1379/* Get skb and descriptor buffer */
1380static int sh_eth_ring_init(struct net_device *ndev)
1381{
1382 struct sh_eth_private *mdp = netdev_priv(ndev);
1383 int rx_ringsize, tx_ringsize;
1384
1385 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1386 * card needs room to do 8 byte alignment, +2 so we can reserve
1387 * the first 2 bytes, and +16 gets room for the status word from the
1388 * card.
1389 */
1390 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1391 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1392 if (mdp->cd->rpadir)
1393 mdp->rx_buf_sz += NET_IP_ALIGN;
1394
1395 /* Allocate RX and TX skb rings */
1396 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1397 GFP_KERNEL);
1398 if (!mdp->rx_skbuff)
1399 return -ENOMEM;
1400
1401 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1402 GFP_KERNEL);
1403 if (!mdp->tx_skbuff)
1404 goto ring_free;
1405
1406 /* Allocate all Rx descriptors. */
1407 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1408 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize,
1409 &mdp->rx_desc_dma, GFP_KERNEL);
1410 if (!mdp->rx_ring)
1411 goto ring_free;
1412
1413 mdp->dirty_rx = 0;
1414
1415 /* Allocate all Tx descriptors. */
1416 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1417 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize,
1418 &mdp->tx_desc_dma, GFP_KERNEL);
1419 if (!mdp->tx_ring)
1420 goto ring_free;
1421 return 0;
1422
1423ring_free:
1424 /* Free Rx and Tx skb ring buffer and DMA buffer */
1425 sh_eth_ring_free(ndev);
1426
1427 return -ENOMEM;
1428}
1429
1430static int sh_eth_dev_init(struct net_device *ndev)
1431{
1432 struct sh_eth_private *mdp = netdev_priv(ndev);
1433 int ret;
1434
1435 /* Soft Reset */
1436 ret = mdp->cd->soft_reset(ndev);
1437 if (ret)
1438 return ret;
1439
1440 if (mdp->cd->rmiimode)
1441 sh_eth_write(ndev, 0x1, RMIIMODE);
1442
1443 /* Descriptor format */
1444 sh_eth_ring_format(ndev);
1445 if (mdp->cd->rpadir)
1446 sh_eth_write(ndev, NET_IP_ALIGN << 16, RPADIR);
1447
1448 /* all sh_eth int mask */
1449 sh_eth_write(ndev, 0, EESIPR);
1450
1451#if defined(__LITTLE_ENDIAN)
1452 if (mdp->cd->hw_swap)
1453 sh_eth_write(ndev, EDMR_EL, EDMR);
1454 else
1455#endif
1456 sh_eth_write(ndev, 0, EDMR);
1457
1458 /* FIFO size set */
1459 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1460 sh_eth_write(ndev, 0, TFTR);
1461
1462 /* Frame recv control (enable multiple-packets per rx irq) */
1463 sh_eth_write(ndev, RMCR_RNC, RMCR);
1464
1465 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1466
1467 /* DMA transfer burst mode */
1468 if (mdp->cd->nbst)
1469 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST);
1470
1471 /* Burst cycle count upper-limit */
1472 if (mdp->cd->bculr)
1473 sh_eth_write(ndev, 0x800, BCULR);
1474
1475 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1476
1477 if (!mdp->cd->no_trimd)
1478 sh_eth_write(ndev, 0, TRIMD);
1479
1480 /* Recv frame limit set register */
1481 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1482 RFLR);
1483
1484 sh_eth_modify(ndev, EESR, 0, 0);
1485 mdp->irq_enabled = true;
1486 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1487
1488 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
1489 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1490 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
1491 ECMR_TE | ECMR_RE, ECMR);
1492
1493 if (mdp->cd->set_rate)
1494 mdp->cd->set_rate(ndev);
1495
1496 /* E-MAC Status Register clear */
1497 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1498
1499 /* E-MAC Interrupt Enable register */
1500 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1501
1502 /* Set MAC address */
1503 update_mac_address(ndev);
1504
1505 /* mask reset */
1506 if (mdp->cd->apr)
1507 sh_eth_write(ndev, 1, APR);
1508 if (mdp->cd->mpr)
1509 sh_eth_write(ndev, 1, MPR);
1510 if (mdp->cd->tpauser)
1511 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1512
1513 /* Setting the Rx mode will start the Rx process. */
1514 sh_eth_write(ndev, EDRRR_R, EDRRR);
1515
1516 return ret;
1517}
1518
1519static void sh_eth_dev_exit(struct net_device *ndev)
1520{
1521 struct sh_eth_private *mdp = netdev_priv(ndev);
1522 int i;
1523
1524 /* Deactivate all TX descriptors, so DMA should stop at next
1525 * packet boundary if it's currently running
1526 */
1527 for (i = 0; i < mdp->num_tx_ring; i++)
1528 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1529
1530 /* Disable TX FIFO egress to MAC */
1531 sh_eth_rcv_snd_disable(ndev);
1532
1533 /* Stop RX DMA at next packet boundary */
1534 sh_eth_write(ndev, 0, EDRRR);
1535
1536 /* Aside from TX DMA, we can't tell when the hardware is
1537 * really stopped, so we need to reset to make sure.
1538 * Before doing that, wait for long enough to *probably*
1539 * finish transmitting the last packet and poll stats.
1540 */
1541 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1542 sh_eth_get_stats(ndev);
1543 mdp->cd->soft_reset(ndev);
1544
1545 /* Set the RMII mode again if required */
1546 if (mdp->cd->rmiimode)
1547 sh_eth_write(ndev, 0x1, RMIIMODE);
1548
1549 /* Set MAC address again */
1550 update_mac_address(ndev);
1551}
1552
1553static void sh_eth_rx_csum(struct sk_buff *skb)
1554{
1555 u8 *hw_csum;
1556
1557 /* The hardware checksum is 2 bytes appended to packet data */
1558 if (unlikely(skb->len < sizeof(__sum16)))
1559 return;
1560 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
1561 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
1562 skb->ip_summed = CHECKSUM_COMPLETE;
1563 skb_trim(skb, skb->len - sizeof(__sum16));
1564}
1565
1566/* Packet receive function */
1567static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1568{
1569 struct sh_eth_private *mdp = netdev_priv(ndev);
1570 struct sh_eth_rxdesc *rxdesc;
1571
1572 int entry = mdp->cur_rx % mdp->num_rx_ring;
1573 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1574 int limit;
1575 struct sk_buff *skb;
1576 u32 desc_status;
1577 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1578 dma_addr_t dma_addr;
1579 u16 pkt_len;
1580 u32 buf_len;
1581
1582 boguscnt = min(boguscnt, *quota);
1583 limit = boguscnt;
1584 rxdesc = &mdp->rx_ring[entry];
1585 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1586 /* RACT bit must be checked before all the following reads */
1587 dma_rmb();
1588 desc_status = le32_to_cpu(rxdesc->status);
1589 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1590
1591 if (--boguscnt < 0)
1592 break;
1593
1594 netif_info(mdp, rx_status, ndev,
1595 "rx entry %d status 0x%08x len %d\n",
1596 entry, desc_status, pkt_len);
1597
1598 if (!(desc_status & RDFEND))
1599 ndev->stats.rx_length_errors++;
1600
1601 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1602 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1603 * bit 0. However, in case of the R8A7740 and R7S72100
1604 * the RFS bits are from bit 25 to bit 16. So, the
1605 * driver needs right shifting by 16.
1606 */
1607 if (mdp->cd->csmr)
1608 desc_status >>= 16;
1609
1610 skb = mdp->rx_skbuff[entry];
1611 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1612 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1613 ndev->stats.rx_errors++;
1614 if (desc_status & RD_RFS1)
1615 ndev->stats.rx_crc_errors++;
1616 if (desc_status & RD_RFS2)
1617 ndev->stats.rx_frame_errors++;
1618 if (desc_status & RD_RFS3)
1619 ndev->stats.rx_length_errors++;
1620 if (desc_status & RD_RFS4)
1621 ndev->stats.rx_length_errors++;
1622 if (desc_status & RD_RFS6)
1623 ndev->stats.rx_missed_errors++;
1624 if (desc_status & RD_RFS10)
1625 ndev->stats.rx_over_errors++;
1626 } else if (skb) {
1627 dma_addr = le32_to_cpu(rxdesc->addr);
1628 if (!mdp->cd->hw_swap)
1629 sh_eth_soft_swap(
1630 phys_to_virt(ALIGN(dma_addr, 4)),
1631 pkt_len + 2);
1632 mdp->rx_skbuff[entry] = NULL;
1633 if (mdp->cd->rpadir)
1634 skb_reserve(skb, NET_IP_ALIGN);
1635 dma_unmap_single(&mdp->pdev->dev, dma_addr,
1636 ALIGN(mdp->rx_buf_sz, 32),
1637 DMA_FROM_DEVICE);
1638 skb_put(skb, pkt_len);
1639 skb->protocol = eth_type_trans(skb, ndev);
1640 if (ndev->features & NETIF_F_RXCSUM)
1641 sh_eth_rx_csum(skb);
1642 netif_receive_skb(skb);
1643 ndev->stats.rx_packets++;
1644 ndev->stats.rx_bytes += pkt_len;
1645 if (desc_status & RD_RFS8)
1646 ndev->stats.multicast++;
1647 }
1648 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1649 rxdesc = &mdp->rx_ring[entry];
1650 }
1651
1652 /* Refill the Rx ring buffers. */
1653 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1654 entry = mdp->dirty_rx % mdp->num_rx_ring;
1655 rxdesc = &mdp->rx_ring[entry];
1656 /* The size of the buffer is 32 byte boundary. */
1657 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1658 rxdesc->len = cpu_to_le32(buf_len << 16);
1659
1660 if (mdp->rx_skbuff[entry] == NULL) {
1661 skb = netdev_alloc_skb(ndev, skbuff_size);
1662 if (skb == NULL)
1663 break; /* Better luck next round. */
1664 sh_eth_set_receive_align(skb);
1665 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data,
1666 buf_len, DMA_FROM_DEVICE);
1667 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1668 kfree_skb(skb);
1669 break;
1670 }
1671 mdp->rx_skbuff[entry] = skb;
1672
1673 skb_checksum_none_assert(skb);
1674 rxdesc->addr = cpu_to_le32(dma_addr);
1675 }
1676 dma_wmb(); /* RACT bit must be set after all the above writes */
1677 if (entry >= mdp->num_rx_ring - 1)
1678 rxdesc->status |=
1679 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1680 else
1681 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1682 }
1683
1684 /* Restart Rx engine if stopped. */
1685 /* If we don't need to check status, don't. -KDU */
1686 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1687 /* fix the values for the next receiving if RDE is set */
1688 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) {
1689 u32 count = (sh_eth_read(ndev, RDFAR) -
1690 sh_eth_read(ndev, RDLAR)) >> 4;
1691
1692 mdp->cur_rx = count;
1693 mdp->dirty_rx = count;
1694 }
1695 sh_eth_write(ndev, EDRRR_R, EDRRR);
1696 }
1697
1698 *quota -= limit - boguscnt - 1;
1699
1700 return *quota <= 0;
1701}
1702
1703static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1704{
1705 /* disable tx and rx */
1706 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1707}
1708
1709static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1710{
1711 /* enable tx and rx */
1712 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1713}
1714
1715/* E-MAC interrupt handler */
1716static void sh_eth_emac_interrupt(struct net_device *ndev)
1717{
1718 struct sh_eth_private *mdp = netdev_priv(ndev);
1719 u32 felic_stat;
1720 u32 link_stat;
1721
1722 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1723 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1724 if (felic_stat & ECSR_ICD)
1725 ndev->stats.tx_carrier_errors++;
1726 if (felic_stat & ECSR_MPD)
1727 pm_wakeup_event(&mdp->pdev->dev, 0);
1728 if (felic_stat & ECSR_LCHNG) {
1729 /* Link Changed */
1730 if (mdp->cd->no_psr || mdp->no_ether_link)
1731 return;
1732 link_stat = sh_eth_read(ndev, PSR);
1733 if (mdp->ether_link_active_low)
1734 link_stat = ~link_stat;
1735 if (!(link_stat & PHY_ST_LINK)) {
1736 sh_eth_rcv_snd_disable(ndev);
1737 } else {
1738 /* Link Up */
1739 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
1740 /* clear int */
1741 sh_eth_modify(ndev, ECSR, 0, 0);
1742 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
1743 /* enable tx and rx */
1744 sh_eth_rcv_snd_enable(ndev);
1745 }
1746 }
1747}
1748
1749/* error control function */
1750static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1751{
1752 struct sh_eth_private *mdp = netdev_priv(ndev);
1753 u32 mask;
1754
1755 if (intr_status & EESR_TWB) {
1756 /* Unused write back interrupt */
1757 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1758 ndev->stats.tx_aborted_errors++;
1759 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1760 }
1761 }
1762
1763 if (intr_status & EESR_RABT) {
1764 /* Receive Abort int */
1765 if (intr_status & EESR_RFRMER) {
1766 /* Receive Frame Overflow int */
1767 ndev->stats.rx_frame_errors++;
1768 }
1769 }
1770
1771 if (intr_status & EESR_TDE) {
1772 /* Transmit Descriptor Empty int */
1773 ndev->stats.tx_fifo_errors++;
1774 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1775 }
1776
1777 if (intr_status & EESR_TFE) {
1778 /* FIFO under flow */
1779 ndev->stats.tx_fifo_errors++;
1780 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1781 }
1782
1783 if (intr_status & EESR_RDE) {
1784 /* Receive Descriptor Empty int */
1785 ndev->stats.rx_over_errors++;
1786 }
1787
1788 if (intr_status & EESR_RFE) {
1789 /* Receive FIFO Overflow int */
1790 ndev->stats.rx_fifo_errors++;
1791 }
1792
1793 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1794 /* Address Error */
1795 ndev->stats.tx_fifo_errors++;
1796 netif_err(mdp, tx_err, ndev, "Address Error\n");
1797 }
1798
1799 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1800 if (mdp->cd->no_ade)
1801 mask &= ~EESR_ADE;
1802 if (intr_status & mask) {
1803 /* Tx error */
1804 u32 edtrr = sh_eth_read(ndev, EDTRR);
1805
1806 /* dmesg */
1807 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1808 intr_status, mdp->cur_tx, mdp->dirty_tx,
1809 (u32)ndev->state, edtrr);
1810 /* dirty buffer free */
1811 sh_eth_tx_free(ndev, true);
1812
1813 /* SH7712 BUG */
1814 if (edtrr ^ mdp->cd->edtrr_trns) {
1815 /* tx dma start */
1816 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
1817 }
1818 /* wakeup */
1819 netif_wake_queue(ndev);
1820 }
1821}
1822
1823static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1824{
1825 struct net_device *ndev = netdev;
1826 struct sh_eth_private *mdp = netdev_priv(ndev);
1827 struct sh_eth_cpu_data *cd = mdp->cd;
1828 irqreturn_t ret = IRQ_NONE;
1829 u32 intr_status, intr_enable;
1830
1831 spin_lock(&mdp->lock);
1832
1833 /* Get interrupt status */
1834 intr_status = sh_eth_read(ndev, EESR);
1835 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1836 * enabled since it's the one that comes thru regardless of the mask,
1837 * and we need to fully handle it in sh_eth_emac_interrupt() in order
1838 * to quench it as it doesn't get cleared by just writing 1 to the ECI
1839 * bit...
1840 */
1841 intr_enable = sh_eth_read(ndev, EESIPR);
1842 intr_status &= intr_enable | EESIPR_ECIIP;
1843 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1844 cd->eesr_err_check))
1845 ret = IRQ_HANDLED;
1846 else
1847 goto out;
1848
1849 if (unlikely(!mdp->irq_enabled)) {
1850 sh_eth_write(ndev, 0, EESIPR);
1851 goto out;
1852 }
1853
1854 if (intr_status & EESR_RX_CHECK) {
1855 if (napi_schedule_prep(&mdp->napi)) {
1856 /* Mask Rx interrupts */
1857 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1858 EESIPR);
1859 __napi_schedule(&mdp->napi);
1860 } else {
1861 netdev_warn(ndev,
1862 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1863 intr_status, intr_enable);
1864 }
1865 }
1866
1867 /* Tx Check */
1868 if (intr_status & cd->tx_check) {
1869 /* Clear Tx interrupts */
1870 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1871
1872 sh_eth_tx_free(ndev, true);
1873 netif_wake_queue(ndev);
1874 }
1875
1876 /* E-MAC interrupt */
1877 if (intr_status & EESR_ECI)
1878 sh_eth_emac_interrupt(ndev);
1879
1880 if (intr_status & cd->eesr_err_check) {
1881 /* Clear error interrupts */
1882 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1883
1884 sh_eth_error(ndev, intr_status);
1885 }
1886
1887out:
1888 spin_unlock(&mdp->lock);
1889
1890 return ret;
1891}
1892
1893static int sh_eth_poll(struct napi_struct *napi, int budget)
1894{
1895 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1896 napi);
1897 struct net_device *ndev = napi->dev;
1898 int quota = budget;
1899 u32 intr_status;
1900
1901 for (;;) {
1902 intr_status = sh_eth_read(ndev, EESR);
1903 if (!(intr_status & EESR_RX_CHECK))
1904 break;
1905 /* Clear Rx interrupts */
1906 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1907
1908 if (sh_eth_rx(ndev, intr_status, "a))
1909 goto out;
1910 }
1911
1912 napi_complete(napi);
1913
1914 /* Reenable Rx interrupts */
1915 if (mdp->irq_enabled)
1916 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1917out:
1918 return budget - quota;
1919}
1920
1921/* PHY state control function */
1922static void sh_eth_adjust_link(struct net_device *ndev)
1923{
1924 struct sh_eth_private *mdp = netdev_priv(ndev);
1925 struct phy_device *phydev = ndev->phydev;
1926 unsigned long flags;
1927 int new_state = 0;
1928
1929 spin_lock_irqsave(&mdp->lock, flags);
1930
1931 /* Disable TX and RX right over here, if E-MAC change is ignored */
1932 if (mdp->cd->no_psr || mdp->no_ether_link)
1933 sh_eth_rcv_snd_disable(ndev);
1934
1935 if (phydev->link) {
1936 if (phydev->duplex != mdp->duplex) {
1937 new_state = 1;
1938 mdp->duplex = phydev->duplex;
1939 if (mdp->cd->set_duplex)
1940 mdp->cd->set_duplex(ndev);
1941 }
1942
1943 if (phydev->speed != mdp->speed) {
1944 new_state = 1;
1945 mdp->speed = phydev->speed;
1946 if (mdp->cd->set_rate)
1947 mdp->cd->set_rate(ndev);
1948 }
1949 if (!mdp->link) {
1950 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1951 new_state = 1;
1952 mdp->link = phydev->link;
1953 }
1954 } else if (mdp->link) {
1955 new_state = 1;
1956 mdp->link = 0;
1957 mdp->speed = 0;
1958 mdp->duplex = -1;
1959 }
1960
1961 /* Enable TX and RX right over here, if E-MAC change is ignored */
1962 if ((mdp->cd->no_psr || mdp->no_ether_link) && phydev->link)
1963 sh_eth_rcv_snd_enable(ndev);
1964
1965 spin_unlock_irqrestore(&mdp->lock, flags);
1966
1967 if (new_state && netif_msg_link(mdp))
1968 phy_print_status(phydev);
1969}
1970
1971/* PHY init function */
1972static int sh_eth_phy_init(struct net_device *ndev)
1973{
1974 struct device_node *np = ndev->dev.parent->of_node;
1975 struct sh_eth_private *mdp = netdev_priv(ndev);
1976 struct phy_device *phydev;
1977
1978 mdp->link = 0;
1979 mdp->speed = 0;
1980 mdp->duplex = -1;
1981
1982 /* Try connect to PHY */
1983 if (np) {
1984 struct device_node *pn;
1985
1986 pn = of_parse_phandle(np, "phy-handle", 0);
1987 phydev = of_phy_connect(ndev, pn,
1988 sh_eth_adjust_link, 0,
1989 mdp->phy_interface);
1990
1991 of_node_put(pn);
1992 if (!phydev)
1993 phydev = ERR_PTR(-ENOENT);
1994 } else {
1995 char phy_id[MII_BUS_ID_SIZE + 3];
1996
1997 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1998 mdp->mii_bus->id, mdp->phy_id);
1999
2000 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
2001 mdp->phy_interface);
2002 }
2003
2004 if (IS_ERR(phydev)) {
2005 netdev_err(ndev, "failed to connect PHY\n");
2006 return PTR_ERR(phydev);
2007 }
2008
2009 /* mask with MAC supported features */
2010 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) {
2011 int err = phy_set_max_speed(phydev, SPEED_100);
2012 if (err) {
2013 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n");
2014 phy_disconnect(phydev);
2015 return err;
2016 }
2017 }
2018
2019 phy_attached_info(phydev);
2020
2021 return 0;
2022}
2023
2024/* PHY control start function */
2025static int sh_eth_phy_start(struct net_device *ndev)
2026{
2027 int ret;
2028
2029 ret = sh_eth_phy_init(ndev);
2030 if (ret)
2031 return ret;
2032
2033 phy_start(ndev->phydev);
2034
2035 return 0;
2036}
2037
2038/* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
2039 * version must be bumped as well. Just adding registers up to that
2040 * limit is fine, as long as the existing register indices don't
2041 * change.
2042 */
2043#define SH_ETH_REG_DUMP_VERSION 1
2044#define SH_ETH_REG_DUMP_MAX_REGS 256
2045
2046static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
2047{
2048 struct sh_eth_private *mdp = netdev_priv(ndev);
2049 struct sh_eth_cpu_data *cd = mdp->cd;
2050 u32 *valid_map;
2051 size_t len;
2052
2053 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
2054
2055 /* Dump starts with a bitmap that tells ethtool which
2056 * registers are defined for this chip.
2057 */
2058 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
2059 if (buf) {
2060 valid_map = buf;
2061 buf += len;
2062 } else {
2063 valid_map = NULL;
2064 }
2065
2066 /* Add a register to the dump, if it has a defined offset.
2067 * This automatically skips most undefined registers, but for
2068 * some it is also necessary to check a capability flag in
2069 * struct sh_eth_cpu_data.
2070 */
2071#define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
2072#define add_reg_from(reg, read_expr) do { \
2073 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
2074 if (buf) { \
2075 mark_reg_valid(reg); \
2076 *buf++ = read_expr; \
2077 } \
2078 ++len; \
2079 } \
2080 } while (0)
2081#define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2082#define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2083
2084 add_reg(EDSR);
2085 add_reg(EDMR);
2086 add_reg(EDTRR);
2087 add_reg(EDRRR);
2088 add_reg(EESR);
2089 add_reg(EESIPR);
2090 add_reg(TDLAR);
2091 if (!cd->no_xdfar)
2092 add_reg(TDFAR);
2093 add_reg(TDFXR);
2094 add_reg(TDFFR);
2095 add_reg(RDLAR);
2096 if (!cd->no_xdfar)
2097 add_reg(RDFAR);
2098 add_reg(RDFXR);
2099 add_reg(RDFFR);
2100 add_reg(TRSCER);
2101 add_reg(RMFCR);
2102 add_reg(TFTR);
2103 add_reg(FDR);
2104 add_reg(RMCR);
2105 add_reg(TFUCR);
2106 add_reg(RFOCR);
2107 if (cd->rmiimode)
2108 add_reg(RMIIMODE);
2109 add_reg(FCFTR);
2110 if (cd->rpadir)
2111 add_reg(RPADIR);
2112 if (!cd->no_trimd)
2113 add_reg(TRIMD);
2114 add_reg(ECMR);
2115 add_reg(ECSR);
2116 add_reg(ECSIPR);
2117 add_reg(PIR);
2118 if (!cd->no_psr)
2119 add_reg(PSR);
2120 add_reg(RDMLR);
2121 add_reg(RFLR);
2122 add_reg(IPGR);
2123 if (cd->apr)
2124 add_reg(APR);
2125 if (cd->mpr)
2126 add_reg(MPR);
2127 add_reg(RFCR);
2128 add_reg(RFCF);
2129 if (cd->tpauser)
2130 add_reg(TPAUSER);
2131 add_reg(TPAUSECR);
2132 if (cd->gecmr)
2133 add_reg(GECMR);
2134 if (cd->bculr)
2135 add_reg(BCULR);
2136 add_reg(MAHR);
2137 add_reg(MALR);
2138 if (!cd->no_tx_cntrs) {
2139 add_reg(TROCR);
2140 add_reg(CDCR);
2141 add_reg(LCCR);
2142 add_reg(CNDCR);
2143 }
2144 add_reg(CEFCR);
2145 add_reg(FRECR);
2146 add_reg(TSFRCR);
2147 add_reg(TLFRCR);
2148 if (cd->cexcr) {
2149 add_reg(CERCR);
2150 add_reg(CEECR);
2151 }
2152 add_reg(MAFCR);
2153 if (cd->rtrate)
2154 add_reg(RTRATE);
2155 if (cd->csmr)
2156 add_reg(CSMR);
2157 if (cd->select_mii)
2158 add_reg(RMII_MII);
2159 if (cd->tsu) {
2160 add_tsu_reg(ARSTR);
2161 add_tsu_reg(TSU_CTRST);
2162 if (cd->dual_port) {
2163 add_tsu_reg(TSU_FWEN0);
2164 add_tsu_reg(TSU_FWEN1);
2165 add_tsu_reg(TSU_FCM);
2166 add_tsu_reg(TSU_BSYSL0);
2167 add_tsu_reg(TSU_BSYSL1);
2168 add_tsu_reg(TSU_PRISL0);
2169 add_tsu_reg(TSU_PRISL1);
2170 add_tsu_reg(TSU_FWSL0);
2171 add_tsu_reg(TSU_FWSL1);
2172 }
2173 add_tsu_reg(TSU_FWSLC);
2174 if (cd->dual_port) {
2175 add_tsu_reg(TSU_QTAGM0);
2176 add_tsu_reg(TSU_QTAGM1);
2177 add_tsu_reg(TSU_FWSR);
2178 add_tsu_reg(TSU_FWINMK);
2179 add_tsu_reg(TSU_ADQT0);
2180 add_tsu_reg(TSU_ADQT1);
2181 add_tsu_reg(TSU_VTAG0);
2182 add_tsu_reg(TSU_VTAG1);
2183 }
2184 add_tsu_reg(TSU_ADSBSY);
2185 add_tsu_reg(TSU_TEN);
2186 add_tsu_reg(TSU_POST1);
2187 add_tsu_reg(TSU_POST2);
2188 add_tsu_reg(TSU_POST3);
2189 add_tsu_reg(TSU_POST4);
2190 /* This is the start of a table, not just a single register. */
2191 if (buf) {
2192 unsigned int i;
2193
2194 mark_reg_valid(TSU_ADRH0);
2195 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2196 *buf++ = ioread32(mdp->tsu_addr +
2197 mdp->reg_offset[TSU_ADRH0] +
2198 i * 4);
2199 }
2200 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2201 }
2202
2203#undef mark_reg_valid
2204#undef add_reg_from
2205#undef add_reg
2206#undef add_tsu_reg
2207
2208 return len * 4;
2209}
2210
2211static int sh_eth_get_regs_len(struct net_device *ndev)
2212{
2213 return __sh_eth_get_regs(ndev, NULL);
2214}
2215
2216static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2217 void *buf)
2218{
2219 struct sh_eth_private *mdp = netdev_priv(ndev);
2220
2221 regs->version = SH_ETH_REG_DUMP_VERSION;
2222
2223 pm_runtime_get_sync(&mdp->pdev->dev);
2224 __sh_eth_get_regs(ndev, buf);
2225 pm_runtime_put_sync(&mdp->pdev->dev);
2226}
2227
2228static u32 sh_eth_get_msglevel(struct net_device *ndev)
2229{
2230 struct sh_eth_private *mdp = netdev_priv(ndev);
2231 return mdp->msg_enable;
2232}
2233
2234static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2235{
2236 struct sh_eth_private *mdp = netdev_priv(ndev);
2237 mdp->msg_enable = value;
2238}
2239
2240static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2241 "rx_current", "tx_current",
2242 "rx_dirty", "tx_dirty",
2243};
2244#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2245
2246static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2247{
2248 switch (sset) {
2249 case ETH_SS_STATS:
2250 return SH_ETH_STATS_LEN;
2251 default:
2252 return -EOPNOTSUPP;
2253 }
2254}
2255
2256static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2257 struct ethtool_stats *stats, u64 *data)
2258{
2259 struct sh_eth_private *mdp = netdev_priv(ndev);
2260 int i = 0;
2261
2262 /* device-specific stats */
2263 data[i++] = mdp->cur_rx;
2264 data[i++] = mdp->cur_tx;
2265 data[i++] = mdp->dirty_rx;
2266 data[i++] = mdp->dirty_tx;
2267}
2268
2269static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2270{
2271 switch (stringset) {
2272 case ETH_SS_STATS:
2273 memcpy(data, *sh_eth_gstrings_stats,
2274 sizeof(sh_eth_gstrings_stats));
2275 break;
2276 }
2277}
2278
2279static void sh_eth_get_ringparam(struct net_device *ndev,
2280 struct ethtool_ringparam *ring)
2281{
2282 struct sh_eth_private *mdp = netdev_priv(ndev);
2283
2284 ring->rx_max_pending = RX_RING_MAX;
2285 ring->tx_max_pending = TX_RING_MAX;
2286 ring->rx_pending = mdp->num_rx_ring;
2287 ring->tx_pending = mdp->num_tx_ring;
2288}
2289
2290static int sh_eth_set_ringparam(struct net_device *ndev,
2291 struct ethtool_ringparam *ring)
2292{
2293 struct sh_eth_private *mdp = netdev_priv(ndev);
2294 int ret;
2295
2296 if (ring->tx_pending > TX_RING_MAX ||
2297 ring->rx_pending > RX_RING_MAX ||
2298 ring->tx_pending < TX_RING_MIN ||
2299 ring->rx_pending < RX_RING_MIN)
2300 return -EINVAL;
2301 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2302 return -EINVAL;
2303
2304 if (netif_running(ndev)) {
2305 netif_device_detach(ndev);
2306 netif_tx_disable(ndev);
2307
2308 /* Serialise with the interrupt handler and NAPI, then
2309 * disable interrupts. We have to clear the
2310 * irq_enabled flag first to ensure that interrupts
2311 * won't be re-enabled.
2312 */
2313 mdp->irq_enabled = false;
2314 synchronize_irq(ndev->irq);
2315 napi_synchronize(&mdp->napi);
2316 sh_eth_write(ndev, 0x0000, EESIPR);
2317
2318 sh_eth_dev_exit(ndev);
2319
2320 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2321 sh_eth_ring_free(ndev);
2322 }
2323
2324 /* Set new parameters */
2325 mdp->num_rx_ring = ring->rx_pending;
2326 mdp->num_tx_ring = ring->tx_pending;
2327
2328 if (netif_running(ndev)) {
2329 ret = sh_eth_ring_init(ndev);
2330 if (ret < 0) {
2331 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2332 __func__);
2333 return ret;
2334 }
2335 ret = sh_eth_dev_init(ndev);
2336 if (ret < 0) {
2337 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2338 __func__);
2339 return ret;
2340 }
2341
2342 netif_device_attach(ndev);
2343 }
2344
2345 return 0;
2346}
2347
2348static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2349{
2350 struct sh_eth_private *mdp = netdev_priv(ndev);
2351
2352 wol->supported = 0;
2353 wol->wolopts = 0;
2354
2355 if (mdp->cd->magic) {
2356 wol->supported = WAKE_MAGIC;
2357 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2358 }
2359}
2360
2361static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2362{
2363 struct sh_eth_private *mdp = netdev_priv(ndev);
2364
2365 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC)
2366 return -EOPNOTSUPP;
2367
2368 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2369
2370 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2371
2372 return 0;
2373}
2374
2375static const struct ethtool_ops sh_eth_ethtool_ops = {
2376 .get_regs_len = sh_eth_get_regs_len,
2377 .get_regs = sh_eth_get_regs,
2378 .nway_reset = phy_ethtool_nway_reset,
2379 .get_msglevel = sh_eth_get_msglevel,
2380 .set_msglevel = sh_eth_set_msglevel,
2381 .get_link = ethtool_op_get_link,
2382 .get_strings = sh_eth_get_strings,
2383 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2384 .get_sset_count = sh_eth_get_sset_count,
2385 .get_ringparam = sh_eth_get_ringparam,
2386 .set_ringparam = sh_eth_set_ringparam,
2387 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2388 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2389 .get_wol = sh_eth_get_wol,
2390 .set_wol = sh_eth_set_wol,
2391};
2392
2393/* network device open function */
2394static int sh_eth_open(struct net_device *ndev)
2395{
2396 struct sh_eth_private *mdp = netdev_priv(ndev);
2397 int ret;
2398
2399 pm_runtime_get_sync(&mdp->pdev->dev);
2400
2401 napi_enable(&mdp->napi);
2402
2403 ret = request_irq(ndev->irq, sh_eth_interrupt,
2404 mdp->cd->irq_flags, ndev->name, ndev);
2405 if (ret) {
2406 netdev_err(ndev, "Can not assign IRQ number\n");
2407 goto out_napi_off;
2408 }
2409
2410 /* Descriptor set */
2411 ret = sh_eth_ring_init(ndev);
2412 if (ret)
2413 goto out_free_irq;
2414
2415 /* device init */
2416 ret = sh_eth_dev_init(ndev);
2417 if (ret)
2418 goto out_free_irq;
2419
2420 /* PHY control start*/
2421 ret = sh_eth_phy_start(ndev);
2422 if (ret)
2423 goto out_free_irq;
2424
2425 netif_start_queue(ndev);
2426
2427 mdp->is_opened = 1;
2428
2429 return ret;
2430
2431out_free_irq:
2432 free_irq(ndev->irq, ndev);
2433out_napi_off:
2434 napi_disable(&mdp->napi);
2435 pm_runtime_put_sync(&mdp->pdev->dev);
2436 return ret;
2437}
2438
2439/* Timeout function */
2440static void sh_eth_tx_timeout(struct net_device *ndev, unsigned int txqueue)
2441{
2442 struct sh_eth_private *mdp = netdev_priv(ndev);
2443 struct sh_eth_rxdesc *rxdesc;
2444 int i;
2445
2446 netif_stop_queue(ndev);
2447
2448 netif_err(mdp, timer, ndev,
2449 "transmit timed out, status %8.8x, resetting...\n",
2450 sh_eth_read(ndev, EESR));
2451
2452 /* tx_errors count up */
2453 ndev->stats.tx_errors++;
2454
2455 /* Free all the skbuffs in the Rx queue. */
2456 for (i = 0; i < mdp->num_rx_ring; i++) {
2457 rxdesc = &mdp->rx_ring[i];
2458 rxdesc->status = cpu_to_le32(0);
2459 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2460 dev_kfree_skb(mdp->rx_skbuff[i]);
2461 mdp->rx_skbuff[i] = NULL;
2462 }
2463 for (i = 0; i < mdp->num_tx_ring; i++) {
2464 dev_kfree_skb(mdp->tx_skbuff[i]);
2465 mdp->tx_skbuff[i] = NULL;
2466 }
2467
2468 /* device init */
2469 sh_eth_dev_init(ndev);
2470
2471 netif_start_queue(ndev);
2472}
2473
2474/* Packet transmit function */
2475static netdev_tx_t sh_eth_start_xmit(struct sk_buff *skb,
2476 struct net_device *ndev)
2477{
2478 struct sh_eth_private *mdp = netdev_priv(ndev);
2479 struct sh_eth_txdesc *txdesc;
2480 dma_addr_t dma_addr;
2481 u32 entry;
2482 unsigned long flags;
2483
2484 spin_lock_irqsave(&mdp->lock, flags);
2485 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2486 if (!sh_eth_tx_free(ndev, true)) {
2487 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2488 netif_stop_queue(ndev);
2489 spin_unlock_irqrestore(&mdp->lock, flags);
2490 return NETDEV_TX_BUSY;
2491 }
2492 }
2493 spin_unlock_irqrestore(&mdp->lock, flags);
2494
2495 if (skb_put_padto(skb, ETH_ZLEN))
2496 return NETDEV_TX_OK;
2497
2498 entry = mdp->cur_tx % mdp->num_tx_ring;
2499 mdp->tx_skbuff[entry] = skb;
2500 txdesc = &mdp->tx_ring[entry];
2501 /* soft swap. */
2502 if (!mdp->cd->hw_swap)
2503 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2504 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len,
2505 DMA_TO_DEVICE);
2506 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
2507 kfree_skb(skb);
2508 return NETDEV_TX_OK;
2509 }
2510 txdesc->addr = cpu_to_le32(dma_addr);
2511 txdesc->len = cpu_to_le32(skb->len << 16);
2512
2513 dma_wmb(); /* TACT bit must be set after all the above writes */
2514 if (entry >= mdp->num_tx_ring - 1)
2515 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2516 else
2517 txdesc->status |= cpu_to_le32(TD_TACT);
2518
2519 mdp->cur_tx++;
2520
2521 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns))
2522 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
2523
2524 return NETDEV_TX_OK;
2525}
2526
2527/* The statistics registers have write-clear behaviour, which means we
2528 * will lose any increment between the read and write. We mitigate
2529 * this by only clearing when we read a non-zero value, so we will
2530 * never falsely report a total of zero.
2531 */
2532static void
2533sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2534{
2535 u32 delta = sh_eth_read(ndev, reg);
2536
2537 if (delta) {
2538 *stat += delta;
2539 sh_eth_write(ndev, 0, reg);
2540 }
2541}
2542
2543static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2544{
2545 struct sh_eth_private *mdp = netdev_priv(ndev);
2546
2547 if (mdp->cd->no_tx_cntrs)
2548 return &ndev->stats;
2549
2550 if (!mdp->is_opened)
2551 return &ndev->stats;
2552
2553 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2554 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2555 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2556
2557 if (mdp->cd->cexcr) {
2558 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2559 CERCR);
2560 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2561 CEECR);
2562 } else {
2563 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2564 CNDCR);
2565 }
2566
2567 return &ndev->stats;
2568}
2569
2570/* device close function */
2571static int sh_eth_close(struct net_device *ndev)
2572{
2573 struct sh_eth_private *mdp = netdev_priv(ndev);
2574
2575 netif_stop_queue(ndev);
2576
2577 /* Serialise with the interrupt handler and NAPI, then disable
2578 * interrupts. We have to clear the irq_enabled flag first to
2579 * ensure that interrupts won't be re-enabled.
2580 */
2581 mdp->irq_enabled = false;
2582 synchronize_irq(ndev->irq);
2583 napi_disable(&mdp->napi);
2584 sh_eth_write(ndev, 0x0000, EESIPR);
2585
2586 sh_eth_dev_exit(ndev);
2587
2588 /* PHY Disconnect */
2589 if (ndev->phydev) {
2590 phy_stop(ndev->phydev);
2591 phy_disconnect(ndev->phydev);
2592 }
2593
2594 free_irq(ndev->irq, ndev);
2595
2596 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2597 sh_eth_ring_free(ndev);
2598
2599 pm_runtime_put_sync(&mdp->pdev->dev);
2600
2601 mdp->is_opened = 0;
2602
2603 return 0;
2604}
2605
2606static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
2607{
2608 if (netif_running(ndev))
2609 return -EBUSY;
2610
2611 ndev->mtu = new_mtu;
2612 netdev_update_features(ndev);
2613
2614 return 0;
2615}
2616
2617/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2618static u32 sh_eth_tsu_get_post_mask(int entry)
2619{
2620 return 0x0f << (28 - ((entry % 8) * 4));
2621}
2622
2623static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2624{
2625 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2626}
2627
2628static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2629 int entry)
2630{
2631 struct sh_eth_private *mdp = netdev_priv(ndev);
2632 int reg = TSU_POST1 + entry / 8;
2633 u32 tmp;
2634
2635 tmp = sh_eth_tsu_read(mdp, reg);
2636 sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg);
2637}
2638
2639static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2640 int entry)
2641{
2642 struct sh_eth_private *mdp = netdev_priv(ndev);
2643 int reg = TSU_POST1 + entry / 8;
2644 u32 post_mask, ref_mask, tmp;
2645
2646 post_mask = sh_eth_tsu_get_post_mask(entry);
2647 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2648
2649 tmp = sh_eth_tsu_read(mdp, reg);
2650 sh_eth_tsu_write(mdp, tmp & ~post_mask, reg);
2651
2652 /* If other port enables, the function returns "true" */
2653 return tmp & ref_mask;
2654}
2655
2656static int sh_eth_tsu_busy(struct net_device *ndev)
2657{
2658 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2659 struct sh_eth_private *mdp = netdev_priv(ndev);
2660
2661 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2662 udelay(10);
2663 timeout--;
2664 if (timeout <= 0) {
2665 netdev_err(ndev, "%s: timeout\n", __func__);
2666 return -ETIMEDOUT;
2667 }
2668 }
2669
2670 return 0;
2671}
2672
2673static int sh_eth_tsu_write_entry(struct net_device *ndev, u16 offset,
2674 const u8 *addr)
2675{
2676 struct sh_eth_private *mdp = netdev_priv(ndev);
2677 u32 val;
2678
2679 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2680 iowrite32(val, mdp->tsu_addr + offset);
2681 if (sh_eth_tsu_busy(ndev) < 0)
2682 return -EBUSY;
2683
2684 val = addr[4] << 8 | addr[5];
2685 iowrite32(val, mdp->tsu_addr + offset + 4);
2686 if (sh_eth_tsu_busy(ndev) < 0)
2687 return -EBUSY;
2688
2689 return 0;
2690}
2691
2692static void sh_eth_tsu_read_entry(struct net_device *ndev, u16 offset, u8 *addr)
2693{
2694 struct sh_eth_private *mdp = netdev_priv(ndev);
2695 u32 val;
2696
2697 val = ioread32(mdp->tsu_addr + offset);
2698 addr[0] = (val >> 24) & 0xff;
2699 addr[1] = (val >> 16) & 0xff;
2700 addr[2] = (val >> 8) & 0xff;
2701 addr[3] = val & 0xff;
2702 val = ioread32(mdp->tsu_addr + offset + 4);
2703 addr[4] = (val >> 8) & 0xff;
2704 addr[5] = val & 0xff;
2705}
2706
2707
2708static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2709{
2710 struct sh_eth_private *mdp = netdev_priv(ndev);
2711 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2712 int i;
2713 u8 c_addr[ETH_ALEN];
2714
2715 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2716 sh_eth_tsu_read_entry(ndev, reg_offset, c_addr);
2717 if (ether_addr_equal(addr, c_addr))
2718 return i;
2719 }
2720
2721 return -ENOENT;
2722}
2723
2724static int sh_eth_tsu_find_empty(struct net_device *ndev)
2725{
2726 u8 blank[ETH_ALEN];
2727 int entry;
2728
2729 memset(blank, 0, sizeof(blank));
2730 entry = sh_eth_tsu_find_entry(ndev, blank);
2731 return (entry < 0) ? -ENOMEM : entry;
2732}
2733
2734static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2735 int entry)
2736{
2737 struct sh_eth_private *mdp = netdev_priv(ndev);
2738 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2739 int ret;
2740 u8 blank[ETH_ALEN];
2741
2742 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2743 ~(1 << (31 - entry)), TSU_TEN);
2744
2745 memset(blank, 0, sizeof(blank));
2746 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2747 if (ret < 0)
2748 return ret;
2749 return 0;
2750}
2751
2752static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2753{
2754 struct sh_eth_private *mdp = netdev_priv(ndev);
2755 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2756 int i, ret;
2757
2758 if (!mdp->cd->tsu)
2759 return 0;
2760
2761 i = sh_eth_tsu_find_entry(ndev, addr);
2762 if (i < 0) {
2763 /* No entry found, create one */
2764 i = sh_eth_tsu_find_empty(ndev);
2765 if (i < 0)
2766 return -ENOMEM;
2767 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2768 if (ret < 0)
2769 return ret;
2770
2771 /* Enable the entry */
2772 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2773 (1 << (31 - i)), TSU_TEN);
2774 }
2775
2776 /* Entry found or created, enable POST */
2777 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2778
2779 return 0;
2780}
2781
2782static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2783{
2784 struct sh_eth_private *mdp = netdev_priv(ndev);
2785 int i, ret;
2786
2787 if (!mdp->cd->tsu)
2788 return 0;
2789
2790 i = sh_eth_tsu_find_entry(ndev, addr);
2791 if (i) {
2792 /* Entry found */
2793 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2794 goto done;
2795
2796 /* Disable the entry if both ports was disabled */
2797 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2798 if (ret < 0)
2799 return ret;
2800 }
2801done:
2802 return 0;
2803}
2804
2805static int sh_eth_tsu_purge_all(struct net_device *ndev)
2806{
2807 struct sh_eth_private *mdp = netdev_priv(ndev);
2808 int i, ret;
2809
2810 if (!mdp->cd->tsu)
2811 return 0;
2812
2813 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2814 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2815 continue;
2816
2817 /* Disable the entry if both ports was disabled */
2818 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2819 if (ret < 0)
2820 return ret;
2821 }
2822
2823 return 0;
2824}
2825
2826static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2827{
2828 struct sh_eth_private *mdp = netdev_priv(ndev);
2829 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2830 u8 addr[ETH_ALEN];
2831 int i;
2832
2833 if (!mdp->cd->tsu)
2834 return;
2835
2836 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2837 sh_eth_tsu_read_entry(ndev, reg_offset, addr);
2838 if (is_multicast_ether_addr(addr))
2839 sh_eth_tsu_del_entry(ndev, addr);
2840 }
2841}
2842
2843/* Update promiscuous flag and multicast filter */
2844static void sh_eth_set_rx_mode(struct net_device *ndev)
2845{
2846 struct sh_eth_private *mdp = netdev_priv(ndev);
2847 u32 ecmr_bits;
2848 int mcast_all = 0;
2849 unsigned long flags;
2850
2851 spin_lock_irqsave(&mdp->lock, flags);
2852 /* Initial condition is MCT = 1, PRM = 0.
2853 * Depending on ndev->flags, set PRM or clear MCT
2854 */
2855 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2856 if (mdp->cd->tsu)
2857 ecmr_bits |= ECMR_MCT;
2858
2859 if (!(ndev->flags & IFF_MULTICAST)) {
2860 sh_eth_tsu_purge_mcast(ndev);
2861 mcast_all = 1;
2862 }
2863 if (ndev->flags & IFF_ALLMULTI) {
2864 sh_eth_tsu_purge_mcast(ndev);
2865 ecmr_bits &= ~ECMR_MCT;
2866 mcast_all = 1;
2867 }
2868
2869 if (ndev->flags & IFF_PROMISC) {
2870 sh_eth_tsu_purge_all(ndev);
2871 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2872 } else if (mdp->cd->tsu) {
2873 struct netdev_hw_addr *ha;
2874 netdev_for_each_mc_addr(ha, ndev) {
2875 if (mcast_all && is_multicast_ether_addr(ha->addr))
2876 continue;
2877
2878 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2879 if (!mcast_all) {
2880 sh_eth_tsu_purge_mcast(ndev);
2881 ecmr_bits &= ~ECMR_MCT;
2882 mcast_all = 1;
2883 }
2884 }
2885 }
2886 }
2887
2888 /* update the ethernet mode */
2889 sh_eth_write(ndev, ecmr_bits, ECMR);
2890
2891 spin_unlock_irqrestore(&mdp->lock, flags);
2892}
2893
2894static void sh_eth_set_rx_csum(struct net_device *ndev, bool enable)
2895{
2896 struct sh_eth_private *mdp = netdev_priv(ndev);
2897 unsigned long flags;
2898
2899 spin_lock_irqsave(&mdp->lock, flags);
2900
2901 /* Disable TX and RX */
2902 sh_eth_rcv_snd_disable(ndev);
2903
2904 /* Modify RX Checksum setting */
2905 sh_eth_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
2906
2907 /* Enable TX and RX */
2908 sh_eth_rcv_snd_enable(ndev);
2909
2910 spin_unlock_irqrestore(&mdp->lock, flags);
2911}
2912
2913static int sh_eth_set_features(struct net_device *ndev,
2914 netdev_features_t features)
2915{
2916 netdev_features_t changed = ndev->features ^ features;
2917 struct sh_eth_private *mdp = netdev_priv(ndev);
2918
2919 if (changed & NETIF_F_RXCSUM && mdp->cd->rx_csum)
2920 sh_eth_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
2921
2922 ndev->features = features;
2923
2924 return 0;
2925}
2926
2927static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2928{
2929 if (!mdp->port)
2930 return TSU_VTAG0;
2931 else
2932 return TSU_VTAG1;
2933}
2934
2935static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2936 __be16 proto, u16 vid)
2937{
2938 struct sh_eth_private *mdp = netdev_priv(ndev);
2939 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2940
2941 if (unlikely(!mdp->cd->tsu))
2942 return -EPERM;
2943
2944 /* No filtering if vid = 0 */
2945 if (!vid)
2946 return 0;
2947
2948 mdp->vlan_num_ids++;
2949
2950 /* The controller has one VLAN tag HW filter. So, if the filter is
2951 * already enabled, the driver disables it and the filte
2952 */
2953 if (mdp->vlan_num_ids > 1) {
2954 /* disable VLAN filter */
2955 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2956 return 0;
2957 }
2958
2959 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2960 vtag_reg_index);
2961
2962 return 0;
2963}
2964
2965static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2966 __be16 proto, u16 vid)
2967{
2968 struct sh_eth_private *mdp = netdev_priv(ndev);
2969 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2970
2971 if (unlikely(!mdp->cd->tsu))
2972 return -EPERM;
2973
2974 /* No filtering if vid = 0 */
2975 if (!vid)
2976 return 0;
2977
2978 mdp->vlan_num_ids--;
2979 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2980
2981 return 0;
2982}
2983
2984/* SuperH's TSU register init function */
2985static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2986{
2987 if (!mdp->cd->dual_port) {
2988 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2989 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
2990 TSU_FWSLC); /* Enable POST registers */
2991 return;
2992 }
2993
2994 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2995 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2996 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2997 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2998 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2999 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
3000 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
3001 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
3002 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
3003 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
3004 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
3005 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
3006 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
3007 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
3008 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
3009 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
3010 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
3011 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
3012 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
3013}
3014
3015/* MDIO bus release function */
3016static int sh_mdio_release(struct sh_eth_private *mdp)
3017{
3018 /* unregister mdio bus */
3019 mdiobus_unregister(mdp->mii_bus);
3020
3021 /* free bitbang info */
3022 free_mdio_bitbang(mdp->mii_bus);
3023
3024 return 0;
3025}
3026
3027/* MDIO bus init function */
3028static int sh_mdio_init(struct sh_eth_private *mdp,
3029 struct sh_eth_plat_data *pd)
3030{
3031 int ret;
3032 struct bb_info *bitbang;
3033 struct platform_device *pdev = mdp->pdev;
3034 struct device *dev = &mdp->pdev->dev;
3035
3036 /* create bit control struct for PHY */
3037 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
3038 if (!bitbang)
3039 return -ENOMEM;
3040
3041 /* bitbang init */
3042 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
3043 bitbang->set_gate = pd->set_mdio_gate;
3044 bitbang->ctrl.ops = &bb_ops;
3045
3046 /* MII controller setting */
3047 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
3048 if (!mdp->mii_bus)
3049 return -ENOMEM;
3050
3051 /* Hook up MII support for ethtool */
3052 mdp->mii_bus->name = "sh_mii";
3053 mdp->mii_bus->parent = dev;
3054 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
3055 pdev->name, pdev->id);
3056
3057 /* register MDIO bus */
3058 if (pd->phy_irq > 0)
3059 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
3060
3061 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
3062 if (ret)
3063 goto out_free_bus;
3064
3065 return 0;
3066
3067out_free_bus:
3068 free_mdio_bitbang(mdp->mii_bus);
3069 return ret;
3070}
3071
3072static const u16 *sh_eth_get_register_offset(int register_type)
3073{
3074 const u16 *reg_offset = NULL;
3075
3076 switch (register_type) {
3077 case SH_ETH_REG_GIGABIT:
3078 reg_offset = sh_eth_offset_gigabit;
3079 break;
3080 case SH_ETH_REG_FAST_RCAR:
3081 reg_offset = sh_eth_offset_fast_rcar;
3082 break;
3083 case SH_ETH_REG_FAST_SH4:
3084 reg_offset = sh_eth_offset_fast_sh4;
3085 break;
3086 case SH_ETH_REG_FAST_SH3_SH2:
3087 reg_offset = sh_eth_offset_fast_sh3_sh2;
3088 break;
3089 }
3090
3091 return reg_offset;
3092}
3093
3094static const struct net_device_ops sh_eth_netdev_ops = {
3095 .ndo_open = sh_eth_open,
3096 .ndo_stop = sh_eth_close,
3097 .ndo_start_xmit = sh_eth_start_xmit,
3098 .ndo_get_stats = sh_eth_get_stats,
3099 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3100 .ndo_tx_timeout = sh_eth_tx_timeout,
3101 .ndo_do_ioctl = phy_do_ioctl_running,
3102 .ndo_change_mtu = sh_eth_change_mtu,
3103 .ndo_validate_addr = eth_validate_addr,
3104 .ndo_set_mac_address = eth_mac_addr,
3105 .ndo_set_features = sh_eth_set_features,
3106};
3107
3108static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3109 .ndo_open = sh_eth_open,
3110 .ndo_stop = sh_eth_close,
3111 .ndo_start_xmit = sh_eth_start_xmit,
3112 .ndo_get_stats = sh_eth_get_stats,
3113 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3114 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
3115 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
3116 .ndo_tx_timeout = sh_eth_tx_timeout,
3117 .ndo_do_ioctl = phy_do_ioctl_running,
3118 .ndo_change_mtu = sh_eth_change_mtu,
3119 .ndo_validate_addr = eth_validate_addr,
3120 .ndo_set_mac_address = eth_mac_addr,
3121 .ndo_set_features = sh_eth_set_features,
3122};
3123
3124#ifdef CONFIG_OF
3125static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3126{
3127 struct device_node *np = dev->of_node;
3128 struct sh_eth_plat_data *pdata;
3129 phy_interface_t interface;
3130 const char *mac_addr;
3131 int ret;
3132
3133 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3134 if (!pdata)
3135 return NULL;
3136
3137 ret = of_get_phy_mode(np, &interface);
3138 if (ret)
3139 return NULL;
3140 pdata->phy_interface = interface;
3141
3142 mac_addr = of_get_mac_address(np);
3143 if (!IS_ERR(mac_addr))
3144 ether_addr_copy(pdata->mac_addr, mac_addr);
3145
3146 pdata->no_ether_link =
3147 of_property_read_bool(np, "renesas,no-ether-link");
3148 pdata->ether_link_active_low =
3149 of_property_read_bool(np, "renesas,ether-link-active-low");
3150
3151 return pdata;
3152}
3153
3154static const struct of_device_id sh_eth_match_table[] = {
3155 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3156 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data },
3157 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data },
3158 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data },
3159 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data },
3160 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data },
3161 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data },
3162 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },
3163 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },
3164 { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data },
3165 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3166 { .compatible = "renesas,ether-r7s9210", .data = &r7s9210_data },
3167 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data },
3168 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data },
3169 { }
3170};
3171MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3172#else
3173static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3174{
3175 return NULL;
3176}
3177#endif
3178
3179static int sh_eth_drv_probe(struct platform_device *pdev)
3180{
3181 struct resource *res;
3182 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3183 const struct platform_device_id *id = platform_get_device_id(pdev);
3184 struct sh_eth_private *mdp;
3185 struct net_device *ndev;
3186 int ret;
3187
3188 /* get base addr */
3189 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3190
3191 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3192 if (!ndev)
3193 return -ENOMEM;
3194
3195 pm_runtime_enable(&pdev->dev);
3196 pm_runtime_get_sync(&pdev->dev);
3197
3198 ret = platform_get_irq(pdev, 0);
3199 if (ret < 0)
3200 goto out_release;
3201 ndev->irq = ret;
3202
3203 SET_NETDEV_DEV(ndev, &pdev->dev);
3204
3205 mdp = netdev_priv(ndev);
3206 mdp->num_tx_ring = TX_RING_SIZE;
3207 mdp->num_rx_ring = RX_RING_SIZE;
3208 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3209 if (IS_ERR(mdp->addr)) {
3210 ret = PTR_ERR(mdp->addr);
3211 goto out_release;
3212 }
3213
3214 ndev->base_addr = res->start;
3215
3216 spin_lock_init(&mdp->lock);
3217 mdp->pdev = pdev;
3218
3219 if (pdev->dev.of_node)
3220 pd = sh_eth_parse_dt(&pdev->dev);
3221 if (!pd) {
3222 dev_err(&pdev->dev, "no platform data\n");
3223 ret = -EINVAL;
3224 goto out_release;
3225 }
3226
3227 /* get PHY ID */
3228 mdp->phy_id = pd->phy;
3229 mdp->phy_interface = pd->phy_interface;
3230 mdp->no_ether_link = pd->no_ether_link;
3231 mdp->ether_link_active_low = pd->ether_link_active_low;
3232
3233 /* set cpu data */
3234 if (id)
3235 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3236 else
3237 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3238
3239 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3240 if (!mdp->reg_offset) {
3241 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3242 mdp->cd->register_type);
3243 ret = -EINVAL;
3244 goto out_release;
3245 }
3246 sh_eth_set_default_cpu_data(mdp->cd);
3247
3248 /* User's manual states max MTU should be 2048 but due to the
3249 * alignment calculations in sh_eth_ring_init() the practical
3250 * MTU is a bit less. Maybe this can be optimized some more.
3251 */
3252 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
3253 ndev->min_mtu = ETH_MIN_MTU;
3254
3255 if (mdp->cd->rx_csum) {
3256 ndev->features = NETIF_F_RXCSUM;
3257 ndev->hw_features = NETIF_F_RXCSUM;
3258 }
3259
3260 /* set function */
3261 if (mdp->cd->tsu)
3262 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3263 else
3264 ndev->netdev_ops = &sh_eth_netdev_ops;
3265 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3266 ndev->watchdog_timeo = TX_TIMEOUT;
3267
3268 /* debug message level */
3269 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3270
3271 /* read and set MAC address */
3272 read_mac_address(ndev, pd->mac_addr);
3273 if (!is_valid_ether_addr(ndev->dev_addr)) {
3274 dev_warn(&pdev->dev,
3275 "no valid MAC address supplied, using a random one.\n");
3276 eth_hw_addr_random(ndev);
3277 }
3278
3279 if (mdp->cd->tsu) {
3280 int port = pdev->id < 0 ? 0 : pdev->id % 2;
3281 struct resource *rtsu;
3282
3283 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3284 if (!rtsu) {
3285 dev_err(&pdev->dev, "no TSU resource\n");
3286 ret = -ENODEV;
3287 goto out_release;
3288 }
3289 /* We can only request the TSU region for the first port
3290 * of the two sharing this TSU for the probe to succeed...
3291 */
3292 if (port == 0 &&
3293 !devm_request_mem_region(&pdev->dev, rtsu->start,
3294 resource_size(rtsu),
3295 dev_name(&pdev->dev))) {
3296 dev_err(&pdev->dev, "can't request TSU resource.\n");
3297 ret = -EBUSY;
3298 goto out_release;
3299 }
3300 /* ioremap the TSU registers */
3301 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start,
3302 resource_size(rtsu));
3303 if (!mdp->tsu_addr) {
3304 dev_err(&pdev->dev, "TSU region ioremap() failed.\n");
3305 ret = -ENOMEM;
3306 goto out_release;
3307 }
3308 mdp->port = port;
3309 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3310
3311 /* Need to init only the first port of the two sharing a TSU */
3312 if (port == 0) {
3313 if (mdp->cd->chip_reset)
3314 mdp->cd->chip_reset(ndev);
3315
3316 /* TSU init (Init only)*/
3317 sh_eth_tsu_init(mdp);
3318 }
3319 }
3320
3321 if (mdp->cd->rmiimode)
3322 sh_eth_write(ndev, 0x1, RMIIMODE);
3323
3324 /* MDIO bus init */
3325 ret = sh_mdio_init(mdp, pd);
3326 if (ret) {
3327 if (ret != -EPROBE_DEFER)
3328 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret);
3329 goto out_release;
3330 }
3331
3332 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3333
3334 /* network device register */
3335 ret = register_netdev(ndev);
3336 if (ret)
3337 goto out_napi_del;
3338
3339 if (mdp->cd->magic)
3340 device_set_wakeup_capable(&pdev->dev, 1);
3341
3342 /* print device information */
3343 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3344 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3345
3346 pm_runtime_put(&pdev->dev);
3347 platform_set_drvdata(pdev, ndev);
3348
3349 return ret;
3350
3351out_napi_del:
3352 netif_napi_del(&mdp->napi);
3353 sh_mdio_release(mdp);
3354
3355out_release:
3356 /* net_dev free */
3357 free_netdev(ndev);
3358
3359 pm_runtime_put(&pdev->dev);
3360 pm_runtime_disable(&pdev->dev);
3361 return ret;
3362}
3363
3364static int sh_eth_drv_remove(struct platform_device *pdev)
3365{
3366 struct net_device *ndev = platform_get_drvdata(pdev);
3367 struct sh_eth_private *mdp = netdev_priv(ndev);
3368
3369 unregister_netdev(ndev);
3370 netif_napi_del(&mdp->napi);
3371 sh_mdio_release(mdp);
3372 pm_runtime_disable(&pdev->dev);
3373 free_netdev(ndev);
3374
3375 return 0;
3376}
3377
3378#ifdef CONFIG_PM
3379#ifdef CONFIG_PM_SLEEP
3380static int sh_eth_wol_setup(struct net_device *ndev)
3381{
3382 struct sh_eth_private *mdp = netdev_priv(ndev);
3383
3384 /* Only allow ECI interrupts */
3385 synchronize_irq(ndev->irq);
3386 napi_disable(&mdp->napi);
3387 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
3388
3389 /* Enable MagicPacket */
3390 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
3391
3392 return enable_irq_wake(ndev->irq);
3393}
3394
3395static int sh_eth_wol_restore(struct net_device *ndev)
3396{
3397 struct sh_eth_private *mdp = netdev_priv(ndev);
3398 int ret;
3399
3400 napi_enable(&mdp->napi);
3401
3402 /* Disable MagicPacket */
3403 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3404
3405 /* The device needs to be reset to restore MagicPacket logic
3406 * for next wakeup. If we close and open the device it will
3407 * both be reset and all registers restored. This is what
3408 * happens during suspend and resume without WoL enabled.
3409 */
3410 ret = sh_eth_close(ndev);
3411 if (ret < 0)
3412 return ret;
3413 ret = sh_eth_open(ndev);
3414 if (ret < 0)
3415 return ret;
3416
3417 return disable_irq_wake(ndev->irq);
3418}
3419
3420static int sh_eth_suspend(struct device *dev)
3421{
3422 struct net_device *ndev = dev_get_drvdata(dev);
3423 struct sh_eth_private *mdp = netdev_priv(ndev);
3424 int ret = 0;
3425
3426 if (!netif_running(ndev))
3427 return 0;
3428
3429 netif_device_detach(ndev);
3430
3431 if (mdp->wol_enabled)
3432 ret = sh_eth_wol_setup(ndev);
3433 else
3434 ret = sh_eth_close(ndev);
3435
3436 return ret;
3437}
3438
3439static int sh_eth_resume(struct device *dev)
3440{
3441 struct net_device *ndev = dev_get_drvdata(dev);
3442 struct sh_eth_private *mdp = netdev_priv(ndev);
3443 int ret = 0;
3444
3445 if (!netif_running(ndev))
3446 return 0;
3447
3448 if (mdp->wol_enabled)
3449 ret = sh_eth_wol_restore(ndev);
3450 else
3451 ret = sh_eth_open(ndev);
3452
3453 if (ret < 0)
3454 return ret;
3455
3456 netif_device_attach(ndev);
3457
3458 return ret;
3459}
3460#endif
3461
3462static int sh_eth_runtime_nop(struct device *dev)
3463{
3464 /* Runtime PM callback shared between ->runtime_suspend()
3465 * and ->runtime_resume(). Simply returns success.
3466 *
3467 * This driver re-initializes all registers after
3468 * pm_runtime_get_sync() anyway so there is no need
3469 * to save and restore registers here.
3470 */
3471 return 0;
3472}
3473
3474static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3475 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3476 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3477};
3478#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3479#else
3480#define SH_ETH_PM_OPS NULL
3481#endif
3482
3483static const struct platform_device_id sh_eth_id_table[] = {
3484 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3485 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3486 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3487 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3488 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3489 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3490 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3491 { }
3492};
3493MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3494
3495static struct platform_driver sh_eth_driver = {
3496 .probe = sh_eth_drv_probe,
3497 .remove = sh_eth_drv_remove,
3498 .id_table = sh_eth_id_table,
3499 .driver = {
3500 .name = CARDNAME,
3501 .pm = SH_ETH_PM_OPS,
3502 .of_match_table = of_match_ptr(sh_eth_match_table),
3503 },
3504};
3505
3506module_platform_driver(sh_eth_driver);
3507
3508MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3509MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3510MODULE_LICENSE("GPL v2");