Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 *
5 * Note: This driver is a cleanroom reimplementation based on reverse
6 * engineered documentation written by Carl-Daniel Hailfinger
7 * and Andrew de Quincey.
8 *
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
11 * countries.
12 *
13 * Copyright (C) 2003,4,5 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
17 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
18 *
19 * Known bugs:
20 * We suspect that on some hardware no TX done interrupts are generated.
21 * This means recovery from netif_stop_queue only happens if the hw timer
22 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
23 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
24 * If your hardware reliably generates tx done interrupts, then you can remove
25 * DEV_NEED_TIMERIRQ from the driver_data flags.
26 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
27 * superfluous timer interrupts from the nic.
28 */
29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32#define FORCEDETH_VERSION "0.64"
33#define DRV_NAME "forcedeth"
34
35#include <linux/module.h>
36#include <linux/types.h>
37#include <linux/pci.h>
38#include <linux/interrupt.h>
39#include <linux/netdevice.h>
40#include <linux/etherdevice.h>
41#include <linux/delay.h>
42#include <linux/sched.h>
43#include <linux/spinlock.h>
44#include <linux/ethtool.h>
45#include <linux/timer.h>
46#include <linux/skbuff.h>
47#include <linux/mii.h>
48#include <linux/random.h>
49#include <linux/if_vlan.h>
50#include <linux/dma-mapping.h>
51#include <linux/slab.h>
52#include <linux/uaccess.h>
53#include <linux/prefetch.h>
54#include <linux/u64_stats_sync.h>
55#include <linux/io.h>
56
57#include <asm/irq.h>
58
59#define TX_WORK_PER_LOOP 64
60#define RX_WORK_PER_LOOP 64
61
62/*
63 * Hardware access:
64 */
65
66#define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
67#define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
68#define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
69#define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
70#define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
71#define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
72#define DEV_HAS_MSI 0x0000040 /* device supports MSI */
73#define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
74#define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
75#define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
76#define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */
77#define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */
78#define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */
79#define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */
80#define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
81#define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
82#define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
83#define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
84#define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
85#define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
86#define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
87#define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
88#define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
89#define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
90#define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
91#define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
92#define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
93
94enum {
95 NvRegIrqStatus = 0x000,
96#define NVREG_IRQSTAT_MIIEVENT 0x040
97#define NVREG_IRQSTAT_MASK 0x83ff
98 NvRegIrqMask = 0x004,
99#define NVREG_IRQ_RX_ERROR 0x0001
100#define NVREG_IRQ_RX 0x0002
101#define NVREG_IRQ_RX_NOBUF 0x0004
102#define NVREG_IRQ_TX_ERR 0x0008
103#define NVREG_IRQ_TX_OK 0x0010
104#define NVREG_IRQ_TIMER 0x0020
105#define NVREG_IRQ_LINK 0x0040
106#define NVREG_IRQ_RX_FORCED 0x0080
107#define NVREG_IRQ_TX_FORCED 0x0100
108#define NVREG_IRQ_RECOVER_ERROR 0x8200
109#define NVREG_IRQMASK_THROUGHPUT 0x00df
110#define NVREG_IRQMASK_CPU 0x0060
111#define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
112#define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
113#define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
114
115 NvRegUnknownSetupReg6 = 0x008,
116#define NVREG_UNKSETUP6_VAL 3
117
118/*
119 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
120 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
121 */
122 NvRegPollingInterval = 0x00c,
123#define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
124#define NVREG_POLL_DEFAULT_CPU 13
125 NvRegMSIMap0 = 0x020,
126 NvRegMSIMap1 = 0x024,
127 NvRegMSIIrqMask = 0x030,
128#define NVREG_MSI_VECTOR_0_ENABLED 0x01
129 NvRegMisc1 = 0x080,
130#define NVREG_MISC1_PAUSE_TX 0x01
131#define NVREG_MISC1_HD 0x02
132#define NVREG_MISC1_FORCE 0x3b0f3c
133
134 NvRegMacReset = 0x34,
135#define NVREG_MAC_RESET_ASSERT 0x0F3
136 NvRegTransmitterControl = 0x084,
137#define NVREG_XMITCTL_START 0x01
138#define NVREG_XMITCTL_MGMT_ST 0x40000000
139#define NVREG_XMITCTL_SYNC_MASK 0x000f0000
140#define NVREG_XMITCTL_SYNC_NOT_READY 0x0
141#define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
142#define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
143#define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
144#define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
145#define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
146#define NVREG_XMITCTL_HOST_LOADED 0x00004000
147#define NVREG_XMITCTL_TX_PATH_EN 0x01000000
148#define NVREG_XMITCTL_DATA_START 0x00100000
149#define NVREG_XMITCTL_DATA_READY 0x00010000
150#define NVREG_XMITCTL_DATA_ERROR 0x00020000
151 NvRegTransmitterStatus = 0x088,
152#define NVREG_XMITSTAT_BUSY 0x01
153
154 NvRegPacketFilterFlags = 0x8c,
155#define NVREG_PFF_PAUSE_RX 0x08
156#define NVREG_PFF_ALWAYS 0x7F0000
157#define NVREG_PFF_PROMISC 0x80
158#define NVREG_PFF_MYADDR 0x20
159#define NVREG_PFF_LOOPBACK 0x10
160
161 NvRegOffloadConfig = 0x90,
162#define NVREG_OFFLOAD_HOMEPHY 0x601
163#define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
164 NvRegReceiverControl = 0x094,
165#define NVREG_RCVCTL_START 0x01
166#define NVREG_RCVCTL_RX_PATH_EN 0x01000000
167 NvRegReceiverStatus = 0x98,
168#define NVREG_RCVSTAT_BUSY 0x01
169
170 NvRegSlotTime = 0x9c,
171#define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
172#define NVREG_SLOTTIME_10_100_FULL 0x00007f00
173#define NVREG_SLOTTIME_1000_FULL 0x0003ff00
174#define NVREG_SLOTTIME_HALF 0x0000ff00
175#define NVREG_SLOTTIME_DEFAULT 0x00007f00
176#define NVREG_SLOTTIME_MASK 0x000000ff
177
178 NvRegTxDeferral = 0xA0,
179#define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
180#define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
181#define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
182#define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
183#define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
184#define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
185 NvRegRxDeferral = 0xA4,
186#define NVREG_RX_DEFERRAL_DEFAULT 0x16
187 NvRegMacAddrA = 0xA8,
188 NvRegMacAddrB = 0xAC,
189 NvRegMulticastAddrA = 0xB0,
190#define NVREG_MCASTADDRA_FORCE 0x01
191 NvRegMulticastAddrB = 0xB4,
192 NvRegMulticastMaskA = 0xB8,
193#define NVREG_MCASTMASKA_NONE 0xffffffff
194 NvRegMulticastMaskB = 0xBC,
195#define NVREG_MCASTMASKB_NONE 0xffff
196
197 NvRegPhyInterface = 0xC0,
198#define PHY_RGMII 0x10000000
199 NvRegBackOffControl = 0xC4,
200#define NVREG_BKOFFCTRL_DEFAULT 0x70000000
201#define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
202#define NVREG_BKOFFCTRL_SELECT 24
203#define NVREG_BKOFFCTRL_GEAR 12
204
205 NvRegTxRingPhysAddr = 0x100,
206 NvRegRxRingPhysAddr = 0x104,
207 NvRegRingSizes = 0x108,
208#define NVREG_RINGSZ_TXSHIFT 0
209#define NVREG_RINGSZ_RXSHIFT 16
210 NvRegTransmitPoll = 0x10c,
211#define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
212 NvRegLinkSpeed = 0x110,
213#define NVREG_LINKSPEED_FORCE 0x10000
214#define NVREG_LINKSPEED_10 1000
215#define NVREG_LINKSPEED_100 100
216#define NVREG_LINKSPEED_1000 50
217#define NVREG_LINKSPEED_MASK (0xFFF)
218 NvRegUnknownSetupReg5 = 0x130,
219#define NVREG_UNKSETUP5_BIT31 (1<<31)
220 NvRegTxWatermark = 0x13c,
221#define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
222#define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
223#define NVREG_TX_WM_DESC2_3_1000 0xfe08000
224 NvRegTxRxControl = 0x144,
225#define NVREG_TXRXCTL_KICK 0x0001
226#define NVREG_TXRXCTL_BIT1 0x0002
227#define NVREG_TXRXCTL_BIT2 0x0004
228#define NVREG_TXRXCTL_IDLE 0x0008
229#define NVREG_TXRXCTL_RESET 0x0010
230#define NVREG_TXRXCTL_RXCHECK 0x0400
231#define NVREG_TXRXCTL_DESC_1 0
232#define NVREG_TXRXCTL_DESC_2 0x002100
233#define NVREG_TXRXCTL_DESC_3 0xc02200
234#define NVREG_TXRXCTL_VLANSTRIP 0x00040
235#define NVREG_TXRXCTL_VLANINS 0x00080
236 NvRegTxRingPhysAddrHigh = 0x148,
237 NvRegRxRingPhysAddrHigh = 0x14C,
238 NvRegTxPauseFrame = 0x170,
239#define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
240#define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
241#define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
242#define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
243 NvRegTxPauseFrameLimit = 0x174,
244#define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
245 NvRegMIIStatus = 0x180,
246#define NVREG_MIISTAT_ERROR 0x0001
247#define NVREG_MIISTAT_LINKCHANGE 0x0008
248#define NVREG_MIISTAT_MASK_RW 0x0007
249#define NVREG_MIISTAT_MASK_ALL 0x000f
250 NvRegMIIMask = 0x184,
251#define NVREG_MII_LINKCHANGE 0x0008
252
253 NvRegAdapterControl = 0x188,
254#define NVREG_ADAPTCTL_START 0x02
255#define NVREG_ADAPTCTL_LINKUP 0x04
256#define NVREG_ADAPTCTL_PHYVALID 0x40000
257#define NVREG_ADAPTCTL_RUNNING 0x100000
258#define NVREG_ADAPTCTL_PHYSHIFT 24
259 NvRegMIISpeed = 0x18c,
260#define NVREG_MIISPEED_BIT8 (1<<8)
261#define NVREG_MIIDELAY 5
262 NvRegMIIControl = 0x190,
263#define NVREG_MIICTL_INUSE 0x08000
264#define NVREG_MIICTL_WRITE 0x00400
265#define NVREG_MIICTL_ADDRSHIFT 5
266 NvRegMIIData = 0x194,
267 NvRegTxUnicast = 0x1a0,
268 NvRegTxMulticast = 0x1a4,
269 NvRegTxBroadcast = 0x1a8,
270 NvRegWakeUpFlags = 0x200,
271#define NVREG_WAKEUPFLAGS_VAL 0x7770
272#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
273#define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
274#define NVREG_WAKEUPFLAGS_D3SHIFT 12
275#define NVREG_WAKEUPFLAGS_D2SHIFT 8
276#define NVREG_WAKEUPFLAGS_D1SHIFT 4
277#define NVREG_WAKEUPFLAGS_D0SHIFT 0
278#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
279#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
280#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
281#define NVREG_WAKEUPFLAGS_ENABLE 0x1111
282
283 NvRegMgmtUnitGetVersion = 0x204,
284#define NVREG_MGMTUNITGETVERSION 0x01
285 NvRegMgmtUnitVersion = 0x208,
286#define NVREG_MGMTUNITVERSION 0x08
287 NvRegPowerCap = 0x268,
288#define NVREG_POWERCAP_D3SUPP (1<<30)
289#define NVREG_POWERCAP_D2SUPP (1<<26)
290#define NVREG_POWERCAP_D1SUPP (1<<25)
291 NvRegPowerState = 0x26c,
292#define NVREG_POWERSTATE_POWEREDUP 0x8000
293#define NVREG_POWERSTATE_VALID 0x0100
294#define NVREG_POWERSTATE_MASK 0x0003
295#define NVREG_POWERSTATE_D0 0x0000
296#define NVREG_POWERSTATE_D1 0x0001
297#define NVREG_POWERSTATE_D2 0x0002
298#define NVREG_POWERSTATE_D3 0x0003
299 NvRegMgmtUnitControl = 0x278,
300#define NVREG_MGMTUNITCONTROL_INUSE 0x20000
301 NvRegTxCnt = 0x280,
302 NvRegTxZeroReXmt = 0x284,
303 NvRegTxOneReXmt = 0x288,
304 NvRegTxManyReXmt = 0x28c,
305 NvRegTxLateCol = 0x290,
306 NvRegTxUnderflow = 0x294,
307 NvRegTxLossCarrier = 0x298,
308 NvRegTxExcessDef = 0x29c,
309 NvRegTxRetryErr = 0x2a0,
310 NvRegRxFrameErr = 0x2a4,
311 NvRegRxExtraByte = 0x2a8,
312 NvRegRxLateCol = 0x2ac,
313 NvRegRxRunt = 0x2b0,
314 NvRegRxFrameTooLong = 0x2b4,
315 NvRegRxOverflow = 0x2b8,
316 NvRegRxFCSErr = 0x2bc,
317 NvRegRxFrameAlignErr = 0x2c0,
318 NvRegRxLenErr = 0x2c4,
319 NvRegRxUnicast = 0x2c8,
320 NvRegRxMulticast = 0x2cc,
321 NvRegRxBroadcast = 0x2d0,
322 NvRegTxDef = 0x2d4,
323 NvRegTxFrame = 0x2d8,
324 NvRegRxCnt = 0x2dc,
325 NvRegTxPause = 0x2e0,
326 NvRegRxPause = 0x2e4,
327 NvRegRxDropFrame = 0x2e8,
328 NvRegVlanControl = 0x300,
329#define NVREG_VLANCONTROL_ENABLE 0x2000
330 NvRegMSIXMap0 = 0x3e0,
331 NvRegMSIXMap1 = 0x3e4,
332 NvRegMSIXIrqStatus = 0x3f0,
333
334 NvRegPowerState2 = 0x600,
335#define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
336#define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
337#define NVREG_POWERSTATE2_PHY_RESET 0x0004
338#define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
339};
340
341/* Big endian: should work, but is untested */
342struct ring_desc {
343 __le32 buf;
344 __le32 flaglen;
345};
346
347struct ring_desc_ex {
348 __le32 bufhigh;
349 __le32 buflow;
350 __le32 txvlan;
351 __le32 flaglen;
352};
353
354union ring_type {
355 struct ring_desc *orig;
356 struct ring_desc_ex *ex;
357};
358
359#define FLAG_MASK_V1 0xffff0000
360#define FLAG_MASK_V2 0xffffc000
361#define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
362#define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
363
364#define NV_TX_LASTPACKET (1<<16)
365#define NV_TX_RETRYERROR (1<<19)
366#define NV_TX_RETRYCOUNT_MASK (0xF<<20)
367#define NV_TX_FORCED_INTERRUPT (1<<24)
368#define NV_TX_DEFERRED (1<<26)
369#define NV_TX_CARRIERLOST (1<<27)
370#define NV_TX_LATECOLLISION (1<<28)
371#define NV_TX_UNDERFLOW (1<<29)
372#define NV_TX_ERROR (1<<30)
373#define NV_TX_VALID (1<<31)
374
375#define NV_TX2_LASTPACKET (1<<29)
376#define NV_TX2_RETRYERROR (1<<18)
377#define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
378#define NV_TX2_FORCED_INTERRUPT (1<<30)
379#define NV_TX2_DEFERRED (1<<25)
380#define NV_TX2_CARRIERLOST (1<<26)
381#define NV_TX2_LATECOLLISION (1<<27)
382#define NV_TX2_UNDERFLOW (1<<28)
383/* error and valid are the same for both */
384#define NV_TX2_ERROR (1<<30)
385#define NV_TX2_VALID (1<<31)
386#define NV_TX2_TSO (1<<28)
387#define NV_TX2_TSO_SHIFT 14
388#define NV_TX2_TSO_MAX_SHIFT 14
389#define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
390#define NV_TX2_CHECKSUM_L3 (1<<27)
391#define NV_TX2_CHECKSUM_L4 (1<<26)
392
393#define NV_TX3_VLAN_TAG_PRESENT (1<<18)
394
395#define NV_RX_DESCRIPTORVALID (1<<16)
396#define NV_RX_MISSEDFRAME (1<<17)
397#define NV_RX_SUBTRACT1 (1<<18)
398#define NV_RX_ERROR1 (1<<23)
399#define NV_RX_ERROR2 (1<<24)
400#define NV_RX_ERROR3 (1<<25)
401#define NV_RX_ERROR4 (1<<26)
402#define NV_RX_CRCERR (1<<27)
403#define NV_RX_OVERFLOW (1<<28)
404#define NV_RX_FRAMINGERR (1<<29)
405#define NV_RX_ERROR (1<<30)
406#define NV_RX_AVAIL (1<<31)
407#define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
408
409#define NV_RX2_CHECKSUMMASK (0x1C000000)
410#define NV_RX2_CHECKSUM_IP (0x10000000)
411#define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
412#define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
413#define NV_RX2_DESCRIPTORVALID (1<<29)
414#define NV_RX2_SUBTRACT1 (1<<25)
415#define NV_RX2_ERROR1 (1<<18)
416#define NV_RX2_ERROR2 (1<<19)
417#define NV_RX2_ERROR3 (1<<20)
418#define NV_RX2_ERROR4 (1<<21)
419#define NV_RX2_CRCERR (1<<22)
420#define NV_RX2_OVERFLOW (1<<23)
421#define NV_RX2_FRAMINGERR (1<<24)
422/* error and avail are the same for both */
423#define NV_RX2_ERROR (1<<30)
424#define NV_RX2_AVAIL (1<<31)
425#define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
426
427#define NV_RX3_VLAN_TAG_PRESENT (1<<16)
428#define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
429
430/* Miscellaneous hardware related defines: */
431#define NV_PCI_REGSZ_VER1 0x270
432#define NV_PCI_REGSZ_VER2 0x2d4
433#define NV_PCI_REGSZ_VER3 0x604
434#define NV_PCI_REGSZ_MAX 0x604
435
436/* various timeout delays: all in usec */
437#define NV_TXRX_RESET_DELAY 4
438#define NV_TXSTOP_DELAY1 10
439#define NV_TXSTOP_DELAY1MAX 500000
440#define NV_TXSTOP_DELAY2 100
441#define NV_RXSTOP_DELAY1 10
442#define NV_RXSTOP_DELAY1MAX 500000
443#define NV_RXSTOP_DELAY2 100
444#define NV_SETUP5_DELAY 5
445#define NV_SETUP5_DELAYMAX 50000
446#define NV_POWERUP_DELAY 5
447#define NV_POWERUP_DELAYMAX 5000
448#define NV_MIIBUSY_DELAY 50
449#define NV_MIIPHY_DELAY 10
450#define NV_MIIPHY_DELAYMAX 10000
451#define NV_MAC_RESET_DELAY 64
452
453#define NV_WAKEUPPATTERNS 5
454#define NV_WAKEUPMASKENTRIES 4
455
456/* General driver defaults */
457#define NV_WATCHDOG_TIMEO (5*HZ)
458
459#define RX_RING_DEFAULT 512
460#define TX_RING_DEFAULT 256
461#define RX_RING_MIN 128
462#define TX_RING_MIN 64
463#define RING_MAX_DESC_VER_1 1024
464#define RING_MAX_DESC_VER_2_3 16384
465
466/* rx/tx mac addr + type + vlan + align + slack*/
467#define NV_RX_HEADERS (64)
468/* even more slack. */
469#define NV_RX_ALLOC_PAD (64)
470
471/* maximum mtu size */
472#define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
473#define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
474
475#define OOM_REFILL (1+HZ/20)
476#define POLL_WAIT (1+HZ/100)
477#define LINK_TIMEOUT (3*HZ)
478#define STATS_INTERVAL (10*HZ)
479
480/*
481 * desc_ver values:
482 * The nic supports three different descriptor types:
483 * - DESC_VER_1: Original
484 * - DESC_VER_2: support for jumbo frames.
485 * - DESC_VER_3: 64-bit format.
486 */
487#define DESC_VER_1 1
488#define DESC_VER_2 2
489#define DESC_VER_3 3
490
491/* PHY defines */
492#define PHY_OUI_MARVELL 0x5043
493#define PHY_OUI_CICADA 0x03f1
494#define PHY_OUI_VITESSE 0x01c1
495#define PHY_OUI_REALTEK 0x0732
496#define PHY_OUI_REALTEK2 0x0020
497#define PHYID1_OUI_MASK 0x03ff
498#define PHYID1_OUI_SHFT 6
499#define PHYID2_OUI_MASK 0xfc00
500#define PHYID2_OUI_SHFT 10
501#define PHYID2_MODEL_MASK 0x03f0
502#define PHY_MODEL_REALTEK_8211 0x0110
503#define PHY_REV_MASK 0x0001
504#define PHY_REV_REALTEK_8211B 0x0000
505#define PHY_REV_REALTEK_8211C 0x0001
506#define PHY_MODEL_REALTEK_8201 0x0200
507#define PHY_MODEL_MARVELL_E3016 0x0220
508#define PHY_MARVELL_E3016_INITMASK 0x0300
509#define PHY_CICADA_INIT1 0x0f000
510#define PHY_CICADA_INIT2 0x0e00
511#define PHY_CICADA_INIT3 0x01000
512#define PHY_CICADA_INIT4 0x0200
513#define PHY_CICADA_INIT5 0x0004
514#define PHY_CICADA_INIT6 0x02000
515#define PHY_VITESSE_INIT_REG1 0x1f
516#define PHY_VITESSE_INIT_REG2 0x10
517#define PHY_VITESSE_INIT_REG3 0x11
518#define PHY_VITESSE_INIT_REG4 0x12
519#define PHY_VITESSE_INIT_MSK1 0xc
520#define PHY_VITESSE_INIT_MSK2 0x0180
521#define PHY_VITESSE_INIT1 0x52b5
522#define PHY_VITESSE_INIT2 0xaf8a
523#define PHY_VITESSE_INIT3 0x8
524#define PHY_VITESSE_INIT4 0x8f8a
525#define PHY_VITESSE_INIT5 0xaf86
526#define PHY_VITESSE_INIT6 0x8f86
527#define PHY_VITESSE_INIT7 0xaf82
528#define PHY_VITESSE_INIT8 0x0100
529#define PHY_VITESSE_INIT9 0x8f82
530#define PHY_VITESSE_INIT10 0x0
531#define PHY_REALTEK_INIT_REG1 0x1f
532#define PHY_REALTEK_INIT_REG2 0x19
533#define PHY_REALTEK_INIT_REG3 0x13
534#define PHY_REALTEK_INIT_REG4 0x14
535#define PHY_REALTEK_INIT_REG5 0x18
536#define PHY_REALTEK_INIT_REG6 0x11
537#define PHY_REALTEK_INIT_REG7 0x01
538#define PHY_REALTEK_INIT1 0x0000
539#define PHY_REALTEK_INIT2 0x8e00
540#define PHY_REALTEK_INIT3 0x0001
541#define PHY_REALTEK_INIT4 0xad17
542#define PHY_REALTEK_INIT5 0xfb54
543#define PHY_REALTEK_INIT6 0xf5c7
544#define PHY_REALTEK_INIT7 0x1000
545#define PHY_REALTEK_INIT8 0x0003
546#define PHY_REALTEK_INIT9 0x0008
547#define PHY_REALTEK_INIT10 0x0005
548#define PHY_REALTEK_INIT11 0x0200
549#define PHY_REALTEK_INIT_MSK1 0x0003
550
551#define PHY_GIGABIT 0x0100
552
553#define PHY_TIMEOUT 0x1
554#define PHY_ERROR 0x2
555
556#define PHY_100 0x1
557#define PHY_1000 0x2
558#define PHY_HALF 0x100
559
560#define NV_PAUSEFRAME_RX_CAPABLE 0x0001
561#define NV_PAUSEFRAME_TX_CAPABLE 0x0002
562#define NV_PAUSEFRAME_RX_ENABLE 0x0004
563#define NV_PAUSEFRAME_TX_ENABLE 0x0008
564#define NV_PAUSEFRAME_RX_REQ 0x0010
565#define NV_PAUSEFRAME_TX_REQ 0x0020
566#define NV_PAUSEFRAME_AUTONEG 0x0040
567
568/* MSI/MSI-X defines */
569#define NV_MSI_X_MAX_VECTORS 8
570#define NV_MSI_X_VECTORS_MASK 0x000f
571#define NV_MSI_CAPABLE 0x0010
572#define NV_MSI_X_CAPABLE 0x0020
573#define NV_MSI_ENABLED 0x0040
574#define NV_MSI_X_ENABLED 0x0080
575
576#define NV_MSI_X_VECTOR_ALL 0x0
577#define NV_MSI_X_VECTOR_RX 0x0
578#define NV_MSI_X_VECTOR_TX 0x1
579#define NV_MSI_X_VECTOR_OTHER 0x2
580
581#define NV_MSI_PRIV_OFFSET 0x68
582#define NV_MSI_PRIV_VALUE 0xffffffff
583
584#define NV_RESTART_TX 0x1
585#define NV_RESTART_RX 0x2
586
587#define NV_TX_LIMIT_COUNT 16
588
589#define NV_DYNAMIC_THRESHOLD 4
590#define NV_DYNAMIC_MAX_QUIET_COUNT 2048
591
592/* statistics */
593struct nv_ethtool_str {
594 char name[ETH_GSTRING_LEN];
595};
596
597static const struct nv_ethtool_str nv_estats_str[] = {
598 { "tx_bytes" }, /* includes Ethernet FCS CRC */
599 { "tx_zero_rexmt" },
600 { "tx_one_rexmt" },
601 { "tx_many_rexmt" },
602 { "tx_late_collision" },
603 { "tx_fifo_errors" },
604 { "tx_carrier_errors" },
605 { "tx_excess_deferral" },
606 { "tx_retry_error" },
607 { "rx_frame_error" },
608 { "rx_extra_byte" },
609 { "rx_late_collision" },
610 { "rx_runt" },
611 { "rx_frame_too_long" },
612 { "rx_over_errors" },
613 { "rx_crc_errors" },
614 { "rx_frame_align_error" },
615 { "rx_length_error" },
616 { "rx_unicast" },
617 { "rx_multicast" },
618 { "rx_broadcast" },
619 { "rx_packets" },
620 { "rx_errors_total" },
621 { "tx_errors_total" },
622
623 /* version 2 stats */
624 { "tx_deferral" },
625 { "tx_packets" },
626 { "rx_bytes" }, /* includes Ethernet FCS CRC */
627 { "tx_pause" },
628 { "rx_pause" },
629 { "rx_drop_frame" },
630
631 /* version 3 stats */
632 { "tx_unicast" },
633 { "tx_multicast" },
634 { "tx_broadcast" }
635};
636
637struct nv_ethtool_stats {
638 u64 tx_bytes; /* should be ifconfig->tx_bytes + 4*tx_packets */
639 u64 tx_zero_rexmt;
640 u64 tx_one_rexmt;
641 u64 tx_many_rexmt;
642 u64 tx_late_collision;
643 u64 tx_fifo_errors;
644 u64 tx_carrier_errors;
645 u64 tx_excess_deferral;
646 u64 tx_retry_error;
647 u64 rx_frame_error;
648 u64 rx_extra_byte;
649 u64 rx_late_collision;
650 u64 rx_runt;
651 u64 rx_frame_too_long;
652 u64 rx_over_errors;
653 u64 rx_crc_errors;
654 u64 rx_frame_align_error;
655 u64 rx_length_error;
656 u64 rx_unicast;
657 u64 rx_multicast;
658 u64 rx_broadcast;
659 u64 rx_packets; /* should be ifconfig->rx_packets */
660 u64 rx_errors_total;
661 u64 tx_errors_total;
662
663 /* version 2 stats */
664 u64 tx_deferral;
665 u64 tx_packets; /* should be ifconfig->tx_packets */
666 u64 rx_bytes; /* should be ifconfig->rx_bytes + 4*rx_packets */
667 u64 tx_pause;
668 u64 rx_pause;
669 u64 rx_drop_frame;
670
671 /* version 3 stats */
672 u64 tx_unicast;
673 u64 tx_multicast;
674 u64 tx_broadcast;
675};
676
677#define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
678#define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
679#define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
680
681/* diagnostics */
682#define NV_TEST_COUNT_BASE 3
683#define NV_TEST_COUNT_EXTENDED 4
684
685static const struct nv_ethtool_str nv_etests_str[] = {
686 { "link (online/offline)" },
687 { "register (offline) " },
688 { "interrupt (offline) " },
689 { "loopback (offline) " }
690};
691
692struct register_test {
693 __u32 reg;
694 __u32 mask;
695};
696
697static const struct register_test nv_registers_test[] = {
698 { NvRegUnknownSetupReg6, 0x01 },
699 { NvRegMisc1, 0x03c },
700 { NvRegOffloadConfig, 0x03ff },
701 { NvRegMulticastAddrA, 0xffffffff },
702 { NvRegTxWatermark, 0x0ff },
703 { NvRegWakeUpFlags, 0x07777 },
704 { 0, 0 }
705};
706
707struct nv_skb_map {
708 struct sk_buff *skb;
709 dma_addr_t dma;
710 unsigned int dma_len:31;
711 unsigned int dma_single:1;
712 struct ring_desc_ex *first_tx_desc;
713 struct nv_skb_map *next_tx_ctx;
714};
715
716struct nv_txrx_stats {
717 u64 stat_rx_packets;
718 u64 stat_rx_bytes; /* not always available in HW */
719 u64 stat_rx_missed_errors;
720 u64 stat_rx_dropped;
721 u64 stat_tx_packets; /* not always available in HW */
722 u64 stat_tx_bytes;
723 u64 stat_tx_dropped;
724};
725
726#define nv_txrx_stats_inc(member) \
727 __this_cpu_inc(np->txrx_stats->member)
728#define nv_txrx_stats_add(member, count) \
729 __this_cpu_add(np->txrx_stats->member, (count))
730
731/*
732 * SMP locking:
733 * All hardware access under netdev_priv(dev)->lock, except the performance
734 * critical parts:
735 * - rx is (pseudo-) lockless: it relies on the single-threading provided
736 * by the arch code for interrupts.
737 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
738 * needs netdev_priv(dev)->lock :-(
739 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
740 *
741 * Hardware stats updates are protected by hwstats_lock:
742 * - updated by nv_do_stats_poll (timer). This is meant to avoid
743 * integer wraparound in the NIC stats registers, at low frequency
744 * (0.1 Hz)
745 * - updated by nv_get_ethtool_stats + nv_get_stats64
746 *
747 * Software stats are accessed only through 64b synchronization points
748 * and are not subject to other synchronization techniques (single
749 * update thread on the TX or RX paths).
750 */
751
752/* in dev: base, irq */
753struct fe_priv {
754 spinlock_t lock;
755
756 struct net_device *dev;
757 struct napi_struct napi;
758
759 /* hardware stats are updated in syscall and timer */
760 spinlock_t hwstats_lock;
761 struct nv_ethtool_stats estats;
762
763 int in_shutdown;
764 u32 linkspeed;
765 int duplex;
766 int autoneg;
767 int fixed_mode;
768 int phyaddr;
769 int wolenabled;
770 unsigned int phy_oui;
771 unsigned int phy_model;
772 unsigned int phy_rev;
773 u16 gigabit;
774 int intr_test;
775 int recover_error;
776 int quiet_count;
777
778 /* General data: RO fields */
779 dma_addr_t ring_addr;
780 struct pci_dev *pci_dev;
781 u32 orig_mac[2];
782 u32 events;
783 u32 irqmask;
784 u32 desc_ver;
785 u32 txrxctl_bits;
786 u32 vlanctl_bits;
787 u32 driver_data;
788 u32 device_id;
789 u32 register_size;
790 u32 mac_in_use;
791 int mgmt_version;
792 int mgmt_sema;
793
794 void __iomem *base;
795
796 /* rx specific fields.
797 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
798 */
799 union ring_type get_rx, put_rx, last_rx;
800 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
801 struct nv_skb_map *last_rx_ctx;
802 struct nv_skb_map *rx_skb;
803
804 union ring_type rx_ring;
805 unsigned int rx_buf_sz;
806 unsigned int pkt_limit;
807 struct timer_list oom_kick;
808 struct timer_list nic_poll;
809 struct timer_list stats_poll;
810 u32 nic_poll_irq;
811 int rx_ring_size;
812
813 /* RX software stats */
814 struct u64_stats_sync swstats_rx_syncp;
815 struct nv_txrx_stats __percpu *txrx_stats;
816
817 /* media detection workaround.
818 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
819 */
820 int need_linktimer;
821 unsigned long link_timeout;
822 /*
823 * tx specific fields.
824 */
825 union ring_type get_tx, put_tx, last_tx;
826 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
827 struct nv_skb_map *last_tx_ctx;
828 struct nv_skb_map *tx_skb;
829
830 union ring_type tx_ring;
831 u32 tx_flags;
832 int tx_ring_size;
833 int tx_limit;
834 u32 tx_pkts_in_progress;
835 struct nv_skb_map *tx_change_owner;
836 struct nv_skb_map *tx_end_flip;
837 int tx_stop;
838
839 /* TX software stats */
840 struct u64_stats_sync swstats_tx_syncp;
841
842 /* msi/msi-x fields */
843 u32 msi_flags;
844 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
845
846 /* flow control */
847 u32 pause_flags;
848
849 /* power saved state */
850 u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
851
852 /* for different msi-x irq type */
853 char name_rx[IFNAMSIZ + 3]; /* -rx */
854 char name_tx[IFNAMSIZ + 3]; /* -tx */
855 char name_other[IFNAMSIZ + 6]; /* -other */
856};
857
858/*
859 * Maximum number of loops until we assume that a bit in the irq mask
860 * is stuck. Overridable with module param.
861 */
862static int max_interrupt_work = 4;
863
864/*
865 * Optimization can be either throuput mode or cpu mode
866 *
867 * Throughput Mode: Every tx and rx packet will generate an interrupt.
868 * CPU Mode: Interrupts are controlled by a timer.
869 */
870enum {
871 NV_OPTIMIZATION_MODE_THROUGHPUT,
872 NV_OPTIMIZATION_MODE_CPU,
873 NV_OPTIMIZATION_MODE_DYNAMIC
874};
875static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
876
877/*
878 * Poll interval for timer irq
879 *
880 * This interval determines how frequent an interrupt is generated.
881 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
882 * Min = 0, and Max = 65535
883 */
884static int poll_interval = -1;
885
886/*
887 * MSI interrupts
888 */
889enum {
890 NV_MSI_INT_DISABLED,
891 NV_MSI_INT_ENABLED
892};
893static int msi = NV_MSI_INT_ENABLED;
894
895/*
896 * MSIX interrupts
897 */
898enum {
899 NV_MSIX_INT_DISABLED,
900 NV_MSIX_INT_ENABLED
901};
902static int msix = NV_MSIX_INT_ENABLED;
903
904/*
905 * DMA 64bit
906 */
907enum {
908 NV_DMA_64BIT_DISABLED,
909 NV_DMA_64BIT_ENABLED
910};
911static int dma_64bit = NV_DMA_64BIT_ENABLED;
912
913/*
914 * Debug output control for tx_timeout
915 */
916static bool debug_tx_timeout = false;
917
918/*
919 * Crossover Detection
920 * Realtek 8201 phy + some OEM boards do not work properly.
921 */
922enum {
923 NV_CROSSOVER_DETECTION_DISABLED,
924 NV_CROSSOVER_DETECTION_ENABLED
925};
926static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
927
928/*
929 * Power down phy when interface is down (persists through reboot;
930 * older Linux and other OSes may not power it up again)
931 */
932static int phy_power_down;
933
934static inline struct fe_priv *get_nvpriv(struct net_device *dev)
935{
936 return netdev_priv(dev);
937}
938
939static inline u8 __iomem *get_hwbase(struct net_device *dev)
940{
941 return ((struct fe_priv *)netdev_priv(dev))->base;
942}
943
944static inline void pci_push(u8 __iomem *base)
945{
946 /* force out pending posted writes */
947 readl(base);
948}
949
950static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
951{
952 return le32_to_cpu(prd->flaglen)
953 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
954}
955
956static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
957{
958 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
959}
960
961static bool nv_optimized(struct fe_priv *np)
962{
963 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
964 return false;
965 return true;
966}
967
968static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
969 int delay, int delaymax)
970{
971 u8 __iomem *base = get_hwbase(dev);
972
973 pci_push(base);
974 do {
975 udelay(delay);
976 delaymax -= delay;
977 if (delaymax < 0)
978 return 1;
979 } while ((readl(base + offset) & mask) != target);
980 return 0;
981}
982
983#define NV_SETUP_RX_RING 0x01
984#define NV_SETUP_TX_RING 0x02
985
986static inline u32 dma_low(dma_addr_t addr)
987{
988 return addr;
989}
990
991static inline u32 dma_high(dma_addr_t addr)
992{
993 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
994}
995
996static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
997{
998 struct fe_priv *np = get_nvpriv(dev);
999 u8 __iomem *base = get_hwbase(dev);
1000
1001 if (!nv_optimized(np)) {
1002 if (rxtx_flags & NV_SETUP_RX_RING)
1003 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1004 if (rxtx_flags & NV_SETUP_TX_RING)
1005 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1006 } else {
1007 if (rxtx_flags & NV_SETUP_RX_RING) {
1008 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1009 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
1010 }
1011 if (rxtx_flags & NV_SETUP_TX_RING) {
1012 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1013 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
1014 }
1015 }
1016}
1017
1018static void free_rings(struct net_device *dev)
1019{
1020 struct fe_priv *np = get_nvpriv(dev);
1021
1022 if (!nv_optimized(np)) {
1023 if (np->rx_ring.orig)
1024 dma_free_coherent(&np->pci_dev->dev,
1025 sizeof(struct ring_desc) *
1026 (np->rx_ring_size +
1027 np->tx_ring_size),
1028 np->rx_ring.orig, np->ring_addr);
1029 } else {
1030 if (np->rx_ring.ex)
1031 dma_free_coherent(&np->pci_dev->dev,
1032 sizeof(struct ring_desc_ex) *
1033 (np->rx_ring_size +
1034 np->tx_ring_size),
1035 np->rx_ring.ex, np->ring_addr);
1036 }
1037 kfree(np->rx_skb);
1038 kfree(np->tx_skb);
1039}
1040
1041static int using_multi_irqs(struct net_device *dev)
1042{
1043 struct fe_priv *np = get_nvpriv(dev);
1044
1045 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1046 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1047 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1048 return 0;
1049 else
1050 return 1;
1051}
1052
1053static void nv_txrx_gate(struct net_device *dev, bool gate)
1054{
1055 struct fe_priv *np = get_nvpriv(dev);
1056 u8 __iomem *base = get_hwbase(dev);
1057 u32 powerstate;
1058
1059 if (!np->mac_in_use &&
1060 (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1061 powerstate = readl(base + NvRegPowerState2);
1062 if (gate)
1063 powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1064 else
1065 powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1066 writel(powerstate, base + NvRegPowerState2);
1067 }
1068}
1069
1070static void nv_enable_irq(struct net_device *dev)
1071{
1072 struct fe_priv *np = get_nvpriv(dev);
1073
1074 if (!using_multi_irqs(dev)) {
1075 if (np->msi_flags & NV_MSI_X_ENABLED)
1076 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1077 else
1078 enable_irq(np->pci_dev->irq);
1079 } else {
1080 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1081 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1082 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1083 }
1084}
1085
1086static void nv_disable_irq(struct net_device *dev)
1087{
1088 struct fe_priv *np = get_nvpriv(dev);
1089
1090 if (!using_multi_irqs(dev)) {
1091 if (np->msi_flags & NV_MSI_X_ENABLED)
1092 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1093 else
1094 disable_irq(np->pci_dev->irq);
1095 } else {
1096 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1097 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1098 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1099 }
1100}
1101
1102/* In MSIX mode, a write to irqmask behaves as XOR */
1103static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1104{
1105 u8 __iomem *base = get_hwbase(dev);
1106
1107 writel(mask, base + NvRegIrqMask);
1108}
1109
1110static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1111{
1112 struct fe_priv *np = get_nvpriv(dev);
1113 u8 __iomem *base = get_hwbase(dev);
1114
1115 if (np->msi_flags & NV_MSI_X_ENABLED) {
1116 writel(mask, base + NvRegIrqMask);
1117 } else {
1118 if (np->msi_flags & NV_MSI_ENABLED)
1119 writel(0, base + NvRegMSIIrqMask);
1120 writel(0, base + NvRegIrqMask);
1121 }
1122}
1123
1124static void nv_napi_enable(struct net_device *dev)
1125{
1126 struct fe_priv *np = get_nvpriv(dev);
1127
1128 napi_enable(&np->napi);
1129}
1130
1131static void nv_napi_disable(struct net_device *dev)
1132{
1133 struct fe_priv *np = get_nvpriv(dev);
1134
1135 napi_disable(&np->napi);
1136}
1137
1138#define MII_READ (-1)
1139/* mii_rw: read/write a register on the PHY.
1140 *
1141 * Caller must guarantee serialization
1142 */
1143static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1144{
1145 u8 __iomem *base = get_hwbase(dev);
1146 u32 reg;
1147 int retval;
1148
1149 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1150
1151 reg = readl(base + NvRegMIIControl);
1152 if (reg & NVREG_MIICTL_INUSE) {
1153 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1154 udelay(NV_MIIBUSY_DELAY);
1155 }
1156
1157 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1158 if (value != MII_READ) {
1159 writel(value, base + NvRegMIIData);
1160 reg |= NVREG_MIICTL_WRITE;
1161 }
1162 writel(reg, base + NvRegMIIControl);
1163
1164 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1165 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
1166 retval = -1;
1167 } else if (value != MII_READ) {
1168 /* it was a write operation - fewer failures are detectable */
1169 retval = 0;
1170 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1171 retval = -1;
1172 } else {
1173 retval = readl(base + NvRegMIIData);
1174 }
1175
1176 return retval;
1177}
1178
1179static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1180{
1181 struct fe_priv *np = netdev_priv(dev);
1182 u32 miicontrol;
1183 unsigned int tries = 0;
1184
1185 miicontrol = BMCR_RESET | bmcr_setup;
1186 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
1187 return -1;
1188
1189 /* wait for 500ms */
1190 msleep(500);
1191
1192 /* must wait till reset is deasserted */
1193 while (miicontrol & BMCR_RESET) {
1194 usleep_range(10000, 20000);
1195 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1196 /* FIXME: 100 tries seem excessive */
1197 if (tries++ > 100)
1198 return -1;
1199 }
1200 return 0;
1201}
1202
1203static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1204{
1205 static const struct {
1206 int reg;
1207 int init;
1208 } ri[] = {
1209 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1210 { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1211 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1212 { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1213 { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1214 { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1215 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1216 };
1217 int i;
1218
1219 for (i = 0; i < ARRAY_SIZE(ri); i++) {
1220 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
1221 return PHY_ERROR;
1222 }
1223
1224 return 0;
1225}
1226
1227static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1228{
1229 u32 reg;
1230 u8 __iomem *base = get_hwbase(dev);
1231 u32 powerstate = readl(base + NvRegPowerState2);
1232
1233 /* need to perform hw phy reset */
1234 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1235 writel(powerstate, base + NvRegPowerState2);
1236 msleep(25);
1237
1238 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1239 writel(powerstate, base + NvRegPowerState2);
1240 msleep(25);
1241
1242 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1243 reg |= PHY_REALTEK_INIT9;
1244 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1245 return PHY_ERROR;
1246 if (mii_rw(dev, np->phyaddr,
1247 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1248 return PHY_ERROR;
1249 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1250 if (!(reg & PHY_REALTEK_INIT11)) {
1251 reg |= PHY_REALTEK_INIT11;
1252 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1253 return PHY_ERROR;
1254 }
1255 if (mii_rw(dev, np->phyaddr,
1256 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1257 return PHY_ERROR;
1258
1259 return 0;
1260}
1261
1262static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1263{
1264 u32 phy_reserved;
1265
1266 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1267 phy_reserved = mii_rw(dev, np->phyaddr,
1268 PHY_REALTEK_INIT_REG6, MII_READ);
1269 phy_reserved |= PHY_REALTEK_INIT7;
1270 if (mii_rw(dev, np->phyaddr,
1271 PHY_REALTEK_INIT_REG6, phy_reserved))
1272 return PHY_ERROR;
1273 }
1274
1275 return 0;
1276}
1277
1278static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1279{
1280 u32 phy_reserved;
1281
1282 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1283 if (mii_rw(dev, np->phyaddr,
1284 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1285 return PHY_ERROR;
1286 phy_reserved = mii_rw(dev, np->phyaddr,
1287 PHY_REALTEK_INIT_REG2, MII_READ);
1288 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1289 phy_reserved |= PHY_REALTEK_INIT3;
1290 if (mii_rw(dev, np->phyaddr,
1291 PHY_REALTEK_INIT_REG2, phy_reserved))
1292 return PHY_ERROR;
1293 if (mii_rw(dev, np->phyaddr,
1294 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1295 return PHY_ERROR;
1296 }
1297
1298 return 0;
1299}
1300
1301static int init_cicada(struct net_device *dev, struct fe_priv *np,
1302 u32 phyinterface)
1303{
1304 u32 phy_reserved;
1305
1306 if (phyinterface & PHY_RGMII) {
1307 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1308 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1309 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1310 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1311 return PHY_ERROR;
1312 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1313 phy_reserved |= PHY_CICADA_INIT5;
1314 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1315 return PHY_ERROR;
1316 }
1317 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1318 phy_reserved |= PHY_CICADA_INIT6;
1319 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1320 return PHY_ERROR;
1321
1322 return 0;
1323}
1324
1325static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1326{
1327 u32 phy_reserved;
1328
1329 if (mii_rw(dev, np->phyaddr,
1330 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1331 return PHY_ERROR;
1332 if (mii_rw(dev, np->phyaddr,
1333 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1334 return PHY_ERROR;
1335 phy_reserved = mii_rw(dev, np->phyaddr,
1336 PHY_VITESSE_INIT_REG4, MII_READ);
1337 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1338 return PHY_ERROR;
1339 phy_reserved = mii_rw(dev, np->phyaddr,
1340 PHY_VITESSE_INIT_REG3, MII_READ);
1341 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1342 phy_reserved |= PHY_VITESSE_INIT3;
1343 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1344 return PHY_ERROR;
1345 if (mii_rw(dev, np->phyaddr,
1346 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1347 return PHY_ERROR;
1348 if (mii_rw(dev, np->phyaddr,
1349 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1350 return PHY_ERROR;
1351 phy_reserved = mii_rw(dev, np->phyaddr,
1352 PHY_VITESSE_INIT_REG4, MII_READ);
1353 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1354 phy_reserved |= PHY_VITESSE_INIT3;
1355 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1356 return PHY_ERROR;
1357 phy_reserved = mii_rw(dev, np->phyaddr,
1358 PHY_VITESSE_INIT_REG3, MII_READ);
1359 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1360 return PHY_ERROR;
1361 if (mii_rw(dev, np->phyaddr,
1362 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1363 return PHY_ERROR;
1364 if (mii_rw(dev, np->phyaddr,
1365 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1366 return PHY_ERROR;
1367 phy_reserved = mii_rw(dev, np->phyaddr,
1368 PHY_VITESSE_INIT_REG4, MII_READ);
1369 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1370 return PHY_ERROR;
1371 phy_reserved = mii_rw(dev, np->phyaddr,
1372 PHY_VITESSE_INIT_REG3, MII_READ);
1373 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1374 phy_reserved |= PHY_VITESSE_INIT8;
1375 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1376 return PHY_ERROR;
1377 if (mii_rw(dev, np->phyaddr,
1378 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1379 return PHY_ERROR;
1380 if (mii_rw(dev, np->phyaddr,
1381 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1382 return PHY_ERROR;
1383
1384 return 0;
1385}
1386
1387static int phy_init(struct net_device *dev)
1388{
1389 struct fe_priv *np = get_nvpriv(dev);
1390 u8 __iomem *base = get_hwbase(dev);
1391 u32 phyinterface;
1392 u32 mii_status, mii_control, mii_control_1000, reg;
1393
1394 /* phy errata for E3016 phy */
1395 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1396 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1397 reg &= ~PHY_MARVELL_E3016_INITMASK;
1398 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1399 netdev_info(dev, "%s: phy write to errata reg failed\n",
1400 pci_name(np->pci_dev));
1401 return PHY_ERROR;
1402 }
1403 }
1404 if (np->phy_oui == PHY_OUI_REALTEK) {
1405 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1406 np->phy_rev == PHY_REV_REALTEK_8211B) {
1407 if (init_realtek_8211b(dev, np)) {
1408 netdev_info(dev, "%s: phy init failed\n",
1409 pci_name(np->pci_dev));
1410 return PHY_ERROR;
1411 }
1412 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1413 np->phy_rev == PHY_REV_REALTEK_8211C) {
1414 if (init_realtek_8211c(dev, np)) {
1415 netdev_info(dev, "%s: phy init failed\n",
1416 pci_name(np->pci_dev));
1417 return PHY_ERROR;
1418 }
1419 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1420 if (init_realtek_8201(dev, np)) {
1421 netdev_info(dev, "%s: phy init failed\n",
1422 pci_name(np->pci_dev));
1423 return PHY_ERROR;
1424 }
1425 }
1426 }
1427
1428 /* set advertise register */
1429 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1430 reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1431 ADVERTISE_100HALF | ADVERTISE_100FULL |
1432 ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1433 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1434 netdev_info(dev, "%s: phy write to advertise failed\n",
1435 pci_name(np->pci_dev));
1436 return PHY_ERROR;
1437 }
1438
1439 /* get phy interface type */
1440 phyinterface = readl(base + NvRegPhyInterface);
1441
1442 /* see if gigabit phy */
1443 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1444 if (mii_status & PHY_GIGABIT) {
1445 np->gigabit = PHY_GIGABIT;
1446 mii_control_1000 = mii_rw(dev, np->phyaddr,
1447 MII_CTRL1000, MII_READ);
1448 mii_control_1000 &= ~ADVERTISE_1000HALF;
1449 if (phyinterface & PHY_RGMII)
1450 mii_control_1000 |= ADVERTISE_1000FULL;
1451 else
1452 mii_control_1000 &= ~ADVERTISE_1000FULL;
1453
1454 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1455 netdev_info(dev, "%s: phy init failed\n",
1456 pci_name(np->pci_dev));
1457 return PHY_ERROR;
1458 }
1459 } else
1460 np->gigabit = 0;
1461
1462 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1463 mii_control |= BMCR_ANENABLE;
1464
1465 if (np->phy_oui == PHY_OUI_REALTEK &&
1466 np->phy_model == PHY_MODEL_REALTEK_8211 &&
1467 np->phy_rev == PHY_REV_REALTEK_8211C) {
1468 /* start autoneg since we already performed hw reset above */
1469 mii_control |= BMCR_ANRESTART;
1470 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1471 netdev_info(dev, "%s: phy init failed\n",
1472 pci_name(np->pci_dev));
1473 return PHY_ERROR;
1474 }
1475 } else {
1476 /* reset the phy
1477 * (certain phys need bmcr to be setup with reset)
1478 */
1479 if (phy_reset(dev, mii_control)) {
1480 netdev_info(dev, "%s: phy reset failed\n",
1481 pci_name(np->pci_dev));
1482 return PHY_ERROR;
1483 }
1484 }
1485
1486 /* phy vendor specific configuration */
1487 if (np->phy_oui == PHY_OUI_CICADA) {
1488 if (init_cicada(dev, np, phyinterface)) {
1489 netdev_info(dev, "%s: phy init failed\n",
1490 pci_name(np->pci_dev));
1491 return PHY_ERROR;
1492 }
1493 } else if (np->phy_oui == PHY_OUI_VITESSE) {
1494 if (init_vitesse(dev, np)) {
1495 netdev_info(dev, "%s: phy init failed\n",
1496 pci_name(np->pci_dev));
1497 return PHY_ERROR;
1498 }
1499 } else if (np->phy_oui == PHY_OUI_REALTEK) {
1500 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1501 np->phy_rev == PHY_REV_REALTEK_8211B) {
1502 /* reset could have cleared these out, set them back */
1503 if (init_realtek_8211b(dev, np)) {
1504 netdev_info(dev, "%s: phy init failed\n",
1505 pci_name(np->pci_dev));
1506 return PHY_ERROR;
1507 }
1508 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1509 if (init_realtek_8201(dev, np) ||
1510 init_realtek_8201_cross(dev, np)) {
1511 netdev_info(dev, "%s: phy init failed\n",
1512 pci_name(np->pci_dev));
1513 return PHY_ERROR;
1514 }
1515 }
1516 }
1517
1518 /* some phys clear out pause advertisement on reset, set it back */
1519 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1520
1521 /* restart auto negotiation, power down phy */
1522 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1523 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1524 if (phy_power_down)
1525 mii_control |= BMCR_PDOWN;
1526 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
1527 return PHY_ERROR;
1528
1529 return 0;
1530}
1531
1532static void nv_start_rx(struct net_device *dev)
1533{
1534 struct fe_priv *np = netdev_priv(dev);
1535 u8 __iomem *base = get_hwbase(dev);
1536 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1537
1538 /* Already running? Stop it. */
1539 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1540 rx_ctrl &= ~NVREG_RCVCTL_START;
1541 writel(rx_ctrl, base + NvRegReceiverControl);
1542 pci_push(base);
1543 }
1544 writel(np->linkspeed, base + NvRegLinkSpeed);
1545 pci_push(base);
1546 rx_ctrl |= NVREG_RCVCTL_START;
1547 if (np->mac_in_use)
1548 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1549 writel(rx_ctrl, base + NvRegReceiverControl);
1550 pci_push(base);
1551}
1552
1553static void nv_stop_rx(struct net_device *dev)
1554{
1555 struct fe_priv *np = netdev_priv(dev);
1556 u8 __iomem *base = get_hwbase(dev);
1557 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1558
1559 if (!np->mac_in_use)
1560 rx_ctrl &= ~NVREG_RCVCTL_START;
1561 else
1562 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1563 writel(rx_ctrl, base + NvRegReceiverControl);
1564 if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1565 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
1566 netdev_info(dev, "%s: ReceiverStatus remained busy\n",
1567 __func__);
1568
1569 udelay(NV_RXSTOP_DELAY2);
1570 if (!np->mac_in_use)
1571 writel(0, base + NvRegLinkSpeed);
1572}
1573
1574static void nv_start_tx(struct net_device *dev)
1575{
1576 struct fe_priv *np = netdev_priv(dev);
1577 u8 __iomem *base = get_hwbase(dev);
1578 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1579
1580 tx_ctrl |= NVREG_XMITCTL_START;
1581 if (np->mac_in_use)
1582 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1583 writel(tx_ctrl, base + NvRegTransmitterControl);
1584 pci_push(base);
1585}
1586
1587static void nv_stop_tx(struct net_device *dev)
1588{
1589 struct fe_priv *np = netdev_priv(dev);
1590 u8 __iomem *base = get_hwbase(dev);
1591 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1592
1593 if (!np->mac_in_use)
1594 tx_ctrl &= ~NVREG_XMITCTL_START;
1595 else
1596 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1597 writel(tx_ctrl, base + NvRegTransmitterControl);
1598 if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1599 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
1600 netdev_info(dev, "%s: TransmitterStatus remained busy\n",
1601 __func__);
1602
1603 udelay(NV_TXSTOP_DELAY2);
1604 if (!np->mac_in_use)
1605 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1606 base + NvRegTransmitPoll);
1607}
1608
1609static void nv_start_rxtx(struct net_device *dev)
1610{
1611 nv_start_rx(dev);
1612 nv_start_tx(dev);
1613}
1614
1615static void nv_stop_rxtx(struct net_device *dev)
1616{
1617 nv_stop_rx(dev);
1618 nv_stop_tx(dev);
1619}
1620
1621static void nv_txrx_reset(struct net_device *dev)
1622{
1623 struct fe_priv *np = netdev_priv(dev);
1624 u8 __iomem *base = get_hwbase(dev);
1625
1626 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1627 pci_push(base);
1628 udelay(NV_TXRX_RESET_DELAY);
1629 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1630 pci_push(base);
1631}
1632
1633static void nv_mac_reset(struct net_device *dev)
1634{
1635 struct fe_priv *np = netdev_priv(dev);
1636 u8 __iomem *base = get_hwbase(dev);
1637 u32 temp1, temp2, temp3;
1638
1639 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1640 pci_push(base);
1641
1642 /* save registers since they will be cleared on reset */
1643 temp1 = readl(base + NvRegMacAddrA);
1644 temp2 = readl(base + NvRegMacAddrB);
1645 temp3 = readl(base + NvRegTransmitPoll);
1646
1647 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1648 pci_push(base);
1649 udelay(NV_MAC_RESET_DELAY);
1650 writel(0, base + NvRegMacReset);
1651 pci_push(base);
1652 udelay(NV_MAC_RESET_DELAY);
1653
1654 /* restore saved registers */
1655 writel(temp1, base + NvRegMacAddrA);
1656 writel(temp2, base + NvRegMacAddrB);
1657 writel(temp3, base + NvRegTransmitPoll);
1658
1659 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1660 pci_push(base);
1661}
1662
1663/* Caller must appropriately lock netdev_priv(dev)->hwstats_lock */
1664static void nv_update_stats(struct net_device *dev)
1665{
1666 struct fe_priv *np = netdev_priv(dev);
1667 u8 __iomem *base = get_hwbase(dev);
1668
1669 /* If it happens that this is run in top-half context, then
1670 * replace the spin_lock of hwstats_lock with
1671 * spin_lock_irqsave() in calling functions. */
1672 WARN_ONCE(in_irq(), "forcedeth: estats spin_lock(_bh) from top-half");
1673 assert_spin_locked(&np->hwstats_lock);
1674
1675 /* query hardware */
1676 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1677 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1678 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1679 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1680 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1681 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1682 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1683 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1684 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1685 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1686 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1687 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1688 np->estats.rx_runt += readl(base + NvRegRxRunt);
1689 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1690 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1691 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1692 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1693 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1694 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1695 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1696 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1697 np->estats.rx_packets =
1698 np->estats.rx_unicast +
1699 np->estats.rx_multicast +
1700 np->estats.rx_broadcast;
1701 np->estats.rx_errors_total =
1702 np->estats.rx_crc_errors +
1703 np->estats.rx_over_errors +
1704 np->estats.rx_frame_error +
1705 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1706 np->estats.rx_late_collision +
1707 np->estats.rx_runt +
1708 np->estats.rx_frame_too_long;
1709 np->estats.tx_errors_total =
1710 np->estats.tx_late_collision +
1711 np->estats.tx_fifo_errors +
1712 np->estats.tx_carrier_errors +
1713 np->estats.tx_excess_deferral +
1714 np->estats.tx_retry_error;
1715
1716 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1717 np->estats.tx_deferral += readl(base + NvRegTxDef);
1718 np->estats.tx_packets += readl(base + NvRegTxFrame);
1719 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1720 np->estats.tx_pause += readl(base + NvRegTxPause);
1721 np->estats.rx_pause += readl(base + NvRegRxPause);
1722 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1723 np->estats.rx_errors_total += np->estats.rx_drop_frame;
1724 }
1725
1726 if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1727 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1728 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1729 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1730 }
1731}
1732
1733static void nv_get_stats(int cpu, struct fe_priv *np,
1734 struct rtnl_link_stats64 *storage)
1735{
1736 struct nv_txrx_stats *src = per_cpu_ptr(np->txrx_stats, cpu);
1737 unsigned int syncp_start;
1738 u64 rx_packets, rx_bytes, rx_dropped, rx_missed_errors;
1739 u64 tx_packets, tx_bytes, tx_dropped;
1740
1741 do {
1742 syncp_start = u64_stats_fetch_begin_irq(&np->swstats_rx_syncp);
1743 rx_packets = src->stat_rx_packets;
1744 rx_bytes = src->stat_rx_bytes;
1745 rx_dropped = src->stat_rx_dropped;
1746 rx_missed_errors = src->stat_rx_missed_errors;
1747 } while (u64_stats_fetch_retry_irq(&np->swstats_rx_syncp, syncp_start));
1748
1749 storage->rx_packets += rx_packets;
1750 storage->rx_bytes += rx_bytes;
1751 storage->rx_dropped += rx_dropped;
1752 storage->rx_missed_errors += rx_missed_errors;
1753
1754 do {
1755 syncp_start = u64_stats_fetch_begin_irq(&np->swstats_tx_syncp);
1756 tx_packets = src->stat_tx_packets;
1757 tx_bytes = src->stat_tx_bytes;
1758 tx_dropped = src->stat_tx_dropped;
1759 } while (u64_stats_fetch_retry_irq(&np->swstats_tx_syncp, syncp_start));
1760
1761 storage->tx_packets += tx_packets;
1762 storage->tx_bytes += tx_bytes;
1763 storage->tx_dropped += tx_dropped;
1764}
1765
1766/*
1767 * nv_get_stats64: dev->ndo_get_stats64 function
1768 * Get latest stats value from the nic.
1769 * Called with read_lock(&dev_base_lock) held for read -
1770 * only synchronized against unregister_netdevice.
1771 */
1772static void
1773nv_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *storage)
1774 __acquires(&netdev_priv(dev)->hwstats_lock)
1775 __releases(&netdev_priv(dev)->hwstats_lock)
1776{
1777 struct fe_priv *np = netdev_priv(dev);
1778 int cpu;
1779
1780 /*
1781 * Note: because HW stats are not always available and for
1782 * consistency reasons, the following ifconfig stats are
1783 * managed by software: rx_bytes, tx_bytes, rx_packets and
1784 * tx_packets. The related hardware stats reported by ethtool
1785 * should be equivalent to these ifconfig stats, with 4
1786 * additional bytes per packet (Ethernet FCS CRC), except for
1787 * tx_packets when TSO kicks in.
1788 */
1789
1790 /* software stats */
1791 for_each_online_cpu(cpu)
1792 nv_get_stats(cpu, np, storage);
1793
1794 /* If the nic supports hw counters then retrieve latest values */
1795 if (np->driver_data & DEV_HAS_STATISTICS_V123) {
1796 spin_lock_bh(&np->hwstats_lock);
1797
1798 nv_update_stats(dev);
1799
1800 /* generic stats */
1801 storage->rx_errors = np->estats.rx_errors_total;
1802 storage->tx_errors = np->estats.tx_errors_total;
1803
1804 /* meaningful only when NIC supports stats v3 */
1805 storage->multicast = np->estats.rx_multicast;
1806
1807 /* detailed rx_errors */
1808 storage->rx_length_errors = np->estats.rx_length_error;
1809 storage->rx_over_errors = np->estats.rx_over_errors;
1810 storage->rx_crc_errors = np->estats.rx_crc_errors;
1811 storage->rx_frame_errors = np->estats.rx_frame_align_error;
1812 storage->rx_fifo_errors = np->estats.rx_drop_frame;
1813
1814 /* detailed tx_errors */
1815 storage->tx_carrier_errors = np->estats.tx_carrier_errors;
1816 storage->tx_fifo_errors = np->estats.tx_fifo_errors;
1817
1818 spin_unlock_bh(&np->hwstats_lock);
1819 }
1820}
1821
1822/*
1823 * nv_alloc_rx: fill rx ring entries.
1824 * Return 1 if the allocations for the skbs failed and the
1825 * rx engine is without Available descriptors
1826 */
1827static int nv_alloc_rx(struct net_device *dev)
1828{
1829 struct fe_priv *np = netdev_priv(dev);
1830 struct ring_desc *less_rx;
1831
1832 less_rx = np->get_rx.orig;
1833 if (less_rx-- == np->rx_ring.orig)
1834 less_rx = np->last_rx.orig;
1835
1836 while (np->put_rx.orig != less_rx) {
1837 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD);
1838 if (likely(skb)) {
1839 np->put_rx_ctx->skb = skb;
1840 np->put_rx_ctx->dma = dma_map_single(&np->pci_dev->dev,
1841 skb->data,
1842 skb_tailroom(skb),
1843 DMA_FROM_DEVICE);
1844 if (unlikely(dma_mapping_error(&np->pci_dev->dev,
1845 np->put_rx_ctx->dma))) {
1846 kfree_skb(skb);
1847 goto packet_dropped;
1848 }
1849 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1850 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1851 wmb();
1852 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1853 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1854 np->put_rx.orig = np->rx_ring.orig;
1855 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1856 np->put_rx_ctx = np->rx_skb;
1857 } else {
1858packet_dropped:
1859 u64_stats_update_begin(&np->swstats_rx_syncp);
1860 nv_txrx_stats_inc(stat_rx_dropped);
1861 u64_stats_update_end(&np->swstats_rx_syncp);
1862 return 1;
1863 }
1864 }
1865 return 0;
1866}
1867
1868static int nv_alloc_rx_optimized(struct net_device *dev)
1869{
1870 struct fe_priv *np = netdev_priv(dev);
1871 struct ring_desc_ex *less_rx;
1872
1873 less_rx = np->get_rx.ex;
1874 if (less_rx-- == np->rx_ring.ex)
1875 less_rx = np->last_rx.ex;
1876
1877 while (np->put_rx.ex != less_rx) {
1878 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD);
1879 if (likely(skb)) {
1880 np->put_rx_ctx->skb = skb;
1881 np->put_rx_ctx->dma = dma_map_single(&np->pci_dev->dev,
1882 skb->data,
1883 skb_tailroom(skb),
1884 DMA_FROM_DEVICE);
1885 if (unlikely(dma_mapping_error(&np->pci_dev->dev,
1886 np->put_rx_ctx->dma))) {
1887 kfree_skb(skb);
1888 goto packet_dropped;
1889 }
1890 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1891 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1892 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1893 wmb();
1894 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1895 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1896 np->put_rx.ex = np->rx_ring.ex;
1897 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1898 np->put_rx_ctx = np->rx_skb;
1899 } else {
1900packet_dropped:
1901 u64_stats_update_begin(&np->swstats_rx_syncp);
1902 nv_txrx_stats_inc(stat_rx_dropped);
1903 u64_stats_update_end(&np->swstats_rx_syncp);
1904 return 1;
1905 }
1906 }
1907 return 0;
1908}
1909
1910/* If rx bufs are exhausted called after 50ms to attempt to refresh */
1911static void nv_do_rx_refill(struct timer_list *t)
1912{
1913 struct fe_priv *np = from_timer(np, t, oom_kick);
1914
1915 /* Just reschedule NAPI rx processing */
1916 napi_schedule(&np->napi);
1917}
1918
1919static void nv_init_rx(struct net_device *dev)
1920{
1921 struct fe_priv *np = netdev_priv(dev);
1922 int i;
1923
1924 np->get_rx = np->rx_ring;
1925 np->put_rx = np->rx_ring;
1926
1927 if (!nv_optimized(np))
1928 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1929 else
1930 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1931 np->get_rx_ctx = np->rx_skb;
1932 np->put_rx_ctx = np->rx_skb;
1933 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1934
1935 for (i = 0; i < np->rx_ring_size; i++) {
1936 if (!nv_optimized(np)) {
1937 np->rx_ring.orig[i].flaglen = 0;
1938 np->rx_ring.orig[i].buf = 0;
1939 } else {
1940 np->rx_ring.ex[i].flaglen = 0;
1941 np->rx_ring.ex[i].txvlan = 0;
1942 np->rx_ring.ex[i].bufhigh = 0;
1943 np->rx_ring.ex[i].buflow = 0;
1944 }
1945 np->rx_skb[i].skb = NULL;
1946 np->rx_skb[i].dma = 0;
1947 }
1948}
1949
1950static void nv_init_tx(struct net_device *dev)
1951{
1952 struct fe_priv *np = netdev_priv(dev);
1953 int i;
1954
1955 np->get_tx = np->tx_ring;
1956 np->put_tx = np->tx_ring;
1957
1958 if (!nv_optimized(np))
1959 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1960 else
1961 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1962 np->get_tx_ctx = np->tx_skb;
1963 np->put_tx_ctx = np->tx_skb;
1964 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1965 netdev_reset_queue(np->dev);
1966 np->tx_pkts_in_progress = 0;
1967 np->tx_change_owner = NULL;
1968 np->tx_end_flip = NULL;
1969 np->tx_stop = 0;
1970
1971 for (i = 0; i < np->tx_ring_size; i++) {
1972 if (!nv_optimized(np)) {
1973 np->tx_ring.orig[i].flaglen = 0;
1974 np->tx_ring.orig[i].buf = 0;
1975 } else {
1976 np->tx_ring.ex[i].flaglen = 0;
1977 np->tx_ring.ex[i].txvlan = 0;
1978 np->tx_ring.ex[i].bufhigh = 0;
1979 np->tx_ring.ex[i].buflow = 0;
1980 }
1981 np->tx_skb[i].skb = NULL;
1982 np->tx_skb[i].dma = 0;
1983 np->tx_skb[i].dma_len = 0;
1984 np->tx_skb[i].dma_single = 0;
1985 np->tx_skb[i].first_tx_desc = NULL;
1986 np->tx_skb[i].next_tx_ctx = NULL;
1987 }
1988}
1989
1990static int nv_init_ring(struct net_device *dev)
1991{
1992 struct fe_priv *np = netdev_priv(dev);
1993
1994 nv_init_tx(dev);
1995 nv_init_rx(dev);
1996
1997 if (!nv_optimized(np))
1998 return nv_alloc_rx(dev);
1999 else
2000 return nv_alloc_rx_optimized(dev);
2001}
2002
2003static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
2004{
2005 if (tx_skb->dma) {
2006 if (tx_skb->dma_single)
2007 dma_unmap_single(&np->pci_dev->dev, tx_skb->dma,
2008 tx_skb->dma_len,
2009 DMA_TO_DEVICE);
2010 else
2011 dma_unmap_page(&np->pci_dev->dev, tx_skb->dma,
2012 tx_skb->dma_len,
2013 DMA_TO_DEVICE);
2014 tx_skb->dma = 0;
2015 }
2016}
2017
2018static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
2019{
2020 nv_unmap_txskb(np, tx_skb);
2021 if (tx_skb->skb) {
2022 dev_kfree_skb_any(tx_skb->skb);
2023 tx_skb->skb = NULL;
2024 return 1;
2025 }
2026 return 0;
2027}
2028
2029static void nv_drain_tx(struct net_device *dev)
2030{
2031 struct fe_priv *np = netdev_priv(dev);
2032 unsigned int i;
2033
2034 for (i = 0; i < np->tx_ring_size; i++) {
2035 if (!nv_optimized(np)) {
2036 np->tx_ring.orig[i].flaglen = 0;
2037 np->tx_ring.orig[i].buf = 0;
2038 } else {
2039 np->tx_ring.ex[i].flaglen = 0;
2040 np->tx_ring.ex[i].txvlan = 0;
2041 np->tx_ring.ex[i].bufhigh = 0;
2042 np->tx_ring.ex[i].buflow = 0;
2043 }
2044 if (nv_release_txskb(np, &np->tx_skb[i])) {
2045 u64_stats_update_begin(&np->swstats_tx_syncp);
2046 nv_txrx_stats_inc(stat_tx_dropped);
2047 u64_stats_update_end(&np->swstats_tx_syncp);
2048 }
2049 np->tx_skb[i].dma = 0;
2050 np->tx_skb[i].dma_len = 0;
2051 np->tx_skb[i].dma_single = 0;
2052 np->tx_skb[i].first_tx_desc = NULL;
2053 np->tx_skb[i].next_tx_ctx = NULL;
2054 }
2055 np->tx_pkts_in_progress = 0;
2056 np->tx_change_owner = NULL;
2057 np->tx_end_flip = NULL;
2058}
2059
2060static void nv_drain_rx(struct net_device *dev)
2061{
2062 struct fe_priv *np = netdev_priv(dev);
2063 int i;
2064
2065 for (i = 0; i < np->rx_ring_size; i++) {
2066 if (!nv_optimized(np)) {
2067 np->rx_ring.orig[i].flaglen = 0;
2068 np->rx_ring.orig[i].buf = 0;
2069 } else {
2070 np->rx_ring.ex[i].flaglen = 0;
2071 np->rx_ring.ex[i].txvlan = 0;
2072 np->rx_ring.ex[i].bufhigh = 0;
2073 np->rx_ring.ex[i].buflow = 0;
2074 }
2075 wmb();
2076 if (np->rx_skb[i].skb) {
2077 dma_unmap_single(&np->pci_dev->dev, np->rx_skb[i].dma,
2078 (skb_end_pointer(np->rx_skb[i].skb) -
2079 np->rx_skb[i].skb->data),
2080 DMA_FROM_DEVICE);
2081 dev_kfree_skb(np->rx_skb[i].skb);
2082 np->rx_skb[i].skb = NULL;
2083 }
2084 }
2085}
2086
2087static void nv_drain_rxtx(struct net_device *dev)
2088{
2089 nv_drain_tx(dev);
2090 nv_drain_rx(dev);
2091}
2092
2093static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
2094{
2095 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
2096}
2097
2098static void nv_legacybackoff_reseed(struct net_device *dev)
2099{
2100 u8 __iomem *base = get_hwbase(dev);
2101 u32 reg;
2102 u32 low;
2103 int tx_status = 0;
2104
2105 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2106 get_random_bytes(&low, sizeof(low));
2107 reg |= low & NVREG_SLOTTIME_MASK;
2108
2109 /* Need to stop tx before change takes effect.
2110 * Caller has already gained np->lock.
2111 */
2112 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2113 if (tx_status)
2114 nv_stop_tx(dev);
2115 nv_stop_rx(dev);
2116 writel(reg, base + NvRegSlotTime);
2117 if (tx_status)
2118 nv_start_tx(dev);
2119 nv_start_rx(dev);
2120}
2121
2122/* Gear Backoff Seeds */
2123#define BACKOFF_SEEDSET_ROWS 8
2124#define BACKOFF_SEEDSET_LFSRS 15
2125
2126/* Known Good seed sets */
2127static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2128 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2129 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2130 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2131 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2132 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2133 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2134 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2135 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
2136
2137static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2138 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2139 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2140 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2141 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2142 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2143 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2144 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2145 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
2146
2147static void nv_gear_backoff_reseed(struct net_device *dev)
2148{
2149 u8 __iomem *base = get_hwbase(dev);
2150 u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2151 u32 temp, seedset, combinedSeed;
2152 int i;
2153
2154 /* Setup seed for free running LFSR */
2155 /* We are going to read the time stamp counter 3 times
2156 and swizzle bits around to increase randomness */
2157 get_random_bytes(&miniseed1, sizeof(miniseed1));
2158 miniseed1 &= 0x0fff;
2159 if (miniseed1 == 0)
2160 miniseed1 = 0xabc;
2161
2162 get_random_bytes(&miniseed2, sizeof(miniseed2));
2163 miniseed2 &= 0x0fff;
2164 if (miniseed2 == 0)
2165 miniseed2 = 0xabc;
2166 miniseed2_reversed =
2167 ((miniseed2 & 0xF00) >> 8) |
2168 (miniseed2 & 0x0F0) |
2169 ((miniseed2 & 0x00F) << 8);
2170
2171 get_random_bytes(&miniseed3, sizeof(miniseed3));
2172 miniseed3 &= 0x0fff;
2173 if (miniseed3 == 0)
2174 miniseed3 = 0xabc;
2175 miniseed3_reversed =
2176 ((miniseed3 & 0xF00) >> 8) |
2177 (miniseed3 & 0x0F0) |
2178 ((miniseed3 & 0x00F) << 8);
2179
2180 combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2181 (miniseed2 ^ miniseed3_reversed);
2182
2183 /* Seeds can not be zero */
2184 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2185 combinedSeed |= 0x08;
2186 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2187 combinedSeed |= 0x8000;
2188
2189 /* No need to disable tx here */
2190 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2191 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2192 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2193 writel(temp, base + NvRegBackOffControl);
2194
2195 /* Setup seeds for all gear LFSRs. */
2196 get_random_bytes(&seedset, sizeof(seedset));
2197 seedset = seedset % BACKOFF_SEEDSET_ROWS;
2198 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
2199 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2200 temp |= main_seedset[seedset][i-1] & 0x3ff;
2201 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2202 writel(temp, base + NvRegBackOffControl);
2203 }
2204}
2205
2206/*
2207 * nv_start_xmit: dev->hard_start_xmit function
2208 * Called with netif_tx_lock held.
2209 */
2210static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2211{
2212 struct fe_priv *np = netdev_priv(dev);
2213 u32 tx_flags = 0;
2214 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2215 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2216 unsigned int i;
2217 u32 offset = 0;
2218 u32 bcnt;
2219 u32 size = skb_headlen(skb);
2220 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2221 u32 empty_slots;
2222 struct ring_desc *put_tx;
2223 struct ring_desc *start_tx;
2224 struct ring_desc *prev_tx;
2225 struct nv_skb_map *prev_tx_ctx;
2226 struct nv_skb_map *tmp_tx_ctx = NULL, *start_tx_ctx = NULL;
2227 unsigned long flags;
2228 netdev_tx_t ret = NETDEV_TX_OK;
2229
2230 /* add fragments to entries count */
2231 for (i = 0; i < fragments; i++) {
2232 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2233
2234 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2235 ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2236 }
2237
2238 spin_lock_irqsave(&np->lock, flags);
2239 empty_slots = nv_get_empty_tx_slots(np);
2240 if (unlikely(empty_slots <= entries)) {
2241 netif_stop_queue(dev);
2242 np->tx_stop = 1;
2243 spin_unlock_irqrestore(&np->lock, flags);
2244
2245 /* When normal packets and/or xmit_more packets fill up
2246 * tx_desc, it is necessary to trigger NIC tx reg.
2247 */
2248 ret = NETDEV_TX_BUSY;
2249 goto txkick;
2250 }
2251 spin_unlock_irqrestore(&np->lock, flags);
2252
2253 start_tx = put_tx = np->put_tx.orig;
2254
2255 /* setup the header buffer */
2256 do {
2257 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2258 np->put_tx_ctx->dma = dma_map_single(&np->pci_dev->dev,
2259 skb->data + offset, bcnt,
2260 DMA_TO_DEVICE);
2261 if (unlikely(dma_mapping_error(&np->pci_dev->dev,
2262 np->put_tx_ctx->dma))) {
2263 /* on DMA mapping error - drop the packet */
2264 dev_kfree_skb_any(skb);
2265 u64_stats_update_begin(&np->swstats_tx_syncp);
2266 nv_txrx_stats_inc(stat_tx_dropped);
2267 u64_stats_update_end(&np->swstats_tx_syncp);
2268
2269 ret = NETDEV_TX_OK;
2270
2271 goto dma_error;
2272 }
2273 np->put_tx_ctx->dma_len = bcnt;
2274 np->put_tx_ctx->dma_single = 1;
2275 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2276 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2277
2278 tx_flags = np->tx_flags;
2279 offset += bcnt;
2280 size -= bcnt;
2281 if (unlikely(put_tx++ == np->last_tx.orig))
2282 put_tx = np->tx_ring.orig;
2283 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2284 np->put_tx_ctx = np->tx_skb;
2285 } while (size);
2286
2287 /* setup the fragments */
2288 for (i = 0; i < fragments; i++) {
2289 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2290 u32 frag_size = skb_frag_size(frag);
2291 offset = 0;
2292
2293 do {
2294 if (!start_tx_ctx)
2295 start_tx_ctx = tmp_tx_ctx = np->put_tx_ctx;
2296
2297 bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2298 np->put_tx_ctx->dma = skb_frag_dma_map(
2299 &np->pci_dev->dev,
2300 frag, offset,
2301 bcnt,
2302 DMA_TO_DEVICE);
2303 if (unlikely(dma_mapping_error(&np->pci_dev->dev,
2304 np->put_tx_ctx->dma))) {
2305
2306 /* Unwind the mapped fragments */
2307 do {
2308 nv_unmap_txskb(np, start_tx_ctx);
2309 if (unlikely(tmp_tx_ctx++ == np->last_tx_ctx))
2310 tmp_tx_ctx = np->tx_skb;
2311 } while (tmp_tx_ctx != np->put_tx_ctx);
2312 dev_kfree_skb_any(skb);
2313 np->put_tx_ctx = start_tx_ctx;
2314 u64_stats_update_begin(&np->swstats_tx_syncp);
2315 nv_txrx_stats_inc(stat_tx_dropped);
2316 u64_stats_update_end(&np->swstats_tx_syncp);
2317
2318 ret = NETDEV_TX_OK;
2319
2320 goto dma_error;
2321 }
2322
2323 np->put_tx_ctx->dma_len = bcnt;
2324 np->put_tx_ctx->dma_single = 0;
2325 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2326 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2327
2328 offset += bcnt;
2329 frag_size -= bcnt;
2330 if (unlikely(put_tx++ == np->last_tx.orig))
2331 put_tx = np->tx_ring.orig;
2332 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2333 np->put_tx_ctx = np->tx_skb;
2334 } while (frag_size);
2335 }
2336
2337 if (unlikely(put_tx == np->tx_ring.orig))
2338 prev_tx = np->last_tx.orig;
2339 else
2340 prev_tx = put_tx - 1;
2341
2342 if (unlikely(np->put_tx_ctx == np->tx_skb))
2343 prev_tx_ctx = np->last_tx_ctx;
2344 else
2345 prev_tx_ctx = np->put_tx_ctx - 1;
2346
2347 /* set last fragment flag */
2348 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2349
2350 /* save skb in this slot's context area */
2351 prev_tx_ctx->skb = skb;
2352
2353 if (skb_is_gso(skb))
2354 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2355 else
2356 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2357 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2358
2359 spin_lock_irqsave(&np->lock, flags);
2360
2361 /* set tx flags */
2362 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2363
2364 netdev_sent_queue(np->dev, skb->len);
2365
2366 skb_tx_timestamp(skb);
2367
2368 np->put_tx.orig = put_tx;
2369
2370 spin_unlock_irqrestore(&np->lock, flags);
2371
2372txkick:
2373 if (netif_queue_stopped(dev) || !netdev_xmit_more()) {
2374 u32 txrxctl_kick;
2375dma_error:
2376 txrxctl_kick = NVREG_TXRXCTL_KICK | np->txrxctl_bits;
2377 writel(txrxctl_kick, get_hwbase(dev) + NvRegTxRxControl);
2378 }
2379
2380 return ret;
2381}
2382
2383static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2384 struct net_device *dev)
2385{
2386 struct fe_priv *np = netdev_priv(dev);
2387 u32 tx_flags = 0;
2388 u32 tx_flags_extra;
2389 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2390 unsigned int i;
2391 u32 offset = 0;
2392 u32 bcnt;
2393 u32 size = skb_headlen(skb);
2394 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2395 u32 empty_slots;
2396 struct ring_desc_ex *put_tx;
2397 struct ring_desc_ex *start_tx;
2398 struct ring_desc_ex *prev_tx;
2399 struct nv_skb_map *prev_tx_ctx;
2400 struct nv_skb_map *start_tx_ctx = NULL;
2401 struct nv_skb_map *tmp_tx_ctx = NULL;
2402 unsigned long flags;
2403 netdev_tx_t ret = NETDEV_TX_OK;
2404
2405 /* add fragments to entries count */
2406 for (i = 0; i < fragments; i++) {
2407 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2408
2409 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2410 ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2411 }
2412
2413 spin_lock_irqsave(&np->lock, flags);
2414 empty_slots = nv_get_empty_tx_slots(np);
2415 if (unlikely(empty_slots <= entries)) {
2416 netif_stop_queue(dev);
2417 np->tx_stop = 1;
2418 spin_unlock_irqrestore(&np->lock, flags);
2419
2420 /* When normal packets and/or xmit_more packets fill up
2421 * tx_desc, it is necessary to trigger NIC tx reg.
2422 */
2423 ret = NETDEV_TX_BUSY;
2424
2425 goto txkick;
2426 }
2427 spin_unlock_irqrestore(&np->lock, flags);
2428
2429 start_tx = put_tx = np->put_tx.ex;
2430 start_tx_ctx = np->put_tx_ctx;
2431
2432 /* setup the header buffer */
2433 do {
2434 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2435 np->put_tx_ctx->dma = dma_map_single(&np->pci_dev->dev,
2436 skb->data + offset, bcnt,
2437 DMA_TO_DEVICE);
2438 if (unlikely(dma_mapping_error(&np->pci_dev->dev,
2439 np->put_tx_ctx->dma))) {
2440 /* on DMA mapping error - drop the packet */
2441 dev_kfree_skb_any(skb);
2442 u64_stats_update_begin(&np->swstats_tx_syncp);
2443 nv_txrx_stats_inc(stat_tx_dropped);
2444 u64_stats_update_end(&np->swstats_tx_syncp);
2445
2446 ret = NETDEV_TX_OK;
2447
2448 goto dma_error;
2449 }
2450 np->put_tx_ctx->dma_len = bcnt;
2451 np->put_tx_ctx->dma_single = 1;
2452 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2453 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2454 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2455
2456 tx_flags = NV_TX2_VALID;
2457 offset += bcnt;
2458 size -= bcnt;
2459 if (unlikely(put_tx++ == np->last_tx.ex))
2460 put_tx = np->tx_ring.ex;
2461 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2462 np->put_tx_ctx = np->tx_skb;
2463 } while (size);
2464
2465 /* setup the fragments */
2466 for (i = 0; i < fragments; i++) {
2467 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2468 u32 frag_size = skb_frag_size(frag);
2469 offset = 0;
2470
2471 do {
2472 bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2473 if (!start_tx_ctx)
2474 start_tx_ctx = tmp_tx_ctx = np->put_tx_ctx;
2475 np->put_tx_ctx->dma = skb_frag_dma_map(
2476 &np->pci_dev->dev,
2477 frag, offset,
2478 bcnt,
2479 DMA_TO_DEVICE);
2480
2481 if (unlikely(dma_mapping_error(&np->pci_dev->dev,
2482 np->put_tx_ctx->dma))) {
2483
2484 /* Unwind the mapped fragments */
2485 do {
2486 nv_unmap_txskb(np, start_tx_ctx);
2487 if (unlikely(tmp_tx_ctx++ == np->last_tx_ctx))
2488 tmp_tx_ctx = np->tx_skb;
2489 } while (tmp_tx_ctx != np->put_tx_ctx);
2490 dev_kfree_skb_any(skb);
2491 np->put_tx_ctx = start_tx_ctx;
2492 u64_stats_update_begin(&np->swstats_tx_syncp);
2493 nv_txrx_stats_inc(stat_tx_dropped);
2494 u64_stats_update_end(&np->swstats_tx_syncp);
2495
2496 ret = NETDEV_TX_OK;
2497
2498 goto dma_error;
2499 }
2500 np->put_tx_ctx->dma_len = bcnt;
2501 np->put_tx_ctx->dma_single = 0;
2502 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2503 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2504 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2505
2506 offset += bcnt;
2507 frag_size -= bcnt;
2508 if (unlikely(put_tx++ == np->last_tx.ex))
2509 put_tx = np->tx_ring.ex;
2510 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2511 np->put_tx_ctx = np->tx_skb;
2512 } while (frag_size);
2513 }
2514
2515 if (unlikely(put_tx == np->tx_ring.ex))
2516 prev_tx = np->last_tx.ex;
2517 else
2518 prev_tx = put_tx - 1;
2519
2520 if (unlikely(np->put_tx_ctx == np->tx_skb))
2521 prev_tx_ctx = np->last_tx_ctx;
2522 else
2523 prev_tx_ctx = np->put_tx_ctx - 1;
2524
2525 /* set last fragment flag */
2526 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2527
2528 /* save skb in this slot's context area */
2529 prev_tx_ctx->skb = skb;
2530
2531 if (skb_is_gso(skb))
2532 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2533 else
2534 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2535 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2536
2537 /* vlan tag */
2538 if (skb_vlan_tag_present(skb))
2539 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2540 skb_vlan_tag_get(skb));
2541 else
2542 start_tx->txvlan = 0;
2543
2544 spin_lock_irqsave(&np->lock, flags);
2545
2546 if (np->tx_limit) {
2547 /* Limit the number of outstanding tx. Setup all fragments, but
2548 * do not set the VALID bit on the first descriptor. Save a pointer
2549 * to that descriptor and also for next skb_map element.
2550 */
2551
2552 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2553 if (!np->tx_change_owner)
2554 np->tx_change_owner = start_tx_ctx;
2555
2556 /* remove VALID bit */
2557 tx_flags &= ~NV_TX2_VALID;
2558 start_tx_ctx->first_tx_desc = start_tx;
2559 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2560 np->tx_end_flip = np->put_tx_ctx;
2561 } else {
2562 np->tx_pkts_in_progress++;
2563 }
2564 }
2565
2566 /* set tx flags */
2567 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2568
2569 netdev_sent_queue(np->dev, skb->len);
2570
2571 skb_tx_timestamp(skb);
2572
2573 np->put_tx.ex = put_tx;
2574
2575 spin_unlock_irqrestore(&np->lock, flags);
2576
2577txkick:
2578 if (netif_queue_stopped(dev) || !netdev_xmit_more()) {
2579 u32 txrxctl_kick;
2580dma_error:
2581 txrxctl_kick = NVREG_TXRXCTL_KICK | np->txrxctl_bits;
2582 writel(txrxctl_kick, get_hwbase(dev) + NvRegTxRxControl);
2583 }
2584
2585 return ret;
2586}
2587
2588static inline void nv_tx_flip_ownership(struct net_device *dev)
2589{
2590 struct fe_priv *np = netdev_priv(dev);
2591
2592 np->tx_pkts_in_progress--;
2593 if (np->tx_change_owner) {
2594 np->tx_change_owner->first_tx_desc->flaglen |=
2595 cpu_to_le32(NV_TX2_VALID);
2596 np->tx_pkts_in_progress++;
2597
2598 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2599 if (np->tx_change_owner == np->tx_end_flip)
2600 np->tx_change_owner = NULL;
2601
2602 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2603 }
2604}
2605
2606/*
2607 * nv_tx_done: check for completed packets, release the skbs.
2608 *
2609 * Caller must own np->lock.
2610 */
2611static int nv_tx_done(struct net_device *dev, int limit)
2612{
2613 struct fe_priv *np = netdev_priv(dev);
2614 u32 flags;
2615 int tx_work = 0;
2616 struct ring_desc *orig_get_tx = np->get_tx.orig;
2617 unsigned int bytes_compl = 0;
2618
2619 while ((np->get_tx.orig != np->put_tx.orig) &&
2620 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2621 (tx_work < limit)) {
2622
2623 nv_unmap_txskb(np, np->get_tx_ctx);
2624
2625 if (np->desc_ver == DESC_VER_1) {
2626 if (flags & NV_TX_LASTPACKET) {
2627 if (unlikely(flags & NV_TX_ERROR)) {
2628 if ((flags & NV_TX_RETRYERROR)
2629 && !(flags & NV_TX_RETRYCOUNT_MASK))
2630 nv_legacybackoff_reseed(dev);
2631 } else {
2632 unsigned int len;
2633
2634 u64_stats_update_begin(&np->swstats_tx_syncp);
2635 nv_txrx_stats_inc(stat_tx_packets);
2636 len = np->get_tx_ctx->skb->len;
2637 nv_txrx_stats_add(stat_tx_bytes, len);
2638 u64_stats_update_end(&np->swstats_tx_syncp);
2639 }
2640 bytes_compl += np->get_tx_ctx->skb->len;
2641 dev_kfree_skb_any(np->get_tx_ctx->skb);
2642 np->get_tx_ctx->skb = NULL;
2643 tx_work++;
2644 }
2645 } else {
2646 if (flags & NV_TX2_LASTPACKET) {
2647 if (unlikely(flags & NV_TX2_ERROR)) {
2648 if ((flags & NV_TX2_RETRYERROR)
2649 && !(flags & NV_TX2_RETRYCOUNT_MASK))
2650 nv_legacybackoff_reseed(dev);
2651 } else {
2652 unsigned int len;
2653
2654 u64_stats_update_begin(&np->swstats_tx_syncp);
2655 nv_txrx_stats_inc(stat_tx_packets);
2656 len = np->get_tx_ctx->skb->len;
2657 nv_txrx_stats_add(stat_tx_bytes, len);
2658 u64_stats_update_end(&np->swstats_tx_syncp);
2659 }
2660 bytes_compl += np->get_tx_ctx->skb->len;
2661 dev_kfree_skb_any(np->get_tx_ctx->skb);
2662 np->get_tx_ctx->skb = NULL;
2663 tx_work++;
2664 }
2665 }
2666 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2667 np->get_tx.orig = np->tx_ring.orig;
2668 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2669 np->get_tx_ctx = np->tx_skb;
2670 }
2671
2672 netdev_completed_queue(np->dev, tx_work, bytes_compl);
2673
2674 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2675 np->tx_stop = 0;
2676 netif_wake_queue(dev);
2677 }
2678 return tx_work;
2679}
2680
2681static int nv_tx_done_optimized(struct net_device *dev, int limit)
2682{
2683 struct fe_priv *np = netdev_priv(dev);
2684 u32 flags;
2685 int tx_work = 0;
2686 struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
2687 unsigned long bytes_cleaned = 0;
2688
2689 while ((np->get_tx.ex != np->put_tx.ex) &&
2690 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
2691 (tx_work < limit)) {
2692
2693 nv_unmap_txskb(np, np->get_tx_ctx);
2694
2695 if (flags & NV_TX2_LASTPACKET) {
2696 if (unlikely(flags & NV_TX2_ERROR)) {
2697 if ((flags & NV_TX2_RETRYERROR)
2698 && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2699 if (np->driver_data & DEV_HAS_GEAR_MODE)
2700 nv_gear_backoff_reseed(dev);
2701 else
2702 nv_legacybackoff_reseed(dev);
2703 }
2704 } else {
2705 unsigned int len;
2706
2707 u64_stats_update_begin(&np->swstats_tx_syncp);
2708 nv_txrx_stats_inc(stat_tx_packets);
2709 len = np->get_tx_ctx->skb->len;
2710 nv_txrx_stats_add(stat_tx_bytes, len);
2711 u64_stats_update_end(&np->swstats_tx_syncp);
2712 }
2713
2714 bytes_cleaned += np->get_tx_ctx->skb->len;
2715 dev_kfree_skb_any(np->get_tx_ctx->skb);
2716 np->get_tx_ctx->skb = NULL;
2717 tx_work++;
2718
2719 if (np->tx_limit)
2720 nv_tx_flip_ownership(dev);
2721 }
2722
2723 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2724 np->get_tx.ex = np->tx_ring.ex;
2725 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2726 np->get_tx_ctx = np->tx_skb;
2727 }
2728
2729 netdev_completed_queue(np->dev, tx_work, bytes_cleaned);
2730
2731 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2732 np->tx_stop = 0;
2733 netif_wake_queue(dev);
2734 }
2735 return tx_work;
2736}
2737
2738/*
2739 * nv_tx_timeout: dev->tx_timeout function
2740 * Called with netif_tx_lock held.
2741 */
2742static void nv_tx_timeout(struct net_device *dev, unsigned int txqueue)
2743{
2744 struct fe_priv *np = netdev_priv(dev);
2745 u8 __iomem *base = get_hwbase(dev);
2746 u32 status;
2747 union ring_type put_tx;
2748 int saved_tx_limit;
2749
2750 if (np->msi_flags & NV_MSI_X_ENABLED)
2751 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2752 else
2753 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2754
2755 netdev_warn(dev, "Got tx_timeout. irq status: %08x\n", status);
2756
2757 if (unlikely(debug_tx_timeout)) {
2758 int i;
2759
2760 netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
2761 netdev_info(dev, "Dumping tx registers\n");
2762 for (i = 0; i <= np->register_size; i += 32) {
2763 netdev_info(dev,
2764 "%3x: %08x %08x %08x %08x "
2765 "%08x %08x %08x %08x\n",
2766 i,
2767 readl(base + i + 0), readl(base + i + 4),
2768 readl(base + i + 8), readl(base + i + 12),
2769 readl(base + i + 16), readl(base + i + 20),
2770 readl(base + i + 24), readl(base + i + 28));
2771 }
2772 netdev_info(dev, "Dumping tx ring\n");
2773 for (i = 0; i < np->tx_ring_size; i += 4) {
2774 if (!nv_optimized(np)) {
2775 netdev_info(dev,
2776 "%03x: %08x %08x // %08x %08x "
2777 "// %08x %08x // %08x %08x\n",
2778 i,
2779 le32_to_cpu(np->tx_ring.orig[i].buf),
2780 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2781 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2782 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2783 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2784 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2785 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2786 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2787 } else {
2788 netdev_info(dev,
2789 "%03x: %08x %08x %08x "
2790 "// %08x %08x %08x "
2791 "// %08x %08x %08x "
2792 "// %08x %08x %08x\n",
2793 i,
2794 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2795 le32_to_cpu(np->tx_ring.ex[i].buflow),
2796 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2797 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2798 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2799 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2800 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2801 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2802 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2803 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2804 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2805 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2806 }
2807 }
2808 }
2809
2810 spin_lock_irq(&np->lock);
2811
2812 /* 1) stop tx engine */
2813 nv_stop_tx(dev);
2814
2815 /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2816 saved_tx_limit = np->tx_limit;
2817 np->tx_limit = 0; /* prevent giving HW any limited pkts */
2818 np->tx_stop = 0; /* prevent waking tx queue */
2819 if (!nv_optimized(np))
2820 nv_tx_done(dev, np->tx_ring_size);
2821 else
2822 nv_tx_done_optimized(dev, np->tx_ring_size);
2823
2824 /* save current HW position */
2825 if (np->tx_change_owner)
2826 put_tx.ex = np->tx_change_owner->first_tx_desc;
2827 else
2828 put_tx = np->put_tx;
2829
2830 /* 3) clear all tx state */
2831 nv_drain_tx(dev);
2832 nv_init_tx(dev);
2833
2834 /* 4) restore state to current HW position */
2835 np->get_tx = np->put_tx = put_tx;
2836 np->tx_limit = saved_tx_limit;
2837
2838 /* 5) restart tx engine */
2839 nv_start_tx(dev);
2840 netif_wake_queue(dev);
2841 spin_unlock_irq(&np->lock);
2842}
2843
2844/*
2845 * Called when the nic notices a mismatch between the actual data len on the
2846 * wire and the len indicated in the 802 header
2847 */
2848static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2849{
2850 int hdrlen; /* length of the 802 header */
2851 int protolen; /* length as stored in the proto field */
2852
2853 /* 1) calculate len according to header */
2854 if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2855 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
2856 hdrlen = VLAN_HLEN;
2857 } else {
2858 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
2859 hdrlen = ETH_HLEN;
2860 }
2861 if (protolen > ETH_DATA_LEN)
2862 return datalen; /* Value in proto field not a len, no checks possible */
2863
2864 protolen += hdrlen;
2865 /* consistency checks: */
2866 if (datalen > ETH_ZLEN) {
2867 if (datalen >= protolen) {
2868 /* more data on wire than in 802 header, trim of
2869 * additional data.
2870 */
2871 return protolen;
2872 } else {
2873 /* less data on wire than mentioned in header.
2874 * Discard the packet.
2875 */
2876 return -1;
2877 }
2878 } else {
2879 /* short packet. Accept only if 802 values are also short */
2880 if (protolen > ETH_ZLEN) {
2881 return -1;
2882 }
2883 return datalen;
2884 }
2885}
2886
2887static void rx_missing_handler(u32 flags, struct fe_priv *np)
2888{
2889 if (flags & NV_RX_MISSEDFRAME) {
2890 u64_stats_update_begin(&np->swstats_rx_syncp);
2891 nv_txrx_stats_inc(stat_rx_missed_errors);
2892 u64_stats_update_end(&np->swstats_rx_syncp);
2893 }
2894}
2895
2896static int nv_rx_process(struct net_device *dev, int limit)
2897{
2898 struct fe_priv *np = netdev_priv(dev);
2899 u32 flags;
2900 int rx_work = 0;
2901 struct sk_buff *skb;
2902 int len;
2903
2904 while ((np->get_rx.orig != np->put_rx.orig) &&
2905 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2906 (rx_work < limit)) {
2907
2908 /*
2909 * the packet is for us - immediately tear down the pci mapping.
2910 * TODO: check if a prefetch of the first cacheline improves
2911 * the performance.
2912 */
2913 dma_unmap_single(&np->pci_dev->dev, np->get_rx_ctx->dma,
2914 np->get_rx_ctx->dma_len,
2915 DMA_FROM_DEVICE);
2916 skb = np->get_rx_ctx->skb;
2917 np->get_rx_ctx->skb = NULL;
2918
2919 /* look at what we actually got: */
2920 if (np->desc_ver == DESC_VER_1) {
2921 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2922 len = flags & LEN_MASK_V1;
2923 if (unlikely(flags & NV_RX_ERROR)) {
2924 if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2925 len = nv_getlen(dev, skb->data, len);
2926 if (len < 0) {
2927 dev_kfree_skb(skb);
2928 goto next_pkt;
2929 }
2930 }
2931 /* framing errors are soft errors */
2932 else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2933 if (flags & NV_RX_SUBTRACT1)
2934 len--;
2935 }
2936 /* the rest are hard errors */
2937 else {
2938 rx_missing_handler(flags, np);
2939 dev_kfree_skb(skb);
2940 goto next_pkt;
2941 }
2942 }
2943 } else {
2944 dev_kfree_skb(skb);
2945 goto next_pkt;
2946 }
2947 } else {
2948 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2949 len = flags & LEN_MASK_V2;
2950 if (unlikely(flags & NV_RX2_ERROR)) {
2951 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2952 len = nv_getlen(dev, skb->data, len);
2953 if (len < 0) {
2954 dev_kfree_skb(skb);
2955 goto next_pkt;
2956 }
2957 }
2958 /* framing errors are soft errors */
2959 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2960 if (flags & NV_RX2_SUBTRACT1)
2961 len--;
2962 }
2963 /* the rest are hard errors */
2964 else {
2965 dev_kfree_skb(skb);
2966 goto next_pkt;
2967 }
2968 }
2969 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2970 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2971 skb->ip_summed = CHECKSUM_UNNECESSARY;
2972 } else {
2973 dev_kfree_skb(skb);
2974 goto next_pkt;
2975 }
2976 }
2977 /* got a valid packet - forward it to the network core */
2978 skb_put(skb, len);
2979 skb->protocol = eth_type_trans(skb, dev);
2980 napi_gro_receive(&np->napi, skb);
2981 u64_stats_update_begin(&np->swstats_rx_syncp);
2982 nv_txrx_stats_inc(stat_rx_packets);
2983 nv_txrx_stats_add(stat_rx_bytes, len);
2984 u64_stats_update_end(&np->swstats_rx_syncp);
2985next_pkt:
2986 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2987 np->get_rx.orig = np->rx_ring.orig;
2988 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2989 np->get_rx_ctx = np->rx_skb;
2990
2991 rx_work++;
2992 }
2993
2994 return rx_work;
2995}
2996
2997static int nv_rx_process_optimized(struct net_device *dev, int limit)
2998{
2999 struct fe_priv *np = netdev_priv(dev);
3000 u32 flags;
3001 u32 vlanflags = 0;
3002 int rx_work = 0;
3003 struct sk_buff *skb;
3004 int len;
3005
3006 while ((np->get_rx.ex != np->put_rx.ex) &&
3007 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
3008 (rx_work < limit)) {
3009
3010 /*
3011 * the packet is for us - immediately tear down the pci mapping.
3012 * TODO: check if a prefetch of the first cacheline improves
3013 * the performance.
3014 */
3015 dma_unmap_single(&np->pci_dev->dev, np->get_rx_ctx->dma,
3016 np->get_rx_ctx->dma_len,
3017 DMA_FROM_DEVICE);
3018 skb = np->get_rx_ctx->skb;
3019 np->get_rx_ctx->skb = NULL;
3020
3021 /* look at what we actually got: */
3022 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
3023 len = flags & LEN_MASK_V2;
3024 if (unlikely(flags & NV_RX2_ERROR)) {
3025 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
3026 len = nv_getlen(dev, skb->data, len);
3027 if (len < 0) {
3028 dev_kfree_skb(skb);
3029 goto next_pkt;
3030 }
3031 }
3032 /* framing errors are soft errors */
3033 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
3034 if (flags & NV_RX2_SUBTRACT1)
3035 len--;
3036 }
3037 /* the rest are hard errors */
3038 else {
3039 dev_kfree_skb(skb);
3040 goto next_pkt;
3041 }
3042 }
3043
3044 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
3045 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
3046 skb->ip_summed = CHECKSUM_UNNECESSARY;
3047
3048 /* got a valid packet - forward it to the network core */
3049 skb_put(skb, len);
3050 skb->protocol = eth_type_trans(skb, dev);
3051 prefetch(skb->data);
3052
3053 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
3054
3055 /*
3056 * There's need to check for NETIF_F_HW_VLAN_CTAG_RX
3057 * here. Even if vlan rx accel is disabled,
3058 * NV_RX3_VLAN_TAG_PRESENT is pseudo randomly set.
3059 */
3060 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
3061 vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
3062 u16 vid = vlanflags & NV_RX3_VLAN_TAG_MASK;
3063
3064 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
3065 }
3066 napi_gro_receive(&np->napi, skb);
3067 u64_stats_update_begin(&np->swstats_rx_syncp);
3068 nv_txrx_stats_inc(stat_rx_packets);
3069 nv_txrx_stats_add(stat_rx_bytes, len);
3070 u64_stats_update_end(&np->swstats_rx_syncp);
3071 } else {
3072 dev_kfree_skb(skb);
3073 }
3074next_pkt:
3075 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
3076 np->get_rx.ex = np->rx_ring.ex;
3077 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
3078 np->get_rx_ctx = np->rx_skb;
3079
3080 rx_work++;
3081 }
3082
3083 return rx_work;
3084}
3085
3086static void set_bufsize(struct net_device *dev)
3087{
3088 struct fe_priv *np = netdev_priv(dev);
3089
3090 if (dev->mtu <= ETH_DATA_LEN)
3091 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
3092 else
3093 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
3094}
3095
3096/*
3097 * nv_change_mtu: dev->change_mtu function
3098 * Called with dev_base_lock held for read.
3099 */
3100static int nv_change_mtu(struct net_device *dev, int new_mtu)
3101{
3102 struct fe_priv *np = netdev_priv(dev);
3103 int old_mtu;
3104
3105 old_mtu = dev->mtu;
3106 dev->mtu = new_mtu;
3107
3108 /* return early if the buffer sizes will not change */
3109 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
3110 return 0;
3111
3112 /* synchronized against open : rtnl_lock() held by caller */
3113 if (netif_running(dev)) {
3114 u8 __iomem *base = get_hwbase(dev);
3115 /*
3116 * It seems that the nic preloads valid ring entries into an
3117 * internal buffer. The procedure for flushing everything is
3118 * guessed, there is probably a simpler approach.
3119 * Changing the MTU is a rare event, it shouldn't matter.
3120 */
3121 nv_disable_irq(dev);
3122 nv_napi_disable(dev);
3123 netif_tx_lock_bh(dev);
3124 netif_addr_lock(dev);
3125 spin_lock(&np->lock);
3126 /* stop engines */
3127 nv_stop_rxtx(dev);
3128 nv_txrx_reset(dev);
3129 /* drain rx queue */
3130 nv_drain_rxtx(dev);
3131 /* reinit driver view of the rx queue */
3132 set_bufsize(dev);
3133 if (nv_init_ring(dev)) {
3134 if (!np->in_shutdown)
3135 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3136 }
3137 /* reinit nic view of the rx queue */
3138 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3139 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3140 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3141 base + NvRegRingSizes);
3142 pci_push(base);
3143 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3144 pci_push(base);
3145
3146 /* restart rx engine */
3147 nv_start_rxtx(dev);
3148 spin_unlock(&np->lock);
3149 netif_addr_unlock(dev);
3150 netif_tx_unlock_bh(dev);
3151 nv_napi_enable(dev);
3152 nv_enable_irq(dev);
3153 }
3154 return 0;
3155}
3156
3157static void nv_copy_mac_to_hw(struct net_device *dev)
3158{
3159 u8 __iomem *base = get_hwbase(dev);
3160 u32 mac[2];
3161
3162 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
3163 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
3164 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
3165
3166 writel(mac[0], base + NvRegMacAddrA);
3167 writel(mac[1], base + NvRegMacAddrB);
3168}
3169
3170/*
3171 * nv_set_mac_address: dev->set_mac_address function
3172 * Called with rtnl_lock() held.
3173 */
3174static int nv_set_mac_address(struct net_device *dev, void *addr)
3175{
3176 struct fe_priv *np = netdev_priv(dev);
3177 struct sockaddr *macaddr = (struct sockaddr *)addr;
3178
3179 if (!is_valid_ether_addr(macaddr->sa_data))
3180 return -EADDRNOTAVAIL;
3181
3182 /* synchronized against open : rtnl_lock() held by caller */
3183 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
3184
3185 if (netif_running(dev)) {
3186 netif_tx_lock_bh(dev);
3187 netif_addr_lock(dev);
3188 spin_lock_irq(&np->lock);
3189
3190 /* stop rx engine */
3191 nv_stop_rx(dev);
3192
3193 /* set mac address */
3194 nv_copy_mac_to_hw(dev);
3195
3196 /* restart rx engine */
3197 nv_start_rx(dev);
3198 spin_unlock_irq(&np->lock);
3199 netif_addr_unlock(dev);
3200 netif_tx_unlock_bh(dev);
3201 } else {
3202 nv_copy_mac_to_hw(dev);
3203 }
3204 return 0;
3205}
3206
3207/*
3208 * nv_set_multicast: dev->set_multicast function
3209 * Called with netif_tx_lock held.
3210 */
3211static void nv_set_multicast(struct net_device *dev)
3212{
3213 struct fe_priv *np = netdev_priv(dev);
3214 u8 __iomem *base = get_hwbase(dev);
3215 u32 addr[2];
3216 u32 mask[2];
3217 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3218
3219 memset(addr, 0, sizeof(addr));
3220 memset(mask, 0, sizeof(mask));
3221
3222 if (dev->flags & IFF_PROMISC) {
3223 pff |= NVREG_PFF_PROMISC;
3224 } else {
3225 pff |= NVREG_PFF_MYADDR;
3226
3227 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
3228 u32 alwaysOff[2];
3229 u32 alwaysOn[2];
3230
3231 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3232 if (dev->flags & IFF_ALLMULTI) {
3233 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3234 } else {
3235 struct netdev_hw_addr *ha;
3236
3237 netdev_for_each_mc_addr(ha, dev) {
3238 unsigned char *hw_addr = ha->addr;
3239 u32 a, b;
3240
3241 a = le32_to_cpu(*(__le32 *) hw_addr);
3242 b = le16_to_cpu(*(__le16 *) (&hw_addr[4]));
3243 alwaysOn[0] &= a;
3244 alwaysOff[0] &= ~a;
3245 alwaysOn[1] &= b;
3246 alwaysOff[1] &= ~b;
3247 }
3248 }
3249 addr[0] = alwaysOn[0];
3250 addr[1] = alwaysOn[1];
3251 mask[0] = alwaysOn[0] | alwaysOff[0];
3252 mask[1] = alwaysOn[1] | alwaysOff[1];
3253 } else {
3254 mask[0] = NVREG_MCASTMASKA_NONE;
3255 mask[1] = NVREG_MCASTMASKB_NONE;
3256 }
3257 }
3258 addr[0] |= NVREG_MCASTADDRA_FORCE;
3259 pff |= NVREG_PFF_ALWAYS;
3260 spin_lock_irq(&np->lock);
3261 nv_stop_rx(dev);
3262 writel(addr[0], base + NvRegMulticastAddrA);
3263 writel(addr[1], base + NvRegMulticastAddrB);
3264 writel(mask[0], base + NvRegMulticastMaskA);
3265 writel(mask[1], base + NvRegMulticastMaskB);
3266 writel(pff, base + NvRegPacketFilterFlags);
3267 nv_start_rx(dev);
3268 spin_unlock_irq(&np->lock);
3269}
3270
3271static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3272{
3273 struct fe_priv *np = netdev_priv(dev);
3274 u8 __iomem *base = get_hwbase(dev);
3275
3276 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3277
3278 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3279 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3280 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3281 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3282 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3283 } else {
3284 writel(pff, base + NvRegPacketFilterFlags);
3285 }
3286 }
3287 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3288 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3289 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3290 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3291 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3292 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3293 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3294 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3295 /* limit the number of tx pause frames to a default of 8 */
3296 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3297 }
3298 writel(pause_enable, base + NvRegTxPauseFrame);
3299 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3300 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3301 } else {
3302 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3303 writel(regmisc, base + NvRegMisc1);
3304 }
3305 }
3306}
3307
3308static void nv_force_linkspeed(struct net_device *dev, int speed, int duplex)
3309{
3310 struct fe_priv *np = netdev_priv(dev);
3311 u8 __iomem *base = get_hwbase(dev);
3312 u32 phyreg, txreg;
3313 int mii_status;
3314
3315 np->linkspeed = NVREG_LINKSPEED_FORCE|speed;
3316 np->duplex = duplex;
3317
3318 /* see if gigabit phy */
3319 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3320 if (mii_status & PHY_GIGABIT) {
3321 np->gigabit = PHY_GIGABIT;
3322 phyreg = readl(base + NvRegSlotTime);
3323 phyreg &= ~(0x3FF00);
3324 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
3325 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3326 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
3327 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3328 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3329 phyreg |= NVREG_SLOTTIME_1000_FULL;
3330 writel(phyreg, base + NvRegSlotTime);
3331 }
3332
3333 phyreg = readl(base + NvRegPhyInterface);
3334 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3335 if (np->duplex == 0)
3336 phyreg |= PHY_HALF;
3337 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3338 phyreg |= PHY_100;
3339 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3340 NVREG_LINKSPEED_1000)
3341 phyreg |= PHY_1000;
3342 writel(phyreg, base + NvRegPhyInterface);
3343
3344 if (phyreg & PHY_RGMII) {
3345 if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3346 NVREG_LINKSPEED_1000)
3347 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3348 else
3349 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3350 } else {
3351 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3352 }
3353 writel(txreg, base + NvRegTxDeferral);
3354
3355 if (np->desc_ver == DESC_VER_1) {
3356 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3357 } else {
3358 if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3359 NVREG_LINKSPEED_1000)
3360 txreg = NVREG_TX_WM_DESC2_3_1000;
3361 else
3362 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3363 }
3364 writel(txreg, base + NvRegTxWatermark);
3365
3366 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3367 base + NvRegMisc1);
3368 pci_push(base);
3369 writel(np->linkspeed, base + NvRegLinkSpeed);
3370 pci_push(base);
3371}
3372
3373/**
3374 * nv_update_linkspeed - Setup the MAC according to the link partner
3375 * @dev: Network device to be configured
3376 *
3377 * The function queries the PHY and checks if there is a link partner.
3378 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3379 * set to 10 MBit HD.
3380 *
3381 * The function returns 0 if there is no link partner and 1 if there is
3382 * a good link partner.
3383 */
3384static int nv_update_linkspeed(struct net_device *dev)
3385{
3386 struct fe_priv *np = netdev_priv(dev);
3387 u8 __iomem *base = get_hwbase(dev);
3388 int adv = 0;
3389 int lpa = 0;
3390 int adv_lpa, adv_pause, lpa_pause;
3391 int newls = np->linkspeed;
3392 int newdup = np->duplex;
3393 int mii_status;
3394 u32 bmcr;
3395 int retval = 0;
3396 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3397 u32 txrxFlags = 0;
3398 u32 phy_exp;
3399
3400 /* If device loopback is enabled, set carrier on and enable max link
3401 * speed.
3402 */
3403 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3404 if (bmcr & BMCR_LOOPBACK) {
3405 if (netif_running(dev)) {
3406 nv_force_linkspeed(dev, NVREG_LINKSPEED_1000, 1);
3407 if (!netif_carrier_ok(dev))
3408 netif_carrier_on(dev);
3409 }
3410 return 1;
3411 }
3412
3413 /* BMSR_LSTATUS is latched, read it twice:
3414 * we want the current value.
3415 */
3416 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3417 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3418
3419 if (!(mii_status & BMSR_LSTATUS)) {
3420 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3421 newdup = 0;
3422 retval = 0;
3423 goto set_speed;
3424 }
3425
3426 if (np->autoneg == 0) {
3427 if (np->fixed_mode & LPA_100FULL) {
3428 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3429 newdup = 1;
3430 } else if (np->fixed_mode & LPA_100HALF) {
3431 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3432 newdup = 0;
3433 } else if (np->fixed_mode & LPA_10FULL) {
3434 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3435 newdup = 1;
3436 } else {
3437 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3438 newdup = 0;
3439 }
3440 retval = 1;
3441 goto set_speed;
3442 }
3443 /* check auto negotiation is complete */
3444 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3445 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3446 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3447 newdup = 0;
3448 retval = 0;
3449 goto set_speed;
3450 }
3451
3452 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3453 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3454
3455 retval = 1;
3456 if (np->gigabit == PHY_GIGABIT) {
3457 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3458 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3459
3460 if ((control_1000 & ADVERTISE_1000FULL) &&
3461 (status_1000 & LPA_1000FULL)) {
3462 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3463 newdup = 1;
3464 goto set_speed;
3465 }
3466 }
3467
3468 /* FIXME: handle parallel detection properly */
3469 adv_lpa = lpa & adv;
3470 if (adv_lpa & LPA_100FULL) {
3471 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3472 newdup = 1;
3473 } else if (adv_lpa & LPA_100HALF) {
3474 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3475 newdup = 0;
3476 } else if (adv_lpa & LPA_10FULL) {
3477 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3478 newdup = 1;
3479 } else if (adv_lpa & LPA_10HALF) {
3480 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3481 newdup = 0;
3482 } else {
3483 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3484 newdup = 0;
3485 }
3486
3487set_speed:
3488 if (np->duplex == newdup && np->linkspeed == newls)
3489 return retval;
3490
3491 np->duplex = newdup;
3492 np->linkspeed = newls;
3493
3494 /* The transmitter and receiver must be restarted for safe update */
3495 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3496 txrxFlags |= NV_RESTART_TX;
3497 nv_stop_tx(dev);
3498 }
3499 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3500 txrxFlags |= NV_RESTART_RX;
3501 nv_stop_rx(dev);
3502 }
3503
3504 if (np->gigabit == PHY_GIGABIT) {
3505 phyreg = readl(base + NvRegSlotTime);
3506 phyreg &= ~(0x3FF00);
3507 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3508 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3509 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3510 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3511 phyreg |= NVREG_SLOTTIME_1000_FULL;
3512 writel(phyreg, base + NvRegSlotTime);
3513 }
3514
3515 phyreg = readl(base + NvRegPhyInterface);
3516 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3517 if (np->duplex == 0)
3518 phyreg |= PHY_HALF;
3519 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3520 phyreg |= PHY_100;
3521 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3522 phyreg |= PHY_1000;
3523 writel(phyreg, base + NvRegPhyInterface);
3524
3525 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3526 if (phyreg & PHY_RGMII) {
3527 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3528 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3529 } else {
3530 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3531 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3532 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3533 else
3534 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3535 } else {
3536 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3537 }
3538 }
3539 } else {
3540 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3541 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3542 else
3543 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3544 }
3545 writel(txreg, base + NvRegTxDeferral);
3546
3547 if (np->desc_ver == DESC_VER_1) {
3548 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3549 } else {
3550 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3551 txreg = NVREG_TX_WM_DESC2_3_1000;
3552 else
3553 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3554 }
3555 writel(txreg, base + NvRegTxWatermark);
3556
3557 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3558 base + NvRegMisc1);
3559 pci_push(base);
3560 writel(np->linkspeed, base + NvRegLinkSpeed);
3561 pci_push(base);
3562
3563 pause_flags = 0;
3564 /* setup pause frame */
3565 if (netif_running(dev) && (np->duplex != 0)) {
3566 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3567 adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3568 lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
3569
3570 switch (adv_pause) {
3571 case ADVERTISE_PAUSE_CAP:
3572 if (lpa_pause & LPA_PAUSE_CAP) {
3573 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3574 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3575 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3576 }
3577 break;
3578 case ADVERTISE_PAUSE_ASYM:
3579 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
3580 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3581 break;
3582 case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3583 if (lpa_pause & LPA_PAUSE_CAP) {
3584 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3585 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3586 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3587 }
3588 if (lpa_pause == LPA_PAUSE_ASYM)
3589 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3590 break;
3591 }
3592 } else {
3593 pause_flags = np->pause_flags;
3594 }
3595 }
3596 nv_update_pause(dev, pause_flags);
3597
3598 if (txrxFlags & NV_RESTART_TX)
3599 nv_start_tx(dev);
3600 if (txrxFlags & NV_RESTART_RX)
3601 nv_start_rx(dev);
3602
3603 return retval;
3604}
3605
3606static void nv_linkchange(struct net_device *dev)
3607{
3608 if (nv_update_linkspeed(dev)) {
3609 if (!netif_carrier_ok(dev)) {
3610 netif_carrier_on(dev);
3611 netdev_info(dev, "link up\n");
3612 nv_txrx_gate(dev, false);
3613 nv_start_rx(dev);
3614 }
3615 } else {
3616 if (netif_carrier_ok(dev)) {
3617 netif_carrier_off(dev);
3618 netdev_info(dev, "link down\n");
3619 nv_txrx_gate(dev, true);
3620 nv_stop_rx(dev);
3621 }
3622 }
3623}
3624
3625static void nv_link_irq(struct net_device *dev)
3626{
3627 u8 __iomem *base = get_hwbase(dev);
3628 u32 miistat;
3629
3630 miistat = readl(base + NvRegMIIStatus);
3631 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3632
3633 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3634 nv_linkchange(dev);
3635}
3636
3637static void nv_msi_workaround(struct fe_priv *np)
3638{
3639
3640 /* Need to toggle the msi irq mask within the ethernet device,
3641 * otherwise, future interrupts will not be detected.
3642 */
3643 if (np->msi_flags & NV_MSI_ENABLED) {
3644 u8 __iomem *base = np->base;
3645
3646 writel(0, base + NvRegMSIIrqMask);
3647 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3648 }
3649}
3650
3651static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3652{
3653 struct fe_priv *np = netdev_priv(dev);
3654
3655 if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3656 if (total_work > NV_DYNAMIC_THRESHOLD) {
3657 /* transition to poll based interrupts */
3658 np->quiet_count = 0;
3659 if (np->irqmask != NVREG_IRQMASK_CPU) {
3660 np->irqmask = NVREG_IRQMASK_CPU;
3661 return 1;
3662 }
3663 } else {
3664 if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3665 np->quiet_count++;
3666 } else {
3667 /* reached a period of low activity, switch
3668 to per tx/rx packet interrupts */
3669 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3670 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3671 return 1;
3672 }
3673 }
3674 }
3675 }
3676 return 0;
3677}
3678
3679static irqreturn_t nv_nic_irq(int foo, void *data)
3680{
3681 struct net_device *dev = (struct net_device *) data;
3682 struct fe_priv *np = netdev_priv(dev);
3683 u8 __iomem *base = get_hwbase(dev);
3684
3685 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3686 np->events = readl(base + NvRegIrqStatus);
3687 writel(np->events, base + NvRegIrqStatus);
3688 } else {
3689 np->events = readl(base + NvRegMSIXIrqStatus);
3690 writel(np->events, base + NvRegMSIXIrqStatus);
3691 }
3692 if (!(np->events & np->irqmask))
3693 return IRQ_NONE;
3694
3695 nv_msi_workaround(np);
3696
3697 if (napi_schedule_prep(&np->napi)) {
3698 /*
3699 * Disable further irq's (msix not enabled with napi)
3700 */
3701 writel(0, base + NvRegIrqMask);
3702 __napi_schedule(&np->napi);
3703 }
3704
3705 return IRQ_HANDLED;
3706}
3707
3708/* All _optimized functions are used to help increase performance
3709 * (reduce CPU and increase throughput). They use descripter version 3,
3710 * compiler directives, and reduce memory accesses.
3711 */
3712static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3713{
3714 struct net_device *dev = (struct net_device *) data;
3715 struct fe_priv *np = netdev_priv(dev);
3716 u8 __iomem *base = get_hwbase(dev);
3717
3718 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3719 np->events = readl(base + NvRegIrqStatus);
3720 writel(np->events, base + NvRegIrqStatus);
3721 } else {
3722 np->events = readl(base + NvRegMSIXIrqStatus);
3723 writel(np->events, base + NvRegMSIXIrqStatus);
3724 }
3725 if (!(np->events & np->irqmask))
3726 return IRQ_NONE;
3727
3728 nv_msi_workaround(np);
3729
3730 if (napi_schedule_prep(&np->napi)) {
3731 /*
3732 * Disable further irq's (msix not enabled with napi)
3733 */
3734 writel(0, base + NvRegIrqMask);
3735 __napi_schedule(&np->napi);
3736 }
3737
3738 return IRQ_HANDLED;
3739}
3740
3741static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3742{
3743 struct net_device *dev = (struct net_device *) data;
3744 struct fe_priv *np = netdev_priv(dev);
3745 u8 __iomem *base = get_hwbase(dev);
3746 u32 events;
3747 int i;
3748 unsigned long flags;
3749
3750 for (i = 0;; i++) {
3751 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3752 writel(events, base + NvRegMSIXIrqStatus);
3753 netdev_dbg(dev, "tx irq events: %08x\n", events);
3754 if (!(events & np->irqmask))
3755 break;
3756
3757 spin_lock_irqsave(&np->lock, flags);
3758 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3759 spin_unlock_irqrestore(&np->lock, flags);
3760
3761 if (unlikely(i > max_interrupt_work)) {
3762 spin_lock_irqsave(&np->lock, flags);
3763 /* disable interrupts on the nic */
3764 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3765 pci_push(base);
3766
3767 if (!np->in_shutdown) {
3768 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3769 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3770 }
3771 spin_unlock_irqrestore(&np->lock, flags);
3772 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3773 __func__, i);
3774 break;
3775 }
3776
3777 }
3778
3779 return IRQ_RETVAL(i);
3780}
3781
3782static int nv_napi_poll(struct napi_struct *napi, int budget)
3783{
3784 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3785 struct net_device *dev = np->dev;
3786 u8 __iomem *base = get_hwbase(dev);
3787 unsigned long flags;
3788 int retcode;
3789 int rx_count, tx_work = 0, rx_work = 0;
3790
3791 do {
3792 if (!nv_optimized(np)) {
3793 spin_lock_irqsave(&np->lock, flags);
3794 tx_work += nv_tx_done(dev, np->tx_ring_size);
3795 spin_unlock_irqrestore(&np->lock, flags);
3796
3797 rx_count = nv_rx_process(dev, budget - rx_work);
3798 retcode = nv_alloc_rx(dev);
3799 } else {
3800 spin_lock_irqsave(&np->lock, flags);
3801 tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3802 spin_unlock_irqrestore(&np->lock, flags);
3803
3804 rx_count = nv_rx_process_optimized(dev,
3805 budget - rx_work);
3806 retcode = nv_alloc_rx_optimized(dev);
3807 }
3808 } while (retcode == 0 &&
3809 rx_count > 0 && (rx_work += rx_count) < budget);
3810
3811 if (retcode) {
3812 spin_lock_irqsave(&np->lock, flags);
3813 if (!np->in_shutdown)
3814 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3815 spin_unlock_irqrestore(&np->lock, flags);
3816 }
3817
3818 nv_change_interrupt_mode(dev, tx_work + rx_work);
3819
3820 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3821 spin_lock_irqsave(&np->lock, flags);
3822 nv_link_irq(dev);
3823 spin_unlock_irqrestore(&np->lock, flags);
3824 }
3825 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3826 spin_lock_irqsave(&np->lock, flags);
3827 nv_linkchange(dev);
3828 spin_unlock_irqrestore(&np->lock, flags);
3829 np->link_timeout = jiffies + LINK_TIMEOUT;
3830 }
3831 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3832 spin_lock_irqsave(&np->lock, flags);
3833 if (!np->in_shutdown) {
3834 np->nic_poll_irq = np->irqmask;
3835 np->recover_error = 1;
3836 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3837 }
3838 spin_unlock_irqrestore(&np->lock, flags);
3839 napi_complete(napi);
3840 return rx_work;
3841 }
3842
3843 if (rx_work < budget) {
3844 /* re-enable interrupts
3845 (msix not enabled in napi) */
3846 napi_complete_done(napi, rx_work);
3847
3848 writel(np->irqmask, base + NvRegIrqMask);
3849 }
3850 return rx_work;
3851}
3852
3853static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3854{
3855 struct net_device *dev = (struct net_device *) data;
3856 struct fe_priv *np = netdev_priv(dev);
3857 u8 __iomem *base = get_hwbase(dev);
3858 u32 events;
3859 int i;
3860 unsigned long flags;
3861
3862 for (i = 0;; i++) {
3863 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3864 writel(events, base + NvRegMSIXIrqStatus);
3865 netdev_dbg(dev, "rx irq events: %08x\n", events);
3866 if (!(events & np->irqmask))
3867 break;
3868
3869 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3870 if (unlikely(nv_alloc_rx_optimized(dev))) {
3871 spin_lock_irqsave(&np->lock, flags);
3872 if (!np->in_shutdown)
3873 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3874 spin_unlock_irqrestore(&np->lock, flags);
3875 }
3876 }
3877
3878 if (unlikely(i > max_interrupt_work)) {
3879 spin_lock_irqsave(&np->lock, flags);
3880 /* disable interrupts on the nic */
3881 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3882 pci_push(base);
3883
3884 if (!np->in_shutdown) {
3885 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3886 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3887 }
3888 spin_unlock_irqrestore(&np->lock, flags);
3889 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3890 __func__, i);
3891 break;
3892 }
3893 }
3894
3895 return IRQ_RETVAL(i);
3896}
3897
3898static irqreturn_t nv_nic_irq_other(int foo, void *data)
3899{
3900 struct net_device *dev = (struct net_device *) data;
3901 struct fe_priv *np = netdev_priv(dev);
3902 u8 __iomem *base = get_hwbase(dev);
3903 u32 events;
3904 int i;
3905 unsigned long flags;
3906
3907 for (i = 0;; i++) {
3908 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3909 writel(events, base + NvRegMSIXIrqStatus);
3910 netdev_dbg(dev, "irq events: %08x\n", events);
3911 if (!(events & np->irqmask))
3912 break;
3913
3914 /* check tx in case we reached max loop limit in tx isr */
3915 spin_lock_irqsave(&np->lock, flags);
3916 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3917 spin_unlock_irqrestore(&np->lock, flags);
3918
3919 if (events & NVREG_IRQ_LINK) {
3920 spin_lock_irqsave(&np->lock, flags);
3921 nv_link_irq(dev);
3922 spin_unlock_irqrestore(&np->lock, flags);
3923 }
3924 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3925 spin_lock_irqsave(&np->lock, flags);
3926 nv_linkchange(dev);
3927 spin_unlock_irqrestore(&np->lock, flags);
3928 np->link_timeout = jiffies + LINK_TIMEOUT;
3929 }
3930 if (events & NVREG_IRQ_RECOVER_ERROR) {
3931 spin_lock_irqsave(&np->lock, flags);
3932 /* disable interrupts on the nic */
3933 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3934 pci_push(base);
3935
3936 if (!np->in_shutdown) {
3937 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3938 np->recover_error = 1;
3939 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3940 }
3941 spin_unlock_irqrestore(&np->lock, flags);
3942 break;
3943 }
3944 if (unlikely(i > max_interrupt_work)) {
3945 spin_lock_irqsave(&np->lock, flags);
3946 /* disable interrupts on the nic */
3947 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3948 pci_push(base);
3949
3950 if (!np->in_shutdown) {
3951 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3952 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3953 }
3954 spin_unlock_irqrestore(&np->lock, flags);
3955 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3956 __func__, i);
3957 break;
3958 }
3959
3960 }
3961
3962 return IRQ_RETVAL(i);
3963}
3964
3965static irqreturn_t nv_nic_irq_test(int foo, void *data)
3966{
3967 struct net_device *dev = (struct net_device *) data;
3968 struct fe_priv *np = netdev_priv(dev);
3969 u8 __iomem *base = get_hwbase(dev);
3970 u32 events;
3971
3972 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3973 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3974 writel(events & NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3975 } else {
3976 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3977 writel(events & NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3978 }
3979 pci_push(base);
3980 if (!(events & NVREG_IRQ_TIMER))
3981 return IRQ_RETVAL(0);
3982
3983 nv_msi_workaround(np);
3984
3985 spin_lock(&np->lock);
3986 np->intr_test = 1;
3987 spin_unlock(&np->lock);
3988
3989 return IRQ_RETVAL(1);
3990}
3991
3992static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3993{
3994 u8 __iomem *base = get_hwbase(dev);
3995 int i;
3996 u32 msixmap = 0;
3997
3998 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3999 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
4000 * the remaining 8 interrupts.
4001 */
4002 for (i = 0; i < 8; i++) {
4003 if ((irqmask >> i) & 0x1)
4004 msixmap |= vector << (i << 2);
4005 }
4006 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
4007
4008 msixmap = 0;
4009 for (i = 0; i < 8; i++) {
4010 if ((irqmask >> (i + 8)) & 0x1)
4011 msixmap |= vector << (i << 2);
4012 }
4013 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
4014}
4015
4016static int nv_request_irq(struct net_device *dev, int intr_test)
4017{
4018 struct fe_priv *np = get_nvpriv(dev);
4019 u8 __iomem *base = get_hwbase(dev);
4020 int ret;
4021 int i;
4022 irqreturn_t (*handler)(int foo, void *data);
4023
4024 if (intr_test) {
4025 handler = nv_nic_irq_test;
4026 } else {
4027 if (nv_optimized(np))
4028 handler = nv_nic_irq_optimized;
4029 else
4030 handler = nv_nic_irq;
4031 }
4032
4033 if (np->msi_flags & NV_MSI_X_CAPABLE) {
4034 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
4035 np->msi_x_entry[i].entry = i;
4036 ret = pci_enable_msix_range(np->pci_dev,
4037 np->msi_x_entry,
4038 np->msi_flags & NV_MSI_X_VECTORS_MASK,
4039 np->msi_flags & NV_MSI_X_VECTORS_MASK);
4040 if (ret > 0) {
4041 np->msi_flags |= NV_MSI_X_ENABLED;
4042 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
4043 /* Request irq for rx handling */
4044 sprintf(np->name_rx, "%s-rx", dev->name);
4045 ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
4046 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev);
4047 if (ret) {
4048 netdev_info(dev,
4049 "request_irq failed for rx %d\n",
4050 ret);
4051 pci_disable_msix(np->pci_dev);
4052 np->msi_flags &= ~NV_MSI_X_ENABLED;
4053 goto out_err;
4054 }
4055 /* Request irq for tx handling */
4056 sprintf(np->name_tx, "%s-tx", dev->name);
4057 ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
4058 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev);
4059 if (ret) {
4060 netdev_info(dev,
4061 "request_irq failed for tx %d\n",
4062 ret);
4063 pci_disable_msix(np->pci_dev);
4064 np->msi_flags &= ~NV_MSI_X_ENABLED;
4065 goto out_free_rx;
4066 }
4067 /* Request irq for link and timer handling */
4068 sprintf(np->name_other, "%s-other", dev->name);
4069 ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
4070 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev);
4071 if (ret) {
4072 netdev_info(dev,
4073 "request_irq failed for link %d\n",
4074 ret);
4075 pci_disable_msix(np->pci_dev);
4076 np->msi_flags &= ~NV_MSI_X_ENABLED;
4077 goto out_free_tx;
4078 }
4079 /* map interrupts to their respective vector */
4080 writel(0, base + NvRegMSIXMap0);
4081 writel(0, base + NvRegMSIXMap1);
4082 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
4083 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
4084 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
4085 } else {
4086 /* Request irq for all interrupts */
4087 ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector,
4088 handler, IRQF_SHARED, dev->name, dev);
4089 if (ret) {
4090 netdev_info(dev,
4091 "request_irq failed %d\n",
4092 ret);
4093 pci_disable_msix(np->pci_dev);
4094 np->msi_flags &= ~NV_MSI_X_ENABLED;
4095 goto out_err;
4096 }
4097
4098 /* map interrupts to vector 0 */
4099 writel(0, base + NvRegMSIXMap0);
4100 writel(0, base + NvRegMSIXMap1);
4101 }
4102 netdev_info(dev, "MSI-X enabled\n");
4103 return 0;
4104 }
4105 }
4106 if (np->msi_flags & NV_MSI_CAPABLE) {
4107 ret = pci_enable_msi(np->pci_dev);
4108 if (ret == 0) {
4109 np->msi_flags |= NV_MSI_ENABLED;
4110 ret = request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev);
4111 if (ret) {
4112 netdev_info(dev, "request_irq failed %d\n",
4113 ret);
4114 pci_disable_msi(np->pci_dev);
4115 np->msi_flags &= ~NV_MSI_ENABLED;
4116 goto out_err;
4117 }
4118
4119 /* map interrupts to vector 0 */
4120 writel(0, base + NvRegMSIMap0);
4121 writel(0, base + NvRegMSIMap1);
4122 /* enable msi vector 0 */
4123 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
4124 netdev_info(dev, "MSI enabled\n");
4125 return 0;
4126 }
4127 }
4128
4129 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
4130 goto out_err;
4131
4132 return 0;
4133out_free_tx:
4134 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
4135out_free_rx:
4136 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
4137out_err:
4138 return 1;
4139}
4140
4141static void nv_free_irq(struct net_device *dev)
4142{
4143 struct fe_priv *np = get_nvpriv(dev);
4144 int i;
4145
4146 if (np->msi_flags & NV_MSI_X_ENABLED) {
4147 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
4148 free_irq(np->msi_x_entry[i].vector, dev);
4149 pci_disable_msix(np->pci_dev);
4150 np->msi_flags &= ~NV_MSI_X_ENABLED;
4151 } else {
4152 free_irq(np->pci_dev->irq, dev);
4153 if (np->msi_flags & NV_MSI_ENABLED) {
4154 pci_disable_msi(np->pci_dev);
4155 np->msi_flags &= ~NV_MSI_ENABLED;
4156 }
4157 }
4158}
4159
4160static void nv_do_nic_poll(struct timer_list *t)
4161{
4162 struct fe_priv *np = from_timer(np, t, nic_poll);
4163 struct net_device *dev = np->dev;
4164 u8 __iomem *base = get_hwbase(dev);
4165 u32 mask = 0;
4166 unsigned long flags;
4167 unsigned int irq = 0;
4168
4169 /*
4170 * First disable irq(s) and then
4171 * reenable interrupts on the nic, we have to do this before calling
4172 * nv_nic_irq because that may decide to do otherwise
4173 */
4174
4175 if (!using_multi_irqs(dev)) {
4176 if (np->msi_flags & NV_MSI_X_ENABLED)
4177 irq = np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector;
4178 else
4179 irq = np->pci_dev->irq;
4180 mask = np->irqmask;
4181 } else {
4182 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4183 irq = np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector;
4184 mask |= NVREG_IRQ_RX_ALL;
4185 }
4186 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4187 irq = np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector;
4188 mask |= NVREG_IRQ_TX_ALL;
4189 }
4190 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4191 irq = np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector;
4192 mask |= NVREG_IRQ_OTHER;
4193 }
4194 }
4195
4196 disable_irq_nosync_lockdep_irqsave(irq, &flags);
4197 synchronize_irq(irq);
4198
4199 if (np->recover_error) {
4200 np->recover_error = 0;
4201 netdev_info(dev, "MAC in recoverable error state\n");
4202 if (netif_running(dev)) {
4203 netif_tx_lock_bh(dev);
4204 netif_addr_lock(dev);
4205 spin_lock(&np->lock);
4206 /* stop engines */
4207 nv_stop_rxtx(dev);
4208 if (np->driver_data & DEV_HAS_POWER_CNTRL)
4209 nv_mac_reset(dev);
4210 nv_txrx_reset(dev);
4211 /* drain rx queue */
4212 nv_drain_rxtx(dev);
4213 /* reinit driver view of the rx queue */
4214 set_bufsize(dev);
4215 if (nv_init_ring(dev)) {
4216 if (!np->in_shutdown)
4217 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4218 }
4219 /* reinit nic view of the rx queue */
4220 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4221 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4222 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4223 base + NvRegRingSizes);
4224 pci_push(base);
4225 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4226 pci_push(base);
4227 /* clear interrupts */
4228 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4229 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4230 else
4231 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4232
4233 /* restart rx engine */
4234 nv_start_rxtx(dev);
4235 spin_unlock(&np->lock);
4236 netif_addr_unlock(dev);
4237 netif_tx_unlock_bh(dev);
4238 }
4239 }
4240
4241 writel(mask, base + NvRegIrqMask);
4242 pci_push(base);
4243
4244 if (!using_multi_irqs(dev)) {
4245 np->nic_poll_irq = 0;
4246 if (nv_optimized(np))
4247 nv_nic_irq_optimized(0, dev);
4248 else
4249 nv_nic_irq(0, dev);
4250 } else {
4251 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4252 np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4253 nv_nic_irq_rx(0, dev);
4254 }
4255 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4256 np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4257 nv_nic_irq_tx(0, dev);
4258 }
4259 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4260 np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4261 nv_nic_irq_other(0, dev);
4262 }
4263 }
4264
4265 enable_irq_lockdep_irqrestore(irq, &flags);
4266}
4267
4268#ifdef CONFIG_NET_POLL_CONTROLLER
4269static void nv_poll_controller(struct net_device *dev)
4270{
4271 struct fe_priv *np = netdev_priv(dev);
4272
4273 nv_do_nic_poll(&np->nic_poll);
4274}
4275#endif
4276
4277static void nv_do_stats_poll(struct timer_list *t)
4278 __acquires(&netdev_priv(dev)->hwstats_lock)
4279 __releases(&netdev_priv(dev)->hwstats_lock)
4280{
4281 struct fe_priv *np = from_timer(np, t, stats_poll);
4282 struct net_device *dev = np->dev;
4283
4284 /* If lock is currently taken, the stats are being refreshed
4285 * and hence fresh enough */
4286 if (spin_trylock(&np->hwstats_lock)) {
4287 nv_update_stats(dev);
4288 spin_unlock(&np->hwstats_lock);
4289 }
4290
4291 if (!np->in_shutdown)
4292 mod_timer(&np->stats_poll,
4293 round_jiffies(jiffies + STATS_INTERVAL));
4294}
4295
4296static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4297{
4298 struct fe_priv *np = netdev_priv(dev);
4299 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
4300 strlcpy(info->version, FORCEDETH_VERSION, sizeof(info->version));
4301 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
4302}
4303
4304static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4305{
4306 struct fe_priv *np = netdev_priv(dev);
4307 wolinfo->supported = WAKE_MAGIC;
4308
4309 spin_lock_irq(&np->lock);
4310 if (np->wolenabled)
4311 wolinfo->wolopts = WAKE_MAGIC;
4312 spin_unlock_irq(&np->lock);
4313}
4314
4315static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4316{
4317 struct fe_priv *np = netdev_priv(dev);
4318 u8 __iomem *base = get_hwbase(dev);
4319 u32 flags = 0;
4320
4321 if (wolinfo->wolopts == 0) {
4322 np->wolenabled = 0;
4323 } else if (wolinfo->wolopts & WAKE_MAGIC) {
4324 np->wolenabled = 1;
4325 flags = NVREG_WAKEUPFLAGS_ENABLE;
4326 }
4327 if (netif_running(dev)) {
4328 spin_lock_irq(&np->lock);
4329 writel(flags, base + NvRegWakeUpFlags);
4330 spin_unlock_irq(&np->lock);
4331 }
4332 device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
4333 return 0;
4334}
4335
4336static int nv_get_link_ksettings(struct net_device *dev,
4337 struct ethtool_link_ksettings *cmd)
4338{
4339 struct fe_priv *np = netdev_priv(dev);
4340 u32 speed, supported, advertising;
4341 int adv;
4342
4343 spin_lock_irq(&np->lock);
4344 cmd->base.port = PORT_MII;
4345 if (!netif_running(dev)) {
4346 /* We do not track link speed / duplex setting if the
4347 * interface is disabled. Force a link check */
4348 if (nv_update_linkspeed(dev)) {
4349 netif_carrier_on(dev);
4350 } else {
4351 netif_carrier_off(dev);
4352 }
4353 }
4354
4355 if (netif_carrier_ok(dev)) {
4356 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4357 case NVREG_LINKSPEED_10:
4358 speed = SPEED_10;
4359 break;
4360 case NVREG_LINKSPEED_100:
4361 speed = SPEED_100;
4362 break;
4363 case NVREG_LINKSPEED_1000:
4364 speed = SPEED_1000;
4365 break;
4366 default:
4367 speed = -1;
4368 break;
4369 }
4370 cmd->base.duplex = DUPLEX_HALF;
4371 if (np->duplex)
4372 cmd->base.duplex = DUPLEX_FULL;
4373 } else {
4374 speed = SPEED_UNKNOWN;
4375 cmd->base.duplex = DUPLEX_UNKNOWN;
4376 }
4377 cmd->base.speed = speed;
4378 cmd->base.autoneg = np->autoneg;
4379
4380 advertising = ADVERTISED_MII;
4381 if (np->autoneg) {
4382 advertising |= ADVERTISED_Autoneg;
4383 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4384 if (adv & ADVERTISE_10HALF)
4385 advertising |= ADVERTISED_10baseT_Half;
4386 if (adv & ADVERTISE_10FULL)
4387 advertising |= ADVERTISED_10baseT_Full;
4388 if (adv & ADVERTISE_100HALF)
4389 advertising |= ADVERTISED_100baseT_Half;
4390 if (adv & ADVERTISE_100FULL)
4391 advertising |= ADVERTISED_100baseT_Full;
4392 if (np->gigabit == PHY_GIGABIT) {
4393 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4394 if (adv & ADVERTISE_1000FULL)
4395 advertising |= ADVERTISED_1000baseT_Full;
4396 }
4397 }
4398 supported = (SUPPORTED_Autoneg |
4399 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4400 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4401 SUPPORTED_MII);
4402 if (np->gigabit == PHY_GIGABIT)
4403 supported |= SUPPORTED_1000baseT_Full;
4404
4405 cmd->base.phy_address = np->phyaddr;
4406
4407 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
4408 supported);
4409 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
4410 advertising);
4411
4412 /* ignore maxtxpkt, maxrxpkt for now */
4413 spin_unlock_irq(&np->lock);
4414 return 0;
4415}
4416
4417static int nv_set_link_ksettings(struct net_device *dev,
4418 const struct ethtool_link_ksettings *cmd)
4419{
4420 struct fe_priv *np = netdev_priv(dev);
4421 u32 speed = cmd->base.speed;
4422 u32 advertising;
4423
4424 ethtool_convert_link_mode_to_legacy_u32(&advertising,
4425 cmd->link_modes.advertising);
4426
4427 if (cmd->base.port != PORT_MII)
4428 return -EINVAL;
4429 if (cmd->base.phy_address != np->phyaddr) {
4430 /* TODO: support switching between multiple phys. Should be
4431 * trivial, but not enabled due to lack of test hardware. */
4432 return -EINVAL;
4433 }
4434 if (cmd->base.autoneg == AUTONEG_ENABLE) {
4435 u32 mask;
4436
4437 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4438 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4439 if (np->gigabit == PHY_GIGABIT)
4440 mask |= ADVERTISED_1000baseT_Full;
4441
4442 if ((advertising & mask) == 0)
4443 return -EINVAL;
4444
4445 } else if (cmd->base.autoneg == AUTONEG_DISABLE) {
4446 /* Note: autonegotiation disable, speed 1000 intentionally
4447 * forbidden - no one should need that. */
4448
4449 if (speed != SPEED_10 && speed != SPEED_100)
4450 return -EINVAL;
4451 if (cmd->base.duplex != DUPLEX_HALF &&
4452 cmd->base.duplex != DUPLEX_FULL)
4453 return -EINVAL;
4454 } else {
4455 return -EINVAL;
4456 }
4457
4458 netif_carrier_off(dev);
4459 if (netif_running(dev)) {
4460 unsigned long flags;
4461
4462 nv_disable_irq(dev);
4463 netif_tx_lock_bh(dev);
4464 netif_addr_lock(dev);
4465 /* with plain spinlock lockdep complains */
4466 spin_lock_irqsave(&np->lock, flags);
4467 /* stop engines */
4468 /* FIXME:
4469 * this can take some time, and interrupts are disabled
4470 * due to spin_lock_irqsave, but let's hope no daemon
4471 * is going to change the settings very often...
4472 * Worst case:
4473 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4474 * + some minor delays, which is up to a second approximately
4475 */
4476 nv_stop_rxtx(dev);
4477 spin_unlock_irqrestore(&np->lock, flags);
4478 netif_addr_unlock(dev);
4479 netif_tx_unlock_bh(dev);
4480 }
4481
4482 if (cmd->base.autoneg == AUTONEG_ENABLE) {
4483 int adv, bmcr;
4484
4485 np->autoneg = 1;
4486
4487 /* advertise only what has been requested */
4488 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4489 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4490 if (advertising & ADVERTISED_10baseT_Half)
4491 adv |= ADVERTISE_10HALF;
4492 if (advertising & ADVERTISED_10baseT_Full)
4493 adv |= ADVERTISE_10FULL;
4494 if (advertising & ADVERTISED_100baseT_Half)
4495 adv |= ADVERTISE_100HALF;
4496 if (advertising & ADVERTISED_100baseT_Full)
4497 adv |= ADVERTISE_100FULL;
4498 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4499 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4500 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4501 adv |= ADVERTISE_PAUSE_ASYM;
4502 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4503
4504 if (np->gigabit == PHY_GIGABIT) {
4505 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4506 adv &= ~ADVERTISE_1000FULL;
4507 if (advertising & ADVERTISED_1000baseT_Full)
4508 adv |= ADVERTISE_1000FULL;
4509 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4510 }
4511
4512 if (netif_running(dev))
4513 netdev_info(dev, "link down\n");
4514 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4515 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4516 bmcr |= BMCR_ANENABLE;
4517 /* reset the phy in order for settings to stick,
4518 * and cause autoneg to start */
4519 if (phy_reset(dev, bmcr)) {
4520 netdev_info(dev, "phy reset failed\n");
4521 return -EINVAL;
4522 }
4523 } else {
4524 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4525 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4526 }
4527 } else {
4528 int adv, bmcr;
4529
4530 np->autoneg = 0;
4531
4532 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4533 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4534 if (speed == SPEED_10 && cmd->base.duplex == DUPLEX_HALF)
4535 adv |= ADVERTISE_10HALF;
4536 if (speed == SPEED_10 && cmd->base.duplex == DUPLEX_FULL)
4537 adv |= ADVERTISE_10FULL;
4538 if (speed == SPEED_100 && cmd->base.duplex == DUPLEX_HALF)
4539 adv |= ADVERTISE_100HALF;
4540 if (speed == SPEED_100 && cmd->base.duplex == DUPLEX_FULL)
4541 adv |= ADVERTISE_100FULL;
4542 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4543 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */
4544 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4545 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4546 }
4547 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4548 adv |= ADVERTISE_PAUSE_ASYM;
4549 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4550 }
4551 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4552 np->fixed_mode = adv;
4553
4554 if (np->gigabit == PHY_GIGABIT) {
4555 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4556 adv &= ~ADVERTISE_1000FULL;
4557 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4558 }
4559
4560 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4561 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4562 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4563 bmcr |= BMCR_FULLDPLX;
4564 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4565 bmcr |= BMCR_SPEED100;
4566 if (np->phy_oui == PHY_OUI_MARVELL) {
4567 /* reset the phy in order for forced mode settings to stick */
4568 if (phy_reset(dev, bmcr)) {
4569 netdev_info(dev, "phy reset failed\n");
4570 return -EINVAL;
4571 }
4572 } else {
4573 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4574 if (netif_running(dev)) {
4575 /* Wait a bit and then reconfigure the nic. */
4576 udelay(10);
4577 nv_linkchange(dev);
4578 }
4579 }
4580 }
4581
4582 if (netif_running(dev)) {
4583 nv_start_rxtx(dev);
4584 nv_enable_irq(dev);
4585 }
4586
4587 return 0;
4588}
4589
4590#define FORCEDETH_REGS_VER 1
4591
4592static int nv_get_regs_len(struct net_device *dev)
4593{
4594 struct fe_priv *np = netdev_priv(dev);
4595 return np->register_size;
4596}
4597
4598static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4599{
4600 struct fe_priv *np = netdev_priv(dev);
4601 u8 __iomem *base = get_hwbase(dev);
4602 u32 *rbuf = buf;
4603 int i;
4604
4605 regs->version = FORCEDETH_REGS_VER;
4606 spin_lock_irq(&np->lock);
4607 for (i = 0; i < np->register_size/sizeof(u32); i++)
4608 rbuf[i] = readl(base + i*sizeof(u32));
4609 spin_unlock_irq(&np->lock);
4610}
4611
4612static int nv_nway_reset(struct net_device *dev)
4613{
4614 struct fe_priv *np = netdev_priv(dev);
4615 int ret;
4616
4617 if (np->autoneg) {
4618 int bmcr;
4619
4620 netif_carrier_off(dev);
4621 if (netif_running(dev)) {
4622 nv_disable_irq(dev);
4623 netif_tx_lock_bh(dev);
4624 netif_addr_lock(dev);
4625 spin_lock(&np->lock);
4626 /* stop engines */
4627 nv_stop_rxtx(dev);
4628 spin_unlock(&np->lock);
4629 netif_addr_unlock(dev);
4630 netif_tx_unlock_bh(dev);
4631 netdev_info(dev, "link down\n");
4632 }
4633
4634 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4635 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4636 bmcr |= BMCR_ANENABLE;
4637 /* reset the phy in order for settings to stick*/
4638 if (phy_reset(dev, bmcr)) {
4639 netdev_info(dev, "phy reset failed\n");
4640 return -EINVAL;
4641 }
4642 } else {
4643 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4644 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4645 }
4646
4647 if (netif_running(dev)) {
4648 nv_start_rxtx(dev);
4649 nv_enable_irq(dev);
4650 }
4651 ret = 0;
4652 } else {
4653 ret = -EINVAL;
4654 }
4655
4656 return ret;
4657}
4658
4659static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4660{
4661 struct fe_priv *np = netdev_priv(dev);
4662
4663 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4664 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4665
4666 ring->rx_pending = np->rx_ring_size;
4667 ring->tx_pending = np->tx_ring_size;
4668}
4669
4670static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4671{
4672 struct fe_priv *np = netdev_priv(dev);
4673 u8 __iomem *base = get_hwbase(dev);
4674 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4675 dma_addr_t ring_addr;
4676
4677 if (ring->rx_pending < RX_RING_MIN ||
4678 ring->tx_pending < TX_RING_MIN ||
4679 ring->rx_mini_pending != 0 ||
4680 ring->rx_jumbo_pending != 0 ||
4681 (np->desc_ver == DESC_VER_1 &&
4682 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4683 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4684 (np->desc_ver != DESC_VER_1 &&
4685 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4686 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4687 return -EINVAL;
4688 }
4689
4690 /* allocate new rings */
4691 if (!nv_optimized(np)) {
4692 rxtx_ring = dma_alloc_coherent(&np->pci_dev->dev,
4693 sizeof(struct ring_desc) *
4694 (ring->rx_pending +
4695 ring->tx_pending),
4696 &ring_addr, GFP_ATOMIC);
4697 } else {
4698 rxtx_ring = dma_alloc_coherent(&np->pci_dev->dev,
4699 sizeof(struct ring_desc_ex) *
4700 (ring->rx_pending +
4701 ring->tx_pending),
4702 &ring_addr, GFP_ATOMIC);
4703 }
4704 rx_skbuff = kmalloc_array(ring->rx_pending, sizeof(struct nv_skb_map),
4705 GFP_KERNEL);
4706 tx_skbuff = kmalloc_array(ring->tx_pending, sizeof(struct nv_skb_map),
4707 GFP_KERNEL);
4708 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4709 /* fall back to old rings */
4710 if (!nv_optimized(np)) {
4711 if (rxtx_ring)
4712 dma_free_coherent(&np->pci_dev->dev,
4713 sizeof(struct ring_desc) *
4714 (ring->rx_pending +
4715 ring->tx_pending),
4716 rxtx_ring, ring_addr);
4717 } else {
4718 if (rxtx_ring)
4719 dma_free_coherent(&np->pci_dev->dev,
4720 sizeof(struct ring_desc_ex) *
4721 (ring->rx_pending +
4722 ring->tx_pending),
4723 rxtx_ring, ring_addr);
4724 }
4725
4726 kfree(rx_skbuff);
4727 kfree(tx_skbuff);
4728 goto exit;
4729 }
4730
4731 if (netif_running(dev)) {
4732 nv_disable_irq(dev);
4733 nv_napi_disable(dev);
4734 netif_tx_lock_bh(dev);
4735 netif_addr_lock(dev);
4736 spin_lock(&np->lock);
4737 /* stop engines */
4738 nv_stop_rxtx(dev);
4739 nv_txrx_reset(dev);
4740 /* drain queues */
4741 nv_drain_rxtx(dev);
4742 /* delete queues */
4743 free_rings(dev);
4744 }
4745
4746 /* set new values */
4747 np->rx_ring_size = ring->rx_pending;
4748 np->tx_ring_size = ring->tx_pending;
4749
4750 if (!nv_optimized(np)) {
4751 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
4752 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4753 } else {
4754 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
4755 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4756 }
4757 np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4758 np->tx_skb = (struct nv_skb_map *)tx_skbuff;
4759 np->ring_addr = ring_addr;
4760
4761 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4762 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4763
4764 if (netif_running(dev)) {
4765 /* reinit driver view of the queues */
4766 set_bufsize(dev);
4767 if (nv_init_ring(dev)) {
4768 if (!np->in_shutdown)
4769 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4770 }
4771
4772 /* reinit nic view of the queues */
4773 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4774 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4775 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4776 base + NvRegRingSizes);
4777 pci_push(base);
4778 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4779 pci_push(base);
4780
4781 /* restart engines */
4782 nv_start_rxtx(dev);
4783 spin_unlock(&np->lock);
4784 netif_addr_unlock(dev);
4785 netif_tx_unlock_bh(dev);
4786 nv_napi_enable(dev);
4787 nv_enable_irq(dev);
4788 }
4789 return 0;
4790exit:
4791 return -ENOMEM;
4792}
4793
4794static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4795{
4796 struct fe_priv *np = netdev_priv(dev);
4797
4798 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4799 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4800 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4801}
4802
4803static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4804{
4805 struct fe_priv *np = netdev_priv(dev);
4806 int adv, bmcr;
4807
4808 if ((!np->autoneg && np->duplex == 0) ||
4809 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4810 netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
4811 return -EINVAL;
4812 }
4813 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4814 netdev_info(dev, "hardware does not support tx pause frames\n");
4815 return -EINVAL;
4816 }
4817
4818 netif_carrier_off(dev);
4819 if (netif_running(dev)) {
4820 nv_disable_irq(dev);
4821 netif_tx_lock_bh(dev);
4822 netif_addr_lock(dev);
4823 spin_lock(&np->lock);
4824 /* stop engines */
4825 nv_stop_rxtx(dev);
4826 spin_unlock(&np->lock);
4827 netif_addr_unlock(dev);
4828 netif_tx_unlock_bh(dev);
4829 }
4830
4831 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4832 if (pause->rx_pause)
4833 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4834 if (pause->tx_pause)
4835 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4836
4837 if (np->autoneg && pause->autoneg) {
4838 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4839
4840 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4841 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4842 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4843 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4844 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4845 adv |= ADVERTISE_PAUSE_ASYM;
4846 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4847
4848 if (netif_running(dev))
4849 netdev_info(dev, "link down\n");
4850 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4851 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4852 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4853 } else {
4854 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4855 if (pause->rx_pause)
4856 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4857 if (pause->tx_pause)
4858 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4859
4860 if (!netif_running(dev))
4861 nv_update_linkspeed(dev);
4862 else
4863 nv_update_pause(dev, np->pause_flags);
4864 }
4865
4866 if (netif_running(dev)) {
4867 nv_start_rxtx(dev);
4868 nv_enable_irq(dev);
4869 }
4870 return 0;
4871}
4872
4873static int nv_set_loopback(struct net_device *dev, netdev_features_t features)
4874{
4875 struct fe_priv *np = netdev_priv(dev);
4876 unsigned long flags;
4877 u32 miicontrol;
4878 int err, retval = 0;
4879
4880 spin_lock_irqsave(&np->lock, flags);
4881 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4882 if (features & NETIF_F_LOOPBACK) {
4883 if (miicontrol & BMCR_LOOPBACK) {
4884 spin_unlock_irqrestore(&np->lock, flags);
4885 netdev_info(dev, "Loopback already enabled\n");
4886 return 0;
4887 }
4888 nv_disable_irq(dev);
4889 /* Turn on loopback mode */
4890 miicontrol |= BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
4891 err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol);
4892 if (err) {
4893 retval = PHY_ERROR;
4894 spin_unlock_irqrestore(&np->lock, flags);
4895 phy_init(dev);
4896 } else {
4897 if (netif_running(dev)) {
4898 /* Force 1000 Mbps full-duplex */
4899 nv_force_linkspeed(dev, NVREG_LINKSPEED_1000,
4900 1);
4901 /* Force link up */
4902 netif_carrier_on(dev);
4903 }
4904 spin_unlock_irqrestore(&np->lock, flags);
4905 netdev_info(dev,
4906 "Internal PHY loopback mode enabled.\n");
4907 }
4908 } else {
4909 if (!(miicontrol & BMCR_LOOPBACK)) {
4910 spin_unlock_irqrestore(&np->lock, flags);
4911 netdev_info(dev, "Loopback already disabled\n");
4912 return 0;
4913 }
4914 nv_disable_irq(dev);
4915 /* Turn off loopback */
4916 spin_unlock_irqrestore(&np->lock, flags);
4917 netdev_info(dev, "Internal PHY loopback mode disabled.\n");
4918 phy_init(dev);
4919 }
4920 msleep(500);
4921 spin_lock_irqsave(&np->lock, flags);
4922 nv_enable_irq(dev);
4923 spin_unlock_irqrestore(&np->lock, flags);
4924
4925 return retval;
4926}
4927
4928static netdev_features_t nv_fix_features(struct net_device *dev,
4929 netdev_features_t features)
4930{
4931 /* vlan is dependent on rx checksum offload */
4932 if (features & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX))
4933 features |= NETIF_F_RXCSUM;
4934
4935 return features;
4936}
4937
4938static void nv_vlan_mode(struct net_device *dev, netdev_features_t features)
4939{
4940 struct fe_priv *np = get_nvpriv(dev);
4941
4942 spin_lock_irq(&np->lock);
4943
4944 if (features & NETIF_F_HW_VLAN_CTAG_RX)
4945 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP;
4946 else
4947 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4948
4949 if (features & NETIF_F_HW_VLAN_CTAG_TX)
4950 np->txrxctl_bits |= NVREG_TXRXCTL_VLANINS;
4951 else
4952 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4953
4954 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4955
4956 spin_unlock_irq(&np->lock);
4957}
4958
4959static int nv_set_features(struct net_device *dev, netdev_features_t features)
4960{
4961 struct fe_priv *np = netdev_priv(dev);
4962 u8 __iomem *base = get_hwbase(dev);
4963 netdev_features_t changed = dev->features ^ features;
4964 int retval;
4965
4966 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) {
4967 retval = nv_set_loopback(dev, features);
4968 if (retval != 0)
4969 return retval;
4970 }
4971
4972 if (changed & NETIF_F_RXCSUM) {
4973 spin_lock_irq(&np->lock);
4974
4975 if (features & NETIF_F_RXCSUM)
4976 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4977 else
4978 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4979
4980 if (netif_running(dev))
4981 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4982
4983 spin_unlock_irq(&np->lock);
4984 }
4985
4986 if (changed & (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX))
4987 nv_vlan_mode(dev, features);
4988
4989 return 0;
4990}
4991
4992static int nv_get_sset_count(struct net_device *dev, int sset)
4993{
4994 struct fe_priv *np = netdev_priv(dev);
4995
4996 switch (sset) {
4997 case ETH_SS_TEST:
4998 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4999 return NV_TEST_COUNT_EXTENDED;
5000 else
5001 return NV_TEST_COUNT_BASE;
5002 case ETH_SS_STATS:
5003 if (np->driver_data & DEV_HAS_STATISTICS_V3)
5004 return NV_DEV_STATISTICS_V3_COUNT;
5005 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
5006 return NV_DEV_STATISTICS_V2_COUNT;
5007 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
5008 return NV_DEV_STATISTICS_V1_COUNT;
5009 else
5010 return 0;
5011 default:
5012 return -EOPNOTSUPP;
5013 }
5014}
5015
5016static void nv_get_ethtool_stats(struct net_device *dev,
5017 struct ethtool_stats *estats, u64 *buffer)
5018 __acquires(&netdev_priv(dev)->hwstats_lock)
5019 __releases(&netdev_priv(dev)->hwstats_lock)
5020{
5021 struct fe_priv *np = netdev_priv(dev);
5022
5023 spin_lock_bh(&np->hwstats_lock);
5024 nv_update_stats(dev);
5025 memcpy(buffer, &np->estats,
5026 nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
5027 spin_unlock_bh(&np->hwstats_lock);
5028}
5029
5030static int nv_link_test(struct net_device *dev)
5031{
5032 struct fe_priv *np = netdev_priv(dev);
5033 int mii_status;
5034
5035 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5036 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5037
5038 /* check phy link status */
5039 if (!(mii_status & BMSR_LSTATUS))
5040 return 0;
5041 else
5042 return 1;
5043}
5044
5045static int nv_register_test(struct net_device *dev)
5046{
5047 u8 __iomem *base = get_hwbase(dev);
5048 int i = 0;
5049 u32 orig_read, new_read;
5050
5051 do {
5052 orig_read = readl(base + nv_registers_test[i].reg);
5053
5054 /* xor with mask to toggle bits */
5055 orig_read ^= nv_registers_test[i].mask;
5056
5057 writel(orig_read, base + nv_registers_test[i].reg);
5058
5059 new_read = readl(base + nv_registers_test[i].reg);
5060
5061 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
5062 return 0;
5063
5064 /* restore original value */
5065 orig_read ^= nv_registers_test[i].mask;
5066 writel(orig_read, base + nv_registers_test[i].reg);
5067
5068 } while (nv_registers_test[++i].reg != 0);
5069
5070 return 1;
5071}
5072
5073static int nv_interrupt_test(struct net_device *dev)
5074{
5075 struct fe_priv *np = netdev_priv(dev);
5076 u8 __iomem *base = get_hwbase(dev);
5077 int ret = 1;
5078 int testcnt;
5079 u32 save_msi_flags, save_poll_interval = 0;
5080
5081 if (netif_running(dev)) {
5082 /* free current irq */
5083 nv_free_irq(dev);
5084 save_poll_interval = readl(base+NvRegPollingInterval);
5085 }
5086
5087 /* flag to test interrupt handler */
5088 np->intr_test = 0;
5089
5090 /* setup test irq */
5091 save_msi_flags = np->msi_flags;
5092 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
5093 np->msi_flags |= 0x001; /* setup 1 vector */
5094 if (nv_request_irq(dev, 1))
5095 return 0;
5096
5097 /* setup timer interrupt */
5098 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5099 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5100
5101 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
5102
5103 /* wait for at least one interrupt */
5104 msleep(100);
5105
5106 spin_lock_irq(&np->lock);
5107
5108 /* flag should be set within ISR */
5109 testcnt = np->intr_test;
5110 if (!testcnt)
5111 ret = 2;
5112
5113 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
5114 if (!(np->msi_flags & NV_MSI_X_ENABLED))
5115 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5116 else
5117 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5118
5119 spin_unlock_irq(&np->lock);
5120
5121 nv_free_irq(dev);
5122
5123 np->msi_flags = save_msi_flags;
5124
5125 if (netif_running(dev)) {
5126 writel(save_poll_interval, base + NvRegPollingInterval);
5127 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5128 /* restore original irq */
5129 if (nv_request_irq(dev, 0))
5130 return 0;
5131 }
5132
5133 return ret;
5134}
5135
5136static int nv_loopback_test(struct net_device *dev)
5137{
5138 struct fe_priv *np = netdev_priv(dev);
5139 u8 __iomem *base = get_hwbase(dev);
5140 struct sk_buff *tx_skb, *rx_skb;
5141 dma_addr_t test_dma_addr;
5142 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
5143 u32 flags;
5144 int len, i, pkt_len;
5145 u8 *pkt_data;
5146 u32 filter_flags = 0;
5147 u32 misc1_flags = 0;
5148 int ret = 1;
5149
5150 if (netif_running(dev)) {
5151 nv_disable_irq(dev);
5152 filter_flags = readl(base + NvRegPacketFilterFlags);
5153 misc1_flags = readl(base + NvRegMisc1);
5154 } else {
5155 nv_txrx_reset(dev);
5156 }
5157
5158 /* reinit driver view of the rx queue */
5159 set_bufsize(dev);
5160 nv_init_ring(dev);
5161
5162 /* setup hardware for loopback */
5163 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
5164 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
5165
5166 /* reinit nic view of the rx queue */
5167 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5168 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5169 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5170 base + NvRegRingSizes);
5171 pci_push(base);
5172
5173 /* restart rx engine */
5174 nv_start_rxtx(dev);
5175
5176 /* setup packet for tx */
5177 pkt_len = ETH_DATA_LEN;
5178 tx_skb = netdev_alloc_skb(dev, pkt_len);
5179 if (!tx_skb) {
5180 ret = 0;
5181 goto out;
5182 }
5183 test_dma_addr = dma_map_single(&np->pci_dev->dev, tx_skb->data,
5184 skb_tailroom(tx_skb),
5185 DMA_FROM_DEVICE);
5186 if (unlikely(dma_mapping_error(&np->pci_dev->dev,
5187 test_dma_addr))) {
5188 dev_kfree_skb_any(tx_skb);
5189 goto out;
5190 }
5191 pkt_data = skb_put(tx_skb, pkt_len);
5192 for (i = 0; i < pkt_len; i++)
5193 pkt_data[i] = (u8)(i & 0xff);
5194
5195 if (!nv_optimized(np)) {
5196 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
5197 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5198 } else {
5199 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
5200 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
5201 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5202 }
5203 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5204 pci_push(get_hwbase(dev));
5205
5206 msleep(500);
5207
5208 /* check for rx of the packet */
5209 if (!nv_optimized(np)) {
5210 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
5211 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
5212
5213 } else {
5214 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
5215 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
5216 }
5217
5218 if (flags & NV_RX_AVAIL) {
5219 ret = 0;
5220 } else if (np->desc_ver == DESC_VER_1) {
5221 if (flags & NV_RX_ERROR)
5222 ret = 0;
5223 } else {
5224 if (flags & NV_RX2_ERROR)
5225 ret = 0;
5226 }
5227
5228 if (ret) {
5229 if (len != pkt_len) {
5230 ret = 0;
5231 } else {
5232 rx_skb = np->rx_skb[0].skb;
5233 for (i = 0; i < pkt_len; i++) {
5234 if (rx_skb->data[i] != (u8)(i & 0xff)) {
5235 ret = 0;
5236 break;
5237 }
5238 }
5239 }
5240 }
5241
5242 dma_unmap_single(&np->pci_dev->dev, test_dma_addr,
5243 (skb_end_pointer(tx_skb) - tx_skb->data),
5244 DMA_TO_DEVICE);
5245 dev_kfree_skb_any(tx_skb);
5246 out:
5247 /* stop engines */
5248 nv_stop_rxtx(dev);
5249 nv_txrx_reset(dev);
5250 /* drain rx queue */
5251 nv_drain_rxtx(dev);
5252
5253 if (netif_running(dev)) {
5254 writel(misc1_flags, base + NvRegMisc1);
5255 writel(filter_flags, base + NvRegPacketFilterFlags);
5256 nv_enable_irq(dev);
5257 }
5258
5259 return ret;
5260}
5261
5262static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5263{
5264 struct fe_priv *np = netdev_priv(dev);
5265 u8 __iomem *base = get_hwbase(dev);
5266 int result, count;
5267
5268 count = nv_get_sset_count(dev, ETH_SS_TEST);
5269 memset(buffer, 0, count * sizeof(u64));
5270
5271 if (!nv_link_test(dev)) {
5272 test->flags |= ETH_TEST_FL_FAILED;
5273 buffer[0] = 1;
5274 }
5275
5276 if (test->flags & ETH_TEST_FL_OFFLINE) {
5277 if (netif_running(dev)) {
5278 netif_stop_queue(dev);
5279 nv_napi_disable(dev);
5280 netif_tx_lock_bh(dev);
5281 netif_addr_lock(dev);
5282 spin_lock_irq(&np->lock);
5283 nv_disable_hw_interrupts(dev, np->irqmask);
5284 if (!(np->msi_flags & NV_MSI_X_ENABLED))
5285 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5286 else
5287 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5288 /* stop engines */
5289 nv_stop_rxtx(dev);
5290 nv_txrx_reset(dev);
5291 /* drain rx queue */
5292 nv_drain_rxtx(dev);
5293 spin_unlock_irq(&np->lock);
5294 netif_addr_unlock(dev);
5295 netif_tx_unlock_bh(dev);
5296 }
5297
5298 if (!nv_register_test(dev)) {
5299 test->flags |= ETH_TEST_FL_FAILED;
5300 buffer[1] = 1;
5301 }
5302
5303 result = nv_interrupt_test(dev);
5304 if (result != 1) {
5305 test->flags |= ETH_TEST_FL_FAILED;
5306 buffer[2] = 1;
5307 }
5308 if (result == 0) {
5309 /* bail out */
5310 return;
5311 }
5312
5313 if (count > NV_TEST_COUNT_BASE && !nv_loopback_test(dev)) {
5314 test->flags |= ETH_TEST_FL_FAILED;
5315 buffer[3] = 1;
5316 }
5317
5318 if (netif_running(dev)) {
5319 /* reinit driver view of the rx queue */
5320 set_bufsize(dev);
5321 if (nv_init_ring(dev)) {
5322 if (!np->in_shutdown)
5323 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5324 }
5325 /* reinit nic view of the rx queue */
5326 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5327 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5328 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5329 base + NvRegRingSizes);
5330 pci_push(base);
5331 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5332 pci_push(base);
5333 /* restart rx engine */
5334 nv_start_rxtx(dev);
5335 netif_start_queue(dev);
5336 nv_napi_enable(dev);
5337 nv_enable_hw_interrupts(dev, np->irqmask);
5338 }
5339 }
5340}
5341
5342static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5343{
5344 switch (stringset) {
5345 case ETH_SS_STATS:
5346 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5347 break;
5348 case ETH_SS_TEST:
5349 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5350 break;
5351 }
5352}
5353
5354static const struct ethtool_ops ops = {
5355 .get_drvinfo = nv_get_drvinfo,
5356 .get_link = ethtool_op_get_link,
5357 .get_wol = nv_get_wol,
5358 .set_wol = nv_set_wol,
5359 .get_regs_len = nv_get_regs_len,
5360 .get_regs = nv_get_regs,
5361 .nway_reset = nv_nway_reset,
5362 .get_ringparam = nv_get_ringparam,
5363 .set_ringparam = nv_set_ringparam,
5364 .get_pauseparam = nv_get_pauseparam,
5365 .set_pauseparam = nv_set_pauseparam,
5366 .get_strings = nv_get_strings,
5367 .get_ethtool_stats = nv_get_ethtool_stats,
5368 .get_sset_count = nv_get_sset_count,
5369 .self_test = nv_self_test,
5370 .get_ts_info = ethtool_op_get_ts_info,
5371 .get_link_ksettings = nv_get_link_ksettings,
5372 .set_link_ksettings = nv_set_link_ksettings,
5373};
5374
5375/* The mgmt unit and driver use a semaphore to access the phy during init */
5376static int nv_mgmt_acquire_sema(struct net_device *dev)
5377{
5378 struct fe_priv *np = netdev_priv(dev);
5379 u8 __iomem *base = get_hwbase(dev);
5380 int i;
5381 u32 tx_ctrl, mgmt_sema;
5382
5383 for (i = 0; i < 10; i++) {
5384 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5385 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5386 break;
5387 msleep(500);
5388 }
5389
5390 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5391 return 0;
5392
5393 for (i = 0; i < 2; i++) {
5394 tx_ctrl = readl(base + NvRegTransmitterControl);
5395 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5396 writel(tx_ctrl, base + NvRegTransmitterControl);
5397
5398 /* verify that semaphore was acquired */
5399 tx_ctrl = readl(base + NvRegTransmitterControl);
5400 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5401 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5402 np->mgmt_sema = 1;
5403 return 1;
5404 } else
5405 udelay(50);
5406 }
5407
5408 return 0;
5409}
5410
5411static void nv_mgmt_release_sema(struct net_device *dev)
5412{
5413 struct fe_priv *np = netdev_priv(dev);
5414 u8 __iomem *base = get_hwbase(dev);
5415 u32 tx_ctrl;
5416
5417 if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5418 if (np->mgmt_sema) {
5419 tx_ctrl = readl(base + NvRegTransmitterControl);
5420 tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5421 writel(tx_ctrl, base + NvRegTransmitterControl);
5422 }
5423 }
5424}
5425
5426
5427static int nv_mgmt_get_version(struct net_device *dev)
5428{
5429 struct fe_priv *np = netdev_priv(dev);
5430 u8 __iomem *base = get_hwbase(dev);
5431 u32 data_ready = readl(base + NvRegTransmitterControl);
5432 u32 data_ready2 = 0;
5433 unsigned long start;
5434 int ready = 0;
5435
5436 writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5437 writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5438 start = jiffies;
5439 while (time_before(jiffies, start + 5*HZ)) {
5440 data_ready2 = readl(base + NvRegTransmitterControl);
5441 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5442 ready = 1;
5443 break;
5444 }
5445 schedule_timeout_uninterruptible(1);
5446 }
5447
5448 if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5449 return 0;
5450
5451 np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5452
5453 return 1;
5454}
5455
5456static int nv_open(struct net_device *dev)
5457{
5458 struct fe_priv *np = netdev_priv(dev);
5459 u8 __iomem *base = get_hwbase(dev);
5460 int ret = 1;
5461 int oom, i;
5462 u32 low;
5463
5464 /* power up phy */
5465 mii_rw(dev, np->phyaddr, MII_BMCR,
5466 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5467
5468 nv_txrx_gate(dev, false);
5469 /* erase previous misconfiguration */
5470 if (np->driver_data & DEV_HAS_POWER_CNTRL)
5471 nv_mac_reset(dev);
5472 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5473 writel(0, base + NvRegMulticastAddrB);
5474 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5475 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5476 writel(0, base + NvRegPacketFilterFlags);
5477
5478 writel(0, base + NvRegTransmitterControl);
5479 writel(0, base + NvRegReceiverControl);
5480
5481 writel(0, base + NvRegAdapterControl);
5482
5483 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5484 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
5485
5486 /* initialize descriptor rings */
5487 set_bufsize(dev);
5488 oom = nv_init_ring(dev);
5489
5490 writel(0, base + NvRegLinkSpeed);
5491 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5492 nv_txrx_reset(dev);
5493 writel(0, base + NvRegUnknownSetupReg6);
5494
5495 np->in_shutdown = 0;
5496
5497 /* give hw rings */
5498 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5499 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5500 base + NvRegRingSizes);
5501
5502 writel(np->linkspeed, base + NvRegLinkSpeed);
5503 if (np->desc_ver == DESC_VER_1)
5504 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5505 else
5506 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5507 writel(np->txrxctl_bits, base + NvRegTxRxControl);
5508 writel(np->vlanctl_bits, base + NvRegVlanControl);
5509 pci_push(base);
5510 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5511 if (reg_delay(dev, NvRegUnknownSetupReg5,
5512 NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5513 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
5514 netdev_info(dev,
5515 "%s: SetupReg5, Bit 31 remained off\n", __func__);
5516
5517 writel(0, base + NvRegMIIMask);
5518 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5519 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5520
5521 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5522 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5523 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5524 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5525
5526 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5527
5528 get_random_bytes(&low, sizeof(low));
5529 low &= NVREG_SLOTTIME_MASK;
5530 if (np->desc_ver == DESC_VER_1) {
5531 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5532 } else {
5533 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5534 /* setup legacy backoff */
5535 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5536 } else {
5537 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5538 nv_gear_backoff_reseed(dev);
5539 }
5540 }
5541 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5542 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5543 if (poll_interval == -1) {
5544 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5545 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5546 else
5547 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5548 } else
5549 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5550 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5551 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5552 base + NvRegAdapterControl);
5553 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5554 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5555 if (np->wolenabled)
5556 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5557
5558 i = readl(base + NvRegPowerState);
5559 if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
5560 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5561
5562 pci_push(base);
5563 udelay(10);
5564 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5565
5566 nv_disable_hw_interrupts(dev, np->irqmask);
5567 pci_push(base);
5568 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5569 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5570 pci_push(base);
5571
5572 if (nv_request_irq(dev, 0))
5573 goto out_drain;
5574
5575 /* ask for interrupts */
5576 nv_enable_hw_interrupts(dev, np->irqmask);
5577
5578 spin_lock_irq(&np->lock);
5579 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5580 writel(0, base + NvRegMulticastAddrB);
5581 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5582 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5583 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5584 /* One manual link speed update: Interrupts are enabled, future link
5585 * speed changes cause interrupts and are handled by nv_link_irq().
5586 */
5587 readl(base + NvRegMIIStatus);
5588 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5589
5590 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5591 * to init hw */
5592 np->linkspeed = 0;
5593 ret = nv_update_linkspeed(dev);
5594 nv_start_rxtx(dev);
5595 netif_start_queue(dev);
5596 nv_napi_enable(dev);
5597
5598 if (ret) {
5599 netif_carrier_on(dev);
5600 } else {
5601 netdev_info(dev, "no link during initialization\n");
5602 netif_carrier_off(dev);
5603 }
5604 if (oom)
5605 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5606
5607 /* start statistics timer */
5608 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5609 mod_timer(&np->stats_poll,
5610 round_jiffies(jiffies + STATS_INTERVAL));
5611
5612 spin_unlock_irq(&np->lock);
5613
5614 /* If the loopback feature was set while the device was down, make sure
5615 * that it's set correctly now.
5616 */
5617 if (dev->features & NETIF_F_LOOPBACK)
5618 nv_set_loopback(dev, dev->features);
5619
5620 return 0;
5621out_drain:
5622 nv_drain_rxtx(dev);
5623 return ret;
5624}
5625
5626static int nv_close(struct net_device *dev)
5627{
5628 struct fe_priv *np = netdev_priv(dev);
5629 u8 __iomem *base;
5630
5631 spin_lock_irq(&np->lock);
5632 np->in_shutdown = 1;
5633 spin_unlock_irq(&np->lock);
5634 nv_napi_disable(dev);
5635 synchronize_irq(np->pci_dev->irq);
5636
5637 del_timer_sync(&np->oom_kick);
5638 del_timer_sync(&np->nic_poll);
5639 del_timer_sync(&np->stats_poll);
5640
5641 netif_stop_queue(dev);
5642 spin_lock_irq(&np->lock);
5643 nv_update_pause(dev, 0); /* otherwise stop_tx bricks NIC */
5644 nv_stop_rxtx(dev);
5645 nv_txrx_reset(dev);
5646
5647 /* disable interrupts on the nic or we will lock up */
5648 base = get_hwbase(dev);
5649 nv_disable_hw_interrupts(dev, np->irqmask);
5650 pci_push(base);
5651
5652 spin_unlock_irq(&np->lock);
5653
5654 nv_free_irq(dev);
5655
5656 nv_drain_rxtx(dev);
5657
5658 if (np->wolenabled || !phy_power_down) {
5659 nv_txrx_gate(dev, false);
5660 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5661 nv_start_rx(dev);
5662 } else {
5663 /* power down phy */
5664 mii_rw(dev, np->phyaddr, MII_BMCR,
5665 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5666 nv_txrx_gate(dev, true);
5667 }
5668
5669 /* FIXME: power down nic */
5670
5671 return 0;
5672}
5673
5674static const struct net_device_ops nv_netdev_ops = {
5675 .ndo_open = nv_open,
5676 .ndo_stop = nv_close,
5677 .ndo_get_stats64 = nv_get_stats64,
5678 .ndo_start_xmit = nv_start_xmit,
5679 .ndo_tx_timeout = nv_tx_timeout,
5680 .ndo_change_mtu = nv_change_mtu,
5681 .ndo_fix_features = nv_fix_features,
5682 .ndo_set_features = nv_set_features,
5683 .ndo_validate_addr = eth_validate_addr,
5684 .ndo_set_mac_address = nv_set_mac_address,
5685 .ndo_set_rx_mode = nv_set_multicast,
5686#ifdef CONFIG_NET_POLL_CONTROLLER
5687 .ndo_poll_controller = nv_poll_controller,
5688#endif
5689};
5690
5691static const struct net_device_ops nv_netdev_ops_optimized = {
5692 .ndo_open = nv_open,
5693 .ndo_stop = nv_close,
5694 .ndo_get_stats64 = nv_get_stats64,
5695 .ndo_start_xmit = nv_start_xmit_optimized,
5696 .ndo_tx_timeout = nv_tx_timeout,
5697 .ndo_change_mtu = nv_change_mtu,
5698 .ndo_fix_features = nv_fix_features,
5699 .ndo_set_features = nv_set_features,
5700 .ndo_validate_addr = eth_validate_addr,
5701 .ndo_set_mac_address = nv_set_mac_address,
5702 .ndo_set_rx_mode = nv_set_multicast,
5703#ifdef CONFIG_NET_POLL_CONTROLLER
5704 .ndo_poll_controller = nv_poll_controller,
5705#endif
5706};
5707
5708static int nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5709{
5710 struct net_device *dev;
5711 struct fe_priv *np;
5712 unsigned long addr;
5713 u8 __iomem *base;
5714 int err, i;
5715 u32 powerstate, txreg;
5716 u32 phystate_orig = 0, phystate;
5717 int phyinitialized = 0;
5718 static int printed_version;
5719
5720 if (!printed_version++)
5721 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5722 FORCEDETH_VERSION);
5723
5724 dev = alloc_etherdev(sizeof(struct fe_priv));
5725 err = -ENOMEM;
5726 if (!dev)
5727 goto out;
5728
5729 np = netdev_priv(dev);
5730 np->dev = dev;
5731 np->pci_dev = pci_dev;
5732 spin_lock_init(&np->lock);
5733 spin_lock_init(&np->hwstats_lock);
5734 SET_NETDEV_DEV(dev, &pci_dev->dev);
5735 u64_stats_init(&np->swstats_rx_syncp);
5736 u64_stats_init(&np->swstats_tx_syncp);
5737 np->txrx_stats = alloc_percpu(struct nv_txrx_stats);
5738 if (!np->txrx_stats) {
5739 pr_err("np->txrx_stats, alloc memory error.\n");
5740 err = -ENOMEM;
5741 goto out_alloc_percpu;
5742 }
5743
5744 timer_setup(&np->oom_kick, nv_do_rx_refill, 0);
5745 timer_setup(&np->nic_poll, nv_do_nic_poll, 0);
5746 timer_setup(&np->stats_poll, nv_do_stats_poll, TIMER_DEFERRABLE);
5747
5748 err = pci_enable_device(pci_dev);
5749 if (err)
5750 goto out_free;
5751
5752 pci_set_master(pci_dev);
5753
5754 err = pci_request_regions(pci_dev, DRV_NAME);
5755 if (err < 0)
5756 goto out_disable;
5757
5758 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5759 np->register_size = NV_PCI_REGSZ_VER3;
5760 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5761 np->register_size = NV_PCI_REGSZ_VER2;
5762 else
5763 np->register_size = NV_PCI_REGSZ_VER1;
5764
5765 err = -EINVAL;
5766 addr = 0;
5767 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5768 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5769 pci_resource_len(pci_dev, i) >= np->register_size) {
5770 addr = pci_resource_start(pci_dev, i);
5771 break;
5772 }
5773 }
5774 if (i == DEVICE_COUNT_RESOURCE) {
5775 dev_info(&pci_dev->dev, "Couldn't find register window\n");
5776 goto out_relreg;
5777 }
5778
5779 /* copy of driver data */
5780 np->driver_data = id->driver_data;
5781 /* copy of device id */
5782 np->device_id = id->device;
5783
5784 /* handle different descriptor versions */
5785 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5786 /* packet format 3: supports 40-bit addressing */
5787 np->desc_ver = DESC_VER_3;
5788 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5789 if (dma_64bit) {
5790 if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5791 dev_info(&pci_dev->dev,
5792 "64-bit DMA failed, using 32-bit addressing\n");
5793 else
5794 dev->features |= NETIF_F_HIGHDMA;
5795 if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5796 dev_info(&pci_dev->dev,
5797 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5798 }
5799 }
5800 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5801 /* packet format 2: supports jumbo frames */
5802 np->desc_ver = DESC_VER_2;
5803 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5804 } else {
5805 /* original packet format */
5806 np->desc_ver = DESC_VER_1;
5807 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5808 }
5809
5810 np->pkt_limit = NV_PKTLIMIT_1;
5811 if (id->driver_data & DEV_HAS_LARGEDESC)
5812 np->pkt_limit = NV_PKTLIMIT_2;
5813
5814 if (id->driver_data & DEV_HAS_CHECKSUM) {
5815 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5816 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG |
5817 NETIF_F_TSO | NETIF_F_RXCSUM;
5818 }
5819
5820 np->vlanctl_bits = 0;
5821 if (id->driver_data & DEV_HAS_VLAN) {
5822 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5823 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX |
5824 NETIF_F_HW_VLAN_CTAG_TX;
5825 }
5826
5827 dev->features |= dev->hw_features;
5828
5829 /* Add loopback capability to the device. */
5830 dev->hw_features |= NETIF_F_LOOPBACK;
5831
5832 /* MTU range: 64 - 1500 or 9100 */
5833 dev->min_mtu = ETH_ZLEN + ETH_FCS_LEN;
5834 dev->max_mtu = np->pkt_limit;
5835
5836 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5837 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5838 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5839 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5840 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5841 }
5842
5843 err = -ENOMEM;
5844 np->base = ioremap(addr, np->register_size);
5845 if (!np->base)
5846 goto out_relreg;
5847
5848 np->rx_ring_size = RX_RING_DEFAULT;
5849 np->tx_ring_size = TX_RING_DEFAULT;
5850
5851 if (!nv_optimized(np)) {
5852 np->rx_ring.orig = dma_alloc_coherent(&pci_dev->dev,
5853 sizeof(struct ring_desc) *
5854 (np->rx_ring_size +
5855 np->tx_ring_size),
5856 &np->ring_addr,
5857 GFP_KERNEL);
5858 if (!np->rx_ring.orig)
5859 goto out_unmap;
5860 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5861 } else {
5862 np->rx_ring.ex = dma_alloc_coherent(&pci_dev->dev,
5863 sizeof(struct ring_desc_ex) *
5864 (np->rx_ring_size +
5865 np->tx_ring_size),
5866 &np->ring_addr, GFP_KERNEL);
5867 if (!np->rx_ring.ex)
5868 goto out_unmap;
5869 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5870 }
5871 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5872 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5873 if (!np->rx_skb || !np->tx_skb)
5874 goto out_freering;
5875
5876 if (!nv_optimized(np))
5877 dev->netdev_ops = &nv_netdev_ops;
5878 else
5879 dev->netdev_ops = &nv_netdev_ops_optimized;
5880
5881 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5882 dev->ethtool_ops = &ops;
5883 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5884
5885 pci_set_drvdata(pci_dev, dev);
5886
5887 /* read the mac address */
5888 base = get_hwbase(dev);
5889 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5890 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5891
5892 /* check the workaround bit for correct mac address order */
5893 txreg = readl(base + NvRegTransmitPoll);
5894 if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5895 /* mac address is already in correct order */
5896 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5897 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5898 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5899 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5900 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5901 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5902 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5903 /* mac address is already in correct order */
5904 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5905 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5906 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5907 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5908 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5909 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5910 /*
5911 * Set orig mac address back to the reversed version.
5912 * This flag will be cleared during low power transition.
5913 * Therefore, we should always put back the reversed address.
5914 */
5915 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5916 (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5917 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5918 } else {
5919 /* need to reverse mac address to correct order */
5920 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5921 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5922 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5923 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5924 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5925 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
5926 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5927 dev_dbg(&pci_dev->dev,
5928 "%s: set workaround bit for reversed mac addr\n",
5929 __func__);
5930 }
5931
5932 if (!is_valid_ether_addr(dev->dev_addr)) {
5933 /*
5934 * Bad mac address. At least one bios sets the mac address
5935 * to 01:23:45:67:89:ab
5936 */
5937 dev_err(&pci_dev->dev,
5938 "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
5939 dev->dev_addr);
5940 eth_hw_addr_random(dev);
5941 dev_err(&pci_dev->dev,
5942 "Using random MAC address: %pM\n", dev->dev_addr);
5943 }
5944
5945 /* set mac address */
5946 nv_copy_mac_to_hw(dev);
5947
5948 /* disable WOL */
5949 writel(0, base + NvRegWakeUpFlags);
5950 np->wolenabled = 0;
5951 device_set_wakeup_enable(&pci_dev->dev, false);
5952
5953 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5954
5955 /* take phy and nic out of low power mode */
5956 powerstate = readl(base + NvRegPowerState2);
5957 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5958 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5959 pci_dev->revision >= 0xA3)
5960 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5961 writel(powerstate, base + NvRegPowerState2);
5962 }
5963
5964 if (np->desc_ver == DESC_VER_1)
5965 np->tx_flags = NV_TX_VALID;
5966 else
5967 np->tx_flags = NV_TX2_VALID;
5968
5969 np->msi_flags = 0;
5970 if ((id->driver_data & DEV_HAS_MSI) && msi)
5971 np->msi_flags |= NV_MSI_CAPABLE;
5972
5973 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5974 /* msix has had reported issues when modifying irqmask
5975 as in the case of napi, therefore, disable for now
5976 */
5977#if 0
5978 np->msi_flags |= NV_MSI_X_CAPABLE;
5979#endif
5980 }
5981
5982 if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5983 np->irqmask = NVREG_IRQMASK_CPU;
5984 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5985 np->msi_flags |= 0x0001;
5986 } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5987 !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5988 /* start off in throughput mode */
5989 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5990 /* remove support for msix mode */
5991 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5992 } else {
5993 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5994 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5995 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5996 np->msi_flags |= 0x0003;
5997 }
5998
5999 if (id->driver_data & DEV_NEED_TIMERIRQ)
6000 np->irqmask |= NVREG_IRQ_TIMER;
6001 if (id->driver_data & DEV_NEED_LINKTIMER) {
6002 np->need_linktimer = 1;
6003 np->link_timeout = jiffies + LINK_TIMEOUT;
6004 } else {
6005 np->need_linktimer = 0;
6006 }
6007
6008 /* Limit the number of tx's outstanding for hw bug */
6009 if (id->driver_data & DEV_NEED_TX_LIMIT) {
6010 np->tx_limit = 1;
6011 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
6012 pci_dev->revision >= 0xA2)
6013 np->tx_limit = 0;
6014 }
6015
6016 /* clear phy state and temporarily halt phy interrupts */
6017 writel(0, base + NvRegMIIMask);
6018 phystate = readl(base + NvRegAdapterControl);
6019 if (phystate & NVREG_ADAPTCTL_RUNNING) {
6020 phystate_orig = 1;
6021 phystate &= ~NVREG_ADAPTCTL_RUNNING;
6022 writel(phystate, base + NvRegAdapterControl);
6023 }
6024 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
6025
6026 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
6027 /* management unit running on the mac? */
6028 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
6029 (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
6030 nv_mgmt_acquire_sema(dev) &&
6031 nv_mgmt_get_version(dev)) {
6032 np->mac_in_use = 1;
6033 if (np->mgmt_version > 0)
6034 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
6035 /* management unit setup the phy already? */
6036 if (np->mac_in_use &&
6037 ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
6038 NVREG_XMITCTL_SYNC_PHY_INIT)) {
6039 /* phy is inited by mgmt unit */
6040 phyinitialized = 1;
6041 } else {
6042 /* we need to init the phy */
6043 }
6044 }
6045 }
6046
6047 /* find a suitable phy */
6048 for (i = 1; i <= 32; i++) {
6049 int id1, id2;
6050 int phyaddr = i & 0x1F;
6051
6052 spin_lock_irq(&np->lock);
6053 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
6054 spin_unlock_irq(&np->lock);
6055 if (id1 < 0 || id1 == 0xffff)
6056 continue;
6057 spin_lock_irq(&np->lock);
6058 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
6059 spin_unlock_irq(&np->lock);
6060 if (id2 < 0 || id2 == 0xffff)
6061 continue;
6062
6063 np->phy_model = id2 & PHYID2_MODEL_MASK;
6064 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
6065 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
6066 np->phyaddr = phyaddr;
6067 np->phy_oui = id1 | id2;
6068
6069 /* Realtek hardcoded phy id1 to all zero's on certain phys */
6070 if (np->phy_oui == PHY_OUI_REALTEK2)
6071 np->phy_oui = PHY_OUI_REALTEK;
6072 /* Setup phy revision for Realtek */
6073 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
6074 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
6075
6076 break;
6077 }
6078 if (i == 33) {
6079 dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
6080 goto out_error;
6081 }
6082
6083 if (!phyinitialized) {
6084 /* reset it */
6085 phy_init(dev);
6086 } else {
6087 /* see if it is a gigabit phy */
6088 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
6089 if (mii_status & PHY_GIGABIT)
6090 np->gigabit = PHY_GIGABIT;
6091 }
6092
6093 /* set default link speed settings */
6094 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
6095 np->duplex = 0;
6096 np->autoneg = 1;
6097
6098 err = register_netdev(dev);
6099 if (err) {
6100 dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
6101 goto out_error;
6102 }
6103
6104 netif_carrier_off(dev);
6105
6106 /* Some NICs freeze when TX pause is enabled while NIC is
6107 * down, and this stays across warm reboots. The sequence
6108 * below should be enough to recover from that state.
6109 */
6110 nv_update_pause(dev, 0);
6111 nv_start_tx(dev);
6112 nv_stop_tx(dev);
6113
6114 if (id->driver_data & DEV_HAS_VLAN)
6115 nv_vlan_mode(dev, dev->features);
6116
6117 dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
6118 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
6119
6120 dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
6121 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
6122 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
6123 "csum " : "",
6124 dev->features & (NETIF_F_HW_VLAN_CTAG_RX |
6125 NETIF_F_HW_VLAN_CTAG_TX) ?
6126 "vlan " : "",
6127 dev->features & (NETIF_F_LOOPBACK) ?
6128 "loopback " : "",
6129 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
6130 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
6131 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
6132 np->gigabit == PHY_GIGABIT ? "gbit " : "",
6133 np->need_linktimer ? "lnktim " : "",
6134 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
6135 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
6136 np->desc_ver);
6137
6138 return 0;
6139
6140out_error:
6141 if (phystate_orig)
6142 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
6143out_freering:
6144 free_rings(dev);
6145out_unmap:
6146 iounmap(get_hwbase(dev));
6147out_relreg:
6148 pci_release_regions(pci_dev);
6149out_disable:
6150 pci_disable_device(pci_dev);
6151out_free:
6152 free_percpu(np->txrx_stats);
6153out_alloc_percpu:
6154 free_netdev(dev);
6155out:
6156 return err;
6157}
6158
6159static void nv_restore_phy(struct net_device *dev)
6160{
6161 struct fe_priv *np = netdev_priv(dev);
6162 u16 phy_reserved, mii_control;
6163
6164 if (np->phy_oui == PHY_OUI_REALTEK &&
6165 np->phy_model == PHY_MODEL_REALTEK_8201 &&
6166 phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
6167 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
6168 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
6169 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
6170 phy_reserved |= PHY_REALTEK_INIT8;
6171 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
6172 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
6173
6174 /* restart auto negotiation */
6175 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
6176 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
6177 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
6178 }
6179}
6180
6181static void nv_restore_mac_addr(struct pci_dev *pci_dev)
6182{
6183 struct net_device *dev = pci_get_drvdata(pci_dev);
6184 struct fe_priv *np = netdev_priv(dev);
6185 u8 __iomem *base = get_hwbase(dev);
6186
6187 /* special op: write back the misordered MAC address - otherwise
6188 * the next nv_probe would see a wrong address.
6189 */
6190 writel(np->orig_mac[0], base + NvRegMacAddrA);
6191 writel(np->orig_mac[1], base + NvRegMacAddrB);
6192 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
6193 base + NvRegTransmitPoll);
6194}
6195
6196static void nv_remove(struct pci_dev *pci_dev)
6197{
6198 struct net_device *dev = pci_get_drvdata(pci_dev);
6199 struct fe_priv *np = netdev_priv(dev);
6200
6201 free_percpu(np->txrx_stats);
6202
6203 unregister_netdev(dev);
6204
6205 nv_restore_mac_addr(pci_dev);
6206
6207 /* restore any phy related changes */
6208 nv_restore_phy(dev);
6209
6210 nv_mgmt_release_sema(dev);
6211
6212 /* free all structures */
6213 free_rings(dev);
6214 iounmap(get_hwbase(dev));
6215 pci_release_regions(pci_dev);
6216 pci_disable_device(pci_dev);
6217 free_netdev(dev);
6218}
6219
6220#ifdef CONFIG_PM_SLEEP
6221static int nv_suspend(struct device *device)
6222{
6223 struct net_device *dev = dev_get_drvdata(device);
6224 struct fe_priv *np = netdev_priv(dev);
6225 u8 __iomem *base = get_hwbase(dev);
6226 int i;
6227
6228 if (netif_running(dev)) {
6229 /* Gross. */
6230 nv_close(dev);
6231 }
6232 netif_device_detach(dev);
6233
6234 /* save non-pci configuration space */
6235 for (i = 0; i <= np->register_size/sizeof(u32); i++)
6236 np->saved_config_space[i] = readl(base + i*sizeof(u32));
6237
6238 return 0;
6239}
6240
6241static int nv_resume(struct device *device)
6242{
6243 struct pci_dev *pdev = to_pci_dev(device);
6244 struct net_device *dev = pci_get_drvdata(pdev);
6245 struct fe_priv *np = netdev_priv(dev);
6246 u8 __iomem *base = get_hwbase(dev);
6247 int i, rc = 0;
6248
6249 /* restore non-pci configuration space */
6250 for (i = 0; i <= np->register_size/sizeof(u32); i++)
6251 writel(np->saved_config_space[i], base+i*sizeof(u32));
6252
6253 if (np->driver_data & DEV_NEED_MSI_FIX)
6254 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
6255
6256 /* restore phy state, including autoneg */
6257 phy_init(dev);
6258
6259 netif_device_attach(dev);
6260 if (netif_running(dev)) {
6261 rc = nv_open(dev);
6262 nv_set_multicast(dev);
6263 }
6264 return rc;
6265}
6266
6267static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
6268#define NV_PM_OPS (&nv_pm_ops)
6269
6270#else
6271#define NV_PM_OPS NULL
6272#endif /* CONFIG_PM_SLEEP */
6273
6274#ifdef CONFIG_PM
6275static void nv_shutdown(struct pci_dev *pdev)
6276{
6277 struct net_device *dev = pci_get_drvdata(pdev);
6278 struct fe_priv *np = netdev_priv(dev);
6279
6280 if (netif_running(dev))
6281 nv_close(dev);
6282
6283 /*
6284 * Restore the MAC so a kernel started by kexec won't get confused.
6285 * If we really go for poweroff, we must not restore the MAC,
6286 * otherwise the MAC for WOL will be reversed at least on some boards.
6287 */
6288 if (system_state != SYSTEM_POWER_OFF)
6289 nv_restore_mac_addr(pdev);
6290
6291 pci_disable_device(pdev);
6292 /*
6293 * Apparently it is not possible to reinitialise from D3 hot,
6294 * only put the device into D3 if we really go for poweroff.
6295 */
6296 if (system_state == SYSTEM_POWER_OFF) {
6297 pci_wake_from_d3(pdev, np->wolenabled);
6298 pci_set_power_state(pdev, PCI_D3hot);
6299 }
6300}
6301#else
6302#define nv_shutdown NULL
6303#endif /* CONFIG_PM */
6304
6305static const struct pci_device_id pci_tbl[] = {
6306 { /* nForce Ethernet Controller */
6307 PCI_DEVICE(0x10DE, 0x01C3),
6308 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6309 },
6310 { /* nForce2 Ethernet Controller */
6311 PCI_DEVICE(0x10DE, 0x0066),
6312 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6313 },
6314 { /* nForce3 Ethernet Controller */
6315 PCI_DEVICE(0x10DE, 0x00D6),
6316 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6317 },
6318 { /* nForce3 Ethernet Controller */
6319 PCI_DEVICE(0x10DE, 0x0086),
6320 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6321 },
6322 { /* nForce3 Ethernet Controller */
6323 PCI_DEVICE(0x10DE, 0x008C),
6324 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6325 },
6326 { /* nForce3 Ethernet Controller */
6327 PCI_DEVICE(0x10DE, 0x00E6),
6328 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6329 },
6330 { /* nForce3 Ethernet Controller */
6331 PCI_DEVICE(0x10DE, 0x00DF),
6332 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6333 },
6334 { /* CK804 Ethernet Controller */
6335 PCI_DEVICE(0x10DE, 0x0056),
6336 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6337 },
6338 { /* CK804 Ethernet Controller */
6339 PCI_DEVICE(0x10DE, 0x0057),
6340 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6341 },
6342 { /* MCP04 Ethernet Controller */
6343 PCI_DEVICE(0x10DE, 0x0037),
6344 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6345 },
6346 { /* MCP04 Ethernet Controller */
6347 PCI_DEVICE(0x10DE, 0x0038),
6348 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6349 },
6350 { /* MCP51 Ethernet Controller */
6351 PCI_DEVICE(0x10DE, 0x0268),
6352 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6353 },
6354 { /* MCP51 Ethernet Controller */
6355 PCI_DEVICE(0x10DE, 0x0269),
6356 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6357 },
6358 { /* MCP55 Ethernet Controller */
6359 PCI_DEVICE(0x10DE, 0x0372),
6360 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6361 },
6362 { /* MCP55 Ethernet Controller */
6363 PCI_DEVICE(0x10DE, 0x0373),
6364 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6365 },
6366 { /* MCP61 Ethernet Controller */
6367 PCI_DEVICE(0x10DE, 0x03E5),
6368 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6369 },
6370 { /* MCP61 Ethernet Controller */
6371 PCI_DEVICE(0x10DE, 0x03E6),
6372 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6373 },
6374 { /* MCP61 Ethernet Controller */
6375 PCI_DEVICE(0x10DE, 0x03EE),
6376 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6377 },
6378 { /* MCP61 Ethernet Controller */
6379 PCI_DEVICE(0x10DE, 0x03EF),
6380 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6381 },
6382 { /* MCP65 Ethernet Controller */
6383 PCI_DEVICE(0x10DE, 0x0450),
6384 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6385 },
6386 { /* MCP65 Ethernet Controller */
6387 PCI_DEVICE(0x10DE, 0x0451),
6388 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6389 },
6390 { /* MCP65 Ethernet Controller */
6391 PCI_DEVICE(0x10DE, 0x0452),
6392 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6393 },
6394 { /* MCP65 Ethernet Controller */
6395 PCI_DEVICE(0x10DE, 0x0453),
6396 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6397 },
6398 { /* MCP67 Ethernet Controller */
6399 PCI_DEVICE(0x10DE, 0x054C),
6400 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6401 },
6402 { /* MCP67 Ethernet Controller */
6403 PCI_DEVICE(0x10DE, 0x054D),
6404 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6405 },
6406 { /* MCP67 Ethernet Controller */
6407 PCI_DEVICE(0x10DE, 0x054E),
6408 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6409 },
6410 { /* MCP67 Ethernet Controller */
6411 PCI_DEVICE(0x10DE, 0x054F),
6412 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6413 },
6414 { /* MCP73 Ethernet Controller */
6415 PCI_DEVICE(0x10DE, 0x07DC),
6416 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6417 },
6418 { /* MCP73 Ethernet Controller */
6419 PCI_DEVICE(0x10DE, 0x07DD),
6420 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6421 },
6422 { /* MCP73 Ethernet Controller */
6423 PCI_DEVICE(0x10DE, 0x07DE),
6424 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6425 },
6426 { /* MCP73 Ethernet Controller */
6427 PCI_DEVICE(0x10DE, 0x07DF),
6428 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6429 },
6430 { /* MCP77 Ethernet Controller */
6431 PCI_DEVICE(0x10DE, 0x0760),
6432 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6433 },
6434 { /* MCP77 Ethernet Controller */
6435 PCI_DEVICE(0x10DE, 0x0761),
6436 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6437 },
6438 { /* MCP77 Ethernet Controller */
6439 PCI_DEVICE(0x10DE, 0x0762),
6440 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6441 },
6442 { /* MCP77 Ethernet Controller */
6443 PCI_DEVICE(0x10DE, 0x0763),
6444 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6445 },
6446 { /* MCP79 Ethernet Controller */
6447 PCI_DEVICE(0x10DE, 0x0AB0),
6448 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6449 },
6450 { /* MCP79 Ethernet Controller */
6451 PCI_DEVICE(0x10DE, 0x0AB1),
6452 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6453 },
6454 { /* MCP79 Ethernet Controller */
6455 PCI_DEVICE(0x10DE, 0x0AB2),
6456 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6457 },
6458 { /* MCP79 Ethernet Controller */
6459 PCI_DEVICE(0x10DE, 0x0AB3),
6460 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6461 },
6462 { /* MCP89 Ethernet Controller */
6463 PCI_DEVICE(0x10DE, 0x0D7D),
6464 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
6465 },
6466 {0,},
6467};
6468
6469static struct pci_driver forcedeth_pci_driver = {
6470 .name = DRV_NAME,
6471 .id_table = pci_tbl,
6472 .probe = nv_probe,
6473 .remove = nv_remove,
6474 .shutdown = nv_shutdown,
6475 .driver.pm = NV_PM_OPS,
6476};
6477
6478module_param(max_interrupt_work, int, 0);
6479MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6480module_param(optimization_mode, int, 0);
6481MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6482module_param(poll_interval, int, 0);
6483MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6484module_param(msi, int, 0);
6485MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6486module_param(msix, int, 0);
6487MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6488module_param(dma_64bit, int, 0);
6489MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6490module_param(phy_cross, int, 0);
6491MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6492module_param(phy_power_down, int, 0);
6493MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6494module_param(debug_tx_timeout, bool, 0);
6495MODULE_PARM_DESC(debug_tx_timeout,
6496 "Dump tx related registers and ring when tx_timeout happens");
6497
6498module_pci_driver(forcedeth_pci_driver);
6499MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6500MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6501MODULE_LICENSE("GPL");
6502MODULE_DEVICE_TABLE(pci, pci_tbl);