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1/* SPDX-License-Identifier: GPL-2.0+ */
2/* Copyright (C) 2018 Microchip Technology Inc. */
3
4#ifndef _LAN743X_H
5#define _LAN743X_H
6
7#include <linux/phy.h>
8#include "lan743x_ptp.h"
9
10#define DRIVER_AUTHOR "Bryan Whitehead <Bryan.Whitehead@microchip.com>"
11#define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver"
12#define DRIVER_NAME "lan743x"
13
14/* Register Definitions */
15#define ID_REV (0x00)
16#define ID_REV_ID_MASK_ (0xFFFF0000)
17#define ID_REV_ID_LAN7430_ (0x74300000)
18#define ID_REV_ID_LAN7431_ (0x74310000)
19#define ID_REV_IS_VALID_CHIP_ID_(id_rev) \
20 (((id_rev) & 0xFFF00000) == 0x74300000)
21#define ID_REV_CHIP_REV_MASK_ (0x0000FFFF)
22#define ID_REV_CHIP_REV_A0_ (0x00000000)
23#define ID_REV_CHIP_REV_B0_ (0x00000010)
24
25#define FPGA_REV (0x04)
26#define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF)
27#define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF)
28
29#define HW_CFG (0x010)
30#define HW_CFG_RELOAD_TYPE_ALL_ (0x00000FC0)
31#define HW_CFG_EE_OTP_RELOAD_ BIT(4)
32#define HW_CFG_LRST_ BIT(1)
33
34#define PMT_CTL (0x014)
35#define PMT_CTL_ETH_PHY_D3_COLD_OVR_ BIT(27)
36#define PMT_CTL_MAC_D3_RX_CLK_OVR_ BIT(25)
37#define PMT_CTL_ETH_PHY_EDPD_PLL_CTL_ BIT(24)
38#define PMT_CTL_ETH_PHY_D3_OVR_ BIT(23)
39#define PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_ BIT(18)
40#define PMT_CTL_GPIO_WAKEUP_EN_ BIT(15)
41#define PMT_CTL_EEE_WAKEUP_EN_ BIT(13)
42#define PMT_CTL_READY_ BIT(7)
43#define PMT_CTL_ETH_PHY_RST_ BIT(4)
44#define PMT_CTL_WOL_EN_ BIT(3)
45#define PMT_CTL_ETH_PHY_WAKE_EN_ BIT(2)
46#define PMT_CTL_WUPS_MASK_ (0x00000003)
47
48#define DP_SEL (0x024)
49#define DP_SEL_DPRDY_ BIT(31)
50#define DP_SEL_MASK_ (0x0000001F)
51#define DP_SEL_RFE_RAM (0x00000001)
52
53#define DP_SEL_VHF_HASH_LEN (16)
54#define DP_SEL_VHF_VLAN_LEN (128)
55
56#define DP_CMD (0x028)
57#define DP_CMD_WRITE_ (0x00000001)
58
59#define DP_ADDR (0x02C)
60
61#define DP_DATA_0 (0x030)
62
63#define E2P_CMD (0x040)
64#define E2P_CMD_EPC_BUSY_ BIT(31)
65#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000)
66#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000)
67#define E2P_CMD_EPC_CMD_READ_ (0x00000000)
68#define E2P_CMD_EPC_TIMEOUT_ BIT(10)
69#define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF)
70
71#define E2P_DATA (0x044)
72
73#define GPIO_CFG0 (0x050)
74#define GPIO_CFG0_GPIO_DIR_BIT_(bit) BIT(16 + (bit))
75#define GPIO_CFG0_GPIO_DATA_BIT_(bit) BIT(0 + (bit))
76
77#define GPIO_CFG1 (0x054)
78#define GPIO_CFG1_GPIOEN_BIT_(bit) BIT(16 + (bit))
79#define GPIO_CFG1_GPIOBUF_BIT_(bit) BIT(0 + (bit))
80
81#define GPIO_CFG2 (0x058)
82#define GPIO_CFG2_1588_POL_BIT_(bit) BIT(0 + (bit))
83
84#define GPIO_CFG3 (0x05C)
85#define GPIO_CFG3_1588_CH_SEL_BIT_(bit) BIT(16 + (bit))
86#define GPIO_CFG3_1588_OE_BIT_(bit) BIT(0 + (bit))
87
88#define FCT_RX_CTL (0xAC)
89#define FCT_RX_CTL_EN_(channel) BIT(28 + (channel))
90#define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel))
91#define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel))
92
93#define FCT_TX_CTL (0xC4)
94#define FCT_TX_CTL_EN_(channel) BIT(28 + (channel))
95#define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel))
96#define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel))
97
98#define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2))
99#define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00)
100#define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value) \
101 ((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_)
102#define FCT_FLOW_CTL_REQ_EN_ BIT(7)
103#define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F)
104#define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value) \
105 ((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_)
106
107#define MAC_CR (0x100)
108#define MAC_CR_MII_EN_ BIT(19)
109#define MAC_CR_EEE_EN_ BIT(17)
110#define MAC_CR_ADD_ BIT(12)
111#define MAC_CR_ASD_ BIT(11)
112#define MAC_CR_CNTR_RST_ BIT(5)
113#define MAC_CR_DPX_ BIT(3)
114#define MAC_CR_CFG_H_ BIT(2)
115#define MAC_CR_CFG_L_ BIT(1)
116#define MAC_CR_RST_ BIT(0)
117
118#define MAC_RX (0x104)
119#define MAC_RX_MAX_SIZE_SHIFT_ (16)
120#define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000)
121#define MAC_RX_RXD_ BIT(1)
122#define MAC_RX_RXEN_ BIT(0)
123
124#define MAC_TX (0x108)
125#define MAC_TX_TXD_ BIT(1)
126#define MAC_TX_TXEN_ BIT(0)
127
128#define MAC_FLOW (0x10C)
129#define MAC_FLOW_CR_TX_FCEN_ BIT(30)
130#define MAC_FLOW_CR_RX_FCEN_ BIT(29)
131#define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF)
132
133#define MAC_RX_ADDRH (0x118)
134
135#define MAC_RX_ADDRL (0x11C)
136
137#define MAC_MII_ACC (0x120)
138#define MAC_MII_ACC_PHY_ADDR_SHIFT_ (11)
139#define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800)
140#define MAC_MII_ACC_MIIRINDA_SHIFT_ (6)
141#define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0)
142#define MAC_MII_ACC_MII_READ_ (0x00000000)
143#define MAC_MII_ACC_MII_WRITE_ (0x00000002)
144#define MAC_MII_ACC_MII_BUSY_ BIT(0)
145
146#define MAC_MII_DATA (0x124)
147
148#define MAC_EEE_TX_LPI_REQ_DLY_CNT (0x130)
149
150#define MAC_WUCSR (0x140)
151#define MAC_WUCSR_RFE_WAKE_EN_ BIT(14)
152#define MAC_WUCSR_PFDA_EN_ BIT(3)
153#define MAC_WUCSR_WAKE_EN_ BIT(2)
154#define MAC_WUCSR_MPEN_ BIT(1)
155#define MAC_WUCSR_BCST_EN_ BIT(0)
156
157#define MAC_WK_SRC (0x144)
158
159#define MAC_WUF_CFG0 (0x150)
160#define MAC_NUM_OF_WUF_CFG (32)
161#define MAC_WUF_CFG_BEGIN (MAC_WUF_CFG0)
162#define MAC_WUF_CFG(index) (MAC_WUF_CFG_BEGIN + (4 * (index)))
163#define MAC_WUF_CFG_EN_ BIT(31)
164#define MAC_WUF_CFG_TYPE_MCAST_ (0x02000000)
165#define MAC_WUF_CFG_TYPE_ALL_ (0x01000000)
166#define MAC_WUF_CFG_OFFSET_SHIFT_ (16)
167#define MAC_WUF_CFG_CRC16_MASK_ (0x0000FFFF)
168
169#define MAC_WUF_MASK0_0 (0x200)
170#define MAC_WUF_MASK0_1 (0x204)
171#define MAC_WUF_MASK0_2 (0x208)
172#define MAC_WUF_MASK0_3 (0x20C)
173#define MAC_WUF_MASK0_BEGIN (MAC_WUF_MASK0_0)
174#define MAC_WUF_MASK1_BEGIN (MAC_WUF_MASK0_1)
175#define MAC_WUF_MASK2_BEGIN (MAC_WUF_MASK0_2)
176#define MAC_WUF_MASK3_BEGIN (MAC_WUF_MASK0_3)
177#define MAC_WUF_MASK0(index) (MAC_WUF_MASK0_BEGIN + (0x10 * (index)))
178#define MAC_WUF_MASK1(index) (MAC_WUF_MASK1_BEGIN + (0x10 * (index)))
179#define MAC_WUF_MASK2(index) (MAC_WUF_MASK2_BEGIN + (0x10 * (index)))
180#define MAC_WUF_MASK3(index) (MAC_WUF_MASK3_BEGIN + (0x10 * (index)))
181
182/* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */
183#define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x)))
184#define RFE_ADDR_FILT_HI_VALID_ BIT(31)
185
186/* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */
187#define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x)))
188
189#define RFE_CTL (0x508)
190#define RFE_CTL_AB_ BIT(10)
191#define RFE_CTL_AM_ BIT(9)
192#define RFE_CTL_AU_ BIT(8)
193#define RFE_CTL_MCAST_HASH_ BIT(3)
194#define RFE_CTL_DA_PERFECT_ BIT(1)
195
196#define RFE_RSS_CFG (0x554)
197#define RFE_RSS_CFG_UDP_IPV6_EX_ BIT(16)
198#define RFE_RSS_CFG_TCP_IPV6_EX_ BIT(15)
199#define RFE_RSS_CFG_IPV6_EX_ BIT(14)
200#define RFE_RSS_CFG_UDP_IPV6_ BIT(13)
201#define RFE_RSS_CFG_TCP_IPV6_ BIT(12)
202#define RFE_RSS_CFG_IPV6_ BIT(11)
203#define RFE_RSS_CFG_UDP_IPV4_ BIT(10)
204#define RFE_RSS_CFG_TCP_IPV4_ BIT(9)
205#define RFE_RSS_CFG_IPV4_ BIT(8)
206#define RFE_RSS_CFG_VALID_HASH_BITS_ (0x000000E0)
207#define RFE_RSS_CFG_RSS_QUEUE_ENABLE_ BIT(2)
208#define RFE_RSS_CFG_RSS_HASH_STORE_ BIT(1)
209#define RFE_RSS_CFG_RSS_ENABLE_ BIT(0)
210
211#define RFE_HASH_KEY(index) (0x558 + (index << 2))
212
213#define RFE_INDX(index) (0x580 + (index << 2))
214
215#define MAC_WUCSR2 (0x600)
216
217#define INT_STS (0x780)
218#define INT_BIT_DMA_RX_(channel) BIT(24 + (channel))
219#define INT_BIT_ALL_RX_ (0x0F000000)
220#define INT_BIT_DMA_TX_(channel) BIT(16 + (channel))
221#define INT_BIT_ALL_TX_ (0x000F0000)
222#define INT_BIT_SW_GP_ BIT(9)
223#define INT_BIT_1588_ BIT(7)
224#define INT_BIT_ALL_OTHER_ (INT_BIT_SW_GP_ | INT_BIT_1588_)
225#define INT_BIT_MAS_ BIT(0)
226
227#define INT_SET (0x784)
228
229#define INT_EN_SET (0x788)
230
231#define INT_EN_CLR (0x78C)
232
233#define INT_STS_R2C (0x790)
234
235#define INT_VEC_EN_SET (0x794)
236#define INT_VEC_EN_CLR (0x798)
237#define INT_VEC_EN_AUTO_CLR (0x79C)
238#define INT_VEC_EN_(vector_index) BIT(0 + vector_index)
239
240#define INT_VEC_MAP0 (0x7A0)
241#define INT_VEC_MAP0_RX_VEC_(channel, vector) \
242 (((u32)(vector)) << ((channel) << 2))
243
244#define INT_VEC_MAP1 (0x7A4)
245#define INT_VEC_MAP1_TX_VEC_(channel, vector) \
246 (((u32)(vector)) << ((channel) << 2))
247
248#define INT_VEC_MAP2 (0x7A8)
249
250#define INT_MOD_MAP0 (0x7B0)
251
252#define INT_MOD_MAP1 (0x7B4)
253
254#define INT_MOD_MAP2 (0x7B8)
255
256#define INT_MOD_CFG0 (0x7C0)
257#define INT_MOD_CFG1 (0x7C4)
258#define INT_MOD_CFG2 (0x7C8)
259#define INT_MOD_CFG3 (0x7CC)
260#define INT_MOD_CFG4 (0x7D0)
261#define INT_MOD_CFG5 (0x7D4)
262#define INT_MOD_CFG6 (0x7D8)
263#define INT_MOD_CFG7 (0x7DC)
264
265#define PTP_CMD_CTL (0x0A00)
266#define PTP_CMD_CTL_PTP_CLK_STP_NSEC_ BIT(6)
267#define PTP_CMD_CTL_PTP_CLOCK_STEP_SEC_ BIT(5)
268#define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4)
269#define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3)
270#define PTP_CMD_CTL_PTP_ENABLE_ BIT(2)
271#define PTP_CMD_CTL_PTP_DISABLE_ BIT(1)
272#define PTP_CMD_CTL_PTP_RESET_ BIT(0)
273#define PTP_GENERAL_CONFIG (0x0A04)
274#define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \
275 (0x7 << (1 + ((channel) << 2)))
276#define PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0)
277#define PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (1)
278#define PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (2)
279#define PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (3)
280#define PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (4)
281#define PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (5)
282#define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \
283 (((value) & 0x7) << (1 + ((channel) << 2)))
284#define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) << 2))
285
286#define PTP_INT_STS (0x0A08)
287#define PTP_INT_EN_SET (0x0A0C)
288#define PTP_INT_EN_CLR (0x0A10)
289#define PTP_INT_BIT_TX_SWTS_ERR_ BIT(13)
290#define PTP_INT_BIT_TX_TS_ BIT(12)
291#define PTP_INT_BIT_TIMER_B_ BIT(1)
292#define PTP_INT_BIT_TIMER_A_ BIT(0)
293
294#define PTP_CLOCK_SEC (0x0A14)
295#define PTP_CLOCK_NS (0x0A18)
296#define PTP_CLOCK_SUBNS (0x0A1C)
297#define PTP_CLOCK_RATE_ADJ (0x0A20)
298#define PTP_CLOCK_RATE_ADJ_DIR_ BIT(31)
299#define PTP_CLOCK_STEP_ADJ (0x0A2C)
300#define PTP_CLOCK_STEP_ADJ_DIR_ BIT(31)
301#define PTP_CLOCK_STEP_ADJ_VALUE_MASK_ (0x3FFFFFFF)
302#define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4))
303#define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4))
304#define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4))
305#define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4))
306#define PTP_LATENCY (0x0A5C)
307#define PTP_LATENCY_TX_SET_(tx_latency) (((u32)(tx_latency)) << 16)
308#define PTP_LATENCY_RX_SET_(rx_latency) \
309 (((u32)(rx_latency)) & 0x0000FFFF)
310#define PTP_CAP_INFO (0x0A60)
311#define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x00000070) >> 4)
312
313#define PTP_TX_MOD (0x0AA4)
314#define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ (0x10000000)
315
316#define PTP_TX_MOD2 (0x0AA8)
317#define PTP_TX_MOD2_TX_PTP_CLR_UDPV4_CHKSUM_ (0x00000001)
318
319#define PTP_TX_EGRESS_SEC (0x0AAC)
320#define PTP_TX_EGRESS_NS (0x0AB0)
321#define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_ (0xC0000000)
322#define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_ (0x00000000)
323#define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_ (0x40000000)
324#define PTP_TX_EGRESS_NS_TS_NS_MASK_ (0x3FFFFFFF)
325
326#define PTP_TX_MSG_HEADER (0x0AB4)
327#define PTP_TX_MSG_HEADER_MSG_TYPE_ (0x000F0000)
328#define PTP_TX_MSG_HEADER_MSG_TYPE_SYNC_ (0x00000000)
329
330#define DMAC_CFG (0xC00)
331#define DMAC_CFG_COAL_EN_ BIT(16)
332#define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000)
333#define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070)
334#define DMAC_CFG_MAX_READ_REQ_SET_(val) \
335 ((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_)
336#define DMAC_CFG_MAX_DSPACE_16_ (0x00000000)
337#define DMAC_CFG_MAX_DSPACE_32_ (0x00000001)
338#define DMAC_CFG_MAX_DSPACE_64_ BIT(1)
339#define DMAC_CFG_MAX_DSPACE_128_ (0x00000003)
340
341#define DMAC_COAL_CFG (0xC04)
342#define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000)
343#define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val) \
344 ((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_)
345#define DMAC_COAL_CFG_TIMER_TX_START_ BIT(19)
346#define DMAC_COAL_CFG_FLUSH_INTS_ BIT(18)
347#define DMAC_COAL_CFG_INT_EXIT_COAL_ BIT(17)
348#define DMAC_COAL_CFG_CSR_EXIT_COAL_ BIT(16)
349#define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00)
350#define DMAC_COAL_CFG_TX_THRES_SET_(val) \
351 ((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_)
352#define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF)
353#define DMAC_COAL_CFG_RX_THRES_SET_(val) \
354 (((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_)
355
356#define DMAC_OBFF_CFG (0xC08)
357#define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00)
358#define DMAC_OBFF_TX_THRES_SET_(val) \
359 ((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_)
360#define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF)
361#define DMAC_OBFF_RX_THRES_SET_(val) \
362 (((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_)
363
364#define DMAC_CMD (0xC0C)
365#define DMAC_CMD_SWR_ BIT(31)
366#define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel))
367#define DMAC_CMD_START_T_(channel) BIT(20 + (channel))
368#define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel))
369#define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel))
370#define DMAC_CMD_START_R_(channel) BIT(4 + (channel))
371#define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel))
372
373#define DMAC_INT_STS (0xC10)
374#define DMAC_INT_EN_SET (0xC14)
375#define DMAC_INT_EN_CLR (0xC18)
376#define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel))
377#define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel))
378
379#define RX_CFG_A(channel) (0xC40 + ((channel) << 6))
380#define RX_CFG_A_RX_WB_ON_INT_TMR_ BIT(30)
381#define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000)
382#define RX_CFG_A_RX_WB_THRES_SET_(val) \
383 ((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_)
384#define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000)
385#define RX_CFG_A_RX_PF_THRES_SET_(val) \
386 ((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_)
387#define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00)
388#define RX_CFG_A_RX_PF_PRI_THRES_SET_(val) \
389 ((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_)
390#define RX_CFG_A_RX_HP_WB_EN_ BIT(5)
391
392#define RX_CFG_B(channel) (0xC44 + ((channel) << 6))
393#define RX_CFG_B_TS_ALL_RX_ BIT(29)
394#define RX_CFG_B_RX_PAD_MASK_ (0x03000000)
395#define RX_CFG_B_RX_PAD_0_ (0x00000000)
396#define RX_CFG_B_RX_PAD_2_ (0x02000000)
397#define RX_CFG_B_RDMABL_512_ (0x00040000)
398#define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF)
399
400#define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6))
401
402#define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6))
403
404#define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6))
405
406#define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6))
407
408#define RX_HEAD(channel) (0xC58 + ((channel) << 6))
409
410#define RX_TAIL(channel) (0xC5C + ((channel) << 6))
411#define RX_TAIL_SET_TOP_INT_EN_ BIT(30)
412#define RX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29)
413
414#define RX_CFG_C(channel) (0xC64 + ((channel) << 6))
415#define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_ BIT(6)
416#define RX_CFG_C_RX_INT_EN_R2C_ BIT(4)
417#define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_ BIT(3)
418#define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007)
419
420#define TX_CFG_A(channel) (0xD40 + ((channel) << 6))
421#define TX_CFG_A_TX_HP_WB_ON_INT_TMR_ BIT(30)
422#define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000)
423#define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000)
424#define TX_CFG_A_TX_PF_THRES_SET_(value) \
425 ((((u32)(value)) << 16) & TX_CFG_A_TX_PF_THRES_MASK_)
426#define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00)
427#define TX_CFG_A_TX_PF_PRI_THRES_SET_(value) \
428 ((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_)
429#define TX_CFG_A_TX_HP_WB_EN_ BIT(5)
430#define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F)
431#define TX_CFG_A_TX_HP_WB_THRES_SET_(value) \
432 (((u32)(value)) & TX_CFG_A_TX_HP_WB_THRES_MASK_)
433
434#define TX_CFG_B(channel) (0xD44 + ((channel) << 6))
435#define TX_CFG_B_TDMABL_512_ (0x00040000)
436#define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF)
437
438#define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6))
439
440#define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6))
441
442#define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6))
443
444#define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6))
445
446#define TX_HEAD(channel) (0xD58 + ((channel) << 6))
447
448#define TX_TAIL(channel) (0xD5C + ((channel) << 6))
449#define TX_TAIL_SET_DMAC_INT_EN_ BIT(31)
450#define TX_TAIL_SET_TOP_INT_EN_ BIT(30)
451#define TX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29)
452
453#define TX_CFG_C(channel) (0xD64 + ((channel) << 6))
454#define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_ BIT(6)
455#define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_ BIT(5)
456#define TX_CFG_C_TX_INT_EN_R2C_ BIT(4)
457#define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_ BIT(3)
458#define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007)
459
460#define OTP_PWR_DN (0x1000)
461#define OTP_PWR_DN_PWRDN_N_ BIT(0)
462
463#define OTP_ADDR_HIGH (0x1004)
464#define OTP_ADDR_LOW (0x1008)
465
466#define OTP_PRGM_DATA (0x1010)
467
468#define OTP_PRGM_MODE (0x1014)
469#define OTP_PRGM_MODE_BYTE_ BIT(0)
470
471#define OTP_READ_DATA (0x1018)
472
473#define OTP_FUNC_CMD (0x1020)
474#define OTP_FUNC_CMD_READ_ BIT(0)
475
476#define OTP_TST_CMD (0x1024)
477#define OTP_TST_CMD_PRGVRFY_ BIT(3)
478
479#define OTP_CMD_GO (0x1028)
480#define OTP_CMD_GO_GO_ BIT(0)
481
482#define OTP_STATUS (0x1030)
483#define OTP_STATUS_BUSY_ BIT(0)
484
485/* MAC statistics registers */
486#define STAT_RX_FCS_ERRORS (0x1200)
487#define STAT_RX_ALIGNMENT_ERRORS (0x1204)
488#define STAT_RX_FRAGMENT_ERRORS (0x1208)
489#define STAT_RX_JABBER_ERRORS (0x120C)
490#define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210)
491#define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214)
492#define STAT_RX_DROPPED_FRAMES (0x1218)
493#define STAT_RX_UNICAST_BYTE_COUNT (0x121C)
494#define STAT_RX_BROADCAST_BYTE_COUNT (0x1220)
495#define STAT_RX_MULTICAST_BYTE_COUNT (0x1224)
496#define STAT_RX_UNICAST_FRAMES (0x1228)
497#define STAT_RX_BROADCAST_FRAMES (0x122C)
498#define STAT_RX_MULTICAST_FRAMES (0x1230)
499#define STAT_RX_PAUSE_FRAMES (0x1234)
500#define STAT_RX_64_BYTE_FRAMES (0x1238)
501#define STAT_RX_65_127_BYTE_FRAMES (0x123C)
502#define STAT_RX_128_255_BYTE_FRAMES (0x1240)
503#define STAT_RX_256_511_BYTES_FRAMES (0x1244)
504#define STAT_RX_512_1023_BYTE_FRAMES (0x1248)
505#define STAT_RX_1024_1518_BYTE_FRAMES (0x124C)
506#define STAT_RX_GREATER_1518_BYTE_FRAMES (0x1250)
507#define STAT_RX_TOTAL_FRAMES (0x1254)
508#define STAT_EEE_RX_LPI_TRANSITIONS (0x1258)
509#define STAT_EEE_RX_LPI_TIME (0x125C)
510#define STAT_RX_COUNTER_ROLLOVER_STATUS (0x127C)
511
512#define STAT_TX_FCS_ERRORS (0x1280)
513#define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284)
514#define STAT_TX_CARRIER_ERRORS (0x1288)
515#define STAT_TX_BAD_BYTE_COUNT (0x128C)
516#define STAT_TX_SINGLE_COLLISIONS (0x1290)
517#define STAT_TX_MULTIPLE_COLLISIONS (0x1294)
518#define STAT_TX_EXCESSIVE_COLLISION (0x1298)
519#define STAT_TX_LATE_COLLISIONS (0x129C)
520#define STAT_TX_UNICAST_BYTE_COUNT (0x12A0)
521#define STAT_TX_BROADCAST_BYTE_COUNT (0x12A4)
522#define STAT_TX_MULTICAST_BYTE_COUNT (0x12A8)
523#define STAT_TX_UNICAST_FRAMES (0x12AC)
524#define STAT_TX_BROADCAST_FRAMES (0x12B0)
525#define STAT_TX_MULTICAST_FRAMES (0x12B4)
526#define STAT_TX_PAUSE_FRAMES (0x12B8)
527#define STAT_TX_64_BYTE_FRAMES (0x12BC)
528#define STAT_TX_65_127_BYTE_FRAMES (0x12C0)
529#define STAT_TX_128_255_BYTE_FRAMES (0x12C4)
530#define STAT_TX_256_511_BYTES_FRAMES (0x12C8)
531#define STAT_TX_512_1023_BYTE_FRAMES (0x12CC)
532#define STAT_TX_1024_1518_BYTE_FRAMES (0x12D0)
533#define STAT_TX_GREATER_1518_BYTE_FRAMES (0x12D4)
534#define STAT_TX_TOTAL_FRAMES (0x12D8)
535#define STAT_EEE_TX_LPI_TRANSITIONS (0x12DC)
536#define STAT_EEE_TX_LPI_TIME (0x12E0)
537#define STAT_TX_COUNTER_ROLLOVER_STATUS (0x12FC)
538
539/* End of Register definitions */
540
541#define LAN743X_MAX_RX_CHANNELS (4)
542#define LAN743X_MAX_TX_CHANNELS (1)
543struct lan743x_adapter;
544
545#define LAN743X_USED_RX_CHANNELS (4)
546#define LAN743X_USED_TX_CHANNELS (1)
547#define LAN743X_INT_MOD (400)
548
549#if (LAN743X_USED_RX_CHANNELS > LAN743X_MAX_RX_CHANNELS)
550#error Invalid LAN743X_USED_RX_CHANNELS
551#endif
552#if (LAN743X_USED_TX_CHANNELS > LAN743X_MAX_TX_CHANNELS)
553#error Invalid LAN743X_USED_TX_CHANNELS
554#endif
555
556/* PCI */
557/* SMSC acquired EFAR late 1990's, MCHP acquired SMSC 2012 */
558#define PCI_VENDOR_ID_SMSC PCI_VENDOR_ID_EFAR
559#define PCI_DEVICE_ID_SMSC_LAN7430 (0x7430)
560#define PCI_DEVICE_ID_SMSC_LAN7431 (0x7431)
561
562#define PCI_CONFIG_LENGTH (0x1000)
563
564/* CSR */
565#define CSR_LENGTH (0x2000)
566
567#define LAN743X_CSR_FLAG_IS_A0 BIT(0)
568#define LAN743X_CSR_FLAG_IS_B0 BIT(1)
569#define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR BIT(8)
570
571struct lan743x_csr {
572 u32 flags;
573 u8 __iomem *csr_address;
574 u32 id_rev;
575 u32 fpga_rev;
576};
577
578/* INTERRUPTS */
579typedef void(*lan743x_vector_handler)(void *context, u32 int_sts, u32 flags);
580
581#define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0)
582#define LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ BIT(1)
583#define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C BIT(2)
584#define LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C BIT(3)
585#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK BIT(4)
586#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR BIT(5)
587#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C BIT(6)
588#define LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR BIT(7)
589#define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET BIT(8)
590#define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR BIT(9)
591#define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET BIT(10)
592#define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR BIT(11)
593#define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET BIT(12)
594#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR BIT(13)
595#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET BIT(14)
596#define LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR BIT(15)
597
598struct lan743x_vector {
599 int irq;
600 u32 flags;
601 struct lan743x_adapter *adapter;
602 int vector_index;
603 u32 int_mask;
604 lan743x_vector_handler handler;
605 void *context;
606};
607
608#define LAN743X_MAX_VECTOR_COUNT (8)
609
610struct lan743x_intr {
611 int flags;
612
613 unsigned int irq;
614
615 struct lan743x_vector vector_list[LAN743X_MAX_VECTOR_COUNT];
616 int number_of_vectors;
617 bool using_vectors;
618
619 int software_isr_flag;
620};
621
622#define LAN743X_MAX_FRAME_SIZE (9 * 1024)
623
624/* PHY */
625struct lan743x_phy {
626 bool fc_autoneg;
627 u8 fc_request_control;
628};
629
630/* TX */
631struct lan743x_tx_descriptor;
632struct lan743x_tx_buffer_info;
633
634#define GPIO_QUEUE_STARTED (0)
635#define GPIO_TX_FUNCTION (1)
636#define GPIO_TX_COMPLETION (2)
637#define GPIO_TX_FRAGMENT (3)
638
639#define TX_FRAME_FLAG_IN_PROGRESS BIT(0)
640
641#define TX_TS_FLAG_TIMESTAMPING_ENABLED BIT(0)
642#define TX_TS_FLAG_ONE_STEP_SYNC BIT(1)
643
644struct lan743x_tx {
645 struct lan743x_adapter *adapter;
646 u32 ts_flags;
647 u32 vector_flags;
648 int channel_number;
649
650 int ring_size;
651 size_t ring_allocation_size;
652 struct lan743x_tx_descriptor *ring_cpu_ptr;
653 dma_addr_t ring_dma_ptr;
654 /* ring_lock: used to prevent concurrent access to tx ring */
655 spinlock_t ring_lock;
656 u32 frame_flags;
657 u32 frame_first;
658 u32 frame_data0;
659 u32 frame_tail;
660
661 struct lan743x_tx_buffer_info *buffer_info;
662
663 u32 *head_cpu_ptr;
664 dma_addr_t head_dma_ptr;
665 int last_head;
666 int last_tail;
667
668 struct napi_struct napi;
669
670 struct sk_buff *overflow_skb;
671};
672
673void lan743x_tx_set_timestamping_mode(struct lan743x_tx *tx,
674 bool enable_timestamping,
675 bool enable_onestep_sync);
676
677/* RX */
678struct lan743x_rx_descriptor;
679struct lan743x_rx_buffer_info;
680
681struct lan743x_rx {
682 struct lan743x_adapter *adapter;
683 u32 vector_flags;
684 int channel_number;
685
686 int ring_size;
687 size_t ring_allocation_size;
688 struct lan743x_rx_descriptor *ring_cpu_ptr;
689 dma_addr_t ring_dma_ptr;
690
691 struct lan743x_rx_buffer_info *buffer_info;
692
693 u32 *head_cpu_ptr;
694 dma_addr_t head_dma_ptr;
695 u32 last_head;
696 u32 last_tail;
697
698 struct napi_struct napi;
699
700 u32 frame_count;
701};
702
703struct lan743x_adapter {
704 struct net_device *netdev;
705 struct mii_bus *mdiobus;
706 phy_interface_t phy_mode;
707 int msg_enable;
708#ifdef CONFIG_PM
709 u32 wolopts;
710#endif
711 struct pci_dev *pdev;
712 struct lan743x_csr csr;
713 struct lan743x_intr intr;
714
715 /* lock, used to prevent concurrent access to data port */
716 struct mutex dp_lock;
717
718 struct lan743x_gpio gpio;
719 struct lan743x_ptp ptp;
720
721 u8 mac_address[ETH_ALEN];
722
723 struct lan743x_phy phy;
724 struct lan743x_tx tx[LAN743X_MAX_TX_CHANNELS];
725 struct lan743x_rx rx[LAN743X_MAX_RX_CHANNELS];
726
727#define LAN743X_ADAPTER_FLAG_OTP BIT(0)
728 u32 flags;
729};
730
731#define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel))
732
733#define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index)
734#define INTR_FLAG_MSI_ENABLED BIT(8)
735#define INTR_FLAG_MSIX_ENABLED BIT(9)
736
737#define MAC_MII_READ 1
738#define MAC_MII_WRITE 0
739
740#define PHY_FLAG_OPENED BIT(0)
741#define PHY_FLAG_ATTACHED BIT(1)
742
743#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
744#define DMA_ADDR_HIGH32(dma_addr) ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF))
745#else
746#define DMA_ADDR_HIGH32(dma_addr) ((u32)(0))
747#endif
748#define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF))
749#define DMA_DESCRIPTOR_SPACING_16 (16)
750#define DMA_DESCRIPTOR_SPACING_32 (32)
751#define DMA_DESCRIPTOR_SPACING_64 (64)
752#define DMA_DESCRIPTOR_SPACING_128 (128)
753#define DEFAULT_DMA_DESCRIPTOR_SPACING (L1_CACHE_BYTES)
754
755#define DMAC_CHANNEL_STATE_SET(start_bit, stop_bit) \
756 (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0))
757#define DMAC_CHANNEL_STATE_INITIAL DMAC_CHANNEL_STATE_SET(0, 0)
758#define DMAC_CHANNEL_STATE_STARTED DMAC_CHANNEL_STATE_SET(1, 0)
759#define DMAC_CHANNEL_STATE_STOP_PENDING DMAC_CHANNEL_STATE_SET(1, 1)
760#define DMAC_CHANNEL_STATE_STOPPED DMAC_CHANNEL_STATE_SET(0, 1)
761
762/* TX Descriptor bits */
763#define TX_DESC_DATA0_DTYPE_MASK_ (0xC0000000)
764#define TX_DESC_DATA0_DTYPE_DATA_ (0x00000000)
765#define TX_DESC_DATA0_DTYPE_EXT_ (0x40000000)
766#define TX_DESC_DATA0_FS_ (0x20000000)
767#define TX_DESC_DATA0_LS_ (0x10000000)
768#define TX_DESC_DATA0_EXT_ (0x08000000)
769#define TX_DESC_DATA0_IOC_ (0x04000000)
770#define TX_DESC_DATA0_ICE_ (0x00400000)
771#define TX_DESC_DATA0_IPE_ (0x00200000)
772#define TX_DESC_DATA0_TPE_ (0x00100000)
773#define TX_DESC_DATA0_FCS_ (0x00020000)
774#define TX_DESC_DATA0_TSE_ (0x00010000)
775#define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF)
776#define TX_DESC_DATA0_EXT_LSO_ (0x00200000)
777#define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF)
778#define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_ (0x3FFF0000)
779
780struct lan743x_tx_descriptor {
781 u32 data0;
782 u32 data1;
783 u32 data2;
784 u32 data3;
785} __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING);
786
787#define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0)
788#define TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED BIT(1)
789#define TX_BUFFER_INFO_FLAG_IGNORE_SYNC BIT(2)
790#define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT BIT(3)
791struct lan743x_tx_buffer_info {
792 int flags;
793 struct sk_buff *skb;
794 dma_addr_t dma_ptr;
795 unsigned int buffer_length;
796};
797
798#define LAN743X_TX_RING_SIZE (50)
799
800/* OWN bit is set. ie, Descs are owned by RX DMAC */
801#define RX_DESC_DATA0_OWN_ (0x00008000)
802/* OWN bit is clear. ie, Descs are owned by host */
803#define RX_DESC_DATA0_FS_ (0x80000000)
804#define RX_DESC_DATA0_LS_ (0x40000000)
805#define RX_DESC_DATA0_FRAME_LENGTH_MASK_ (0x3FFF0000)
806#define RX_DESC_DATA0_FRAME_LENGTH_GET_(data0) \
807 (((data0) & RX_DESC_DATA0_FRAME_LENGTH_MASK_) >> 16)
808#define RX_DESC_DATA0_EXT_ (0x00004000)
809#define RX_DESC_DATA0_BUF_LENGTH_MASK_ (0x00003FFF)
810#define RX_DESC_DATA2_TS_NS_MASK_ (0x3FFFFFFF)
811
812#if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2))
813#error NET_IP_ALIGN must be 0 or 2
814#endif
815
816#define RX_HEAD_PADDING NET_IP_ALIGN
817
818struct lan743x_rx_descriptor {
819 u32 data0;
820 u32 data1;
821 u32 data2;
822 u32 data3;
823} __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING);
824
825#define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0)
826struct lan743x_rx_buffer_info {
827 int flags;
828 struct sk_buff *skb;
829
830 dma_addr_t dma_ptr;
831 unsigned int buffer_length;
832};
833
834#define LAN743X_RX_RING_SIZE (65)
835
836#define RX_PROCESS_RESULT_NOTHING_TO_DO (0)
837#define RX_PROCESS_RESULT_PACKET_RECEIVED (1)
838#define RX_PROCESS_RESULT_PACKET_DROPPED (2)
839
840u32 lan743x_csr_read(struct lan743x_adapter *adapter, int offset);
841void lan743x_csr_write(struct lan743x_adapter *adapter, int offset, u32 data);
842
843#endif /* _LAN743X_H */