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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2014, Sony Mobile Communications AB.
5 *
6 */
7
8#include <linux/acpi.h>
9#include <linux/atomic.h>
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/dmaengine.h>
13#include <linux/dmapool.h>
14#include <linux/dma-mapping.h>
15#include <linux/err.h>
16#include <linux/i2c.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/platform_device.h>
22#include <linux/pm_runtime.h>
23#include <linux/scatterlist.h>
24
25/* QUP Registers */
26#define QUP_CONFIG 0x000
27#define QUP_STATE 0x004
28#define QUP_IO_MODE 0x008
29#define QUP_SW_RESET 0x00c
30#define QUP_OPERATIONAL 0x018
31#define QUP_ERROR_FLAGS 0x01c
32#define QUP_ERROR_FLAGS_EN 0x020
33#define QUP_OPERATIONAL_MASK 0x028
34#define QUP_HW_VERSION 0x030
35#define QUP_MX_OUTPUT_CNT 0x100
36#define QUP_OUT_FIFO_BASE 0x110
37#define QUP_MX_WRITE_CNT 0x150
38#define QUP_MX_INPUT_CNT 0x200
39#define QUP_MX_READ_CNT 0x208
40#define QUP_IN_FIFO_BASE 0x218
41#define QUP_I2C_CLK_CTL 0x400
42#define QUP_I2C_STATUS 0x404
43#define QUP_I2C_MASTER_GEN 0x408
44
45/* QUP States and reset values */
46#define QUP_RESET_STATE 0
47#define QUP_RUN_STATE 1
48#define QUP_PAUSE_STATE 3
49#define QUP_STATE_MASK 3
50
51#define QUP_STATE_VALID BIT(2)
52#define QUP_I2C_MAST_GEN BIT(4)
53#define QUP_I2C_FLUSH BIT(6)
54
55#define QUP_OPERATIONAL_RESET 0x000ff0
56#define QUP_I2C_STATUS_RESET 0xfffffc
57
58/* QUP OPERATIONAL FLAGS */
59#define QUP_I2C_NACK_FLAG BIT(3)
60#define QUP_OUT_NOT_EMPTY BIT(4)
61#define QUP_IN_NOT_EMPTY BIT(5)
62#define QUP_OUT_FULL BIT(6)
63#define QUP_OUT_SVC_FLAG BIT(8)
64#define QUP_IN_SVC_FLAG BIT(9)
65#define QUP_MX_OUTPUT_DONE BIT(10)
66#define QUP_MX_INPUT_DONE BIT(11)
67#define OUT_BLOCK_WRITE_REQ BIT(12)
68#define IN_BLOCK_READ_REQ BIT(13)
69
70/* I2C mini core related values */
71#define QUP_NO_INPUT BIT(7)
72#define QUP_CLOCK_AUTO_GATE BIT(13)
73#define I2C_MINI_CORE (2 << 8)
74#define I2C_N_VAL 15
75#define I2C_N_VAL_V2 7
76
77/* Most significant word offset in FIFO port */
78#define QUP_MSW_SHIFT (I2C_N_VAL + 1)
79
80/* Packing/Unpacking words in FIFOs, and IO modes */
81#define QUP_OUTPUT_BLK_MODE (1 << 10)
82#define QUP_OUTPUT_BAM_MODE (3 << 10)
83#define QUP_INPUT_BLK_MODE (1 << 12)
84#define QUP_INPUT_BAM_MODE (3 << 12)
85#define QUP_BAM_MODE (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE)
86#define QUP_UNPACK_EN BIT(14)
87#define QUP_PACK_EN BIT(15)
88
89#define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN)
90#define QUP_V2_TAGS_EN 1
91
92#define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03)
93#define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07)
94#define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03)
95#define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07)
96
97/* QUP tags */
98#define QUP_TAG_START (1 << 8)
99#define QUP_TAG_DATA (2 << 8)
100#define QUP_TAG_STOP (3 << 8)
101#define QUP_TAG_REC (4 << 8)
102#define QUP_BAM_INPUT_EOT 0x93
103#define QUP_BAM_FLUSH_STOP 0x96
104
105/* QUP v2 tags */
106#define QUP_TAG_V2_START 0x81
107#define QUP_TAG_V2_DATAWR 0x82
108#define QUP_TAG_V2_DATAWR_STOP 0x83
109#define QUP_TAG_V2_DATARD 0x85
110#define QUP_TAG_V2_DATARD_NACK 0x86
111#define QUP_TAG_V2_DATARD_STOP 0x87
112
113/* Status, Error flags */
114#define I2C_STATUS_WR_BUFFER_FULL BIT(0)
115#define I2C_STATUS_BUS_ACTIVE BIT(8)
116#define I2C_STATUS_ERROR_MASK 0x38000fc
117#define QUP_STATUS_ERROR_FLAGS 0x7c
118
119#define QUP_READ_LIMIT 256
120#define SET_BIT 0x1
121#define RESET_BIT 0x0
122#define ONE_BYTE 0x1
123#define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31)
124
125/* Maximum transfer length for single DMA descriptor */
126#define MX_TX_RX_LEN SZ_64K
127#define MX_BLOCKS (MX_TX_RX_LEN / QUP_READ_LIMIT)
128/* Maximum transfer length for all DMA descriptors */
129#define MX_DMA_TX_RX_LEN (2 * MX_TX_RX_LEN)
130#define MX_DMA_BLOCKS (MX_DMA_TX_RX_LEN / QUP_READ_LIMIT)
131
132/*
133 * Minimum transfer timeout for i2c transfers in seconds. It will be added on
134 * the top of maximum transfer time calculated from i2c bus speed to compensate
135 * the overheads.
136 */
137#define TOUT_MIN 2
138
139/* Default values. Use these if FW query fails */
140#define DEFAULT_CLK_FREQ I2C_MAX_STANDARD_MODE_FREQ
141#define DEFAULT_SRC_CLK 20000000
142
143/*
144 * Max tags length (start, stop and maximum 2 bytes address) for each QUP
145 * data transfer
146 */
147#define QUP_MAX_TAGS_LEN 4
148/* Max data length for each DATARD tags */
149#define RECV_MAX_DATA_LEN 254
150/* TAG length for DATA READ in RX FIFO */
151#define READ_RX_TAGS_LEN 2
152
153static unsigned int scl_freq;
154module_param_named(scl_freq, scl_freq, uint, 0444);
155MODULE_PARM_DESC(scl_freq, "SCL frequency override");
156
157/*
158 * count: no of blocks
159 * pos: current block number
160 * tx_tag_len: tx tag length for current block
161 * rx_tag_len: rx tag length for current block
162 * data_len: remaining data length for current message
163 * cur_blk_len: data length for current block
164 * total_tx_len: total tx length including tag bytes for current QUP transfer
165 * total_rx_len: total rx length including tag bytes for current QUP transfer
166 * tx_fifo_data_pos: current byte number in TX FIFO word
167 * tx_fifo_free: number of free bytes in current QUP block write.
168 * rx_fifo_data_pos: current byte number in RX FIFO word
169 * fifo_available: number of available bytes in RX FIFO for current
170 * QUP block read
171 * tx_fifo_data: QUP TX FIFO write works on word basis (4 bytes). New byte write
172 * to TX FIFO will be appended in this data and will be written to
173 * TX FIFO when all the 4 bytes are available.
174 * rx_fifo_data: QUP RX FIFO read works on word basis (4 bytes). This will
175 * contains the 4 bytes of RX data.
176 * cur_data: pointer to tell cur data position for current message
177 * cur_tx_tags: pointer to tell cur position in tags
178 * tx_tags_sent: all tx tag bytes have been written in FIFO word
179 * send_last_word: for tx FIFO, last word send is pending in current block
180 * rx_bytes_read: if all the bytes have been read from rx FIFO.
181 * rx_tags_fetched: all the rx tag bytes have been fetched from rx fifo word
182 * is_tx_blk_mode: whether tx uses block or FIFO mode in case of non BAM xfer.
183 * is_rx_blk_mode: whether rx uses block or FIFO mode in case of non BAM xfer.
184 * tags: contains tx tag bytes for current QUP transfer
185 */
186struct qup_i2c_block {
187 int count;
188 int pos;
189 int tx_tag_len;
190 int rx_tag_len;
191 int data_len;
192 int cur_blk_len;
193 int total_tx_len;
194 int total_rx_len;
195 int tx_fifo_data_pos;
196 int tx_fifo_free;
197 int rx_fifo_data_pos;
198 int fifo_available;
199 u32 tx_fifo_data;
200 u32 rx_fifo_data;
201 u8 *cur_data;
202 u8 *cur_tx_tags;
203 bool tx_tags_sent;
204 bool send_last_word;
205 bool rx_tags_fetched;
206 bool rx_bytes_read;
207 bool is_tx_blk_mode;
208 bool is_rx_blk_mode;
209 u8 tags[6];
210};
211
212struct qup_i2c_tag {
213 u8 *start;
214 dma_addr_t addr;
215};
216
217struct qup_i2c_bam {
218 struct qup_i2c_tag tag;
219 struct dma_chan *dma;
220 struct scatterlist *sg;
221 unsigned int sg_cnt;
222};
223
224struct qup_i2c_dev {
225 struct device *dev;
226 void __iomem *base;
227 int irq;
228 struct clk *clk;
229 struct clk *pclk;
230 struct i2c_adapter adap;
231
232 int clk_ctl;
233 int out_fifo_sz;
234 int in_fifo_sz;
235 int out_blk_sz;
236 int in_blk_sz;
237
238 int blk_xfer_limit;
239 unsigned long one_byte_t;
240 unsigned long xfer_timeout;
241 struct qup_i2c_block blk;
242
243 struct i2c_msg *msg;
244 /* Current posion in user message buffer */
245 int pos;
246 /* I2C protocol errors */
247 u32 bus_err;
248 /* QUP core errors */
249 u32 qup_err;
250
251 /* To check if this is the last msg */
252 bool is_last;
253 bool is_smbus_read;
254
255 /* To configure when bus is in run state */
256 u32 config_run;
257
258 /* dma parameters */
259 bool is_dma;
260 /* To check if the current transfer is using DMA */
261 bool use_dma;
262 unsigned int max_xfer_sg_len;
263 unsigned int tag_buf_pos;
264 /* The threshold length above which block mode will be used */
265 unsigned int blk_mode_threshold;
266 struct dma_pool *dpool;
267 struct qup_i2c_tag start_tag;
268 struct qup_i2c_bam brx;
269 struct qup_i2c_bam btx;
270
271 struct completion xfer;
272 /* function to write data in tx fifo */
273 void (*write_tx_fifo)(struct qup_i2c_dev *qup);
274 /* function to read data from rx fifo */
275 void (*read_rx_fifo)(struct qup_i2c_dev *qup);
276 /* function to write tags in tx fifo for i2c read transfer */
277 void (*write_rx_tags)(struct qup_i2c_dev *qup);
278};
279
280static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
281{
282 struct qup_i2c_dev *qup = dev;
283 struct qup_i2c_block *blk = &qup->blk;
284 u32 bus_err;
285 u32 qup_err;
286 u32 opflags;
287
288 bus_err = readl(qup->base + QUP_I2C_STATUS);
289 qup_err = readl(qup->base + QUP_ERROR_FLAGS);
290 opflags = readl(qup->base + QUP_OPERATIONAL);
291
292 if (!qup->msg) {
293 /* Clear Error interrupt */
294 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
295 return IRQ_HANDLED;
296 }
297
298 bus_err &= I2C_STATUS_ERROR_MASK;
299 qup_err &= QUP_STATUS_ERROR_FLAGS;
300
301 /* Clear the error bits in QUP_ERROR_FLAGS */
302 if (qup_err)
303 writel(qup_err, qup->base + QUP_ERROR_FLAGS);
304
305 /* Clear the error bits in QUP_I2C_STATUS */
306 if (bus_err)
307 writel(bus_err, qup->base + QUP_I2C_STATUS);
308
309 /*
310 * Check for BAM mode and returns if already error has come for current
311 * transfer. In Error case, sometimes, QUP generates more than one
312 * interrupt.
313 */
314 if (qup->use_dma && (qup->qup_err || qup->bus_err))
315 return IRQ_HANDLED;
316
317 /* Reset the QUP State in case of error */
318 if (qup_err || bus_err) {
319 /*
320 * Don’t reset the QUP state in case of BAM mode. The BAM
321 * flush operation needs to be scheduled in transfer function
322 * which will clear the remaining schedule descriptors in BAM
323 * HW FIFO and generates the BAM interrupt.
324 */
325 if (!qup->use_dma)
326 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
327 goto done;
328 }
329
330 if (opflags & QUP_OUT_SVC_FLAG) {
331 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
332
333 if (opflags & OUT_BLOCK_WRITE_REQ) {
334 blk->tx_fifo_free += qup->out_blk_sz;
335 if (qup->msg->flags & I2C_M_RD)
336 qup->write_rx_tags(qup);
337 else
338 qup->write_tx_fifo(qup);
339 }
340 }
341
342 if (opflags & QUP_IN_SVC_FLAG) {
343 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
344
345 if (!blk->is_rx_blk_mode) {
346 blk->fifo_available += qup->in_fifo_sz;
347 qup->read_rx_fifo(qup);
348 } else if (opflags & IN_BLOCK_READ_REQ) {
349 blk->fifo_available += qup->in_blk_sz;
350 qup->read_rx_fifo(qup);
351 }
352 }
353
354 if (qup->msg->flags & I2C_M_RD) {
355 if (!blk->rx_bytes_read)
356 return IRQ_HANDLED;
357 } else {
358 /*
359 * Ideally, QUP_MAX_OUTPUT_DONE_FLAG should be checked
360 * for FIFO mode also. But, QUP_MAX_OUTPUT_DONE_FLAG lags
361 * behind QUP_OUTPUT_SERVICE_FLAG sometimes. The only reason
362 * of interrupt for write message in FIFO mode is
363 * QUP_MAX_OUTPUT_DONE_FLAG condition.
364 */
365 if (blk->is_tx_blk_mode && !(opflags & QUP_MX_OUTPUT_DONE))
366 return IRQ_HANDLED;
367 }
368
369done:
370 qup->qup_err = qup_err;
371 qup->bus_err = bus_err;
372 complete(&qup->xfer);
373 return IRQ_HANDLED;
374}
375
376static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup,
377 u32 req_state, u32 req_mask)
378{
379 int retries = 1;
380 u32 state;
381
382 /*
383 * State transition takes 3 AHB clocks cycles + 3 I2C master clock
384 * cycles. So retry once after a 1uS delay.
385 */
386 do {
387 state = readl(qup->base + QUP_STATE);
388
389 if (state & QUP_STATE_VALID &&
390 (state & req_mask) == req_state)
391 return 0;
392
393 udelay(1);
394 } while (retries--);
395
396 return -ETIMEDOUT;
397}
398
399static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state)
400{
401 return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
402}
403
404static void qup_i2c_flush(struct qup_i2c_dev *qup)
405{
406 u32 val = readl(qup->base + QUP_STATE);
407
408 val |= QUP_I2C_FLUSH;
409 writel(val, qup->base + QUP_STATE);
410}
411
412static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup)
413{
414 return qup_i2c_poll_state_mask(qup, 0, 0);
415}
416
417static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup)
418{
419 return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);
420}
421
422static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state)
423{
424 if (qup_i2c_poll_state_valid(qup) != 0)
425 return -EIO;
426
427 writel(state, qup->base + QUP_STATE);
428
429 if (qup_i2c_poll_state(qup, state) != 0)
430 return -EIO;
431 return 0;
432}
433
434/* Check if I2C bus returns to IDLE state */
435static int qup_i2c_bus_active(struct qup_i2c_dev *qup, int len)
436{
437 unsigned long timeout;
438 u32 status;
439 int ret = 0;
440
441 timeout = jiffies + len * 4;
442 for (;;) {
443 status = readl(qup->base + QUP_I2C_STATUS);
444 if (!(status & I2C_STATUS_BUS_ACTIVE))
445 break;
446
447 if (time_after(jiffies, timeout))
448 ret = -ETIMEDOUT;
449
450 usleep_range(len, len * 2);
451 }
452
453 return ret;
454}
455
456static void qup_i2c_write_tx_fifo_v1(struct qup_i2c_dev *qup)
457{
458 struct qup_i2c_block *blk = &qup->blk;
459 struct i2c_msg *msg = qup->msg;
460 u32 addr = i2c_8bit_addr_from_msg(msg);
461 u32 qup_tag;
462 int idx;
463 u32 val;
464
465 if (qup->pos == 0) {
466 val = QUP_TAG_START | addr;
467 idx = 1;
468 blk->tx_fifo_free--;
469 } else {
470 val = 0;
471 idx = 0;
472 }
473
474 while (blk->tx_fifo_free && qup->pos < msg->len) {
475 if (qup->pos == msg->len - 1)
476 qup_tag = QUP_TAG_STOP;
477 else
478 qup_tag = QUP_TAG_DATA;
479
480 if (idx & 1)
481 val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT;
482 else
483 val = qup_tag | msg->buf[qup->pos];
484
485 /* Write out the pair and the last odd value */
486 if (idx & 1 || qup->pos == msg->len - 1)
487 writel(val, qup->base + QUP_OUT_FIFO_BASE);
488
489 qup->pos++;
490 idx++;
491 blk->tx_fifo_free--;
492 }
493}
494
495static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup,
496 struct i2c_msg *msg)
497{
498 qup->blk.pos = 0;
499 qup->blk.data_len = msg->len;
500 qup->blk.count = DIV_ROUND_UP(msg->len, qup->blk_xfer_limit);
501}
502
503static int qup_i2c_get_data_len(struct qup_i2c_dev *qup)
504{
505 int data_len;
506
507 if (qup->blk.data_len > qup->blk_xfer_limit)
508 data_len = qup->blk_xfer_limit;
509 else
510 data_len = qup->blk.data_len;
511
512 return data_len;
513}
514
515static bool qup_i2c_check_msg_len(struct i2c_msg *msg)
516{
517 return ((msg->flags & I2C_M_RD) && (msg->flags & I2C_M_RECV_LEN));
518}
519
520static int qup_i2c_set_tags_smb(u16 addr, u8 *tags, struct qup_i2c_dev *qup,
521 struct i2c_msg *msg)
522{
523 int len = 0;
524
525 if (qup->is_smbus_read) {
526 tags[len++] = QUP_TAG_V2_DATARD_STOP;
527 tags[len++] = qup_i2c_get_data_len(qup);
528 } else {
529 tags[len++] = QUP_TAG_V2_START;
530 tags[len++] = addr & 0xff;
531
532 if (msg->flags & I2C_M_TEN)
533 tags[len++] = addr >> 8;
534
535 tags[len++] = QUP_TAG_V2_DATARD;
536 /* Read 1 byte indicating the length of the SMBus message */
537 tags[len++] = 1;
538 }
539 return len;
540}
541
542static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup,
543 struct i2c_msg *msg)
544{
545 u16 addr = i2c_8bit_addr_from_msg(msg);
546 int len = 0;
547 int data_len;
548
549 int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last);
550
551 /* Handle tags for SMBus block read */
552 if (qup_i2c_check_msg_len(msg))
553 return qup_i2c_set_tags_smb(addr, tags, qup, msg);
554
555 if (qup->blk.pos == 0) {
556 tags[len++] = QUP_TAG_V2_START;
557 tags[len++] = addr & 0xff;
558
559 if (msg->flags & I2C_M_TEN)
560 tags[len++] = addr >> 8;
561 }
562
563 /* Send _STOP commands for the last block */
564 if (last) {
565 if (msg->flags & I2C_M_RD)
566 tags[len++] = QUP_TAG_V2_DATARD_STOP;
567 else
568 tags[len++] = QUP_TAG_V2_DATAWR_STOP;
569 } else {
570 if (msg->flags & I2C_M_RD)
571 tags[len++] = qup->blk.pos == (qup->blk.count - 1) ?
572 QUP_TAG_V2_DATARD_NACK :
573 QUP_TAG_V2_DATARD;
574 else
575 tags[len++] = QUP_TAG_V2_DATAWR;
576 }
577
578 data_len = qup_i2c_get_data_len(qup);
579
580 /* 0 implies 256 bytes */
581 if (data_len == QUP_READ_LIMIT)
582 tags[len++] = 0;
583 else
584 tags[len++] = data_len;
585
586 return len;
587}
588
589
590static void qup_i2c_bam_cb(void *data)
591{
592 struct qup_i2c_dev *qup = data;
593
594 complete(&qup->xfer);
595}
596
597static int qup_sg_set_buf(struct scatterlist *sg, void *buf,
598 unsigned int buflen, struct qup_i2c_dev *qup,
599 int dir)
600{
601 int ret;
602
603 sg_set_buf(sg, buf, buflen);
604 ret = dma_map_sg(qup->dev, sg, 1, dir);
605 if (!ret)
606 return -EINVAL;
607
608 return 0;
609}
610
611static void qup_i2c_rel_dma(struct qup_i2c_dev *qup)
612{
613 if (qup->btx.dma)
614 dma_release_channel(qup->btx.dma);
615 if (qup->brx.dma)
616 dma_release_channel(qup->brx.dma);
617 qup->btx.dma = NULL;
618 qup->brx.dma = NULL;
619}
620
621static int qup_i2c_req_dma(struct qup_i2c_dev *qup)
622{
623 int err;
624
625 if (!qup->btx.dma) {
626 qup->btx.dma = dma_request_chan(qup->dev, "tx");
627 if (IS_ERR(qup->btx.dma)) {
628 err = PTR_ERR(qup->btx.dma);
629 qup->btx.dma = NULL;
630 dev_err(qup->dev, "\n tx channel not available");
631 return err;
632 }
633 }
634
635 if (!qup->brx.dma) {
636 qup->brx.dma = dma_request_chan(qup->dev, "rx");
637 if (IS_ERR(qup->brx.dma)) {
638 dev_err(qup->dev, "\n rx channel not available");
639 err = PTR_ERR(qup->brx.dma);
640 qup->brx.dma = NULL;
641 qup_i2c_rel_dma(qup);
642 return err;
643 }
644 }
645 return 0;
646}
647
648static int qup_i2c_bam_make_desc(struct qup_i2c_dev *qup, struct i2c_msg *msg)
649{
650 int ret = 0, limit = QUP_READ_LIMIT;
651 u32 len = 0, blocks, rem;
652 u32 i = 0, tlen, tx_len = 0;
653 u8 *tags;
654
655 qup->blk_xfer_limit = QUP_READ_LIMIT;
656 qup_i2c_set_blk_data(qup, msg);
657
658 blocks = qup->blk.count;
659 rem = msg->len - (blocks - 1) * limit;
660
661 if (msg->flags & I2C_M_RD) {
662 while (qup->blk.pos < blocks) {
663 tlen = (i == (blocks - 1)) ? rem : limit;
664 tags = &qup->start_tag.start[qup->tag_buf_pos + len];
665 len += qup_i2c_set_tags(tags, qup, msg);
666 qup->blk.data_len -= tlen;
667
668 /* scratch buf to read the start and len tags */
669 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++],
670 &qup->brx.tag.start[0],
671 2, qup, DMA_FROM_DEVICE);
672
673 if (ret)
674 return ret;
675
676 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++],
677 &msg->buf[limit * i],
678 tlen, qup,
679 DMA_FROM_DEVICE);
680 if (ret)
681 return ret;
682
683 i++;
684 qup->blk.pos = i;
685 }
686 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
687 &qup->start_tag.start[qup->tag_buf_pos],
688 len, qup, DMA_TO_DEVICE);
689 if (ret)
690 return ret;
691
692 qup->tag_buf_pos += len;
693 } else {
694 while (qup->blk.pos < blocks) {
695 tlen = (i == (blocks - 1)) ? rem : limit;
696 tags = &qup->start_tag.start[qup->tag_buf_pos + tx_len];
697 len = qup_i2c_set_tags(tags, qup, msg);
698 qup->blk.data_len -= tlen;
699
700 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
701 tags, len,
702 qup, DMA_TO_DEVICE);
703 if (ret)
704 return ret;
705
706 tx_len += len;
707 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
708 &msg->buf[limit * i],
709 tlen, qup, DMA_TO_DEVICE);
710 if (ret)
711 return ret;
712 i++;
713 qup->blk.pos = i;
714 }
715
716 qup->tag_buf_pos += tx_len;
717 }
718
719 return 0;
720}
721
722static int qup_i2c_bam_schedule_desc(struct qup_i2c_dev *qup)
723{
724 struct dma_async_tx_descriptor *txd, *rxd = NULL;
725 int ret = 0;
726 dma_cookie_t cookie_rx, cookie_tx;
727 u32 len = 0;
728 u32 tx_cnt = qup->btx.sg_cnt, rx_cnt = qup->brx.sg_cnt;
729
730 /* schedule the EOT and FLUSH I2C tags */
731 len = 1;
732 if (rx_cnt) {
733 qup->btx.tag.start[0] = QUP_BAM_INPUT_EOT;
734 len++;
735
736 /* scratch buf to read the BAM EOT FLUSH tags */
737 ret = qup_sg_set_buf(&qup->brx.sg[rx_cnt++],
738 &qup->brx.tag.start[0],
739 1, qup, DMA_FROM_DEVICE);
740 if (ret)
741 return ret;
742 }
743
744 qup->btx.tag.start[len - 1] = QUP_BAM_FLUSH_STOP;
745 ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++], &qup->btx.tag.start[0],
746 len, qup, DMA_TO_DEVICE);
747 if (ret)
748 return ret;
749
750 txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_cnt,
751 DMA_MEM_TO_DEV,
752 DMA_PREP_INTERRUPT | DMA_PREP_FENCE);
753 if (!txd) {
754 dev_err(qup->dev, "failed to get tx desc\n");
755 ret = -EINVAL;
756 goto desc_err;
757 }
758
759 if (!rx_cnt) {
760 txd->callback = qup_i2c_bam_cb;
761 txd->callback_param = qup;
762 }
763
764 cookie_tx = dmaengine_submit(txd);
765 if (dma_submit_error(cookie_tx)) {
766 ret = -EINVAL;
767 goto desc_err;
768 }
769
770 dma_async_issue_pending(qup->btx.dma);
771
772 if (rx_cnt) {
773 rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg,
774 rx_cnt, DMA_DEV_TO_MEM,
775 DMA_PREP_INTERRUPT);
776 if (!rxd) {
777 dev_err(qup->dev, "failed to get rx desc\n");
778 ret = -EINVAL;
779
780 /* abort TX descriptors */
781 dmaengine_terminate_all(qup->btx.dma);
782 goto desc_err;
783 }
784
785 rxd->callback = qup_i2c_bam_cb;
786 rxd->callback_param = qup;
787 cookie_rx = dmaengine_submit(rxd);
788 if (dma_submit_error(cookie_rx)) {
789 ret = -EINVAL;
790 goto desc_err;
791 }
792
793 dma_async_issue_pending(qup->brx.dma);
794 }
795
796 if (!wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout)) {
797 dev_err(qup->dev, "normal trans timed out\n");
798 ret = -ETIMEDOUT;
799 }
800
801 if (ret || qup->bus_err || qup->qup_err) {
802 reinit_completion(&qup->xfer);
803
804 if (qup_i2c_change_state(qup, QUP_RUN_STATE)) {
805 dev_err(qup->dev, "change to run state timed out");
806 goto desc_err;
807 }
808
809 qup_i2c_flush(qup);
810
811 /* wait for remaining interrupts to occur */
812 if (!wait_for_completion_timeout(&qup->xfer, HZ))
813 dev_err(qup->dev, "flush timed out\n");
814
815 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
816 }
817
818desc_err:
819 dma_unmap_sg(qup->dev, qup->btx.sg, tx_cnt, DMA_TO_DEVICE);
820
821 if (rx_cnt)
822 dma_unmap_sg(qup->dev, qup->brx.sg, rx_cnt,
823 DMA_FROM_DEVICE);
824
825 return ret;
826}
827
828static void qup_i2c_bam_clear_tag_buffers(struct qup_i2c_dev *qup)
829{
830 qup->btx.sg_cnt = 0;
831 qup->brx.sg_cnt = 0;
832 qup->tag_buf_pos = 0;
833}
834
835static int qup_i2c_bam_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
836 int num)
837{
838 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
839 int ret = 0;
840 int idx = 0;
841
842 enable_irq(qup->irq);
843 ret = qup_i2c_req_dma(qup);
844
845 if (ret)
846 goto out;
847
848 writel(0, qup->base + QUP_MX_INPUT_CNT);
849 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
850
851 /* set BAM mode */
852 writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE);
853
854 /* mask fifo irqs */
855 writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK);
856
857 /* set RUN STATE */
858 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
859 if (ret)
860 goto out;
861
862 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
863 qup_i2c_bam_clear_tag_buffers(qup);
864
865 for (idx = 0; idx < num; idx++) {
866 qup->msg = msg + idx;
867 qup->is_last = idx == (num - 1);
868
869 ret = qup_i2c_bam_make_desc(qup, qup->msg);
870 if (ret)
871 break;
872
873 /*
874 * Make DMA descriptor and schedule the BAM transfer if its
875 * already crossed the maximum length. Since the memory for all
876 * tags buffers have been taken for 2 maximum possible
877 * transfers length so it will never cross the buffer actual
878 * length.
879 */
880 if (qup->btx.sg_cnt > qup->max_xfer_sg_len ||
881 qup->brx.sg_cnt > qup->max_xfer_sg_len ||
882 qup->is_last) {
883 ret = qup_i2c_bam_schedule_desc(qup);
884 if (ret)
885 break;
886
887 qup_i2c_bam_clear_tag_buffers(qup);
888 }
889 }
890
891out:
892 disable_irq(qup->irq);
893
894 qup->msg = NULL;
895 return ret;
896}
897
898static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup,
899 struct i2c_msg *msg)
900{
901 unsigned long left;
902 int ret = 0;
903
904 left = wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout);
905 if (!left) {
906 writel(1, qup->base + QUP_SW_RESET);
907 ret = -ETIMEDOUT;
908 }
909
910 if (qup->bus_err || qup->qup_err)
911 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
912
913 return ret;
914}
915
916static void qup_i2c_read_rx_fifo_v1(struct qup_i2c_dev *qup)
917{
918 struct qup_i2c_block *blk = &qup->blk;
919 struct i2c_msg *msg = qup->msg;
920 u32 val = 0;
921 int idx = 0;
922
923 while (blk->fifo_available && qup->pos < msg->len) {
924 if ((idx & 1) == 0) {
925 /* Reading 2 words at time */
926 val = readl(qup->base + QUP_IN_FIFO_BASE);
927 msg->buf[qup->pos++] = val & 0xFF;
928 } else {
929 msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;
930 }
931 idx++;
932 blk->fifo_available--;
933 }
934
935 if (qup->pos == msg->len)
936 blk->rx_bytes_read = true;
937}
938
939static void qup_i2c_write_rx_tags_v1(struct qup_i2c_dev *qup)
940{
941 struct i2c_msg *msg = qup->msg;
942 u32 addr, len, val;
943
944 addr = i2c_8bit_addr_from_msg(msg);
945
946 /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
947 len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;
948
949 val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr;
950 writel(val, qup->base + QUP_OUT_FIFO_BASE);
951}
952
953static void qup_i2c_conf_v1(struct qup_i2c_dev *qup)
954{
955 struct qup_i2c_block *blk = &qup->blk;
956 u32 qup_config = I2C_MINI_CORE | I2C_N_VAL;
957 u32 io_mode = QUP_REPACK_EN;
958
959 blk->is_tx_blk_mode = blk->total_tx_len > qup->out_fifo_sz;
960 blk->is_rx_blk_mode = blk->total_rx_len > qup->in_fifo_sz;
961
962 if (blk->is_tx_blk_mode) {
963 io_mode |= QUP_OUTPUT_BLK_MODE;
964 writel(0, qup->base + QUP_MX_WRITE_CNT);
965 writel(blk->total_tx_len, qup->base + QUP_MX_OUTPUT_CNT);
966 } else {
967 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
968 writel(blk->total_tx_len, qup->base + QUP_MX_WRITE_CNT);
969 }
970
971 if (blk->total_rx_len) {
972 if (blk->is_rx_blk_mode) {
973 io_mode |= QUP_INPUT_BLK_MODE;
974 writel(0, qup->base + QUP_MX_READ_CNT);
975 writel(blk->total_rx_len, qup->base + QUP_MX_INPUT_CNT);
976 } else {
977 writel(0, qup->base + QUP_MX_INPUT_CNT);
978 writel(blk->total_rx_len, qup->base + QUP_MX_READ_CNT);
979 }
980 } else {
981 qup_config |= QUP_NO_INPUT;
982 }
983
984 writel(qup_config, qup->base + QUP_CONFIG);
985 writel(io_mode, qup->base + QUP_IO_MODE);
986}
987
988static void qup_i2c_clear_blk_v1(struct qup_i2c_block *blk)
989{
990 blk->tx_fifo_free = 0;
991 blk->fifo_available = 0;
992 blk->rx_bytes_read = false;
993}
994
995static int qup_i2c_conf_xfer_v1(struct qup_i2c_dev *qup, bool is_rx)
996{
997 struct qup_i2c_block *blk = &qup->blk;
998 int ret;
999
1000 qup_i2c_clear_blk_v1(blk);
1001 qup_i2c_conf_v1(qup);
1002 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1003 if (ret)
1004 return ret;
1005
1006 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1007
1008 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1009 if (ret)
1010 return ret;
1011
1012 reinit_completion(&qup->xfer);
1013 enable_irq(qup->irq);
1014 if (!blk->is_tx_blk_mode) {
1015 blk->tx_fifo_free = qup->out_fifo_sz;
1016
1017 if (is_rx)
1018 qup_i2c_write_rx_tags_v1(qup);
1019 else
1020 qup_i2c_write_tx_fifo_v1(qup);
1021 }
1022
1023 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1024 if (ret)
1025 goto err;
1026
1027 ret = qup_i2c_wait_for_complete(qup, qup->msg);
1028 if (ret)
1029 goto err;
1030
1031 ret = qup_i2c_bus_active(qup, ONE_BYTE);
1032
1033err:
1034 disable_irq(qup->irq);
1035 return ret;
1036}
1037
1038static int qup_i2c_write_one(struct qup_i2c_dev *qup)
1039{
1040 struct i2c_msg *msg = qup->msg;
1041 struct qup_i2c_block *blk = &qup->blk;
1042
1043 qup->pos = 0;
1044 blk->total_tx_len = msg->len + 1;
1045 blk->total_rx_len = 0;
1046
1047 return qup_i2c_conf_xfer_v1(qup, false);
1048}
1049
1050static int qup_i2c_read_one(struct qup_i2c_dev *qup)
1051{
1052 struct qup_i2c_block *blk = &qup->blk;
1053
1054 qup->pos = 0;
1055 blk->total_tx_len = 2;
1056 blk->total_rx_len = qup->msg->len;
1057
1058 return qup_i2c_conf_xfer_v1(qup, true);
1059}
1060
1061static int qup_i2c_xfer(struct i2c_adapter *adap,
1062 struct i2c_msg msgs[],
1063 int num)
1064{
1065 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1066 int ret, idx;
1067
1068 ret = pm_runtime_get_sync(qup->dev);
1069 if (ret < 0)
1070 goto out;
1071
1072 qup->bus_err = 0;
1073 qup->qup_err = 0;
1074
1075 writel(1, qup->base + QUP_SW_RESET);
1076 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1077 if (ret)
1078 goto out;
1079
1080 /* Configure QUP as I2C mini core */
1081 writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG);
1082
1083 for (idx = 0; idx < num; idx++) {
1084 if (qup_i2c_poll_state_i2c_master(qup)) {
1085 ret = -EIO;
1086 goto out;
1087 }
1088
1089 if (qup_i2c_check_msg_len(&msgs[idx])) {
1090 ret = -EINVAL;
1091 goto out;
1092 }
1093
1094 qup->msg = &msgs[idx];
1095 if (msgs[idx].flags & I2C_M_RD)
1096 ret = qup_i2c_read_one(qup);
1097 else
1098 ret = qup_i2c_write_one(qup);
1099
1100 if (ret)
1101 break;
1102
1103 ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
1104 if (ret)
1105 break;
1106 }
1107
1108 if (ret == 0)
1109 ret = num;
1110out:
1111
1112 pm_runtime_mark_last_busy(qup->dev);
1113 pm_runtime_put_autosuspend(qup->dev);
1114
1115 return ret;
1116}
1117
1118/*
1119 * Configure registers related with reconfiguration during run and call it
1120 * before each i2c sub transfer.
1121 */
1122static void qup_i2c_conf_count_v2(struct qup_i2c_dev *qup)
1123{
1124 struct qup_i2c_block *blk = &qup->blk;
1125 u32 qup_config = I2C_MINI_CORE | I2C_N_VAL_V2;
1126
1127 if (blk->is_tx_blk_mode)
1128 writel(qup->config_run | blk->total_tx_len,
1129 qup->base + QUP_MX_OUTPUT_CNT);
1130 else
1131 writel(qup->config_run | blk->total_tx_len,
1132 qup->base + QUP_MX_WRITE_CNT);
1133
1134 if (blk->total_rx_len) {
1135 if (blk->is_rx_blk_mode)
1136 writel(qup->config_run | blk->total_rx_len,
1137 qup->base + QUP_MX_INPUT_CNT);
1138 else
1139 writel(qup->config_run | blk->total_rx_len,
1140 qup->base + QUP_MX_READ_CNT);
1141 } else {
1142 qup_config |= QUP_NO_INPUT;
1143 }
1144
1145 writel(qup_config, qup->base + QUP_CONFIG);
1146}
1147
1148/*
1149 * Configure registers related with transfer mode (FIFO/Block)
1150 * before starting of i2c transfer. It will be called only once in
1151 * QUP RESET state.
1152 */
1153static void qup_i2c_conf_mode_v2(struct qup_i2c_dev *qup)
1154{
1155 struct qup_i2c_block *blk = &qup->blk;
1156 u32 io_mode = QUP_REPACK_EN;
1157
1158 if (blk->is_tx_blk_mode) {
1159 io_mode |= QUP_OUTPUT_BLK_MODE;
1160 writel(0, qup->base + QUP_MX_WRITE_CNT);
1161 } else {
1162 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
1163 }
1164
1165 if (blk->is_rx_blk_mode) {
1166 io_mode |= QUP_INPUT_BLK_MODE;
1167 writel(0, qup->base + QUP_MX_READ_CNT);
1168 } else {
1169 writel(0, qup->base + QUP_MX_INPUT_CNT);
1170 }
1171
1172 writel(io_mode, qup->base + QUP_IO_MODE);
1173}
1174
1175/* Clear required variables before starting of any QUP v2 sub transfer. */
1176static void qup_i2c_clear_blk_v2(struct qup_i2c_block *blk)
1177{
1178 blk->send_last_word = false;
1179 blk->tx_tags_sent = false;
1180 blk->tx_fifo_data = 0;
1181 blk->tx_fifo_data_pos = 0;
1182 blk->tx_fifo_free = 0;
1183
1184 blk->rx_tags_fetched = false;
1185 blk->rx_bytes_read = false;
1186 blk->rx_fifo_data = 0;
1187 blk->rx_fifo_data_pos = 0;
1188 blk->fifo_available = 0;
1189}
1190
1191/* Receive data from RX FIFO for read message in QUP v2 i2c transfer. */
1192static void qup_i2c_recv_data(struct qup_i2c_dev *qup)
1193{
1194 struct qup_i2c_block *blk = &qup->blk;
1195 int j;
1196
1197 for (j = blk->rx_fifo_data_pos;
1198 blk->cur_blk_len && blk->fifo_available;
1199 blk->cur_blk_len--, blk->fifo_available--) {
1200 if (j == 0)
1201 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE);
1202
1203 *(blk->cur_data++) = blk->rx_fifo_data;
1204 blk->rx_fifo_data >>= 8;
1205
1206 if (j == 3)
1207 j = 0;
1208 else
1209 j++;
1210 }
1211
1212 blk->rx_fifo_data_pos = j;
1213}
1214
1215/* Receive tags for read message in QUP v2 i2c transfer. */
1216static void qup_i2c_recv_tags(struct qup_i2c_dev *qup)
1217{
1218 struct qup_i2c_block *blk = &qup->blk;
1219
1220 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE);
1221 blk->rx_fifo_data >>= blk->rx_tag_len * 8;
1222 blk->rx_fifo_data_pos = blk->rx_tag_len;
1223 blk->fifo_available -= blk->rx_tag_len;
1224}
1225
1226/*
1227 * Read the data and tags from RX FIFO. Since in read case, the tags will be
1228 * preceded by received data bytes so
1229 * 1. Check if rx_tags_fetched is false i.e. the start of QUP block so receive
1230 * all tag bytes and discard that.
1231 * 2. Read the data from RX FIFO. When all the data bytes have been read then
1232 * set rx_bytes_read to true.
1233 */
1234static void qup_i2c_read_rx_fifo_v2(struct qup_i2c_dev *qup)
1235{
1236 struct qup_i2c_block *blk = &qup->blk;
1237
1238 if (!blk->rx_tags_fetched) {
1239 qup_i2c_recv_tags(qup);
1240 blk->rx_tags_fetched = true;
1241 }
1242
1243 qup_i2c_recv_data(qup);
1244 if (!blk->cur_blk_len)
1245 blk->rx_bytes_read = true;
1246}
1247
1248/*
1249 * Write bytes in TX FIFO for write message in QUP v2 i2c transfer. QUP TX FIFO
1250 * write works on word basis (4 bytes). Append new data byte write for TX FIFO
1251 * in tx_fifo_data and write to TX FIFO when all the 4 bytes are present.
1252 */
1253static void
1254qup_i2c_write_blk_data(struct qup_i2c_dev *qup, u8 **data, unsigned int *len)
1255{
1256 struct qup_i2c_block *blk = &qup->blk;
1257 unsigned int j;
1258
1259 for (j = blk->tx_fifo_data_pos; *len && blk->tx_fifo_free;
1260 (*len)--, blk->tx_fifo_free--) {
1261 blk->tx_fifo_data |= *(*data)++ << (j * 8);
1262 if (j == 3) {
1263 writel(blk->tx_fifo_data,
1264 qup->base + QUP_OUT_FIFO_BASE);
1265 blk->tx_fifo_data = 0x0;
1266 j = 0;
1267 } else {
1268 j++;
1269 }
1270 }
1271
1272 blk->tx_fifo_data_pos = j;
1273}
1274
1275/* Transfer tags for read message in QUP v2 i2c transfer. */
1276static void qup_i2c_write_rx_tags_v2(struct qup_i2c_dev *qup)
1277{
1278 struct qup_i2c_block *blk = &qup->blk;
1279
1280 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, &blk->tx_tag_len);
1281 if (blk->tx_fifo_data_pos)
1282 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE);
1283}
1284
1285/*
1286 * Write the data and tags in TX FIFO. Since in write case, both tags and data
1287 * need to be written and QUP write tags can have maximum 256 data length, so
1288 *
1289 * 1. Check if tx_tags_sent is false i.e. the start of QUP block so write the
1290 * tags to TX FIFO and set tx_tags_sent to true.
1291 * 2. Check if send_last_word is true. It will be set when last few data bytes
1292 * (less than 4 bytes) are reamining to be written in FIFO because of no FIFO
1293 * space. All this data bytes are available in tx_fifo_data so write this
1294 * in FIFO.
1295 * 3. Write the data to TX FIFO and check for cur_blk_len. If it is non zero
1296 * then more data is pending otherwise following 3 cases can be possible
1297 * a. if tx_fifo_data_pos is zero i.e. all the data bytes in this block
1298 * have been written in TX FIFO so nothing else is required.
1299 * b. tx_fifo_free is non zero i.e tx FIFO is free so copy the remaining data
1300 * from tx_fifo_data to tx FIFO. Since, qup_i2c_write_blk_data do write
1301 * in 4 bytes and FIFO space is in multiple of 4 bytes so tx_fifo_free
1302 * will be always greater than or equal to 4 bytes.
1303 * c. tx_fifo_free is zero. In this case, last few bytes (less than 4
1304 * bytes) are copied to tx_fifo_data but couldn't be sent because of
1305 * FIFO full so make send_last_word true.
1306 */
1307static void qup_i2c_write_tx_fifo_v2(struct qup_i2c_dev *qup)
1308{
1309 struct qup_i2c_block *blk = &qup->blk;
1310
1311 if (!blk->tx_tags_sent) {
1312 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags,
1313 &blk->tx_tag_len);
1314 blk->tx_tags_sent = true;
1315 }
1316
1317 if (blk->send_last_word)
1318 goto send_last_word;
1319
1320 qup_i2c_write_blk_data(qup, &blk->cur_data, &blk->cur_blk_len);
1321 if (!blk->cur_blk_len) {
1322 if (!blk->tx_fifo_data_pos)
1323 return;
1324
1325 if (blk->tx_fifo_free)
1326 goto send_last_word;
1327
1328 blk->send_last_word = true;
1329 }
1330
1331 return;
1332
1333send_last_word:
1334 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE);
1335}
1336
1337/*
1338 * Main transfer function which read or write i2c data.
1339 * The QUP v2 supports reconfiguration during run in which multiple i2c sub
1340 * transfers can be scheduled.
1341 */
1342static int
1343qup_i2c_conf_xfer_v2(struct qup_i2c_dev *qup, bool is_rx, bool is_first,
1344 bool change_pause_state)
1345{
1346 struct qup_i2c_block *blk = &qup->blk;
1347 struct i2c_msg *msg = qup->msg;
1348 int ret;
1349
1350 /*
1351 * Check if its SMBus Block read for which the top level read will be
1352 * done into 2 QUP reads. One with message length 1 while other one is
1353 * with actual length.
1354 */
1355 if (qup_i2c_check_msg_len(msg)) {
1356 if (qup->is_smbus_read) {
1357 /*
1358 * If the message length is already read in
1359 * the first byte of the buffer, account for
1360 * that by setting the offset
1361 */
1362 blk->cur_data += 1;
1363 is_first = false;
1364 } else {
1365 change_pause_state = false;
1366 }
1367 }
1368
1369 qup->config_run = is_first ? 0 : QUP_I2C_MX_CONFIG_DURING_RUN;
1370
1371 qup_i2c_clear_blk_v2(blk);
1372 qup_i2c_conf_count_v2(qup);
1373
1374 /* If it is first sub transfer, then configure i2c bus clocks */
1375 if (is_first) {
1376 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1377 if (ret)
1378 return ret;
1379
1380 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1381
1382 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1383 if (ret)
1384 return ret;
1385 }
1386
1387 reinit_completion(&qup->xfer);
1388 enable_irq(qup->irq);
1389 /*
1390 * In FIFO mode, tx FIFO can be written directly while in block mode the
1391 * it will be written after getting OUT_BLOCK_WRITE_REQ interrupt
1392 */
1393 if (!blk->is_tx_blk_mode) {
1394 blk->tx_fifo_free = qup->out_fifo_sz;
1395
1396 if (is_rx)
1397 qup_i2c_write_rx_tags_v2(qup);
1398 else
1399 qup_i2c_write_tx_fifo_v2(qup);
1400 }
1401
1402 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1403 if (ret)
1404 goto err;
1405
1406 ret = qup_i2c_wait_for_complete(qup, msg);
1407 if (ret)
1408 goto err;
1409
1410 /* Move to pause state for all the transfers, except last one */
1411 if (change_pause_state) {
1412 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1413 if (ret)
1414 goto err;
1415 }
1416
1417err:
1418 disable_irq(qup->irq);
1419 return ret;
1420}
1421
1422/*
1423 * Transfer one read/write message in i2c transfer. It splits the message into
1424 * multiple of blk_xfer_limit data length blocks and schedule each
1425 * QUP block individually.
1426 */
1427static int qup_i2c_xfer_v2_msg(struct qup_i2c_dev *qup, int msg_id, bool is_rx)
1428{
1429 int ret = 0;
1430 unsigned int data_len, i;
1431 struct i2c_msg *msg = qup->msg;
1432 struct qup_i2c_block *blk = &qup->blk;
1433 u8 *msg_buf = msg->buf;
1434
1435 qup->blk_xfer_limit = is_rx ? RECV_MAX_DATA_LEN : QUP_READ_LIMIT;
1436 qup_i2c_set_blk_data(qup, msg);
1437
1438 for (i = 0; i < blk->count; i++) {
1439 data_len = qup_i2c_get_data_len(qup);
1440 blk->pos = i;
1441 blk->cur_tx_tags = blk->tags;
1442 blk->cur_blk_len = data_len;
1443 blk->tx_tag_len =
1444 qup_i2c_set_tags(blk->cur_tx_tags, qup, qup->msg);
1445
1446 blk->cur_data = msg_buf;
1447
1448 if (is_rx) {
1449 blk->total_tx_len = blk->tx_tag_len;
1450 blk->rx_tag_len = 2;
1451 blk->total_rx_len = blk->rx_tag_len + data_len;
1452 } else {
1453 blk->total_tx_len = blk->tx_tag_len + data_len;
1454 blk->total_rx_len = 0;
1455 }
1456
1457 ret = qup_i2c_conf_xfer_v2(qup, is_rx, !msg_id && !i,
1458 !qup->is_last || i < blk->count - 1);
1459 if (ret)
1460 return ret;
1461
1462 /* Handle SMBus block read length */
1463 if (qup_i2c_check_msg_len(msg) && msg->len == 1 &&
1464 !qup->is_smbus_read) {
1465 if (msg->buf[0] > I2C_SMBUS_BLOCK_MAX)
1466 return -EPROTO;
1467
1468 msg->len = msg->buf[0];
1469 qup->is_smbus_read = true;
1470 ret = qup_i2c_xfer_v2_msg(qup, msg_id, true);
1471 qup->is_smbus_read = false;
1472 if (ret)
1473 return ret;
1474
1475 msg->len += 1;
1476 }
1477
1478 msg_buf += data_len;
1479 blk->data_len -= qup->blk_xfer_limit;
1480 }
1481
1482 return ret;
1483}
1484
1485/*
1486 * QUP v2 supports 3 modes
1487 * Programmed IO using FIFO mode : Less than FIFO size
1488 * Programmed IO using Block mode : Greater than FIFO size
1489 * DMA using BAM : Appropriate for any transaction size but the address should
1490 * be DMA applicable
1491 *
1492 * This function determines the mode which will be used for this transfer. An
1493 * i2c transfer contains multiple message. Following are the rules to determine
1494 * the mode used.
1495 * 1. Determine complete length, maximum tx and rx length for complete transfer.
1496 * 2. If complete transfer length is greater than fifo size then use the DMA
1497 * mode.
1498 * 3. In FIFO or block mode, tx and rx can operate in different mode so check
1499 * for maximum tx and rx length to determine mode.
1500 */
1501static int
1502qup_i2c_determine_mode_v2(struct qup_i2c_dev *qup,
1503 struct i2c_msg msgs[], int num)
1504{
1505 int idx;
1506 bool no_dma = false;
1507 unsigned int max_tx_len = 0, max_rx_len = 0, total_len = 0;
1508
1509 /* All i2c_msgs should be transferred using either dma or cpu */
1510 for (idx = 0; idx < num; idx++) {
1511 if (msgs[idx].flags & I2C_M_RD)
1512 max_rx_len = max_t(unsigned int, max_rx_len,
1513 msgs[idx].len);
1514 else
1515 max_tx_len = max_t(unsigned int, max_tx_len,
1516 msgs[idx].len);
1517
1518 if (is_vmalloc_addr(msgs[idx].buf))
1519 no_dma = true;
1520
1521 total_len += msgs[idx].len;
1522 }
1523
1524 if (!no_dma && qup->is_dma &&
1525 (total_len > qup->out_fifo_sz || total_len > qup->in_fifo_sz)) {
1526 qup->use_dma = true;
1527 } else {
1528 qup->blk.is_tx_blk_mode = max_tx_len > qup->out_fifo_sz -
1529 QUP_MAX_TAGS_LEN;
1530 qup->blk.is_rx_blk_mode = max_rx_len > qup->in_fifo_sz -
1531 READ_RX_TAGS_LEN;
1532 }
1533
1534 return 0;
1535}
1536
1537static int qup_i2c_xfer_v2(struct i2c_adapter *adap,
1538 struct i2c_msg msgs[],
1539 int num)
1540{
1541 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1542 int ret, idx = 0;
1543
1544 qup->bus_err = 0;
1545 qup->qup_err = 0;
1546
1547 ret = pm_runtime_get_sync(qup->dev);
1548 if (ret < 0)
1549 goto out;
1550
1551 ret = qup_i2c_determine_mode_v2(qup, msgs, num);
1552 if (ret)
1553 goto out;
1554
1555 writel(1, qup->base + QUP_SW_RESET);
1556 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1557 if (ret)
1558 goto out;
1559
1560 /* Configure QUP as I2C mini core */
1561 writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG);
1562 writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN);
1563
1564 if (qup_i2c_poll_state_i2c_master(qup)) {
1565 ret = -EIO;
1566 goto out;
1567 }
1568
1569 if (qup->use_dma) {
1570 reinit_completion(&qup->xfer);
1571 ret = qup_i2c_bam_xfer(adap, &msgs[0], num);
1572 qup->use_dma = false;
1573 } else {
1574 qup_i2c_conf_mode_v2(qup);
1575
1576 for (idx = 0; idx < num; idx++) {
1577 qup->msg = &msgs[idx];
1578 qup->is_last = idx == (num - 1);
1579
1580 ret = qup_i2c_xfer_v2_msg(qup, idx,
1581 !!(msgs[idx].flags & I2C_M_RD));
1582 if (ret)
1583 break;
1584 }
1585 qup->msg = NULL;
1586 }
1587
1588 if (!ret)
1589 ret = qup_i2c_bus_active(qup, ONE_BYTE);
1590
1591 if (!ret)
1592 qup_i2c_change_state(qup, QUP_RESET_STATE);
1593
1594 if (ret == 0)
1595 ret = num;
1596out:
1597 pm_runtime_mark_last_busy(qup->dev);
1598 pm_runtime_put_autosuspend(qup->dev);
1599
1600 return ret;
1601}
1602
1603static u32 qup_i2c_func(struct i2c_adapter *adap)
1604{
1605 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
1606}
1607
1608static const struct i2c_algorithm qup_i2c_algo = {
1609 .master_xfer = qup_i2c_xfer,
1610 .functionality = qup_i2c_func,
1611};
1612
1613static const struct i2c_algorithm qup_i2c_algo_v2 = {
1614 .master_xfer = qup_i2c_xfer_v2,
1615 .functionality = qup_i2c_func,
1616};
1617
1618/*
1619 * The QUP block will issue a NACK and STOP on the bus when reaching
1620 * the end of the read, the length of the read is specified as one byte
1621 * which limits the possible read to 256 (QUP_READ_LIMIT) bytes.
1622 */
1623static const struct i2c_adapter_quirks qup_i2c_quirks = {
1624 .flags = I2C_AQ_NO_ZERO_LEN,
1625 .max_read_len = QUP_READ_LIMIT,
1626};
1627
1628static const struct i2c_adapter_quirks qup_i2c_quirks_v2 = {
1629 .flags = I2C_AQ_NO_ZERO_LEN,
1630};
1631
1632static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup)
1633{
1634 clk_prepare_enable(qup->clk);
1635 clk_prepare_enable(qup->pclk);
1636}
1637
1638static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup)
1639{
1640 u32 config;
1641
1642 qup_i2c_change_state(qup, QUP_RESET_STATE);
1643 clk_disable_unprepare(qup->clk);
1644 config = readl(qup->base + QUP_CONFIG);
1645 config |= QUP_CLOCK_AUTO_GATE;
1646 writel(config, qup->base + QUP_CONFIG);
1647 clk_disable_unprepare(qup->pclk);
1648}
1649
1650static const struct acpi_device_id qup_i2c_acpi_match[] = {
1651 { "QCOM8010"},
1652 { },
1653};
1654MODULE_DEVICE_TABLE(acpi, qup_i2c_acpi_match);
1655
1656static int qup_i2c_probe(struct platform_device *pdev)
1657{
1658 static const int blk_sizes[] = {4, 16, 32};
1659 struct qup_i2c_dev *qup;
1660 unsigned long one_bit_t;
1661 u32 io_mode, hw_ver, size;
1662 int ret, fs_div, hs_div;
1663 u32 src_clk_freq = DEFAULT_SRC_CLK;
1664 u32 clk_freq = DEFAULT_CLK_FREQ;
1665 int blocks;
1666 bool is_qup_v1;
1667
1668 qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);
1669 if (!qup)
1670 return -ENOMEM;
1671
1672 qup->dev = &pdev->dev;
1673 init_completion(&qup->xfer);
1674 platform_set_drvdata(pdev, qup);
1675
1676 if (scl_freq) {
1677 dev_notice(qup->dev, "Using override frequency of %u\n", scl_freq);
1678 clk_freq = scl_freq;
1679 } else {
1680 ret = device_property_read_u32(qup->dev, "clock-frequency", &clk_freq);
1681 if (ret) {
1682 dev_notice(qup->dev, "using default clock-frequency %d",
1683 DEFAULT_CLK_FREQ);
1684 }
1685 }
1686
1687 if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) {
1688 qup->adap.algo = &qup_i2c_algo;
1689 qup->adap.quirks = &qup_i2c_quirks;
1690 is_qup_v1 = true;
1691 } else {
1692 qup->adap.algo = &qup_i2c_algo_v2;
1693 qup->adap.quirks = &qup_i2c_quirks_v2;
1694 is_qup_v1 = false;
1695 if (acpi_match_device(qup_i2c_acpi_match, qup->dev))
1696 goto nodma;
1697 else
1698 ret = qup_i2c_req_dma(qup);
1699
1700 if (ret == -EPROBE_DEFER)
1701 goto fail_dma;
1702 else if (ret != 0)
1703 goto nodma;
1704
1705 qup->max_xfer_sg_len = (MX_BLOCKS << 1);
1706 blocks = (MX_DMA_BLOCKS << 1) + 1;
1707 qup->btx.sg = devm_kcalloc(&pdev->dev,
1708 blocks, sizeof(*qup->btx.sg),
1709 GFP_KERNEL);
1710 if (!qup->btx.sg) {
1711 ret = -ENOMEM;
1712 goto fail_dma;
1713 }
1714 sg_init_table(qup->btx.sg, blocks);
1715
1716 qup->brx.sg = devm_kcalloc(&pdev->dev,
1717 blocks, sizeof(*qup->brx.sg),
1718 GFP_KERNEL);
1719 if (!qup->brx.sg) {
1720 ret = -ENOMEM;
1721 goto fail_dma;
1722 }
1723 sg_init_table(qup->brx.sg, blocks);
1724
1725 /* 2 tag bytes for each block + 5 for start, stop tags */
1726 size = blocks * 2 + 5;
1727
1728 qup->start_tag.start = devm_kzalloc(&pdev->dev,
1729 size, GFP_KERNEL);
1730 if (!qup->start_tag.start) {
1731 ret = -ENOMEM;
1732 goto fail_dma;
1733 }
1734
1735 qup->brx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);
1736 if (!qup->brx.tag.start) {
1737 ret = -ENOMEM;
1738 goto fail_dma;
1739 }
1740
1741 qup->btx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);
1742 if (!qup->btx.tag.start) {
1743 ret = -ENOMEM;
1744 goto fail_dma;
1745 }
1746 qup->is_dma = true;
1747 }
1748
1749nodma:
1750 /* We support frequencies up to FAST Mode Plus (1MHz) */
1751 if (!clk_freq || clk_freq > I2C_MAX_FAST_MODE_PLUS_FREQ) {
1752 dev_err(qup->dev, "clock frequency not supported %d\n",
1753 clk_freq);
1754 return -EINVAL;
1755 }
1756
1757 qup->base = devm_platform_ioremap_resource(pdev, 0);
1758 if (IS_ERR(qup->base))
1759 return PTR_ERR(qup->base);
1760
1761 qup->irq = platform_get_irq(pdev, 0);
1762 if (qup->irq < 0)
1763 return qup->irq;
1764
1765 if (has_acpi_companion(qup->dev)) {
1766 ret = device_property_read_u32(qup->dev,
1767 "src-clock-hz", &src_clk_freq);
1768 if (ret) {
1769 dev_notice(qup->dev, "using default src-clock-hz %d",
1770 DEFAULT_SRC_CLK);
1771 }
1772 ACPI_COMPANION_SET(&qup->adap.dev, ACPI_COMPANION(qup->dev));
1773 } else {
1774 qup->clk = devm_clk_get(qup->dev, "core");
1775 if (IS_ERR(qup->clk)) {
1776 dev_err(qup->dev, "Could not get core clock\n");
1777 return PTR_ERR(qup->clk);
1778 }
1779
1780 qup->pclk = devm_clk_get(qup->dev, "iface");
1781 if (IS_ERR(qup->pclk)) {
1782 dev_err(qup->dev, "Could not get iface clock\n");
1783 return PTR_ERR(qup->pclk);
1784 }
1785 qup_i2c_enable_clocks(qup);
1786 src_clk_freq = clk_get_rate(qup->clk);
1787 }
1788
1789 /*
1790 * Bootloaders might leave a pending interrupt on certain QUP's,
1791 * so we reset the core before registering for interrupts.
1792 */
1793 writel(1, qup->base + QUP_SW_RESET);
1794 ret = qup_i2c_poll_state_valid(qup);
1795 if (ret)
1796 goto fail;
1797
1798 ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt,
1799 IRQF_TRIGGER_HIGH, "i2c_qup", qup);
1800 if (ret) {
1801 dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq);
1802 goto fail;
1803 }
1804 disable_irq(qup->irq);
1805
1806 hw_ver = readl(qup->base + QUP_HW_VERSION);
1807 dev_dbg(qup->dev, "Revision %x\n", hw_ver);
1808
1809 io_mode = readl(qup->base + QUP_IO_MODE);
1810
1811 /*
1812 * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
1813 * associated with each byte written/received
1814 */
1815 size = QUP_OUTPUT_BLOCK_SIZE(io_mode);
1816 if (size >= ARRAY_SIZE(blk_sizes)) {
1817 ret = -EIO;
1818 goto fail;
1819 }
1820 qup->out_blk_sz = blk_sizes[size];
1821
1822 size = QUP_INPUT_BLOCK_SIZE(io_mode);
1823 if (size >= ARRAY_SIZE(blk_sizes)) {
1824 ret = -EIO;
1825 goto fail;
1826 }
1827 qup->in_blk_sz = blk_sizes[size];
1828
1829 if (is_qup_v1) {
1830 /*
1831 * in QUP v1, QUP_CONFIG uses N as 15 i.e 16 bits constitutes a
1832 * single transfer but the block size is in bytes so divide the
1833 * in_blk_sz and out_blk_sz by 2
1834 */
1835 qup->in_blk_sz /= 2;
1836 qup->out_blk_sz /= 2;
1837 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v1;
1838 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v1;
1839 qup->write_rx_tags = qup_i2c_write_rx_tags_v1;
1840 } else {
1841 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v2;
1842 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v2;
1843 qup->write_rx_tags = qup_i2c_write_rx_tags_v2;
1844 }
1845
1846 size = QUP_OUTPUT_FIFO_SIZE(io_mode);
1847 qup->out_fifo_sz = qup->out_blk_sz * (2 << size);
1848
1849 size = QUP_INPUT_FIFO_SIZE(io_mode);
1850 qup->in_fifo_sz = qup->in_blk_sz * (2 << size);
1851
1852 hs_div = 3;
1853 if (clk_freq <= I2C_MAX_STANDARD_MODE_FREQ) {
1854 fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
1855 qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
1856 } else {
1857 /* 33%/66% duty cycle */
1858 fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3;
1859 qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff);
1860 }
1861
1862 /*
1863 * Time it takes for a byte to be clocked out on the bus.
1864 * Each byte takes 9 clock cycles (8 bits + 1 ack).
1865 */
1866 one_bit_t = (USEC_PER_SEC / clk_freq) + 1;
1867 qup->one_byte_t = one_bit_t * 9;
1868 qup->xfer_timeout = TOUT_MIN * HZ +
1869 usecs_to_jiffies(MX_DMA_TX_RX_LEN * qup->one_byte_t);
1870
1871 dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
1872 qup->in_blk_sz, qup->in_fifo_sz,
1873 qup->out_blk_sz, qup->out_fifo_sz);
1874
1875 i2c_set_adapdata(&qup->adap, qup);
1876 qup->adap.dev.parent = qup->dev;
1877 qup->adap.dev.of_node = pdev->dev.of_node;
1878 qup->is_last = true;
1879
1880 strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
1881
1882 pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
1883 pm_runtime_use_autosuspend(qup->dev);
1884 pm_runtime_set_active(qup->dev);
1885 pm_runtime_enable(qup->dev);
1886
1887 ret = i2c_add_adapter(&qup->adap);
1888 if (ret)
1889 goto fail_runtime;
1890
1891 return 0;
1892
1893fail_runtime:
1894 pm_runtime_disable(qup->dev);
1895 pm_runtime_set_suspended(qup->dev);
1896fail:
1897 qup_i2c_disable_clocks(qup);
1898fail_dma:
1899 if (qup->btx.dma)
1900 dma_release_channel(qup->btx.dma);
1901 if (qup->brx.dma)
1902 dma_release_channel(qup->brx.dma);
1903 return ret;
1904}
1905
1906static int qup_i2c_remove(struct platform_device *pdev)
1907{
1908 struct qup_i2c_dev *qup = platform_get_drvdata(pdev);
1909
1910 if (qup->is_dma) {
1911 dma_release_channel(qup->btx.dma);
1912 dma_release_channel(qup->brx.dma);
1913 }
1914
1915 disable_irq(qup->irq);
1916 qup_i2c_disable_clocks(qup);
1917 i2c_del_adapter(&qup->adap);
1918 pm_runtime_disable(qup->dev);
1919 pm_runtime_set_suspended(qup->dev);
1920 return 0;
1921}
1922
1923#ifdef CONFIG_PM
1924static int qup_i2c_pm_suspend_runtime(struct device *device)
1925{
1926 struct qup_i2c_dev *qup = dev_get_drvdata(device);
1927
1928 dev_dbg(device, "pm_runtime: suspending...\n");
1929 qup_i2c_disable_clocks(qup);
1930 return 0;
1931}
1932
1933static int qup_i2c_pm_resume_runtime(struct device *device)
1934{
1935 struct qup_i2c_dev *qup = dev_get_drvdata(device);
1936
1937 dev_dbg(device, "pm_runtime: resuming...\n");
1938 qup_i2c_enable_clocks(qup);
1939 return 0;
1940}
1941#endif
1942
1943#ifdef CONFIG_PM_SLEEP
1944static int qup_i2c_suspend(struct device *device)
1945{
1946 if (!pm_runtime_suspended(device))
1947 return qup_i2c_pm_suspend_runtime(device);
1948 return 0;
1949}
1950
1951static int qup_i2c_resume(struct device *device)
1952{
1953 qup_i2c_pm_resume_runtime(device);
1954 pm_runtime_mark_last_busy(device);
1955 pm_request_autosuspend(device);
1956 return 0;
1957}
1958#endif
1959
1960static const struct dev_pm_ops qup_i2c_qup_pm_ops = {
1961 SET_SYSTEM_SLEEP_PM_OPS(
1962 qup_i2c_suspend,
1963 qup_i2c_resume)
1964 SET_RUNTIME_PM_OPS(
1965 qup_i2c_pm_suspend_runtime,
1966 qup_i2c_pm_resume_runtime,
1967 NULL)
1968};
1969
1970static const struct of_device_id qup_i2c_dt_match[] = {
1971 { .compatible = "qcom,i2c-qup-v1.1.1" },
1972 { .compatible = "qcom,i2c-qup-v2.1.1" },
1973 { .compatible = "qcom,i2c-qup-v2.2.1" },
1974 {}
1975};
1976MODULE_DEVICE_TABLE(of, qup_i2c_dt_match);
1977
1978static struct platform_driver qup_i2c_driver = {
1979 .probe = qup_i2c_probe,
1980 .remove = qup_i2c_remove,
1981 .driver = {
1982 .name = "i2c_qup",
1983 .pm = &qup_i2c_qup_pm_ops,
1984 .of_match_table = qup_i2c_dt_match,
1985 .acpi_match_table = ACPI_PTR(qup_i2c_acpi_match),
1986 },
1987};
1988
1989module_platform_driver(qup_i2c_driver);
1990
1991MODULE_LICENSE("GPL v2");
1992MODULE_ALIAS("platform:i2c_qup");